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<div class="title">Startup File startup_<device>.c </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><p>The <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> contains:</p>
<ul>
<li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li>
<li>The setup values for the Main Stack Pointer (MSP).</li>
<li>Exception vectors of the Cortex-M Processor with weak functions that implement default routines.</li>
<li>Interrupt vectors that are device specific with weak functions that implement default routines.</li>
</ul>
<p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p>
<p>To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all the IRQ numbers for each interrupt.</p>
<p><b>Example:</b> </p>
<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p>
<div class="fragment"><div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment"> Exception / Interrupt Handler</span></div>
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
<div class="line"><span class="comment">/* Exceptions */</span></div>
<div class="line"><span class="keywordtype">void</span> WAKEUP0_IRQHandler (<span class="keywordtype">void</span>) __attribute__ ((weak, alias("Default_Handler")));</div>
<div class="line"><span class="keywordtype">void</span> WAKEUP1_IRQHandler (<span class="keywordtype">void</span>) __attribute__ ((weak, alias("Default_Handler")));</div>
<div class="line"><span class="keywordtype">void</span> WAKEUP2_IRQHandler (<span class="keywordtype">void</span>) __attribute__ ((weak, alias("Default_Handler")));</div>
<div class="line"><span class="comment">// :</span></div>
<div class="line"><span class="comment">// :</span></div>
<div class="line"><span class="keywordtype">void</span> EINT1_IRQHandler (<span class="keywordtype">void</span>) __attribute__ ((weak, alias("Default_Handler")));</div>
<div class="line"><span class="keywordtype">void</span> EINT2_IRQHandler (<span class="keywordtype">void</span>) __attribute__ ((weak, alias("Default_Handler")));</div>
<div class="line"><span class="comment">// :</span></div>
<div class="line"><span class="comment">// :</span></div>
<div class="line"></div>
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment"> Exception / Interrupt Vector table</span></div>
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
<div class="line">extern const pFunc <a class="code" href="group__compiler__conntrol__gr.html#gab94ebeb20055f1848d7b707d3c7cfc5d">__VECTOR_TABLE</a>[240];</div>
<div class="line"> const pFunc __VECTOR_TABLE[240] <a class="code" href="group__compiler__conntrol__gr.html#ga4f65c96effa79fbd610fea43ee7d745b">__VECTOR_TABLE_ATTRIBUTE</a> = {</div>
<div class="line"> (pFunc)(&<a class="code" href="group__compiler__conntrol__gr.html#ga1002e751427b1189f92787d4e4eef965">__INITIAL_SP</a>), <span class="comment">/* Initial Stack Pointer */</span></div>
<div class="line"> Reset_Handler, <span class="comment">/* Reset Handler */</span></div>
<div class="line"> NMI_Handler, <span class="comment">/* -14 NMI Handler */</span></div>
<div class="line"> HardFault_Handler, <span class="comment">/* -13 Hard Fault Handler */</span></div>
<div class="line"> MemManage_Handler, <span class="comment">/* -12 MPU Fault Handler */</span></div>
<div class="line"> BusFault_Handler, <span class="comment">/* -11 Bus Fault Handler */</span></div>
<div class="line"> UsageFault_Handler, <span class="comment">/* -10 Usage Fault Handler */</span></div>
<div class="line"> 0, <span class="comment">/* Reserved */</span></div>
<div class="line"> 0, <span class="comment">/* Reserved */</span></div>
<div class="line"> 0, <span class="comment">/* Reserved */</span></div>
<div class="line"> 0, <span class="comment">/* Reserved */</span></div>
<div class="line"> SVC_Handler, <span class="comment">/* -5 SVCall Handler */</span></div>
<div class="line"> DebugMon_Handler, <span class="comment">/* -4 Debug Monitor Handler */</span></div>
<div class="line"> 0, <span class="comment">/* Reserved */</span></div>
<div class="line"> PendSV_Handler, <span class="comment">/* -2 PendSV Handler */</span></div>
<div class="line"> SysTick_Handler, <span class="comment">/* -1 SysTick Handler */</span></div>
<div class="line"></div>
<div class="line"> <span class="comment">/* Interrupts */</span></div>
<div class="line"> WAKEUP0_IRQHandler, <span class="comment">/* 0 Wakeup PIO0.0 */</span></div>
<div class="line"> WAKEUP1_IRQHandler, <span class="comment">/* 1 Wakeup PIO0.1 */</span></div>
<div class="line"> WAKEUP2_IRQHandler, <span class="comment">/* 2 Wakeup PIO0.2 */</span></div>
<div class="line"> <span class="comment">// :</span></div>
<div class="line"> <span class="comment">// :</span></div>
<div class="line"> EINT1_IRQHandler, <span class="comment">/* 30 PIO INT1 */</span></div>
<div class="line"> EINT2_IRQHandler, <span class="comment">/* 31 PIO INT2 */</span></div>
<div class="line"> <span class="comment">// :</span></div>
<div class="line"> <span class="comment">// :</span></div>
<div class="line">};</div>
</div><!-- fragment --><h1><a class="anchor" id="startup_c_sec"></a>
startup_Device.c Template File</h1>
<p>A compiler agnostic <a class="el" href="startup_c_pg.html#startup_c_sec">startup_Device.c Template File</a> for an Armv7-M processor like Cortex-M3 is shown below. The C startup file relys on certain compiler specific preprocessor defines specified in CMSIS compiler headers:</p>
<ul>
<li><a class="el" href="group__compiler__conntrol__gr.html#ga1002e751427b1189f92787d4e4eef965">__INITIAL_SP</a></li>
<li><a class="el" href="group__compiler__conntrol__gr.html#ga84b0bad4aa39632d3faea46aa1e102a8">__STACK_LIMIT</a></li>
<li><a class="el" href="group__compiler__conntrol__gr.html#ga72db8b026c5e100254080fefabd9fd88">__PROGRAM_START</a></li>
<li><a class="el" href="group__compiler__conntrol__gr.html#gab94ebeb20055f1848d7b707d3c7cfc5d">__VECTOR_TABLE</a></li>
<li><a class="el" href="group__compiler__conntrol__gr.html#ga4f65c96effa79fbd610fea43ee7d745b">__VECTOR_TABLE_ATTRIBUTE</a></li>
</ul>
<pre class="fragment">/******************************************************************************
* @file startup_Device.c
* @brief CMSIS-Core(M) Device Startup File for <Device>
* @version V2.0.0
* @date 20. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "<Device>.h"
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
extern const pFunc __VECTOR_TABLE[240];
const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
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<div class="header">
<div class="headertitle">
<div class="title">Startup File startup_<device>.s (deprecated) </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><p>The <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a> contains:</p>
<ul>
<li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li>
<li>The setup values for the Main Stack Pointer (MSP).</li>
<li>Exception vectors of the Cortex-M Processor with weak functions that implement default routines.</li>
<li>Interrupt vectors that are device specific with weak functions that implement default routines.</li>
</ul>
<p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p>
<p>To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all the IRQ numbers for each interrupt.</p>
<p><b>Example:</b> </p>
<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p>
<div class="fragment"><div class="line"> ; External Interrupts</div>
<div class="line"> DCD WAKEUP0_IRQHandler ; 16+ 0: Wakeup PIO0.0</div>
<div class="line"> DCD WAKEUP1_IRQHandler ; 16+ 1: Wakeup PIO0.1</div>
<div class="line"> DCD WAKEUP2_IRQHandler ; 16+ 2: Wakeup PIO0.2</div>
<div class="line"> : :</div>
<div class="line"> : :</div>
<div class="line"> DCD EINT1_IRQHandler ; 16+30: PIO INT1</div>
<div class="line"> DCD EINT0_IRQHandler ; 16+31: PIO INT0</div>
<div class="line"> :</div>
<div class="line"> :</div>
<div class="line"> EXPORT WAKEUP0_IRQHandler [WEAK]</div>
<div class="line"> EXPORT WAKEUP1_IRQHandler [WEAK]</div>
<div class="line"> EXPORT WAKEUP2_IRQHandler [WEAK]</div>
<div class="line"> : :</div>
<div class="line"> : :</div>
<div class="line"> EXPORT EINT1_IRQHandler [WEAK]</div>
<div class="line"> EXPORT EINT0_IRQHandler [WEAK]</div>
<div class="line"></div>
<div class="line">WAKEUP0_IRQHandler</div>
<div class="line">WAKEUP1_IRQHandler</div>
<div class="line">WAKEUP1_IRQHandler</div>
<div class="line"> :</div>
<div class="line"> :</div>
<div class="line">EINT1_IRQHandler</div>
<div class="line">EINT0_IRQHandler</div>
<div class="line"> B .</div>
</div><!-- fragment --><h1><a class="anchor" id="startup_s_sec"></a>
startup_Device.s Template File</h1>
<p>An Arm Compiler <a class="el" href="startup_s_pg.html#startup_s_sec">startup_Device.s Template File</a> for an Armv7-M processor like Cortex-M3 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.</p>
<pre class="fragment">;/**************************************************************************//**
; * @file startup_<Device>.s
; * @brief CMSIS Cortex-M ARMv7-M based Core Device Startup File for
; * Device <Device>
; * @version V5.4.0
; * @date 12. December 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
IF :LNOT::DEF:__MICROLIB
IMPORT __use_two_region_memory
ENDIF
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
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<div class="title">ARM_MPU_Region_t Struct Reference<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a> | <a class="el" href="group__mpu8__functions.html">MPU Functions for Armv8-M</a></div></div> </div>
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<p>Setup information of a single MPU Region.
<a href="structARM__MPU__Region__t.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:afe7a7721aa08988d915670efa432cdd2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html#afe7a7721aa08988d915670efa432cdd2">RBAR</a></td></tr>
<tr class="memdesc:afe7a7721aa08988d915670efa432cdd2"><td class="mdescLeft"> </td><td class="mdescRight">The region base address register value (<a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a>) <a href="#afe7a7721aa08988d915670efa432cdd2">More...</a><br/></td></tr>
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<tr class="memitem:a6a3e404b403c8df611f27d902d745d8d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d">RASR</a></td></tr>
<tr class="memdesc:a6a3e404b403c8df611f27d902d745d8d"><td class="mdescLeft"> </td><td class="mdescRight">The region attribute and size register value (<a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a>), see <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>. <a href="#a6a3e404b403c8df611f27d902d745d8d">More...</a><br/></td></tr>
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<tr class="memitem:ab5d3a650dbffd0b272bf7df5b140e8a8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html#ab5d3a650dbffd0b272bf7df5b140e8a8">RLAR</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>The typedef <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> allows to define a MPU table (array of MPU regions) with pre-compiled register values. Such tables enable efficient MPU setup using the function <a class="el" href="group__mpu8__functions.html#gaca76614e3091c7324aa9d60e634621bf">ARM_MPU_Load</a>.</p>
<p><b>Example:</b> See <a class="el" href="group__mpu8__functions.html#gaca76614e3091c7324aa9d60e634621bf">ARM_MPU_Load</a></p>
<p>Struct for a single MPU Region </p>
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<p>This value specifies region attributes and size. Use the <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> macro to compose this value. </p>
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<p>Region Base Address Register value</p>
<p>This value specifies the start address of the MPU protected memory region. The address must be a multiple of the region size (size aligned).</p>
<p>See <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a> for details about field bit format. </p>
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<p>Region Limit Address Register value </p>
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var structARM__MPU__Region__t =
[
[ "RASR", "structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d", null ],
[ "RBAR", "structARM__MPU__Region__t.html#afe7a7721aa08988d915670efa432cdd2", null ],
[ "RLAR", "structARM__MPU__Region__t.html#ab5d3a650dbffd0b272bf7df5b140e8a8", null ]
]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structARM__MPU__Region__t.js | JavaScript | apache-2.0 | 305 |
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<p>Structure type to access the Core Debug Register (CoreDebug).
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<tr class="memitem:ad63554e4650da91a8e79929cbb63db66"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66">DHCSR</a></td></tr>
<tr class="memdesc:ad63554e4650da91a8e79929cbb63db66"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Debug Halting Control and Status Register. <a href="#ad63554e4650da91a8e79929cbb63db66">More...</a><br/></td></tr>
<tr class="separator:ad63554e4650da91a8e79929cbb63db66"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af907cf64577eaf927dac6787df6dd98b"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b">DCRSR</a></td></tr>
<tr class="memdesc:af907cf64577eaf927dac6787df6dd98b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 ( /W) Debug Core Register Selector Register. <a href="#af907cf64577eaf927dac6787df6dd98b">More...</a><br/></td></tr>
<tr class="separator:af907cf64577eaf927dac6787df6dd98b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">DCRDR</a></td></tr>
<tr class="memdesc:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Debug Core Register Data Register. <a href="#aab3cc92ef07bc1f04b3a3aa6db2c2d55">More...</a><br/></td></tr>
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<tr class="memdesc:aeb3126abc4c258a858f21f356c0df6ee"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. <a href="#aeb3126abc4c258a858f21f356c0df6ee">More...</a><br/></td></tr>
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<td class="memname">__OM uint32_t CoreDebug_Type::DCRSR</td>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structCoreDebug__Type.html | HTML | apache-2.0 | 10,349 |
var structCoreDebug__Type =
[
[ "DCRDR", "structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55", null ],
[ "DCRSR", "structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b", null ],
[ "DEMCR", "structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee", null ],
[ "DHCSR", "structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66", null ]
]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structCoreDebug__Type.js | JavaScript | apache-2.0 | 379 |
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<p>Structure type to access the Data Watchpoint and Trace Register (DWT).
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Data Fields</h2></td></tr>
<tr class="memitem:add790c53410023b3b581919bb681fe2a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">CTRL</a></td></tr>
<tr class="memdesc:add790c53410023b3b581919bb681fe2a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Control Register. <a href="#add790c53410023b3b581919bb681fe2a">More...</a><br/></td></tr>
<tr class="separator:add790c53410023b3b581919bb681fe2a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a102eaa529d9098242851cb57c52b42d9"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9">CYCCNT</a></td></tr>
<tr class="memdesc:a102eaa529d9098242851cb57c52b42d9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Cycle Count Register. <a href="#a102eaa529d9098242851cb57c52b42d9">More...</a><br/></td></tr>
<tr class="separator:a102eaa529d9098242851cb57c52b42d9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2c08096c82abe245c0fa97badc458154"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a2c08096c82abe245c0fa97badc458154">CPICNT</a></td></tr>
<tr class="memdesc:a2c08096c82abe245c0fa97badc458154"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) CPI Count Register. <a href="#a2c08096c82abe245c0fa97badc458154">More...</a><br/></td></tr>
<tr class="separator:a2c08096c82abe245c0fa97badc458154"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9fe20c16c5167ca61486caf6832686d1"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">EXCCNT</a></td></tr>
<tr class="memdesc:a9fe20c16c5167ca61486caf6832686d1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Exception Overhead Count Register. <a href="#a9fe20c16c5167ca61486caf6832686d1">More...</a><br/></td></tr>
<tr class="separator:a9fe20c16c5167ca61486caf6832686d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a416a54e2084ce66e5ca74f152a5ecc70"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a416a54e2084ce66e5ca74f152a5ecc70">SLEEPCNT</a></td></tr>
<tr class="memdesc:a416a54e2084ce66e5ca74f152a5ecc70"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) Sleep Count Register. <a href="#a416a54e2084ce66e5ca74f152a5ecc70">More...</a><br/></td></tr>
<tr class="separator:a416a54e2084ce66e5ca74f152a5ecc70"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acc05d89bdb1b4fe2fa499920ec02d0b1"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#acc05d89bdb1b4fe2fa499920ec02d0b1">LSUCNT</a></td></tr>
<tr class="memdesc:acc05d89bdb1b4fe2fa499920ec02d0b1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) LSU Count Register. <a href="#acc05d89bdb1b4fe2fa499920ec02d0b1">More...</a><br/></td></tr>
<tr class="separator:acc05d89bdb1b4fe2fa499920ec02d0b1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1cfc48384ebd8fd8fb7e5d955aae6c97"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97">FOLDCNT</a></td></tr>
<tr class="memdesc:a1cfc48384ebd8fd8fb7e5d955aae6c97"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) Folded-instruction Count Register. <a href="#a1cfc48384ebd8fd8fb7e5d955aae6c97">More...</a><br/></td></tr>
<tr class="separator:a1cfc48384ebd8fd8fb7e5d955aae6c97"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6353ca1d1ad9bc1be05d3b5632960113"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">PCSR</a></td></tr>
<tr class="memdesc:a6353ca1d1ad9bc1be05d3b5632960113"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01C (R/ ) Program Counter Sample Register. <a href="#a6353ca1d1ad9bc1be05d3b5632960113">More...</a><br/></td></tr>
<tr class="separator:a6353ca1d1ad9bc1be05d3b5632960113"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a61c2965af5bc0643f9af65620b0e67c9"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">COMP0</a></td></tr>
<tr class="memdesc:a61c2965af5bc0643f9af65620b0e67c9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W) Comparator Register 0. <a href="#a61c2965af5bc0643f9af65620b0e67c9">More...</a><br/></td></tr>
<tr class="separator:a61c2965af5bc0643f9af65620b0e67c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a821eb5e71f340ec077efc064cfc567db"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a821eb5e71f340ec077efc064cfc567db">MASK0</a></td></tr>
<tr class="memdesc:a821eb5e71f340ec077efc064cfc567db"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) Mask Register 0. <a href="#a821eb5e71f340ec077efc064cfc567db">More...</a><br/></td></tr>
<tr class="separator:a821eb5e71f340ec077efc064cfc567db"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a579ae082f58a0317b7ef029b20f52889"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a579ae082f58a0317b7ef029b20f52889">FUNCTION0</a></td></tr>
<tr class="memdesc:a579ae082f58a0317b7ef029b20f52889"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Function Register 0. <a href="#a579ae082f58a0317b7ef029b20f52889">More...</a><br/></td></tr>
<tr class="separator:a579ae082f58a0317b7ef029b20f52889"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:addd893d655ed90d40705b20170daac59"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#addd893d655ed90d40705b20170daac59">RESERVED0</a> [1]</td></tr>
<tr class="memdesc:addd893d655ed90d40705b20170daac59"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#addd893d655ed90d40705b20170daac59">More...</a><br/></td></tr>
<tr class="separator:addd893d655ed90d40705b20170daac59"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a38714af6b7fa7c64d68f5e1efbe7a931"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931">COMP1</a></td></tr>
<tr class="memdesc:a38714af6b7fa7c64d68f5e1efbe7a931"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Comparator Register 1. <a href="#a38714af6b7fa7c64d68f5e1efbe7a931">More...</a><br/></td></tr>
<tr class="separator:a38714af6b7fa7c64d68f5e1efbe7a931"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aabf94936c9340e62fed836dcfb152405"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#aabf94936c9340e62fed836dcfb152405">MASK1</a></td></tr>
<tr class="memdesc:aabf94936c9340e62fed836dcfb152405"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 (R/W) Mask Register 1. <a href="#aabf94936c9340e62fed836dcfb152405">More...</a><br/></td></tr>
<tr class="separator:aabf94936c9340e62fed836dcfb152405"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8dfcf25675f9606aa305c46e85182e4e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a8dfcf25675f9606aa305c46e85182e4e">FUNCTION1</a></td></tr>
<tr class="memdesc:a8dfcf25675f9606aa305c46e85182e4e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x038 (R/W) Function Register 1. <a href="#a8dfcf25675f9606aa305c46e85182e4e">More...</a><br/></td></tr>
<tr class="separator:a8dfcf25675f9606aa305c46e85182e4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a069871233a8c1df03521e6d7094f1de4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a069871233a8c1df03521e6d7094f1de4">RESERVED1</a> [1]</td></tr>
<tr class="memdesc:a069871233a8c1df03521e6d7094f1de4"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a069871233a8c1df03521e6d7094f1de4">More...</a><br/></td></tr>
<tr class="separator:a069871233a8c1df03521e6d7094f1de4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5ae6dde39989f27bae90afc2347deb46"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46">COMP2</a></td></tr>
<tr class="memdesc:a5ae6dde39989f27bae90afc2347deb46"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 (R/W) Comparator Register 2. <a href="#a5ae6dde39989f27bae90afc2347deb46">More...</a><br/></td></tr>
<tr class="separator:a5ae6dde39989f27bae90afc2347deb46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a00ac4d830dfe0070a656cda9baed170f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a00ac4d830dfe0070a656cda9baed170f">MASK2</a></td></tr>
<tr class="memdesc:a00ac4d830dfe0070a656cda9baed170f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x044 (R/W) Mask Register 2. <a href="#a00ac4d830dfe0070a656cda9baed170f">More...</a><br/></td></tr>
<tr class="separator:a00ac4d830dfe0070a656cda9baed170f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab1b60d6600c38abae515bab8e86a188f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#ab1b60d6600c38abae515bab8e86a188f">FUNCTION2</a></td></tr>
<tr class="memdesc:ab1b60d6600c38abae515bab8e86a188f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x048 (R/W) Function Register 2. <a href="#ab1b60d6600c38abae515bab8e86a188f">More...</a><br/></td></tr>
<tr class="separator:ab1b60d6600c38abae515bab8e86a188f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8556ca1c32590517602d92fe0cd55738"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a8556ca1c32590517602d92fe0cd55738">RESERVED2</a> [1]</td></tr>
<tr class="memdesc:a8556ca1c32590517602d92fe0cd55738"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a8556ca1c32590517602d92fe0cd55738">More...</a><br/></td></tr>
<tr class="separator:a8556ca1c32590517602d92fe0cd55738"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a85eb73d1848ac3f82d39d6c3e8910847"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847">COMP3</a></td></tr>
<tr class="memdesc:a85eb73d1848ac3f82d39d6c3e8910847"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 (R/W) Comparator Register 3. <a href="#a85eb73d1848ac3f82d39d6c3e8910847">More...</a><br/></td></tr>
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<tr class="memdesc:a2a509d8505c37a3b64f6b24993df5f3f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x054 (R/W) Mask Register 3. <a href="#a2a509d8505c37a3b64f6b24993df5f3f">More...</a><br/></td></tr>
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<tr class="memdesc:a52d4ff278fae6f9216c63b74ce328841"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x058 (R/W) Function Register 3. <a href="#a52d4ff278fae6f9216c63b74ce328841">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>Structure type to access the Floating Point Unit (FPU).
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Data Fields</h2></td></tr>
<tr class="memitem:a7b2967b069046c8544adbbc1db143a36"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a7b2967b069046c8544adbbc1db143a36">RESERVED0</a> [1]</td></tr>
<tr class="memdesc:a7b2967b069046c8544adbbc1db143a36"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a7b2967b069046c8544adbbc1db143a36">More...</a><br/></td></tr>
<tr class="separator:a7b2967b069046c8544adbbc1db143a36"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af1b708c5e413739150df3d16ca3b7061"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#af1b708c5e413739150df3d16ca3b7061">FPCCR</a></td></tr>
<tr class="memdesc:af1b708c5e413739150df3d16ca3b7061"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Floating-Point Context Control Register. <a href="#af1b708c5e413739150df3d16ca3b7061">More...</a><br/></td></tr>
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<tr class="memitem:a55263b468d0f8e11ac77aec9ff87c820"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a55263b468d0f8e11ac77aec9ff87c820">FPCAR</a></td></tr>
<tr class="memdesc:a55263b468d0f8e11ac77aec9ff87c820"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Floating-Point Context Address Register. <a href="#a55263b468d0f8e11ac77aec9ff87c820">More...</a><br/></td></tr>
<tr class="separator:a55263b468d0f8e11ac77aec9ff87c820"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a58d1989664a06db6ec2e122eefa9f04a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a58d1989664a06db6ec2e122eefa9f04a">FPDSCR</a></td></tr>
<tr class="memdesc:a58d1989664a06db6ec2e122eefa9f04a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Floating-Point Default Status Control Register. <a href="#a58d1989664a06db6ec2e122eefa9f04a">More...</a><br/></td></tr>
<tr class="separator:a58d1989664a06db6ec2e122eefa9f04a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4f19014defe6033d070b80af19ef627c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a4f19014defe6033d070b80af19ef627c">MVFR0</a></td></tr>
<tr class="memdesc:a4f19014defe6033d070b80af19ef627c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/ ) Media and FP Feature Register 0. <a href="#a4f19014defe6033d070b80af19ef627c">More...</a><br/></td></tr>
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<tr class="memitem:a66f8cfa49a423b480001a4e101bf842d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d">MVFR1</a></td></tr>
<tr class="memdesc:a66f8cfa49a423b480001a4e101bf842d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/ ) Media and FP Feature Register 1. <a href="#a66f8cfa49a423b480001a4e101bf842d">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>Structure type to access the Instrumentation Trace Macrocell Register (ITM).
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Data Fields</h2></td></tr>
<tr class="memitem:af95bc1810f9ea802d628cb9dea81e02e"><td class="memItemLeft" >union {</td></tr>
<tr class="memitem:a19715ce0fd48d4015c27db6d0a41d49a"><td class="memItemLeft" >   __OM uint8_t   <a class="el" href="structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275">u8</a></td></tr>
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<tr class="memitem:add6779a5b967324d2700661c93283103"><td class="memItemLeft" >   __OM uint16_t   <a class="el" href="structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3">u16</a></td></tr>
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<tr class="memitem:a74a1dd7cc6bced8cb3b1da2ce6ea7eed"><td class="memItemLeft" >   __OM uint32_t   <a class="el" href="structITM__Type.html#a5834885903a557674f078f3b71fa8bc8">u32</a></td></tr>
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<tr class="memitem:af95bc1810f9ea802d628cb9dea81e02e"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e">PORT</a> [32U]</td></tr>
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<tr class="memitem:acd03c6858f7b678dab6a6121462e7807"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#acd03c6858f7b678dab6a6121462e7807">TER</a></td></tr>
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<tr class="memitem:ae907229ba50538bf370fbdfd54c099a2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2">TPR</a></td></tr>
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<tr class="memitem:a04b9fbc83759cb818dfa161d39628426"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a04b9fbc83759cb818dfa161d39628426">TCR</a></td></tr>
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<tr class="memitem:aa9da04891e48d1a2f054de186e9c4c94"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94">IWR</a></td></tr>
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<tr class="memitem:a66eb82a070953f09909f39b8e516fb91"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a66eb82a070953f09909f39b8e516fb91">IRR</a></td></tr>
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<tr class="memitem:ae2ce4d3a54df2fd11a197ccac4406cd0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">IMCR</a></td></tr>
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<tr class="memitem:a7f9c2a2113a11c7f3e98915f95b669d5"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5">LAR</a></td></tr>
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<tr class="memitem:a3861c67933a24dd6632288c4ed0b80c8"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a3861c67933a24dd6632288c4ed0b80c8">LSR</a></td></tr>
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<tr class="memitem:a2372a4ebb63e36d1eb3fcf83a74fd537"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">DEVARCH</a></td></tr>
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<tr class="memitem:aad5e11dd4baf6d941bd6c7450f60a158"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#aad5e11dd4baf6d941bd6c7450f60a158">PID4</a></td></tr>
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<tr class="memitem:a8000b92e4e528ae7ac4cb8b8d9f6757d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d">CID2</a></td></tr>
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<tr class="memitem:a43451f43f514108d9eaed5b017f8d921"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">CID3</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname">__IM uint32_t ITM_Type::CID0</td>
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</div><div class="memdoc">
<p>Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 </p>
</div>
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<td class="memname">__IM uint32_t ITM_Type::CID1</td>
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<p>Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 </p>
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<td class="memname">__IM uint32_t ITM_Type::CID2</td>
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<p>Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 </p>
</div>
</div>
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::CID3</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFFC (R/ ) ITM Component Identification Register #3 </p>
</div>
</div>
<a class="anchor" id="a2372a4ebb63e36d1eb3fcf83a74fd537"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::DEVARCH</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only) </p>
</div>
</div>
<a class="anchor" id="ae2ce4d3a54df2fd11a197ccac4406cd0"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IOM uint32_t ITM_Type::IMCR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xF00 (R/W) ITM Integration Mode Control Register </p>
</div>
</div>
<a class="anchor" id="a66eb82a070953f09909f39b8e516fb91"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::IRR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xEFC (R/ ) ITM Integration Read Register </p>
</div>
</div>
<a class="anchor" id="aa9da04891e48d1a2f054de186e9c4c94"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__OM uint32_t ITM_Type::IWR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xEF8 ( /W) ITM Integration Write Register </p>
</div>
</div>
<a class="anchor" id="a7f9c2a2113a11c7f3e98915f95b669d5"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__OM uint32_t ITM_Type::LAR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFB0 ( /W) ITM Lock Access Register </p>
</div>
</div>
<a class="anchor" id="a3861c67933a24dd6632288c4ed0b80c8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::LSR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFB4 (R/ ) ITM Lock Status Register </p>
</div>
</div>
<a class="anchor" id="ab4a4cc97ad658e9c46cf17490daffb8a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID0</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 </p>
</div>
</div>
<a class="anchor" id="a89ea1d805a668d6589b22d8e678eb6a4"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID1</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 </p>
</div>
</div>
<a class="anchor" id="a8471c4d77b7107cf580587509da69f38"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID2</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 </p>
</div>
</div>
<a class="anchor" id="af317d5e2d946d70e6fb67c02b92cc8a3"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID3</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 </p>
</div>
</div>
<a class="anchor" id="aad5e11dd4baf6d941bd6c7450f60a158"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID4</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 </p>
</div>
</div>
<a class="anchor" id="af9085648bf18f69b5f9d1136d45e1d37"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID5</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 </p>
</div>
</div>
<a class="anchor" id="ad34dbe6b1072c77d36281049c8b169f6"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID6</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 </p>
</div>
</div>
<a class="anchor" id="a2bcec6803f28f30d5baf5e20e3517d3d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IM uint32_t ITM_Type::PID7</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 </p>
</div>
</div>
<a class="anchor" id="af95bc1810f9ea802d628cb9dea81e02e"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__OM { ... } ITM_Type::PORT[32U]</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port Registers </p>
</div>
</div>
<a class="anchor" id="a04b9fbc83759cb818dfa161d39628426"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IOM uint32_t ITM_Type::TCR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xE80 (R/W) ITM Trace Control Register </p>
</div>
</div>
<a class="anchor" id="acd03c6858f7b678dab6a6121462e7807"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IOM uint32_t ITM_Type::TER</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xE00 (R/W) ITM Trace Enable Register </p>
</div>
</div>
<a class="anchor" id="ae907229ba50538bf370fbdfd54c099a2"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__IOM uint32_t ITM_Type::TPR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0xE40 (R/W) ITM Trace Privilege Register </p>
</div>
</div>
<a class="anchor" id="a962a970dfd286cad7f8a8577e87d4ad3"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__OM uint16_t ITM_Type::u16</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port 16-bit </p>
</div>
</div>
<a class="anchor" id="a5834885903a557674f078f3b71fa8bc8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__OM uint32_t ITM_Type::u32</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port 32-bit </p>
</div>
</div>
<a class="anchor" id="ae773bf9f9dac64e6c28b14aa39f74275"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">__OM uint8_t ITM_Type::u8</td>
</tr>
</table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port 8-bit </p>
</div>
</div>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structITM__Type.html | HTML | apache-2.0 | 24,683 |
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<div class="contents">
<p>Structure type to access the Memory Protection Unit (MPU).
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:aba02af87f77577c725cf73879cabb609"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">TYPE</a></td></tr>
<tr class="memdesc:aba02af87f77577c725cf73879cabb609"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) MPU Type Register. <a href="#aba02af87f77577c725cf73879cabb609">More...</a><br/></td></tr>
<tr class="separator:aba02af87f77577c725cf73879cabb609"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">CTRL</a></td></tr>
<tr class="memdesc:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) MPU Control Register. <a href="#a769178ef949f0d5d8f18ddbd9e4e926f">More...</a><br/></td></tr>
<tr class="separator:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2f7a117a12cb661c76edc4765453f05c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">RNR</a></td></tr>
<tr class="memdesc:a2f7a117a12cb661c76edc4765453f05c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) MPU Region RNRber Register. <a href="#a2f7a117a12cb661c76edc4765453f05c">More...</a><br/></td></tr>
<tr class="separator:a2f7a117a12cb661c76edc4765453f05c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a990c609b26d990b8ba832b110adfd353"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a></td></tr>
<tr class="memdesc:a990c609b26d990b8ba832b110adfd353"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) MPU Region Base Address Register. <a href="#a990c609b26d990b8ba832b110adfd353">More...</a><br/></td></tr>
<tr class="separator:a990c609b26d990b8ba832b110adfd353"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a></td></tr>
<tr class="memdesc:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) MPU Region Attribute and Size Register. <a href="#a8f00c4a5e31b0a8d103ed3b0732c17a3">More...</a><br/></td></tr>
<tr class="separator:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af8b510a85b175edfd8dd8cc93e967066"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066">RBAR_A1</a></td></tr>
<tr class="memdesc:af8b510a85b175edfd8dd8cc93e967066"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. <a href="#af8b510a85b175edfd8dd8cc93e967066">More...</a><br/></td></tr>
<tr class="separator:af8b510a85b175edfd8dd8cc93e967066"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1658326c6762637eeef8a79bb467445e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a1658326c6762637eeef8a79bb467445e">RASR_A1</a></td></tr>
<tr class="memdesc:a1658326c6762637eeef8a79bb467445e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. <a href="#a1658326c6762637eeef8a79bb467445e">More...</a><br/></td></tr>
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<tr class="memitem:a80d534f0dfc080c841e1772c7a68e1a2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2">RBAR_A2</a></td></tr>
<tr class="memdesc:a80d534f0dfc080c841e1772c7a68e1a2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. <a href="#a80d534f0dfc080c841e1772c7a68e1a2">More...</a><br/></td></tr>
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<tr class="memitem:a37131c513d8a8d211b402e5dfda97205"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205">RASR_A2</a></td></tr>
<tr class="memdesc:a37131c513d8a8d211b402e5dfda97205"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. <a href="#a37131c513d8a8d211b402e5dfda97205">More...</a><br/></td></tr>
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<tr class="memitem:a207f6e9c3af753367554cc06df300a55"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a207f6e9c3af753367554cc06df300a55">RBAR_A3</a></td></tr>
<tr class="memdesc:a207f6e9c3af753367554cc06df300a55"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. <a href="#a207f6e9c3af753367554cc06df300a55">More...</a><br/></td></tr>
<tr class="separator:a207f6e9c3af753367554cc06df300a55"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd">RASR_A3</a></td></tr>
<tr class="memdesc:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. <a href="#a7d15172b163797736a6c6b4dcc0fa3dd">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">PRIVDEFENA </td><td align="left">0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">HFNMIENA </td><td align="left">0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">ENABLE </td><td align="left">0 - The MPU is disabled. 1 - The MPU is enabled. </td></tr>
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<p>Defines the size and access behavior of the region identified by MPU_RNR, and enables that region.</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:29] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[28] </td><td align="left">XN </td><td align="left">Execute Never. </td></tr>
<tr>
<td align="left">[27] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[26:24] </td><td align="left">AP </td><td align="left">Access Permissions, see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr>
<tr>
<td align="left">[23:22] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[21:19] </td><td align="left">TEX </td><td align="left">Type Extension. </td></tr>
<tr>
<td align="left">[18] </td><td align="left">S </td><td align="left">Shareable. </td></tr>
<tr>
<td align="left">[17] </td><td align="left">C </td><td align="left">Cacheable. </td></tr>
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<td align="left">[16] </td><td align="left">B </td><td align="left">Bufferable. </td></tr>
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<td align="left">[15:8] </td><td align="left">SRD </td><td align="left">Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1). </td></tr>
<tr>
<td align="left">[7:6] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[5:1] </td><td align="left">SIZE </td><td align="left">Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes. </td></tr>
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<td align="left">[0] </td><td align="left">ENABLE </td><td align="left">0 - This region is disabled. 1 - This region is enabled. </td></tr>
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<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p>
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<p>Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:5] </td><td align="left">ADDR </td><td align="left">Base address of the region. </td></tr>
<tr>
<td align="left">[4] </td><td align="left">VALID </td><td align="left">1 - Update <a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">MPU_Type::RNR</a> to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region. </td></tr>
<tr>
<td align="left">[3:0] </td><td align="left">REGION </td><td align="left">On writes, can specify the number of the region to update, see VALID field description. </td></tr>
</table>
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<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p>
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<p>Selects the region currently accessed by <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a> and <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>.</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7:0] </td><td align="left">REGION </td><td align="left">Indicates the memory region accessed. </td></tr>
</table>
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<p>The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[23:16] </td><td align="left">IREGION </td><td align="left">Instruction region. RAZ. Armv7-M only supports a unified MPU. </td></tr>
<tr>
<td align="left">[15:8] </td><td align="left">DREGION </td><td align="left">Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. </td></tr>
<tr>
<td align="left">[7:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">SEPARATE </td><td align="left">Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. </td></tr>
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<p>Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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Data Fields</h2></td></tr>
<tr class="memitem:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47">ISER</a> [8]</td></tr>
<tr class="memdesc:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Interrupt Set Enable Register. <a href="#a9fccef5a60a0d5e81fcd7869a6274f47">More...</a><br/></td></tr>
<tr class="separator:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2de17698945ea49abd58a2d45bdc9c80"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a2de17698945ea49abd58a2d45bdc9c80">RESERVED0</a> [24]</td></tr>
<tr class="memdesc:a2de17698945ea49abd58a2d45bdc9c80"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a2de17698945ea49abd58a2d45bdc9c80">More...</a><br/></td></tr>
<tr class="separator:a2de17698945ea49abd58a2d45bdc9c80"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a245df8bac1da05c39eadabede9323203"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a245df8bac1da05c39eadabede9323203">ICER</a> [8]</td></tr>
<tr class="memdesc:a245df8bac1da05c39eadabede9323203"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Clear Enable Register. <a href="#a245df8bac1da05c39eadabede9323203">More...</a><br/></td></tr>
<tr class="separator:a245df8bac1da05c39eadabede9323203"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">RSERVED1</a> [24]</td></tr>
<tr class="memdesc:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a6d1daf7ab6f2ba83f57ff67ae6f571fe">More...</a><br/></td></tr>
<tr class="separator:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8f731a9f428efc86e8d311b52ce823d0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0">ISPR</a> [8]</td></tr>
<tr class="memdesc:a8f731a9f428efc86e8d311b52ce823d0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set Pending Register. <a href="#a8f731a9f428efc86e8d311b52ce823d0">More...</a><br/></td></tr>
<tr class="separator:a8f731a9f428efc86e8d311b52ce823d0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0953af43af8ec7fd5869a1d826ce5b72"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a0953af43af8ec7fd5869a1d826ce5b72">RESERVED2</a> [24]</td></tr>
<tr class="memdesc:a0953af43af8ec7fd5869a1d826ce5b72"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a0953af43af8ec7fd5869a1d826ce5b72">More...</a><br/></td></tr>
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<tr class="memitem:a8d8f45d9c5c67bba3c153c55574bac95"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95">ICPR</a> [8]</td></tr>
<tr class="memdesc:a8d8f45d9c5c67bba3c153c55574bac95"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear Pending Register. <a href="#a8d8f45d9c5c67bba3c153c55574bac95">More...</a><br/></td></tr>
<tr class="separator:a8d8f45d9c5c67bba3c153c55574bac95"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9dd330835dbf21471e7b5be8692d77ab"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a9dd330835dbf21471e7b5be8692d77ab">RESERVED3</a> [24]</td></tr>
<tr class="memdesc:a9dd330835dbf21471e7b5be8692d77ab"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a9dd330835dbf21471e7b5be8692d77ab">More...</a><br/></td></tr>
<tr class="separator:a9dd330835dbf21471e7b5be8692d77ab"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4bca5452748ba84d64536fb6a5d795af"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a4bca5452748ba84d64536fb6a5d795af">IABR</a> [8]</td></tr>
<tr class="memdesc:a4bca5452748ba84d64536fb6a5d795af"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Active bit Register. <a href="#a4bca5452748ba84d64536fb6a5d795af">More...</a><br/></td></tr>
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<tr class="memitem:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">RESERVED4</a> [56]</td></tr>
<tr class="memdesc:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a5c0e5d507ac3c1bd5cdaaf9bbd177790">More...</a><br/></td></tr>
<tr class="separator:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7ff7364a4260df67a2784811e8da4efd"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">IP</a> [240]</td></tr>
<tr class="memdesc:a7ff7364a4260df67a2784811e8da4efd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) <a href="#a7ff7364a4260df67a2784811e8da4efd">More...</a><br/></td></tr>
<tr class="separator:a7ff7364a4260df67a2784811e8da4efd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4f753b4f824270175af045ac99bc12e8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a4f753b4f824270175af045ac99bc12e8">RESERVED5</a> [644]</td></tr>
<tr class="memdesc:a4f753b4f824270175af045ac99bc12e8"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a4f753b4f824270175af045ac99bc12e8">More...</a><br/></td></tr>
<tr class="separator:a4f753b4f824270175af045ac99bc12e8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a37de89637466e007171c6b135299bc75"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">STIR</a></td></tr>
<tr class="memdesc:a37de89637466e007171c6b135299bc75"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE00 ( /W) Software Trigger Interrupt Register. <a href="#a37de89637466e007171c6b135299bc75">More...</a><br/></td></tr>
<tr class="separator:a37de89637466e007171c6b135299bc75"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structNVIC__Type.html | HTML | apache-2.0 | 18,183 |
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<p>Structure type to access the System Control Block (SCB).
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Data Fields</h2></td></tr>
<tr class="memitem:a21e08d546d8b641bee298a459ea73e46"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46">CPUID</a></td></tr>
<tr class="memdesc:a21e08d546d8b641bee298a459ea73e46"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) CPUID Base Register. <a href="#a21e08d546d8b641bee298a459ea73e46">More...</a><br/></td></tr>
<tr class="separator:a21e08d546d8b641bee298a459ea73e46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">ICSR</a></td></tr>
<tr class="memdesc:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Control and State Register. <a href="#a0ca18ef984d132c6bf4d9b61cd00f05a">More...</a><br/></td></tr>
<tr class="separator:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a187a4578e920544ed967f98020fb8170"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">VTOR</a></td></tr>
<tr class="memdesc:a187a4578e920544ed967f98020fb8170"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Vector Table Offset Register. <a href="#a187a4578e920544ed967f98020fb8170">More...</a><br/></td></tr>
<tr class="separator:a187a4578e920544ed967f98020fb8170"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad3e5b8934c647eb1b7383c1894f01380"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">AIRCR</a></td></tr>
<tr class="memdesc:ad3e5b8934c647eb1b7383c1894f01380"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. <a href="#ad3e5b8934c647eb1b7383c1894f01380">More...</a><br/></td></tr>
<tr class="separator:ad3e5b8934c647eb1b7383c1894f01380"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCR</a></td></tr>
<tr class="memdesc:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) System Control Register. <a href="#a3a4840c6fa4d1ee75544f4032c88ec34">More...</a><br/></td></tr>
<tr class="separator:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2d6653b0b70faac936046a02809b577f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">CCR</a></td></tr>
<tr class="memdesc:a2d6653b0b70faac936046a02809b577f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) Configuration Control Register. <a href="#a2d6653b0b70faac936046a02809b577f">More...</a><br/></td></tr>
<tr class="separator:a2d6653b0b70faac936046a02809b577f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a85768f4b3dbbc41fd760041ee1202162"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a85768f4b3dbbc41fd760041ee1202162">SHP</a> [12]</td></tr>
<tr class="memdesc:a85768f4b3dbbc41fd760041ee1202162"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) <a href="#a85768f4b3dbbc41fd760041ee1202162">More...</a><br/></td></tr>
<tr class="separator:a85768f4b3dbbc41fd760041ee1202162"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7b5ae9741a99808043394c4743b635c4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4">SHCSR</a></td></tr>
<tr class="memdesc:a7b5ae9741a99808043394c4743b635c4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) System Handler Control and State Register. <a href="#a7b5ae9741a99808043394c4743b635c4">More...</a><br/></td></tr>
<tr class="separator:a7b5ae9741a99808043394c4743b635c4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0cda9e061b42373383418663092ad19a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a0cda9e061b42373383418663092ad19a">CFSR</a></td></tr>
<tr class="memdesc:a0cda9e061b42373383418663092ad19a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Configurable Fault Status Register. <a href="#a0cda9e061b42373383418663092ad19a">More...</a><br/></td></tr>
<tr class="separator:a0cda9e061b42373383418663092ad19a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a14ad254659362b9752c69afe3fd80934"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a14ad254659362b9752c69afe3fd80934">HFSR</a></td></tr>
<tr class="memdesc:a14ad254659362b9752c69afe3fd80934"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) HardFault Status Register. <a href="#a14ad254659362b9752c69afe3fd80934">More...</a><br/></td></tr>
<tr class="separator:a14ad254659362b9752c69afe3fd80934"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a191579bde0d21ff51d30a714fd887033"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a191579bde0d21ff51d30a714fd887033">DFSR</a></td></tr>
<tr class="memdesc:a191579bde0d21ff51d30a714fd887033"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Debug Fault Status Register. <a href="#a191579bde0d21ff51d30a714fd887033">More...</a><br/></td></tr>
<tr class="separator:a191579bde0d21ff51d30a714fd887033"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80">MMFAR</a></td></tr>
<tr class="memdesc:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 (R/W) MemManage Fault Address Register. <a href="#a2d03d0b7cec2254f39eb1c46c7445e80">More...</a><br/></td></tr>
<tr class="separator:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c">BFAR</a></td></tr>
<tr class="memdesc:a3f8e7e58be4e41c88dfa78f54589271c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x038 (R/W) BusFault Address Register. <a href="#a3f8e7e58be4e41c88dfa78f54589271c">More...</a><br/></td></tr>
<tr class="separator:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab65372404ce64b0f0b35e2709429404e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e">AFSR</a></td></tr>
<tr class="memdesc:ab65372404ce64b0f0b35e2709429404e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x03C (R/W) Auxiliary Fault Status Register. <a href="#ab65372404ce64b0f0b35e2709429404e">More...</a><br/></td></tr>
<tr class="separator:ab65372404ce64b0f0b35e2709429404e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a681c9d9e518b217976bef38c2423d83d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d">PFR</a> [2]</td></tr>
<tr class="memdesc:a681c9d9e518b217976bef38c2423d83d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 (R/ ) Processor Feature Register. <a href="#a681c9d9e518b217976bef38c2423d83d">More...</a><br/></td></tr>
<tr class="separator:a681c9d9e518b217976bef38c2423d83d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">DFR</a></td></tr>
<tr class="memdesc:a85dd6fe77aab17e7ea89a52c59da6004"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x048 (R/ ) Debug Feature Register. <a href="#a85dd6fe77aab17e7ea89a52c59da6004">More...</a><br/></td></tr>
<tr class="separator:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af084e1b2dad004a88668efea1dfe7fa1"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1">ADR</a></td></tr>
<tr class="memdesc:af084e1b2dad004a88668efea1dfe7fa1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04C (R/ ) Auxiliary Feature Register. <a href="#af084e1b2dad004a88668efea1dfe7fa1">More...</a><br/></td></tr>
<tr class="separator:af084e1b2dad004a88668efea1dfe7fa1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa11887804412bda283cc85a83fdafa7c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c">MMFR</a> [4]</td></tr>
<tr class="memdesc:aa11887804412bda283cc85a83fdafa7c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 (R/ ) Memory Model Feature Register. <a href="#aa11887804412bda283cc85a83fdafa7c">More...</a><br/></td></tr>
<tr class="separator:aa11887804412bda283cc85a83fdafa7c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066">ISAR</a> [5]</td></tr>
<tr class="memdesc:ae0136a2d2d3c45f016b2c449e92b2066"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x060 (R/ ) Instruction Set Attributes Register. <a href="#ae0136a2d2d3c45f016b2c449e92b2066">More...</a><br/></td></tr>
<tr class="separator:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ac89a5d9901e3748d22a7090bfca2bee6">RESERVED0</a> [5]</td></tr>
<tr class="memdesc:ac89a5d9901e3748d22a7090bfca2bee6"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac89a5d9901e3748d22a7090bfca2bee6">More...</a><br/></td></tr>
<tr class="separator:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764">CPACR</a></td></tr>
<tr class="memdesc:ac6a860c1b8d8154a1f00d99d23b67764"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x088 (R/W) Coprocessor Access Control Register. <a href="#ac6a860c1b8d8154a1f00d99d23b67764">More...</a><br/></td></tr>
<tr class="separator:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memSeparator" colspan="2"> </td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structSCB__Type.js | JavaScript | apache-2.0 | 1,709 |
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<p>Structure type to access the System Control and ID Register not in the SCB.
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Data Fields</h2></td></tr>
<tr class="memitem:afe1d5fd2966d5062716613b05c8d0ae1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCnSCB__Type.html#afe1d5fd2966d5062716613b05c8d0ae1">RESERVED0</a> [1]</td></tr>
<tr class="memdesc:afe1d5fd2966d5062716613b05c8d0ae1"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#afe1d5fd2966d5062716613b05c8d0ae1">More...</a><br/></td></tr>
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<tr class="memdesc:a34ec1d771245eb9bd0e3ec9336949762"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/ ) Interrupt Controller Type Register. <a href="#a34ec1d771245eb9bd0e3ec9336949762">More...</a><br/></td></tr>
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<tr class="memdesc:a13af9b718dde7481f1c0344f00593c23"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Auxiliary Control Register. <a href="#a13af9b718dde7481f1c0344f00593c23">More...</a><br/></td></tr>
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<li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structSCnSCB__Type.html | HTML | apache-2.0 | 9,340 |
var structSCnSCB__Type =
[
[ "ACTLR", "structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23", null ],
[ "ICTR", "structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762", null ],
[ "RESERVED0", "structSCnSCB__Type.html#afe1d5fd2966d5062716613b05c8d0ae1", null ]
]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/structSCnSCB__Type.js | JavaScript | apache-2.0 | 283 |
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<p>Structure type to access the System Timer (SysTick).
</p>
<table class="memberdecls">
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Data Fields</h2></td></tr>
<tr class="memitem:a875e7afa5c4fd43997fb544a4ac6e37e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">CTRL</a></td></tr>
<tr class="memdesc:a875e7afa5c4fd43997fb544a4ac6e37e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) SysTick Control and Status Register. <a href="#a875e7afa5c4fd43997fb544a4ac6e37e">More...</a><br/></td></tr>
<tr class="separator:a875e7afa5c4fd43997fb544a4ac6e37e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4780a489256bb9f54d0ba8ed4de191cd"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#a4780a489256bb9f54d0ba8ed4de191cd">LOAD</a></td></tr>
<tr class="memdesc:a4780a489256bb9f54d0ba8ed4de191cd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) SysTick Reload Value Register. <a href="#a4780a489256bb9f54d0ba8ed4de191cd">More...</a><br/></td></tr>
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<tr class="memdesc:a9b5420d17e8e43104ddd4ae5a610af93"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) SysTick Current Value Register. <a href="#a9b5420d17e8e43104ddd4ae5a610af93">More...</a><br/></td></tr>
<tr class="separator:a9b5420d17e8e43104ddd4ae5a610af93"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afcadb0c6d35b21cdc0018658a13942de"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">CALIB</a></td></tr>
<tr class="memdesc:afcadb0c6d35b21cdc0018658a13942de"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/ ) SysTick Calibration Register. <a href="#afcadb0c6d35b21cdc0018658a13942de">More...</a><br/></td></tr>
<tr class="separator:afcadb0c6d35b21cdc0018658a13942de"><td class="memSeparator" colspan="2"> </td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<div class="title">TPI_Type Struct Reference</div> </div>
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<p>Structure type to access the Trace Port Interface Register (TPI).
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a7b72598e20066133e505bb781690dc22"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a7b72598e20066133e505bb781690dc22">SSPSR</a></td></tr>
<tr class="memdesc:a7b72598e20066133e505bb781690dc22"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) Supported Parallel Port Size Register. <a href="#a7b72598e20066133e505bb781690dc22">More...</a><br/></td></tr>
<tr class="separator:a7b72598e20066133e505bb781690dc22"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8826aa84e5806053395a742d38d59d0f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f">CSPSR</a></td></tr>
<tr class="memdesc:a8826aa84e5806053395a742d38d59d0f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Current Parallel Port Size Register. <a href="#a8826aa84e5806053395a742d38d59d0f">More...</a><br/></td></tr>
<tr class="separator:a8826aa84e5806053395a742d38d59d0f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af143c5e8fc9a3b2be2878e9c1f331aa9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">RESERVED0</a> [2]</td></tr>
<tr class="memdesc:af143c5e8fc9a3b2be2878e9c1f331aa9"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#af143c5e8fc9a3b2be2878e9c1f331aa9">More...</a><br/></td></tr>
<tr class="separator:af143c5e8fc9a3b2be2878e9c1f331aa9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">ACPR</a></td></tr>
<tr class="memdesc:a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. <a href="#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">More...</a><br/></td></tr>
<tr class="separator:a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac3956fe93987b725d89d3be32738da12"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ac3956fe93987b725d89d3be32738da12">RESERVED1</a> [55]</td></tr>
<tr class="memdesc:ac3956fe93987b725d89d3be32738da12"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac3956fe93987b725d89d3be32738da12">More...</a><br/></td></tr>
<tr class="separator:ac3956fe93987b725d89d3be32738da12"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a12f79d4e3ddc69893ba8bff890d04cc5"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a12f79d4e3ddc69893ba8bff890d04cc5">SPPR</a></td></tr>
<tr class="memdesc:a12f79d4e3ddc69893ba8bff890d04cc5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F0 (R/W) Selected Pin Protocol Register. <a href="#a12f79d4e3ddc69893ba8bff890d04cc5">More...</a><br/></td></tr>
<tr class="separator:a12f79d4e3ddc69893ba8bff890d04cc5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac7bbb92e6231b9b38ac483f7d161a096"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ac7bbb92e6231b9b38ac483f7d161a096">RESERVED2</a> [131]</td></tr>
<tr class="memdesc:ac7bbb92e6231b9b38ac483f7d161a096"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac7bbb92e6231b9b38ac483f7d161a096">More...</a><br/></td></tr>
<tr class="separator:ac7bbb92e6231b9b38ac483f7d161a096"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6c47a0b4c7ffc66093ef993d36bb441c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a6c47a0b4c7ffc66093ef993d36bb441c">FFSR</a></td></tr>
<tr class="memdesc:a6c47a0b4c7ffc66093ef993d36bb441c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x300 (R/ ) Formatter and Flush Status Register. <a href="#a6c47a0b4c7ffc66093ef993d36bb441c">More...</a><br/></td></tr>
<tr class="separator:a6c47a0b4c7ffc66093ef993d36bb441c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3f68b6e73561b4849ebf953a894df8d2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2">FFCR</a></td></tr>
<tr class="memdesc:a3f68b6e73561b4849ebf953a894df8d2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x304 (R/W) Formatter and Flush Control Register. <a href="#a3f68b6e73561b4849ebf953a894df8d2">More...</a><br/></td></tr>
<tr class="separator:a3f68b6e73561b4849ebf953a894df8d2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad6901bfd8a0089ca7e8a20475cf494a8"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ad6901bfd8a0089ca7e8a20475cf494a8">FSCR</a></td></tr>
<tr class="memdesc:ad6901bfd8a0089ca7e8a20475cf494a8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. <a href="#ad6901bfd8a0089ca7e8a20475cf494a8">More...</a><br/></td></tr>
<tr class="separator:ad6901bfd8a0089ca7e8a20475cf494a8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a31700c8cdd26e4c094db72af33d9f24c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a31700c8cdd26e4c094db72af33d9f24c">RESERVED3</a> [759]</td></tr>
<tr class="memdesc:a31700c8cdd26e4c094db72af33d9f24c"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a31700c8cdd26e4c094db72af33d9f24c">More...</a><br/></td></tr>
<tr class="separator:a31700c8cdd26e4c094db72af33d9f24c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4d4cd2357f72333a82a1313228287bbd"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd">TRIGGER</a></td></tr>
<tr class="memdesc:a4d4cd2357f72333a82a1313228287bbd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEE8 (R/ ) TRIGGER. <a href="#a4d4cd2357f72333a82a1313228287bbd">More...</a><br/></td></tr>
<tr class="separator:a4d4cd2357f72333a82a1313228287bbd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa4d7b5cf39dff9f53bf7f69bc287a814"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#aa4d7b5cf39dff9f53bf7f69bc287a814">FIFO0</a></td></tr>
<tr class="memdesc:aa4d7b5cf39dff9f53bf7f69bc287a814"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEEC (R/ ) Integration ETM Data. <a href="#aa4d7b5cf39dff9f53bf7f69bc287a814">More...</a><br/></td></tr>
<tr class="separator:aa4d7b5cf39dff9f53bf7f69bc287a814"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab358319b969d3fed0f89bbe33e9f1652"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652">ITATBCTR2</a></td></tr>
<tr class="memdesc:ab358319b969d3fed0f89bbe33e9f1652"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEF0 (R/ ) ITATBCTR2. <a href="#ab358319b969d3fed0f89bbe33e9f1652">More...</a><br/></td></tr>
<tr class="separator:ab358319b969d3fed0f89bbe33e9f1652"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a684071216fafee4e80be6aaa932cec46"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a684071216fafee4e80be6aaa932cec46">RESERVED4</a> [1]</td></tr>
<tr class="memdesc:a684071216fafee4e80be6aaa932cec46"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a684071216fafee4e80be6aaa932cec46">More...</a><br/></td></tr>
<tr class="separator:a684071216fafee4e80be6aaa932cec46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaa573b2e073e76e93c51ecec79c616d0"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0">ITATBCTR0</a></td></tr>
<tr class="memdesc:aaa573b2e073e76e93c51ecec79c616d0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEF8 (R/ ) ITATBCTR0. <a href="#aaa573b2e073e76e93c51ecec79c616d0">More...</a><br/></td></tr>
<tr class="separator:aaa573b2e073e76e93c51ecec79c616d0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a061372fcd72f1eea871e2d9c1be849bc"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a061372fcd72f1eea871e2d9c1be849bc">FIFO1</a></td></tr>
<tr class="memdesc:a061372fcd72f1eea871e2d9c1be849bc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEFC (R/ ) Integration ITM Data. <a href="#a061372fcd72f1eea871e2d9c1be849bc">More...</a><br/></td></tr>
<tr class="separator:a061372fcd72f1eea871e2d9c1be849bc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaa4c823c10f115f7517c82ef86a5a68d"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d">ITCTRL</a></td></tr>
<tr class="memdesc:aaa4c823c10f115f7517c82ef86a5a68d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF00 (R/W) Integration Mode Control. <a href="#aaa4c823c10f115f7517c82ef86a5a68d">More...</a><br/></td></tr>
<tr class="separator:aaa4c823c10f115f7517c82ef86a5a68d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3f80dd93f6bab6524603a7aa58de9a30"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a3f80dd93f6bab6524603a7aa58de9a30">RESERVED5</a> [39]</td></tr>
<tr class="memdesc:a3f80dd93f6bab6524603a7aa58de9a30"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a3f80dd93f6bab6524603a7aa58de9a30">More...</a><br/></td></tr>
<tr class="separator:a3f80dd93f6bab6524603a7aa58de9a30"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af8b7d15fa5252b733dd4b11fa1b5730a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">CLAIMSET</a></td></tr>
<tr class="memdesc:af8b7d15fa5252b733dd4b11fa1b5730a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFA0 (R/W) Claim tag set. <a href="#af8b7d15fa5252b733dd4b11fa1b5730a">More...</a><br/></td></tr>
<tr class="separator:af8b7d15fa5252b733dd4b11fa1b5730a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0e10e292cb019a832b03ddd055b2f6ac"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">CLAIMCLR</a></td></tr>
<tr class="memdesc:a0e10e292cb019a832b03ddd055b2f6ac"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFA4 (R/W) Claim tag clear. <a href="#a0e10e292cb019a832b03ddd055b2f6ac">More...</a><br/></td></tr>
<tr class="separator:a0e10e292cb019a832b03ddd055b2f6ac"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a476ca23fbc9480f1697fbec871130550"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a476ca23fbc9480f1697fbec871130550">RESERVED7</a> [8]</td></tr>
<tr class="memdesc:a476ca23fbc9480f1697fbec871130550"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a476ca23fbc9480f1697fbec871130550">More...</a><br/></td></tr>
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<tr class="memitem:abc0ecda8a5446bc754080276bad77514"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">DEVID</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<div class="title">System Configuration Files system_<device>.c and system_<device>.h </div> </div>
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<div class="textblock"><p>The <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> provides as a minimum the functions described under <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a>. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.</p>
<p>For devices with external memory BUS the system_<device>.c also configures the BUS system.</p>
<p>The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.</p>
<h1><a class="anchor" id="system_Device_sec"></a>
system_Device.c Template File</h1>
<p>The <a class="el" href="system_c_pg.html#system_Device_sec">system_Device.c Template File</a> for the Cortex-M3 is shown below.</p>
<pre class="fragment">/**************************************************************************//**
* @file system_<Device>.c
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for
* Device <Device>
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "<Device>.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define XTAL (12000000U) /* Oscillator frequency */
#define SYSTEM_CLOCK (5 * XTAL)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = SYSTEM_CLOCK;
}
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
SystemCoreClock = SYSTEM_CLOCK;
}
</pre><h1><a class="anchor" id="system_Device_h_sec"></a>
system_Device.h Template File</h1>
<p>The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> is shown below.</p>
<pre class="fragment">/**************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
* Device <Device>
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_<Device>_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_<Device>_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */
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<div class="textblock"><p>Arm supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of <a class="el" href="index.html#tested_tools_sec">Tested and Verified Toolchains</a> for compliance.</p>
<p>These CMSIS-Core device template files include the following:</p>
<ul>
<li>Register names of the Core Peripherals and names of the Core Exception Vectors.</li>
<li>Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4 and Cortex-M7)</li>
<li>Generic startup code and system configuration code.</li>
</ul>
<p>The detailed file structure of the CMSIS-Core device templates is shown in the following picture.</p>
<div class="image">
<img src="CMSIS_CORE_Files.png" alt="CMSIS_CORE_Files.png"/>
<div class="caption">
CMSIS-Core File Structure</div></div>
<h1><a class="anchor" id="CMSIS_Processor_files"></a>
CMSIS-Core Processor Files</h1>
<p>The CMSIS-Core processor files provided by Arm are in the directory .\CMSIS\Core\Include. These header files define all processor specific attributes do not need any modifications. The <b>core_<cpu>.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-M processor:</p>
<table class="doxtable">
<tr>
<th align="left">Header File </th><th align="left">Processor </th></tr>
<tr>
<td align="left">core_cm0.h </td><td align="left">for the Cortex-M0 processor </td></tr>
<tr>
<td align="left">core_cm0plus.h </td><td align="left">for the Cortex-M0+ processor </td></tr>
<tr>
<td align="left">core_cm3.h </td><td align="left">for the Cortex-M3 processor </td></tr>
<tr>
<td align="left">core_cm4.h </td><td align="left">for the Cortex-M4 processor </td></tr>
<tr>
<td align="left">core_cm7.h </td><td align="left">for the Cortex-M7 processor </td></tr>
<tr>
<td align="left">core_cm23.h </td><td align="left">for the Cortex-M23 processor </td></tr>
<tr>
<td align="left">core_cm33.h </td><td align="left">for the Cortex-M33 processor </td></tr>
<tr>
<td align="left">core_cm35p.h </td><td align="left">for the Cortex-M35P processor </td></tr>
<tr>
<td align="left">core_sc000.h </td><td align="left">for the SecurCore SC000 processor </td></tr>
<tr>
<td align="left">core_sc300.h </td><td align="left">for the SecurCore SC300 processor </td></tr>
<tr>
<td align="left">core_armv8mbl.h </td><td align="left">for the Armv8-M Baseline processor </td></tr>
<tr>
<td align="left">core_armv8mml.h </td><td align="left">for the Armv8-M Mainline processor </td></tr>
</table>
<h1><a class="anchor" id="device_examples"></a>
Device Examples</h1>
<p>The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\Device\ARM and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:</p>
<table class="doxtable">
<tr>
<th align="left">Family </th><th align="left">Device </th><th align="left">Description </th></tr>
<tr>
<td align="left">ARM Cortex-M0 </td><td align="left">ARMCM0 </td><td align="left">Cortex-M0 based device </td></tr>
<tr>
<td align="left">ARM Cortex-M0 plus </td><td align="left">ARMCM0P </td><td align="left">Cortex-M0+ based device </td></tr>
<tr>
<td align="left">ARM Cortex-M3 </td><td align="left">ARMCM3 </td><td align="left">Cortex-M3 based device </td></tr>
<tr>
<td align="left">ARM Cortex-M4 </td><td align="left">ARMCM4 </td><td align="left">Cortex-M4 based device without floating-point hardware </td></tr>
<tr>
<td align="left">ARM Cortex-M4 </td><td align="left">ARMCM4_FP </td><td align="left">Cortex-M4 based device with floating-point hardware </td></tr>
<tr>
<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7 </td><td align="left">Cortex-M4 based device without floating-point hardware </td></tr>
<tr>
<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7_FP </td><td align="left">Cortex-M7 based device with single precision floating-point unit (FPU) </td></tr>
<tr>
<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7_DP </td><td align="left">Cortex-M7 based device with double precision floating-point unit </td></tr>
<tr>
<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7 </td><td align="left">Cortex-M7 based device without floating-point hardware </td></tr>
<tr>
<td align="left">ARM Cortex-M23 </td><td align="left">ARMCM23 </td><td align="left">Cortex-M23 based device without TrustZone </td></tr>
<tr>
<td align="left">ARM Cortex-M23 </td><td align="left">ARMCM23_TZ </td><td align="left">Cortex-M23 based device with TrustZone </td></tr>
<tr>
<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33 </td><td align="left">Cortex-M33 based device without TrustZone, SIMD, FPU </td></tr>
<tr>
<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33_TZ </td><td align="left">Cortex-M33 based device with TrustZone, no SIMD, no FPU </td></tr>
<tr>
<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33_DSP_FP </td><td align="left">Cortex-M33 based device with SIMD, FPU, no TrustZone </td></tr>
<tr>
<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33_DSP_FP_TZ </td><td align="left">Cortex-M33 based device with TrustZone, SIMD, FPU </td></tr>
<tr>
<td align="left">ARM Cortex-M35P </td><td align="left">ARMCM35P </td><td align="left">Cortex-M35P based device without TrustZone, SIMD, FPU </td></tr>
<tr>
<td align="left">ARM Cortex-M35P </td><td align="left">ARMCM35P_TZ </td><td align="left">Cortex-M35P based device with TrustZone, no SIMD, no FPU </td></tr>
<tr>
<td align="left">ARM Cortex-M35P </td><td align="left">ARMCM35P_DSP_FP </td><td align="left">Cortex-M35P based device with SIMD, FPU, no TrustZone </td></tr>
<tr>
<td align="left">ARM Cortex-M35P </td><td align="left">ARMCM35P_DSP_FP_TZ </td><td align="left">Cortex-M35P based device with TrustZone, SIMD, FPU </td></tr>
<tr>
<td align="left">ARM SC000 </td><td align="left">ARM SC000 </td><td align="left">SC000 based device </td></tr>
<tr>
<td align="left">ARM SC300 </td><td align="left">ARM SC300 </td><td align="left">SC300 based device </td></tr>
<tr>
<td align="left">ARMv8-M Baseline </td><td align="left">ARMv8MBL </td><td align="left">Armv8-M Baseline based device with TrustZone </td></tr>
<tr>
<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML </td><td align="left">Armv8-M Mainline based device with TrustZone </td></tr>
<tr>
<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DP </td><td align="left">Armv8-M Mainline based device with TrustZone and double precision FPU </td></tr>
<tr>
<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_SP </td><td align="left">Armv8-M Mainline based device with TrustZone and single precision FPU </td></tr>
<tr>
<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DSP </td><td align="left">Armv8-M Mainline based device with TrustZone and SIMD </td></tr>
<tr>
<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DSP_DP </td><td align="left">Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU </td></tr>
<tr>
<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DSP_SP </td><td align="left">Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU </td></tr>
</table>
<h1><a class="anchor" id="template_files_sec"></a>
Template Files</h1>
<p>To simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add to these template files the following information:</p>
<ul>
<li><b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.</li>
<li><b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.</li>
<li><b>Interrupt vectors</b> in the startup file that are device specific.</li>
</ul>
<table class="cmtable">
<tr>
<th>Template File </th><th>Description </th></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s </td><td>Startup file template for Arm C/C++ Compiler. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s </td><td>Startup file template for GNU GCC Arm Embedded Compiler. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s </td><td>Startup file template for IAR C/C++ Compiler. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c </td><td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system). </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device\Include\Device.h </td><td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h </td><td>Generic system device configuration include file. </td></tr>
</table>
<p><b>Adapt Template Files to a Device</b></p>
<p>The following steps describe how to adopt the template files to a specific device or device family. Copy the complete all files in the template directory and replace:</p>
<ul>
<li>directory name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.</li>
<li>directory name 'Device' with the specific device name e.g.: LPC17xx.</li>
<li>in the file names 'Device' with the specific device name e.g.: LPC17xx.</li>
</ul>
<p>Each template file contains comments that start with <b>ToDo:</b> that describe a required modification. The template files contain place holders:</p>
<table class="cmtable">
<tr>
<th>Placeholder </th><th>Replaced with </th></tr>
<tr>
<td><Device> </td><td>the specific device name or device family name; i.e. LPC17xx. </td></tr>
<tr>
<td><DeviceInterrupt> </td><td>a specific interrupt name of the device; i.e. TIM1 for Timer 1. </td></tr>
<tr>
<td><DeviceAbbreviation> </td><td>short name or abbreviation of the device family; i.e. LPC. </td></tr>
<tr>
<td>Cortex-M# </td><td>the specific Cortex-M processor name; i.e. Cortex-M3. </td></tr>
</table>
<p>The device configuration of the template files is described in detail on the following pages:</p>
<ul>
<li><a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a></li>
<li><a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a> (deprecated)</li>
<li><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a></li>
<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a></li>
<li><a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> </li>
</ul>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/templates_pg.html | HTML | apache-2.0 | 17,058 |
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]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/templates_pg.js | JavaScript | apache-2.0 | 1,884 |
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<div class="title">APSR_Type Union Reference</div> </div>
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<p>Union type to access the Application Program Status Register (APSR).
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Data Fields</h2></td></tr>
<tr class="memitem:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a40a16164602a889d31a6bd92e9ccde92"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728">_reserved0</a>:27</td></tr>
<tr class="memdesc:a40a16164602a889d31a6bd92e9ccde92"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0..26 Reserved <a href="#a40a16164602a889d31a6bd92e9ccde92">More...</a><br/></td></tr>
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<tr class="memitem:aebf336ed17f711353ef40d16b9fcc305"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a22d10913489d24ab08bd83457daa88de">Q</a>:1</td></tr>
<tr class="memdesc:aebf336ed17f711353ef40d16b9fcc305"><td class="mdescLeft"> </td><td class="mdescRight">bit: 27 Saturation condition flag <a href="#aebf336ed17f711353ef40d16b9fcc305">More...</a><br/></td></tr>
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<tr class="memitem:a8003e190933fcfbff0b0878f48aa32b6"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a8004d224aacb78ca37774c35f9156e7e">V</a>:1</td></tr>
<tr class="memdesc:a8003e190933fcfbff0b0878f48aa32b6"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Overflow condition code flag <a href="#a8003e190933fcfbff0b0878f48aa32b6">More...</a><br/></td></tr>
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<tr class="memitem:a7c6e27604bd227c0c7685ae13ee33dc4"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6">C</a>:1</td></tr>
<tr class="memdesc:a7c6e27604bd227c0c7685ae13ee33dc4"><td class="mdescLeft"> </td><td class="mdescRight">bit: 29 Carry condition code flag <a href="#a7c6e27604bd227c0c7685ae13ee33dc4">More...</a><br/></td></tr>
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<tr class="memitem:a8030e626bbdfa4d8f50cf01ea2d1c0ea"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">Z</a>:1</td></tr>
<tr class="memdesc:a8030e626bbdfa4d8f50cf01ea2d1c0ea"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Zero condition code flag <a href="#a8030e626bbdfa4d8f50cf01ea2d1c0ea">More...</a><br/></td></tr>
<tr class="separator:a8030e626bbdfa4d8f50cf01ea2d1c0ea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a77dede9507ca1f554043f49035299f2e"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">N</a>:1</td></tr>
<tr class="memdesc:a77dede9507ca1f554043f49035299f2e"><td class="mdescLeft"> </td><td class="mdescRight">bit: 31 Negative condition code flag <a href="#a77dede9507ca1f554043f49035299f2e">More...</a><br/></td></tr>
<tr class="separator:a77dede9507ca1f554043f49035299f2e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionAPSR__Type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">b</a></td></tr>
<tr class="memdesc:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a7dbc79a057ded4b11ca5323fc2d5ab14">More...</a><br/></td></tr>
<tr class="separator:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae4c2ef8c9430d7b7bef5cbfbbaed3a94"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionAPSR__Type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">w</a></td></tr>
<tr class="memdesc:ae4c2ef8c9430d7b7bef5cbfbbaed3a94"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<p>Union type to access the Control Registers (CONTROL).
</p>
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Data Fields</h2></td></tr>
<tr class="memitem:adc6a38ab2980d0e9577b5a871da14eb9"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a666f4d16841194dd2ffb38cd9c1ff021"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605">nPRIV</a>:1</td></tr>
<tr class="memdesc:a666f4d16841194dd2ffb38cd9c1ff021"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Execution privilege in Thread mode <a href="#a666f4d16841194dd2ffb38cd9c1ff021">More...</a><br/></td></tr>
<tr class="separator:a666f4d16841194dd2ffb38cd9c1ff021"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae452742bb12b77c4cae20418495334f1"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#a8cc085fea1c50a8bd9adea63931ee8e2">SPSEL</a>:1</td></tr>
<tr class="memdesc:ae452742bb12b77c4cae20418495334f1"><td class="mdescLeft"> </td><td class="mdescRight">bit: 1 Stack to be used <a href="#ae452742bb12b77c4cae20418495334f1">More...</a><br/></td></tr>
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<tr class="memitem:a63fd27005fb7c3828f9f145a4fccf9a8"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#ac62cfff08e6f055e0101785bad7094cd">FPCA</a>:1</td></tr>
<tr class="memdesc:a63fd27005fb7c3828f9f145a4fccf9a8"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 FP extension active flag <a href="#a63fd27005fb7c3828f9f145a4fccf9a8">More...</a><br/></td></tr>
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<tr class="memitem:ada408fafd29cbe29e0c71ef479bd7564"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50">_reserved0</a>:29</td></tr>
<tr class="memdesc:ada408fafd29cbe29e0c71ef479bd7564"><td class="mdescLeft"> </td><td class="mdescRight">bit: 3..31 Reserved <a href="#ada408fafd29cbe29e0c71ef479bd7564">More...</a><br/></td></tr>
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<tr class="memitem:adc6a38ab2980d0e9577b5a871da14eb9"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCONTROL__Type.html#adc6a38ab2980d0e9577b5a871da14eb9">b</a></td></tr>
<tr class="memdesc:adc6a38ab2980d0e9577b5a871da14eb9"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#adc6a38ab2980d0e9577b5a871da14eb9">More...</a><br/></td></tr>
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<tr class="memitem:a6b642cca3d96da660b1198c133ca2a1f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f">w</a></td></tr>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/unionCONTROL__Type.html | HTML | apache-2.0 | 11,793 |
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<p>Union type to access the Interrupt Program Status Register (IPSR).
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Data Fields</h2></td></tr>
<tr class="memitem:add0d6497bd50c25569ea22b48a03ec50"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:afaf0827367274b557f0d28e0a2398229"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">ISR</a>:9</td></tr>
<tr class="memdesc:afaf0827367274b557f0d28e0a2398229"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 8 Exception number <a href="#afaf0827367274b557f0d28e0a2398229">More...</a><br/></td></tr>
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<tr class="memdesc:aa0449af1acf460572a66b57e2d07a931"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9..31 Reserved <a href="#aa0449af1acf460572a66b57e2d07a931">More...</a><br/></td></tr>
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<tr class="memitem:add0d6497bd50c25569ea22b48a03ec50"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIPSR__Type.html#add0d6497bd50c25569ea22b48a03ec50">b</a></td></tr>
<tr class="memdesc:add0d6497bd50c25569ea22b48a03ec50"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#add0d6497bd50c25569ea22b48a03ec50">More...</a><br/></td></tr>
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<tr class="memdesc:a4adca999d3a0bc1ae682d73ea7cfa879"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a4adca999d3a0bc1ae682d73ea7cfa879">More...</a><br/></td></tr>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/unionIPSR__Type.html | HTML | apache-2.0 | 10,088 |
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<p>Union type to access the Special-Purpose Program Status Registers (xPSR).
</p>
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<tr class="memitem:a3b1063bb5cdad67e037cba993b693b70"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a14aa41f658bf70c2d44435d24761a760"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a3e9120dcf1a829fc8d2302b4d0673970">ISR</a>:9</td></tr>
<tr class="memdesc:a14aa41f658bf70c2d44435d24761a760"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 8 Exception number <a href="#a14aa41f658bf70c2d44435d24761a760">More...</a><br/></td></tr>
<tr class="separator:a14aa41f658bf70c2d44435d24761a760"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7af0067da9805e481890c297bf4ed70f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5">_reserved0</a>:15</td></tr>
<tr class="memdesc:a7af0067da9805e481890c297bf4ed70f"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9..23 Reserved <a href="#a7af0067da9805e481890c297bf4ed70f">More...</a><br/></td></tr>
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<tr class="memdesc:a5224815d0f90fb7d26c7007bfb8e38d5"><td class="mdescLeft"> </td><td class="mdescRight">bit: 24 Thumb bit (read 0) <a href="#a5224815d0f90fb7d26c7007bfb8e38d5">More...</a><br/></td></tr>
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<tr class="memdesc:a6dd30396c78f8bc53d30ca13b058cbb2"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Overflow condition code flag <a href="#a6dd30396c78f8bc53d30ca13b058cbb2">More...</a><br/></td></tr>
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<tr class="memdesc:ae33d83822b56cd849b9fa9affddd59b2"><td class="mdescLeft"> </td><td class="mdescRight">bit: 29 Carry condition code flag <a href="#ae33d83822b56cd849b9fa9affddd59b2">More...</a><br/></td></tr>
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<tr class="memdesc:ac1f7475b01a46aef06d9f53d3a2a69ef"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Zero condition code flag <a href="#ac1f7475b01a46aef06d9f53d3a2a69ef">More...</a><br/></td></tr>
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<tr class="memdesc:a38ba57343e56c653939fd792c19af047"><td class="mdescLeft"> </td><td class="mdescRight">bit: 31 Negative condition code flag <a href="#a38ba57343e56c653939fd792c19af047">More...</a><br/></td></tr>
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<tr class="memitem:a3b1063bb5cdad67e037cba993b693b70"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionxPSR__Type.html#a3b1063bb5cdad67e037cba993b693b70">b</a></td></tr>
<tr class="memdesc:a3b1063bb5cdad67e037cba993b693b70"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a3b1063bb5cdad67e037cba993b693b70">More...</a><br/></td></tr>
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<tr class="memitem:a1a47176768f45f79076c4f5b1b534bc2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionxPSR__Type.html#a1a47176768f45f79076c4f5b1b534bc2">w</a></td></tr>
<tr class="memdesc:a1a47176768f45f79076c4f5b1b534bc2"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a1a47176768f45f79076c4f5b1b534bc2">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<div class="title">Using CMSIS with generic Arm Processors </div> </div>
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<div class="textblock"><p>Arm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors. These files can be used when standard Arm processors should be used in a project. The table below lists the folder and device names of the Arm processors.</p>
<table class="cmtable">
<tr>
<th>Folder </th><th>Processor </th><th>Description </th></tr>
<tr>
<td>".\Device\ARM\ARMCM0" </td><td>Cortex-M0 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM0.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMCM0plus" </td><td>Cortex-M0+ </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM0plus.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMCM3" </td><td>Cortex-M3 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM3.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMCM4" </td><td>Cortex-M4 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM4.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMCM7" </td><td>Cortex-M7 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M7 processor. The device name is ARMCM7 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM7.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMSC000" </td><td>SecurCore SC000 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMSC000.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMSC300" </td><td>SecurCore SC300 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMSC300.h>. </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd>CMSIS-Pack provides the <b>#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><em>device</em>.h</b> file of a project. This allows you to generate generic software components that adjust to the device settings.</dd></dl>
<h1><a class="anchor" id="using_ARM_Lib_sec"></a>
Create generic Libraries with CMSIS</h1>
<p>The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The <a href="../../DSP/html/index.html"><b>CMSIS-DSP</b> </a> Libraries are an example for such a generic library.</p>
<p>To build a generic Library set the define <b>__CMSIS_GENERIC</b> and include the relevant <b>core_<cpu>.h</b> CMSIS CPU & Core Access header file for the processor. The define <b>__CMSIS_GENERIC</b> disables device-dependent features such as the <b>SysTick</b> timer and the <b>Interrupt System</b>. Refer to <a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> for a list of the available <b>core_<cpu>.h</b> header files.</p>
<p><b>Example:</b> </p>
<p>The following code section shows the usage of the <b>core_<cpu>.h</b> header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To select the processor, the source code uses the define <b>CORTEX_M7</b>, <b>CORTEX_M4</b>, <b>CORTEX_M3</b>, <b>CORTEX_M0</b>, or <b>CORTEX_M0PLUS</b>. One of these defines needs to be provided on the compiler command line. By using this header file, the source code can access the functions for <a class="el" href="group__Core__Register__gr.html">Core Register Access</a>, <a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a>, <a class="el" href="group__intrinsic__SIMD__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a>, and <a class="el" href="group__ITM__Debug__gr.html">Debug Access</a>.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CMSIS_GENERIC </span><span class="comment">/* disable NVIC and Systick functions */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#if defined (CORTEX_M7)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm7.h"</span></div>
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M4)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm4.h"</span></div>
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M3)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm3.h"</span></div>
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M0)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm0.h"</span></div>
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M0PLUS)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm0plus.h"</span></div>
<div class="line"><span class="preprocessor">#else</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #error "Processor not specified or unsupported."</span></div>
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<div class="textblock"><p>A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#include <stm32f10x.h></span> <span class="comment">// File name depends on device used</span></div>
<div class="line"> </div>
<div class="line">uint32_t <span class="keyword">volatile</span> msTicks; <span class="comment">// Counter for millisecond Interval</span></div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> SysTick_Handler (<span class="keywordtype">void</span>) { <span class="comment">// SysTick Interrupt Handler</span></div>
<div class="line"> msTicks++; <span class="comment">// Increment Counter</span></div>
<div class="line">}</div>
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<div class="line"><span class="keywordtype">void</span> WaitForTick (<span class="keywordtype">void</span>) {</div>
<div class="line"> uint32_t curTicks;</div>
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<div class="line"> curTicks = msTicks; <span class="comment">// Save Current SysTick Value</span></div>
<div class="line"> <span class="keywordflow">while</span> (msTicks == curTicks) { <span class="comment">// Wait for next SysTick Interrupt</span></div>
<div class="line"> <a class="code" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (); <span class="comment">// Power-Down until next Event/Interrupt</span></div>
<div class="line"> }</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> TIM1_UP_IRQHandler (<span class="keywordtype">void</span>) { <span class="comment">// Timer Interrupt Handler</span></div>
<div class="line"> ; <span class="comment">// Add user code here</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> timer1_init(<span class="keywordtype">int</span> frequency) { <span class="comment">// Set up Timer (device specific)</span></div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> (TIM1_UP_IRQn, 1); <span class="comment">// Set Timer priority</span></div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> (TIM1_UP_IRQn); <span class="comment">// Enable Timer Interrupt</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> Device_Initialization (<span class="keywordtype">void</span>) { <span class="comment">// Configure & Initialize MCU</span></div>
<div class="line"> <span class="keywordflow">if</span> (<a class="code" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> (<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000)) { <span class="comment">// SysTick 1mSec</span></div>
<div class="line"> : <span class="comment">// Handle Error </span></div>
<div class="line"> }</div>
<div class="line"> timer1_init (); <span class="comment">// setup device-specific timer</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">// The processor clock is initialized by CMSIS startup + system file</span></div>
<div class="line"><span class="keywordtype">void</span> main (<span class="keywordtype">void</span>) { <span class="comment">// user application starts here</span></div>
<div class="line"> Device_Initialization (); <span class="comment">// Configure & Initialize MCU</span></div>
<div class="line"> <span class="keywordflow">while</span> (1) { <span class="comment">// Endless Loop (the Super-Loop)</span></div>
<div class="line"> <a class="code" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> (); <span class="comment">// Disable all interrupts</span></div>
<div class="line"> Get_InputValues (); <span class="comment">// Read Values</span></div>
<div class="line"> <a class="code" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a> (); <span class="comment">// Enable all interrupts </span></div>
<div class="line"> Calculation_Response (); <span class="comment">// Calculate Results</span></div>
<div class="line"> Output_Response (); <span class="comment">// Output Results</span></div>
<div class="line"> WaitForTick (); <span class="comment">// Synchronize to SysTick Timer</span></div>
<div class="line"> }</div>
<div class="line">}</div>
</div><!-- fragment --><p>CMSIS-Pack provides the <b>#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><em>device</em>.h</b> file of a project. This allows you to generate generic software components that use the device selected in a project.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#include "RTE_Components.h"</span> <span class="comment">// include information about project configuration</span></div>
<div class="line"><span class="preprocessor">#include CMSIS_device_header // include <device>.h file</span></div>
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<div class="title">Using TrustZone for Armv8-M </div> </div>
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<div class="textblock"><p>The optional Armv8-M Security Extension is similar to Arm TrustZone technology used in Cortex-A processors, but is optimized for ultra-low power embedded applications. TrustZone for Armv8-M enables of multiple software security domains that restrict access to secure memory and I/O only for trusted software.</p>
<p>TrustZone for Armv8-M:</p>
<ul>
<li>preserves low interrupt latencies for both Secure and Non-secure domains.</li>
<li>does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.</li>
<li>introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.</li>
</ul>
<p><b>Notations</b> </p>
<p>This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:</p>
<ul>
<li>prefix <b>TZ</b> or <b>__TZ</b> indicates a function that is available only in Armv8-M TrustZone enabled devices.</li>
<li>postfix <b>_NS</b> indicates a hardware resource that belongs to the Non-secure state.</li>
<li>postfix <b>_S</b> indicates a hardware resource that belongs to the Secure state.</li>
</ul>
<h1><a class="anchor" id="useCase_TrustZone"></a>
Simplified Use Case with TrustZone</h1>
<p>An Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted software that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection, or multi-party embedded software deployments.</p>
<p>The figure <b>Simplified Use Case</b> shows and embedded application that is split into a <b>User Project</b> (executed in Non-secure state) and a <b>Firmware Project</b> (executed in Secure state).</p>
<ul>
<li><b>System Start:</b> after power on or reset, an Armv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.</li>
<li><b>User Application:</b> control can be transferred to <b>Non-secure state</b> to execute user code. This code can only call functions in the <b>secure state</b> that are marked for execution with the <b>SG</b> (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the <b>Secure state</b> triggers a security exception.</li>
<li><b>Firmware callbacks:</b> code running in the <b>Secure state</b> can execute code in the <b>Non-secure state</b> using call-back function pointers. For example, a communication stack (protected firmware) could use an I/O driver that is configured in user space.</li>
</ul>
<p><a class="anchor" id="SimpleUseCase"></a></p>
<div class="image">
<img src="SimpleUseCase.png" alt="SimpleUseCase.png"/>
<div class="caption">
Simplified Use Case</div></div>
<p> Program execution in the <b>Secure state</b> is further protected by TrustZone hardware from software failures. For example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution in <b>Non-secure state</b> in case of timing violations. Also function pointer callbacks from <b>Secure state</b> to <b>Non-secure state</b> protected by a special CPU instruction and the address bit 0 which prevents anciently executing code in <b>Non-secure state</b>.</p>
<h2><a class="anchor" id="Example_TrustZone"></a>
Program Examples</h2>
<p>This CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:</p>
<table class="doxtable">
<tr>
<th align="left">Example </th><th align="left">Description </th></tr>
<tr>
<td align="left">TrustZone for Armv8-M No RTOS </td><td align="left">bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case). </td></tr>
<tr>
<td align="left">TrustZone for Armv8-M RTOS </td><td align="left">secure/non-secure RTOS example with thread context management </td></tr>
<tr>
<td align="left">TrustZone for Armv8-M RTOS Security Tests </td><td align="left">secure/non-secure RTOS example with security test cases and system recovery </td></tr>
</table>
<p>Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>Armv8MBL Secure/Non-Secure example</b> that is available in the Software Pack <b>Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b> (Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).</p>
<h1><a class="anchor" id="Model_TrustZone"></a>
Programmers Model with TrustZone</h1>
<p>The figure <a href="#MemoryMap_S"><b>Secure Memory Map</b></a> shows the memory view for the <b>Secure state</b>. In the Secure state all memory and peripherals can be accessed. The <b>System Control and Debug</b> area provides access to secure peripherals and non-secure peripherals that are mirrored at a memory alias.</p>
<p>The secure peripherals are only accessible during program execution in <b>Secure state</b>. The Secure Attribute Unit (SAU) configures the non-secure memory, peripheral, and interrupt access. Also available are a secure MPU (memory protection unit), secure SCB (system control block), and secure SysTick timer.</p>
<p>The system supports two separate interrupt vector tables for secure and non-secure code execution. This interrupt assignment is controlled during <b>Secure state</b> code execution via the NVIC (nested vector interrupt controller).</p>
<p><a class="anchor" id="MemoryMap_S"></a></p>
<div class="image">
<img src="MemoryMap_S.png" alt="MemoryMap_S.png"/>
<div class="caption">
Secure Memory Map</div></div>
<p> The figure <a href="#MemoryMap_NS"><b>Non-Secure Memory Map</b></a> shows the memory view for the Non-secure state. This memory view is identical to the traditional Cortex-M memory map. Access to any secure memory or peripheral space triggers the secure exception that executes a handler in <b>Secure state</b>.</p>
<p>The <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> defines the initial setup of the <a href="#MemoryMap_NS"><b>Non-Secure Memory Map</b></a> during system start in the Secure state (refer to functions <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> and <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a>).</p>
<p><a class="anchor" id="MemoryMap_NS"></a></p>
<div class="image">
<img src="MemoryMap_NS.png" alt="MemoryMap_NS.png"/>
<div class="caption">
Non-Secure Memory Map</div></div>
<p>The figure <b>Registers</b> shows the register view of the Armv8-M system with TrustZone. As the general purpose registers are can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter and return values.</p>
<p>The register R13 is the stack pointer alias, and the actual stack pointer (PSP_NS, MSP_NS, PSP_S, MSP_S) accessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or thread=normal code execution).</p>
<p>In Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S) that traps stack overflows with the <b>UsageFault</b> exception (register UFSR bit STKOF=1).</p>
<p>An Armv8-M system with TrustZone has an independent <b>CONTROL</b> register for each state (Secure or Non-secure). The interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure), however the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that secure interrupts have always higher priority.</p>
<p>The core registers of the current state (Secure or Non-secure) are accessed using the standard <a class="el" href="group__Core__Register__gr.html">Core Register Access</a> functions. In Secure state all non-secure registers are accessible using the <a class="el" href="group__coreregister__trustzone__functions.html">Core Register Access Functions</a> related to TrustZone for Armv8-M.</p>
<div class="image">
<img src="Registers.png" alt="Registers.png"/>
<div class="caption">
Registers</div></div>
<h1><a class="anchor" id="CMSIS_Files_TrustZone"></a>
CMSIS Files for TrustZone</h1>
<p>The CMSIS-Core files are extended by the <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> which defines the initial system configuration and during <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> in Secure state.</p>
<div class="image">
<img src="CMSIS_TZ_files.png" alt="CMSIS_TZ_files.png"/>
<div class="caption">
CMSIS with extensions for TrustZone</div></div>
<dl class="section note"><dt>Note</dt><dd>Refer to <a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> for a general description of the CMSIS-Core (Cortex-M) files.</dd></dl>
<h2><a class="anchor" id="RTOS_TrustZone"></a>
RTOS Thread Context Management</h2>
<p>To provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions. An <em>non-secure application</em> which uses an RTOS and calls <em>secure</em> library modules requires the management of the <em>secure</em> stack space. Since <em>secure state</em> registers cannot be accessed by the RTOS that runs in <em>non-secure state</em> secure functions implement the thread context switch.</p>
<p>As the <em>non-secure state</em> and <em>secure state</em> parts of an application are separated, the API for managing the <em>secure</em> stack space should be standardized. Otherwise the <em>secure</em> library modules would force the <em>non-secure state</em> application to use a matching RTOS implementation.</p>
<div class="image">
<img src="TZ_context.png" alt="TZ_context.png"/>
<div class="caption">
RTOS Thread Context Management for Armv8-M TrustZone</div></div>
<p> To allocate the context memory for threads, an RTOS kernel that runs in <em>non-secure state</em> calls the interface functions defined by the header file <b>TZ_context.h</b>. The <b>TZ_context</b> functions itself are part of the <em>secure state</em> application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory management system with additional features such as access control to <em>secure state</em> memory regions using an MPU.</p>
<p>The API functions of <b>TZ_context</b> are described in the chapter <a href="Modules.html"><b>Reference</b> </a> under <a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M/v8.1-M</a> - <a class="el" href="group__context__trustzone__functions.html">RTOS Context Management</a>.</p>
<p>Refer to <a class="el" href="using_TrustZone_pg.html#Example_TrustZone">Program Examples</a> for RTOS examples that provide a template implementation for <b>TZ_context.c</b>. </p>
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<div class="title">Using Interrupt Vector Remap </div> </div>
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<div class="textblock"><p>Most Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows a typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#include "ARMCM3.h"</span> <span class="comment">// Device header</span></div>
<div class="line"> </div>
<div class="line"><span class="comment">/* externals from startup_ARMCM3.s */</span></div>
<div class="line"><span class="keyword">extern</span> uint32_t __Vectors[]; <span class="comment">/* vector table ROM */</span></div>
<div class="line"> </div>
<div class="line"><span class="preprocessor">#define VECTORTABLE_SIZE (256) </span><span class="comment">/* size Cortex-M3 vector table */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define VECTORTABLE_ALIGNMENT (0x100ul) </span><span class="comment">/* 16 Cortex + 32 ARMCM3 = 48 words */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> <span class="comment">/* next power of 2 = 256 */</span></div>
<div class="line"> </div>
<div class="line"><span class="comment">/* new vector table in RAM */</span></div>
<div class="line">uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));</div>
<div class="line"> </div>
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment"> SysTick_Handler</span></div>
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
<div class="line"><span class="keyword">volatile</span> uint32_t msTicks = 0; <span class="comment">/* counts 1ms timeTicks */</span></div>
<div class="line"><span class="keywordtype">void</span> SysTick_Handler(<span class="keywordtype">void</span>) {</div>
<div class="line"> msTicks++; <span class="comment">/* increment counter */</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment"> SysTick_Handler (RAM)</span></div>
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
<div class="line"><span class="keyword">volatile</span> uint32_t msTicks_RAM = 0; <span class="comment">/* counts 1ms timeTicks */</span></div>
<div class="line"><span class="keywordtype">void</span> SysTick_Handler_RAM(<span class="keywordtype">void</span>) {</div>
<div class="line"> msTicks_RAM++; <span class="comment">/* increment counter */</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment"> MAIN function</span></div>
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div>
<div class="line"> uint32_t i;</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">for</span> (i = 0; i < VECTORTABLE_SIZE; i++) {</div>
<div class="line"> vectorTable_RAM[i] = __Vectors[i]; <span class="comment">/* copy vector table to RAM */</span></div>
<div class="line"> }</div>
<div class="line"> <span class="comment">/* replace SysTick Handler */</span></div>
<div class="line"> vectorTable_RAM[<a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> + 16] = (uint32_t)SysTick_Handler_RAM;</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* relocate vector table */</span> </div>
<div class="line"> <a class="code" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a>();</div>
<div class="line"> SCB->VTOR = (uint32_t)&vectorTable_RAM;</div>
<div class="line"> <a class="code" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>();</div>
<div class="line"> <a class="code" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>();</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a>(); <span class="comment">/* Get Core Clock Frequency */</span></div>
<div class="line"> <a class="code" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a>(<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000ul); <span class="comment">/* Setup SysTick Timer for 1 msec */</span></div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">while</span>(1);</div>
<div class="line">}</div>
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<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a> gives access to processor core and all peripherals.</li>
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<dl class="section note"><dt>Note</dt><dd>The files <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> (or <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a>) and <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.</dd></dl>
<p>The <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> (or <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a>) is executed after reset and calls <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the <b>main</b> function in the user code. In addition the <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> (or <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a>) contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.</p>
<p>The <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> performs the setup for the processor clock. The variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> indicates the CPU clock speed. <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a> describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.</p>
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is the central include file that the application programmer is using in the C source code. It provides the following features:</p>
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<li><a class="el" href="group__peripheral__gr.html">Peripheral Access</a> provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.</li>
<li><a class="el" href="group__NVIC__gr.html">Interrupts and Exceptions (NVIC)</a> can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided.</li>
<li><a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a> allow to access special instructions, for example for activating sleep mode or the NOP instruction.</li>
<li><a class="el" href="group__intrinsic__SIMD__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a> provide access to the DSP-oriented instructions.</li>
<li><a class="el" href="group__SysTick__gr.html">Systick Timer (SYSTICK)</a> function to configure and start a periodic timer interrupt.</li>
<li><a class="el" href="group__ITM__Debug__gr.html">Debug Access</a> are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication.</li>
</ul>
<p>CMSIS-Pack provides the <b>#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to this <b><em>device</em>.h</b> file.</p>
<div class="image">
<img src="CMSIS_CORE_Files_user.png" alt="CMSIS_CORE_Files_user.png"/>
<div class="caption">
CMSIS-Core (Cortex-M) User Files</div></div>
<p> The CMSIS-Core (Cortex-M) system files are device specific. In addition, the deprecated <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a> is also compiler vendor specific. The versions provided by CMSIS are only generic templates. The adopted versions for a concrete device are typically provided by the device vendor through the according device familiy pack (DFP).</p>
<p>For example, the following files are provided by the STM32F10x device family pack:</p>
<table class="cmtable">
<tr>
<th>File </th><th>Description </th></tr>
<tr>
<td>".\Device\Source\ARM\startup_stm32f10x_cl.s" </td><td><a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a> for the STM32F10x Connectivity Line device variants. </td></tr>
<tr>
<td>".\Device\Source\system_stmf10x.c" </td><td><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> for the STM32F10x device families. </td></tr>
<tr>
<td>".\Device\Include\stm32f10x.h" </td><td><a class="el" href="device_h_pg.html">Device Header File <device.h></a> for the STM32F10x device families. </td></tr>
<tr>
<td>".\Device\Include\system_stm32f10x.h" </td><td><a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> for the STM32F10x device families. </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd>The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> provide by Arm.</dd></dl>
<p>Thereafter, the functions described under <a href="Modules.html"><b>Reference</b> </a> can be used in the application.</p>
<p><b>Examples</b> </p>
<ul>
<li><a class="el" href="using_CMSIS.html">Basic CMSIS Example</a> is a simple example that shows the usage of the CMSIS layer.</li>
<li><a class="el" href="using_VTOR_pg.html">Using Interrupt Vector Remap</a> shows how to remap the interrupt vector table.</li>
<li><a class="el" href="using_ARM_pg.html">Using CMSIS with generic Arm Processors</a> explains how to use CMSIS-Core (Cortex-M) for Arm processors. </li>
</ul>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/using_pg.html | HTML | apache-2.0 | 12,792 |
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 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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Macros</h2></td></tr>
<tr class="memitem:a292d4e6da76cde7f721581917f45a756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a292d4e6da76cde7f721581917f45a756">VE_A9_MP_FLASH_BASE0</a>   (0x00000000UL)</td></tr>
<tr class="separator:a292d4e6da76cde7f721581917f45a756"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a51e7ad7d4be59e4a47f4199c08a52f35"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a51e7ad7d4be59e4a47f4199c08a52f35">VE_A9_MP_FLASH_BASE1</a>   (0x0C000000UL)</td></tr>
<tr class="separator:a51e7ad7d4be59e4a47f4199c08a52f35"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af0e04a3bf444617de5e6f1a4132bb33a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#af0e04a3bf444617de5e6f1a4132bb33a">VE_A9_MP_SRAM_BASE</a>   (0x14000000UL)</td></tr>
<tr class="separator:af0e04a3bf444617de5e6f1a4132bb33a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1f0eb04274d447fa1261fc34313bbd2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a1f0eb04274d447fa1261fc34313bbd2f">VE_A9_MP_PERIPH_BASE_CS2</a>   (0x18000000UL)</td></tr>
<tr class="separator:a1f0eb04274d447fa1261fc34313bbd2f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adab8c737342be2fc972b2bc39bdf134d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#adab8c737342be2fc972b2bc39bdf134d">VE_A9_MP_VRAM_BASE</a>   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)</td></tr>
<tr class="separator:adab8c737342be2fc972b2bc39bdf134d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a338e6b0eddbed74bd8dfcf8be8df004c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a338e6b0eddbed74bd8dfcf8be8df004c">VE_A9_MP_ETHERNET_BASE</a>   (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)</td></tr>
<tr class="separator:a338e6b0eddbed74bd8dfcf8be8df004c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8ce6f3127699b175000437b9fd22224c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a8ce6f3127699b175000437b9fd22224c">VE_A9_MP_USB_BASE</a>   (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)</td></tr>
<tr class="separator:a8ce6f3127699b175000437b9fd22224c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a15fccfe28c34be132e4b26fecf459d59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a15fccfe28c34be132e4b26fecf459d59">VE_A9_MP_PERIPH_BASE_CS3</a>   (0x1C000000UL)</td></tr>
<tr class="separator:a15fccfe28c34be132e4b26fecf459d59"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a63a986e5aa2a284f9509b5e91df630dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a63a986e5aa2a284f9509b5e91df630dd">VE_A9_MP_DAP_BASE</a>   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a63a986e5aa2a284f9509b5e91df630dd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6be1b1510ebbf938f10c195c2aae50ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a6be1b1510ebbf938f10c195c2aae50ed">VE_A9_MP_SYSTEM_REG_BASE</a>   (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a6be1b1510ebbf938f10c195c2aae50ed"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae59ea495994a48af31e09af0001c65c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#ae59ea495994a48af31e09af0001c65c6">VE_A9_MP_SERIAL_BASE</a>   (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:ae59ea495994a48af31e09af0001c65c6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a06ba050a1192b25ec6fbb79d6108d2ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a06ba050a1192b25ec6fbb79d6108d2ed">VE_A9_MP_AACI_BASE</a>   (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a06ba050a1192b25ec6fbb79d6108d2ed"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4c93715226810aa05b1475cae477a9d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a4c93715226810aa05b1475cae477a9d1">VE_A9_MP_MMCI_BASE</a>   (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a4c93715226810aa05b1475cae477a9d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abb9205ff2f6f411938d3443f0cc65b4d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#abb9205ff2f6f411938d3443f0cc65b4d">VE_A9_MP_KMI0_BASE</a>   (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:abb9205ff2f6f411938d3443f0cc65b4d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a74740d1654250a51685800d03e3dc1a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a74740d1654250a51685800d03e3dc1a0">VE_A9_MP_UART_BASE</a>   (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a74740d1654250a51685800d03e3dc1a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4d2806a167111f24a4e26764c667db46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a4d2806a167111f24a4e26764c667db46">VE_A9_MP_WDT_BASE</a>   (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a4d2806a167111f24a4e26764c667db46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3dd8c7208925d87eda25e9059e7b5bca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a3dd8c7208925d87eda25e9059e7b5bca">VE_A9_MP_TIMER_BASE</a>   (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a3dd8c7208925d87eda25e9059e7b5bca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abab45916f8216aee2f417e6b041a1a74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#abab45916f8216aee2f417e6b041a1a74">VE_A9_MP_DVI_BASE</a>   (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:abab45916f8216aee2f417e6b041a1a74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a56ccb39193acdd89d79c794bc3d46dd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a56ccb39193acdd89d79c794bc3d46dd8">VE_A9_MP_RTC_BASE</a>   (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a56ccb39193acdd89d79c794bc3d46dd8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a21aa9ad15aa6749c03cadf2dd895aae3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a21aa9ad15aa6749c03cadf2dd895aae3">VE_A9_MP_UART4_BASE</a>   (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a21aa9ad15aa6749c03cadf2dd895aae3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a628c63b1e4c2656100a00d883ab5e824"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a628c63b1e4c2656100a00d883ab5e824">VE_A9_MP_CLCD_BASE</a>   (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)</td></tr>
<tr class="separator:a628c63b1e4c2656100a00d883ab5e824"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adb063e35f3d63c35ce856561df8cedb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#adb063e35f3d63c35ce856561df8cedb4">VE_A9_MP_PL310_BASE</a>   (0x1E00A000UL)</td></tr>
<tr class="separator:adb063e35f3d63c35ce856561df8cedb4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8d664adb95364c864de72494a7603ee4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a8d664adb95364c864de72494a7603ee4">VE_A9_MP_PRIVATE_PERIPH_BASE</a>   (0x2C000000UL)</td></tr>
<tr class="separator:a8d664adb95364c864de72494a7603ee4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abf58e5b4c2424101181e4e90b013565f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#abf58e5b4c2424101181e4e90b013565f">VE_A9_MP_GIC_DISTRIBUTOR_BASE</a>   (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE)</td></tr>
<tr class="separator:abf58e5b4c2424101181e4e90b013565f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2281d069db0154b71d2307b151151624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a2281d069db0154b71d2307b151151624">VE_A9_MP_GIC_INTERFACE_BASE</a>   (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE)</td></tr>
<tr class="separator:a2281d069db0154b71d2307b151151624"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a02dee9c2055176f0f8b39f84188662dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a02dee9c2055176f0f8b39f84188662dc">VE_A9_MP_PRIVATE_TIMER</a>   (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE)</td></tr>
<tr class="separator:a02dee9c2055176f0f8b39f84188662dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a649334fdbe9f99fa6c9e5fb9771deeab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a649334fdbe9f99fa6c9e5fb9771deeab">VE_A9_MP_SSRAM_BASE</a>   (0x2E000000UL)</td></tr>
<tr class="separator:a649334fdbe9f99fa6c9e5fb9771deeab"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a49c91ca86e9eab3aaa8c8f3fbd2b9855"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a49c91ca86e9eab3aaa8c8f3fbd2b9855">VE_A9_MP_DRAM_BASE</a>   (0x80000000UL)</td></tr>
<tr class="separator:a49c91ca86e9eab3aaa8c8f3fbd2b9855"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5cc9c031f86d3fcb7efcbe2fce4cd552"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a5cc9c031f86d3fcb7efcbe2fce4cd552">GIC_DISTRIBUTOR_BASE</a>   <a class="el" href="ARMCA9_8h.html#abf58e5b4c2424101181e4e90b013565f">VE_A9_MP_GIC_DISTRIBUTOR_BASE</a></td></tr>
<tr class="separator:a5cc9c031f86d3fcb7efcbe2fce4cd552"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adc560f42c09a0a3ce5dcc4aa898209ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#adc560f42c09a0a3ce5dcc4aa898209ca">GIC_INTERFACE_BASE</a>   <a class="el" href="ARMCA9_8h.html#a2281d069db0154b71d2307b151151624">VE_A9_MP_GIC_INTERFACE_BASE</a></td></tr>
<tr class="separator:adc560f42c09a0a3ce5dcc4aa898209ca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a251f8c6600afee0dddf950c7a41d4723"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a251f8c6600afee0dddf950c7a41d4723">TIMER_BASE</a>   <a class="el" href="ARMCA9_8h.html#a02dee9c2055176f0f8b39f84188662dc">VE_A9_MP_PRIVATE_TIMER</a></td></tr>
<tr class="separator:a251f8c6600afee0dddf950c7a41d4723"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5ce89d9feb78e20a4034f025eec392b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a5ce89d9feb78e20a4034f025eec392b4">L2C_310_BASE</a>   <a class="el" href="ARMCA9_8h.html#adb063e35f3d63c35ce856561df8cedb4">VE_A9_MP_PL310_BASE</a></td></tr>
<tr class="separator:a5ce89d9feb78e20a4034f025eec392b4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8ebf37d3e9141ccae33bb6b1edf539bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__ctrl.html#ga8ebf37d3e9141ccae33bb6b1edf539bd">__CA_REV</a>   0x0000U</td></tr>
<tr class="memdesc:ga8ebf37d3e9141ccae33bb6b1edf539bd"><td class="mdescLeft"> </td><td class="mdescRight">Contains the core revision for a Cortex-A class device. <a href="group__version__ctrl.html#ga8ebf37d3e9141ccae33bb6b1edf539bd">More...</a><br/></td></tr>
<tr class="separator:ga8ebf37d3e9141ccae33bb6b1edf539bd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga74d176c89aefe783e9ce0712c4360537"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__ctrl.html#ga74d176c89aefe783e9ce0712c4360537">__CORTEX_A</a>   9U</td></tr>
<tr class="memdesc:ga74d176c89aefe783e9ce0712c4360537"><td class="mdescLeft"> </td><td class="mdescRight">Contains the core family for a Cortex-A class device. <a href="group__version__ctrl.html#ga74d176c89aefe783e9ce0712c4360537">More...</a><br/></td></tr>
<tr class="separator:ga74d176c89aefe783e9ce0712c4360537"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac1ba8a48ca926bddc88be9bfd7d42641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#ac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a>   1U /* FPU present */</td></tr>
<tr class="separator:ac1ba8a48ca926bddc88be9bfd7d42641"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6690a7e24ea0ec4b36a8fb077d01a820"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a6690a7e24ea0ec4b36a8fb077d01a820">__GIC_PRESENT</a>   1U /* GIC present */</td></tr>
<tr class="separator:a6690a7e24ea0ec4b36a8fb077d01a820"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0e57ca9f1bc10c2de05d383d2c76267a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a0e57ca9f1bc10c2de05d383d2c76267a">__TIM_PRESENT</a>   1U /* TIM present */</td></tr>
<tr class="separator:a0e57ca9f1bc10c2de05d383d2c76267a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a102b9f59f0fe8f9bb492d42803ebf586"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a102b9f59f0fe8f9bb492d42803ebf586">__L2C_PRESENT</a>   0U /* L2C present */</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:a7e1129cd8a196f4284d41db3e82ad5c8"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> { <br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a> = 0,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b">SGI1_IRQn</a> = 1,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07">SGI2_IRQn</a> = 2,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a310ac1f78af36e0e3b9f6b4f15bd9b68">SGI3_IRQn</a> = 3,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ac5c03a99c620ff116bafa4cf03dd9a07">SGI4_IRQn</a> = 4,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8adb8d49885011a278ed3c671904da7e6e">SGI5_IRQn</a> = 5,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a5f9b1989d051c60ad69147e644853a44">SGI6_IRQn</a> = 6,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8aa1bcd760176e11cdece4386818022631">SGI7_IRQn</a> = 7,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8aabbb7ca9433c474bfeade468e8c66455">SGI8_IRQn</a> = 8,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8afa5f21d9fd3df5817a0f871b72bde681">SGI9_IRQn</a> = 9,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a12993bed484c7a70e6281b102d0e27e9">SGI10_IRQn</a> = 10,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a7826ded51cd379774bb076819ff93cdb">SGI11_IRQn</a> = 11,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a3425bbf0a6da4d0398e63b48a1345d37">SGI12_IRQn</a> = 12,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ace710506c7be1b3b7f9d4a1db2f75391">SGI13_IRQn</a> = 13,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ae57c57a817378102db7bc66351c912f1">SGI14_IRQn</a> = 14,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321">SGI15_IRQn</a> = 15,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a69c74fffb53f9a8739613443943a94c3">GlobalTimer_IRQn</a> = 27,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249">PrivTimer_IRQn</a> = 29,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8aeb45b2fc32150bf94ecf305ee223f28f">PrivWatchdog_IRQn</a> = 30,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a3f04766f3177f0152623a86e39ccef06">Watchdog_IRQn</a> = 32,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8adffcd012ea2c7bf76124965d8506df72">Timer0_IRQn</a> = 34,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ad0611a4c93162877ed3eb622f49e14a3">Timer1_IRQn</a> = 35,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8abdd513b1533957e93fe0d7f26024d28e">RTClock_IRQn</a> = 36,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ae9122b85b58f7c24033a8515615a7b74">UART0_IRQn</a> = 37,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a9650ab92e46bc16f333d4c63ad0459b4">UART1_IRQn</a> = 38,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ab051fac6b15b88454713bb36d96e5dd5">UART2_IRQn</a> = 39,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a11614a227a56dc01859bf803013e6358">UART3_IRQn</a> = 40,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8aaa5c1873412fc0ef1f7e324208671ca2">MCI0_IRQn</a> = 41,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8af803de749ceabdd07a62e90d2989a67e">MCI1_IRQn</a> = 42,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a4c72e4cbe9ce6bae3d29332139dad44a">AACI_IRQn</a> = 43,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a9f6790481c8a659df023aadfe5443cc5">Keyboard_IRQn</a> = 44,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8affc38a882d7c20bf505a160bc5eb3851">Mouse_IRQn</a> = 45,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ae7da3d1e8aae439524761f44ddfe8e0c">CLCD_IRQn</a> = 46,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a58692bf577b8a17ec79fc8472d56ff05">Ethernet_IRQn</a> = 47,
<br/>
  <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ac54c304a64b192755ac352bc0a6dc1ac">VFS2_IRQn</a> = 73
<br/>
}</td></tr>
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</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define __FPU_PRESENT   1U /* FPU present */</td>
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</table>
</div><div class="memdoc">
</div>
</div>
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<td class="memname">#define __GIC_PRESENT   1U /* GIC present */</td>
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</div><div class="memdoc">
</div>
</div>
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<td class="memname">#define __L2C_PRESENT   0U /* L2C present */</td>
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</div><div class="memdoc">
</div>
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<td class="memname">#define __TIM_PRESENT   1U /* TIM present */</td>
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</div>
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<td class="memname">#define GIC_DISTRIBUTOR_BASE   <a class="el" href="ARMCA9_8h.html#abf58e5b4c2424101181e4e90b013565f">VE_A9_MP_GIC_DISTRIBUTOR_BASE</a></td>
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</table>
</div><div class="memdoc">
</div>
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<td class="memname">#define GIC_INTERFACE_BASE   <a class="el" href="ARMCA9_8h.html#a2281d069db0154b71d2307b151151624">VE_A9_MP_GIC_INTERFACE_BASE</a></td>
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</table>
</div><div class="memdoc">
</div>
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<td class="memname">#define L2C_310_BASE   <a class="el" href="ARMCA9_8h.html#adb063e35f3d63c35ce856561df8cedb4">VE_A9_MP_PL310_BASE</a></td>
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</table>
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<td class="memname">#define TIMER_BASE   <a class="el" href="ARMCA9_8h.html#a02dee9c2055176f0f8b39f84188662dc">VE_A9_MP_PRIVATE_TIMER</a></td>
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</table>
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<td class="memname">#define VE_A9_MP_AACI_BASE   (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
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</table>
</div><div class="memdoc">
<p>(AACI ) Base Address </p>
</div>
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<td class="memname">#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
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</table>
</div><div class="memdoc">
<p>(CLCD ) Base Address </p>
</div>
</div>
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<td class="memname">#define VE_A9_MP_DAP_BASE   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
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</table>
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<p>(LOCAL DAP ) Base Address </p>
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<td class="memname">#define VE_A9_MP_DRAM_BASE   (0x80000000UL)</td>
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<p>(DRAM ) Base Address </p>
</div>
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<td class="memname">#define VE_A9_MP_DVI_BASE   (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
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</table>
</div><div class="memdoc">
<p>(DVI ) Base Address </p>
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</div>
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<td class="memname">#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)</td>
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</table>
</div><div class="memdoc">
<p>(ETHERNET ) Base Address </p>
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<td class="memname">#define VE_A9_MP_FLASH_BASE0   (0x00000000UL)</td>
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<p>(FLASH0 ) Base Address </p>
</div>
</div>
<a class="anchor" id="a51e7ad7d4be59e4a47f4199c08a52f35"></a>
<div class="memitem">
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<td class="memname">#define VE_A9_MP_FLASH_BASE1   (0x0C000000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(FLASH1 ) Base Address </p>
</div>
</div>
<a class="anchor" id="abf58e5b4c2424101181e4e90b013565f"></a>
<div class="memitem">
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<td class="memname">#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(GIC DIST ) Base Address </p>
</div>
</div>
<a class="anchor" id="a2281d069db0154b71d2307b151151624"></a>
<div class="memitem">
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<td class="memname">#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(GIC CPU IF ) Base Address </p>
</div>
</div>
<a class="anchor" id="abb9205ff2f6f411938d3443f0cc65b4d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define VE_A9_MP_KMI0_BASE   (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(KMI0 ) Base Address </p>
</div>
</div>
<a class="anchor" id="a4c93715226810aa05b1475cae477a9d1"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_MMCI_BASE   (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(MMCI ) Base Address </p>
</div>
</div>
<a class="anchor" id="a1f0eb04274d447fa1261fc34313bbd2f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define VE_A9_MP_PERIPH_BASE_CS2   (0x18000000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(Peripheral ) Base Address </p>
</div>
</div>
<a class="anchor" id="a15fccfe28c34be132e4b26fecf459d59"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_PERIPH_BASE_CS3   (0x1C000000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(Peripheral ) Base Address </p>
</div>
</div>
<a class="anchor" id="adb063e35f3d63c35ce856561df8cedb4"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_PL310_BASE   (0x1E00A000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(L2C-310 ) Base Address </p>
</div>
</div>
<a class="anchor" id="a8d664adb95364c864de72494a7603ee4"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_PRIVATE_PERIPH_BASE   (0x2C000000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(Peripheral ) Base Address </p>
</div>
</div>
<a class="anchor" id="a02dee9c2055176f0f8b39f84188662dc"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(PTIM ) Base Address </p>
</div>
</div>
<a class="anchor" id="a56ccb39193acdd89d79c794bc3d46dd8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_RTC_BASE   (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(RTC ) Base Address </p>
</div>
</div>
<a class="anchor" id="ae59ea495994a48af31e09af0001c65c6"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(SERIAL ) Base Address </p>
</div>
</div>
<a class="anchor" id="af0e04a3bf444617de5e6f1a4132bb33a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_SRAM_BASE   (0x14000000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(SRAM ) Base Address </p>
</div>
</div>
<a class="anchor" id="a649334fdbe9f99fa6c9e5fb9771deeab"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_SSRAM_BASE   (0x2E000000UL)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(System SRAM) Base Address </p>
</div>
</div>
<a class="anchor" id="a6be1b1510ebbf938f10c195c2aae50ed"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(SYSTEM REG ) Base Address </p>
</div>
</div>
<a class="anchor" id="a3dd8c7208925d87eda25e9059e7b5bca"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_TIMER_BASE   (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(TIMER ) Base Address </p>
</div>
</div>
<a class="anchor" id="a21aa9ad15aa6749c03cadf2dd895aae3"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_UART4_BASE   (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(UART4 ) Base Address </p>
</div>
</div>
<a class="anchor" id="a74740d1654250a51685800d03e3dc1a0"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_UART_BASE   (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(UART ) Base Address </p>
</div>
</div>
<a class="anchor" id="a8ce6f3127699b175000437b9fd22224c"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(USB ) Base Address </p>
</div>
</div>
<a class="anchor" id="adab8c737342be2fc972b2bc39bdf134d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_VRAM_BASE   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(VRAM ) Base Address </p>
</div>
</div>
<a class="anchor" id="a4d2806a167111f24a4e26764c667db46"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define VE_A9_MP_WDT_BASE   (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>(WDT ) Base Address </p>
</div>
</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">enum <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></td>
</tr>
</table>
</div><div class="memdoc">
<p>Device specific Interrupt IDs </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e"></a>SGI0_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 0 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b"></a>SGI1_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 1 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07"></a>SGI2_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 2 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a310ac1f78af36e0e3b9f6b4f15bd9b68"></a>SGI3_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 3 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ac5c03a99c620ff116bafa4cf03dd9a07"></a>SGI4_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 4 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8adb8d49885011a278ed3c671904da7e6e"></a>SGI5_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 5 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a5f9b1989d051c60ad69147e644853a44"></a>SGI6_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 6 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8aa1bcd760176e11cdece4386818022631"></a>SGI7_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 7 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8aabbb7ca9433c474bfeade468e8c66455"></a>SGI8_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 8 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8afa5f21d9fd3df5817a0f871b72bde681"></a>SGI9_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 9 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a12993bed484c7a70e6281b102d0e27e9"></a>SGI10_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 10 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a7826ded51cd379774bb076819ff93cdb"></a>SGI11_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 11 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a3425bbf0a6da4d0398e63b48a1345d37"></a>SGI12_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 12 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ace710506c7be1b3b7f9d4a1db2f75391"></a>SGI13_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 13 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ae57c57a817378102db7bc66351c912f1"></a>SGI14_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 14 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321"></a>SGI15_IRQn</em> </td><td class="fielddoc">
<p>Software Generated Interrupt 15 </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a69c74fffb53f9a8739613443943a94c3"></a>GlobalTimer_IRQn</em> </td><td class="fielddoc">
<p>Global Timer Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249"></a>PrivTimer_IRQn</em> </td><td class="fielddoc">
<p>Private Timer Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8aeb45b2fc32150bf94ecf305ee223f28f"></a>PrivWatchdog_IRQn</em> </td><td class="fielddoc">
<p>Private Watchdog Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a3f04766f3177f0152623a86e39ccef06"></a>Watchdog_IRQn</em> </td><td class="fielddoc">
<p>SP805 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8adffcd012ea2c7bf76124965d8506df72"></a>Timer0_IRQn</em> </td><td class="fielddoc">
<p>SP804 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ad0611a4c93162877ed3eb622f49e14a3"></a>Timer1_IRQn</em> </td><td class="fielddoc">
<p>SP804 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8abdd513b1533957e93fe0d7f26024d28e"></a>RTClock_IRQn</em> </td><td class="fielddoc">
<p>PL031 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ae9122b85b58f7c24033a8515615a7b74"></a>UART0_IRQn</em> </td><td class="fielddoc">
<p>PL011 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a9650ab92e46bc16f333d4c63ad0459b4"></a>UART1_IRQn</em> </td><td class="fielddoc">
<p>PL011 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ab051fac6b15b88454713bb36d96e5dd5"></a>UART2_IRQn</em> </td><td class="fielddoc">
<p>PL011 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a11614a227a56dc01859bf803013e6358"></a>UART3_IRQn</em> </td><td class="fielddoc">
<p>PL011 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8aaa5c1873412fc0ef1f7e324208671ca2"></a>MCI0_IRQn</em> </td><td class="fielddoc">
<p>PL180 Interrupt (1st) </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8af803de749ceabdd07a62e90d2989a67e"></a>MCI1_IRQn</em> </td><td class="fielddoc">
<p>PL180 Interrupt (2nd) </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a4c72e4cbe9ce6bae3d29332139dad44a"></a>AACI_IRQn</em> </td><td class="fielddoc">
<p>PL041 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a9f6790481c8a659df023aadfe5443cc5"></a>Keyboard_IRQn</em> </td><td class="fielddoc">
<p>PL050 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8affc38a882d7c20bf505a160bc5eb3851"></a>Mouse_IRQn</em> </td><td class="fielddoc">
<p>PL050 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ae7da3d1e8aae439524761f44ddfe8e0c"></a>CLCD_IRQn</em> </td><td class="fielddoc">
<p>PL111 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8a58692bf577b8a17ec79fc8472d56ff05"></a>Ethernet_IRQn</em> </td><td class="fielddoc">
<p>SMSC_91C111 Interrupt </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a7e1129cd8a196f4284d41db3e82ad5c8ac54c304a64b192755ac352bc0a6dc1ac"></a>VFS2_IRQn</em> </td><td class="fielddoc">
<p>VFS2 Interrupt </p>
</td></tr>
</table>
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<tr class="memitem:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td></tr>
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<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionACTLR__Type.html" target="_self">ACTLR_Type</a></td><td class="desc">Bit field declaration for ACTLR layout </td></tr>
<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCNTP__CTL__Type.html" target="_self">CNTP_CTL_Type</a></td><td class="desc">Physical Timer Control register </td></tr>
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCPACR__Type.html" target="_self">CPACR_Type</a></td><td class="desc">Bit field declaration for CPACR layout </td></tr>
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCPSR__Type.html" target="_self">CPSR_Type</a></td><td class="desc">Bit field declaration for CPSR layout </td></tr>
<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionDFSR__Type.html" target="_self">DFSR_Type</a></td><td class="desc">Bit field declaration for DFSR layout </td></tr>
<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structFPSCR__Type.html" target="_self">FPSCR_Type</a></td><td class="desc">Bit field declaration for FPSCR layout </td></tr>
<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structGICDistributor__Type.html" target="_self">GICDistributor_Type</a></td><td class="desc">Structure type to access the Generic Interrupt Controller Distributor (GICD) </td></tr>
<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structGICInterface__Type.html" target="_self">GICInterface_Type</a></td><td class="desc">Structure type to access the Generic Interrupt Controller Interface (GICC) </td></tr>
<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionIFSR__Type.html" target="_self">IFSR_Type</a></td><td class="desc">Bit field declaration for IFSR layout </td></tr>
<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionISR__Type.html" target="_self">ISR_Type</a></td><td class="desc">Bit field declaration for ISR layout </td></tr>
<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structL2C__310__TypeDef.html" target="_self">L2C_310_TypeDef</a></td><td class="desc">Union type to access the L2C_310 Cache Controller </td></tr>
<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structmmu__region__attributes__Type.html" target="_self">mmu_region_attributes_Type</a></td><td class="desc"></td></tr>
<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionSCTLR__Type.html" target="_self">SCTLR_Type</a></td><td class="desc">Bit field declaration for SCTLR layout </td></tr>
<tr id="row_13_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTimer__Type.html" target="_self">Timer_Type</a></td><td class="desc">Structure type to access the Private Timer </td></tr>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/annotated.html | HTML | apache-2.0 | 10,904 |
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/cmsis.css | CSS | apache-2.0 | 20,795 |
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<title>CMSIS-Core (Cortex-A): cmsis_armcc.h File Reference</title>
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<a href="#define-members">Macros</a> |
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<div class="title">cmsis_armcc.h File Reference</div> </div>
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<p>CMSIS compiler specific macros, functions, instructions.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gaee91bdfb2b6986731af09835bc9c6e74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gaee91bdfb2b6986731af09835bc9c6e74">__ARM_ARCH_7A__</a>   1</td></tr>
<tr class="memdesc:gaee91bdfb2b6986731af09835bc9c6e74"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 when generating code for Armv7-A (Cortex-A7) <a href="group__comp__cntrl__gr.html#gaee91bdfb2b6986731af09835bc9c6e74">More...</a><br/></td></tr>
<tr class="separator:gaee91bdfb2b6986731af09835bc9c6e74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1378040bcf22428955c6e3ce9c2053cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a>   __asm</td></tr>
<tr class="memdesc:ga1378040bcf22428955c6e3ce9c2053cd"><td class="mdescLeft"> </td><td class="mdescRight">Pass information from the compiler to the assembler. <a href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">More...</a><br/></td></tr>
<tr class="separator:ga1378040bcf22428955c6e3ce9c2053cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gade2d8d7118f8ff49547f60aa0c3382bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb">__INLINE</a>   __inline</td></tr>
<tr class="memdesc:gade2d8d7118f8ff49547f60aa0c3382bb"><td class="mdescLeft"> </td><td class="mdescRight">Recommend that function should be inlined by the compiler. <a href="group__comp__cntrl__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb">More...</a><br/></td></tr>
<tr class="separator:gade2d8d7118f8ff49547f60aa0c3382bb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2ecb43ce8e7aa73d32f50afa67b42c76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a2ecb43ce8e7aa73d32f50afa67b42c76">__FORCEINLINE</a>   __forceinline</td></tr>
<tr class="separator:a2ecb43ce8e7aa73d32f50afa67b42c76"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba87361bfad2ae52cfe2f40c1a1dbf9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a>   static __inline</td></tr>
<tr class="memdesc:gaba87361bfad2ae52cfe2f40c1a1dbf9c"><td class="mdescLeft"> </td><td class="mdescRight">Define a static function should be inlined by the compiler. <a href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">More...</a><br/></td></tr>
<tr class="separator:gaba87361bfad2ae52cfe2f40c1a1dbf9c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab904513442afdf77d4f8c74f23cbb040"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a>   static __forceinline</td></tr>
<tr class="separator:ab904513442afdf77d4f8c74f23cbb040"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga153a4a31b276a9758959580538720a51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#ga153a4a31b276a9758959580538720a51">__NO_RETURN</a>   __declspec(noreturn)</td></tr>
<tr class="memdesc:ga153a4a31b276a9758959580538720a51"><td class="mdescLeft"> </td><td class="mdescRight">Inform the compiler that a function does not return. <a href="group__comp__cntrl__gr.html#ga153a4a31b276a9758959580538720a51">More...</a><br/></td></tr>
<tr class="separator:ga153a4a31b276a9758959580538720a51"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acdc36c1b3d3e16c17a73889b7d06d0d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#acdc36c1b3d3e16c17a73889b7d06d0d2">CMSIS_DEPRECATED</a>   __attribute__((deprecated))</td></tr>
<tr class="separator:acdc36c1b3d3e16c17a73889b7d06d0d2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3e40e4c553fc11588f7a4c2a19e789e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a>   __attribute__((used))</td></tr>
<tr class="memdesc:ga3e40e4c553fc11588f7a4c2a19e789e0"><td class="mdescLeft"> </td><td class="mdescRight">Inform that a variable shall be retained in executable image. <a href="group__comp__cntrl__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">More...</a><br/></td></tr>
<tr class="separator:ga3e40e4c553fc11588f7a4c2a19e789e0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac607bf387b29162be6a9b77fc7999539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gac607bf387b29162be6a9b77fc7999539">__WEAK</a>   __attribute__((weak))</td></tr>
<tr class="memdesc:gac607bf387b29162be6a9b77fc7999539"><td class="mdescLeft"> </td><td class="mdescRight">Export a function or variable weakly to allow overwrites. <a href="group__comp__cntrl__gr.html#gac607bf387b29162be6a9b77fc7999539">More...</a><br/></td></tr>
<tr class="separator:gac607bf387b29162be6a9b77fc7999539"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabe8996d3d985ee1529475443cc635bf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>   __attribute__((packed))</td></tr>
<tr class="memdesc:gabe8996d3d985ee1529475443cc635bf1"><td class="mdescLeft"> </td><td class="mdescRight">Request smallest possible alignment. <a href="group__comp__cntrl__gr.html#gabe8996d3d985ee1529475443cc635bf1">More...</a><br/></td></tr>
<tr class="separator:gabe8996d3d985ee1529475443cc635bf1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4dbb70fab85207c27b581ecb6532b314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a>   __packed struct</td></tr>
<tr class="separator:a4dbb70fab85207c27b581ecb6532b314"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5103fb373cae9837cc4a384be55dc87f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a5103fb373cae9837cc4a384be55dc87f">__UNALIGNED_UINT16_WRITE</a>(addr, val)   ((*((__packed uint16_t *)(addr))) = (val))</td></tr>
<tr class="separator:a5103fb373cae9837cc4a384be55dc87f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab71b66e5ce403158d3dee62a59f9175f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#ab71b66e5ce403158d3dee62a59f9175f">__UNALIGNED_UINT16_READ</a>(addr)   (*((const __packed uint16_t *)(addr)))</td></tr>
<tr class="separator:ab71b66e5ce403158d3dee62a59f9175f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a203f593d140ed88b81bc189edc861110"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a203f593d140ed88b81bc189edc861110">__UNALIGNED_UINT32_WRITE</a>(addr, val)   ((*((__packed uint32_t *)(addr))) = (val))</td></tr>
<tr class="separator:a203f593d140ed88b81bc189edc861110"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3b931f0b051b8c1a6377a3dcc7559b5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a3b931f0b051b8c1a6377a3dcc7559b5e">__UNALIGNED_UINT32_READ</a>(addr)   (*((const __packed uint32_t *)(addr)))</td></tr>
<tr class="separator:a3b931f0b051b8c1a6377a3dcc7559b5e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa65ef8f7a5e8b7a6ea6c1d48b4c78e55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gaa65ef8f7a5e8b7a6ea6c1d48b4c78e55">__ALIGNED</a>(x)   __attribute__((aligned(x)))</td></tr>
<tr class="memdesc:gaa65ef8f7a5e8b7a6ea6c1d48b4c78e55"><td class="mdescLeft"> </td><td class="mdescRight">Minimum alignment for a variable. <a href="group__comp__cntrl__gr.html#gaa65ef8f7a5e8b7a6ea6c1d48b4c78e55">More...</a><br/></td></tr>
<tr class="separator:gaa65ef8f7a5e8b7a6ea6c1d48b4c78e55"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6516fb12ab0dd45c734f8cef7d921af6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a6516fb12ab0dd45c734f8cef7d921af6">__COMPILER_BARRIER</a>()   __memory_changed()</td></tr>
<tr class="separator:a6516fb12ab0dd45c734f8cef7d921af6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd585ddc865fb9b7f2493af1eee1a572"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a>   __nop</td></tr>
<tr class="memdesc:gabd585ddc865fb9b7f2493af1eee1a572"><td class="mdescLeft"> </td><td class="mdescRight">No Operation. <a href="group__CMSIS__Core__InstructionInterface.html#gabd585ddc865fb9b7f2493af1eee1a572">More...</a><br/></td></tr>
<tr class="separator:gabd585ddc865fb9b7f2493af1eee1a572"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad23bf2b78a9a4524157c9de0d30b7448"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gad23bf2b78a9a4524157c9de0d30b7448">__WFI</a>   __wfi</td></tr>
<tr class="memdesc:gad23bf2b78a9a4524157c9de0d30b7448"><td class="mdescLeft"> </td><td class="mdescRight">Wait For Interrupt. <a href="group__CMSIS__Core__InstructionInterface.html#gad23bf2b78a9a4524157c9de0d30b7448">More...</a><br/></td></tr>
<tr class="separator:gad23bf2b78a9a4524157c9de0d30b7448"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gaac6cc7dd4325d9cb40d3290fa5244b3d">__WFE</a>   __wfe</td></tr>
<tr class="memdesc:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="mdescLeft"> </td><td class="mdescRight">Wait For Event. <a href="group__CMSIS__Core__InstructionInterface.html#gaac6cc7dd4325d9cb40d3290fa5244b3d">More...</a><br/></td></tr>
<tr class="separator:gaac6cc7dd4325d9cb40d3290fa5244b3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaab4f296d0022b4b10dc0976eb22052f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gaab4f296d0022b4b10dc0976eb22052f9">__SEV</a>   __sev</td></tr>
<tr class="memdesc:gaab4f296d0022b4b10dc0976eb22052f9"><td class="mdescLeft"> </td><td class="mdescRight">Send Event. <a href="group__CMSIS__Core__InstructionInterface.html#gaab4f296d0022b4b10dc0976eb22052f9">More...</a><br/></td></tr>
<tr class="separator:gaab4f296d0022b4b10dc0976eb22052f9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaad233022e850a009fc6f7602be1182f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gaad233022e850a009fc6f7602be1182f6">__ISB</a>()</td></tr>
<tr class="memdesc:gaad233022e850a009fc6f7602be1182f6"><td class="mdescLeft"> </td><td class="mdescRight">Instruction Synchronization Barrier. <a href="group__CMSIS__Core__InstructionInterface.html#gaad233022e850a009fc6f7602be1182f6">More...</a><br/></td></tr>
<tr class="separator:gaad233022e850a009fc6f7602be1182f6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga067d257a2b34565410acefb5afef2203"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a>()</td></tr>
<tr class="memdesc:ga067d257a2b34565410acefb5afef2203"><td class="mdescLeft"> </td><td class="mdescRight">Data Synchronization Barrier. <a href="group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203">More...</a><br/></td></tr>
<tr class="separator:ga067d257a2b34565410acefb5afef2203"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga671101179b5943990785f36f8c1e2269"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga671101179b5943990785f36f8c1e2269">__DMB</a>()</td></tr>
<tr class="memdesc:ga671101179b5943990785f36f8c1e2269"><td class="mdescLeft"> </td><td class="mdescRight">Data Memory Barrier. <a href="group__CMSIS__Core__InstructionInterface.html#ga671101179b5943990785f36f8c1e2269">More...</a><br/></td></tr>
<tr class="separator:ga671101179b5943990785f36f8c1e2269"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a14f54807872c0f5e05604c4924abfdae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a14f54807872c0f5e05604c4924abfdae">__REV</a>   __rev</td></tr>
<tr class="memdesc:a14f54807872c0f5e05604c4924abfdae"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (32 bit) <a href="#a14f54807872c0f5e05604c4924abfdae">More...</a><br/></td></tr>
<tr class="separator:a14f54807872c0f5e05604c4924abfdae"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a95b9bd281ddeda378b85afdb8f2ced86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a95b9bd281ddeda378b85afdb8f2ced86">__ROR</a>   __ror</td></tr>
<tr class="memdesc:a95b9bd281ddeda378b85afdb8f2ced86"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <a href="#a95b9bd281ddeda378b85afdb8f2ced86">More...</a><br/></td></tr>
<tr class="separator:a95b9bd281ddeda378b85afdb8f2ced86"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga15ea6bd3c507d3e81c3b3a1258e46397">__BKPT</a>(value)   __breakpoint(value)</td></tr>
<tr class="memdesc:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="mdescLeft"> </td><td class="mdescRight">Breakpoint. <a href="group__CMSIS__Core__InstructionInterface.html#ga15ea6bd3c507d3e81c3b3a1258e46397">More...</a><br/></td></tr>
<tr class="separator:ga15ea6bd3c507d3e81c3b3a1258e46397"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab83768933a612816fad669db5488366f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#ab83768933a612816fad669db5488366f">__RBIT</a>   __rbit</td></tr>
<tr class="memdesc:ab83768933a612816fad669db5488366f"><td class="mdescLeft"> </td><td class="mdescRight">Reverse bit order of value. <a href="#ab83768933a612816fad669db5488366f">More...</a><br/></td></tr>
<tr class="separator:ab83768933a612816fad669db5488366f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5d5bb1527e042be4a9fa5a33f65cc248"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a5d5bb1527e042be4a9fa5a33f65cc248">__CLZ</a>   __clz</td></tr>
<tr class="memdesc:a5d5bb1527e042be4a9fa5a33f65cc248"><td class="mdescLeft"> </td><td class="mdescRight">Count leading zeros. <a href="#a5d5bb1527e042be4a9fa5a33f65cc248">More...</a><br/></td></tr>
<tr class="separator:a5d5bb1527e042be4a9fa5a33f65cc248"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8876672c1f185d3253fea6b06bdba771"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a8876672c1f185d3253fea6b06bdba771">__LDREXB</a>(ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")</td></tr>
<tr class="memdesc:a8876672c1f185d3253fea6b06bdba771"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (8 bit) <a href="#a8876672c1f185d3253fea6b06bdba771">More...</a><br/></td></tr>
<tr class="separator:a8876672c1f185d3253fea6b06bdba771"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa7f6f01cf534bc8daccc421dc823fc6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#aa7f6f01cf534bc8daccc421dc823fc6f">__LDREXH</a>(ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")</td></tr>
<tr class="memdesc:aa7f6f01cf534bc8daccc421dc823fc6f"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (16 bit) <a href="#aa7f6f01cf534bc8daccc421dc823fc6f">More...</a><br/></td></tr>
<tr class="separator:aa7f6f01cf534bc8daccc421dc823fc6f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa872ae25197f1dddc52835fdfed9a881"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#aa872ae25197f1dddc52835fdfed9a881">__LDREXW</a>(ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")</td></tr>
<tr class="memdesc:aa872ae25197f1dddc52835fdfed9a881"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (32 bit) <a href="#aa872ae25197f1dddc52835fdfed9a881">More...</a><br/></td></tr>
<tr class="separator:aa872ae25197f1dddc52835fdfed9a881"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a503ba30a93e83963de38e5171fbbabce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a503ba30a93e83963de38e5171fbbabce">__STREXB</a>(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")</td></tr>
<tr class="memdesc:a503ba30a93e83963de38e5171fbbabce"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (8 bit) <a href="#a503ba30a93e83963de38e5171fbbabce">More...</a><br/></td></tr>
<tr class="separator:a503ba30a93e83963de38e5171fbbabce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a63d19c6c7852ada9a1c1aab80e6294b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a63d19c6c7852ada9a1c1aab80e6294b1">__STREXH</a>(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")</td></tr>
<tr class="memdesc:a63d19c6c7852ada9a1c1aab80e6294b1"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (16 bit) <a href="#a63d19c6c7852ada9a1c1aab80e6294b1">More...</a><br/></td></tr>
<tr class="separator:a63d19c6c7852ada9a1c1aab80e6294b1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0c3704e33e90ba0491cee56cfb553090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a0c3704e33e90ba0491cee56cfb553090">__STREXW</a>(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")</td></tr>
<tr class="memdesc:a0c3704e33e90ba0491cee56cfb553090"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (32 bit) <a href="#a0c3704e33e90ba0491cee56cfb553090">More...</a><br/></td></tr>
<tr class="separator:a0c3704e33e90ba0491cee56cfb553090"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7f7b66103530fadcce226375af3c2c03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a7f7b66103530fadcce226375af3c2c03">__CLREX</a>   __clrex</td></tr>
<tr class="memdesc:a7f7b66103530fadcce226375af3c2c03"><td class="mdescLeft"> </td><td class="mdescRight">Remove the exclusive lock. <a href="#a7f7b66103530fadcce226375af3c2c03">More...</a><br/></td></tr>
<tr class="separator:a7f7b66103530fadcce226375af3c2c03"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3c013c2ed76ebc48c283c8bae17b9ab8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a3c013c2ed76ebc48c283c8bae17b9ab8">__SSAT</a>   __ssat</td></tr>
<tr class="memdesc:a3c013c2ed76ebc48c283c8bae17b9ab8"><td class="mdescLeft"> </td><td class="mdescRight">Signed Saturate. <a href="#a3c013c2ed76ebc48c283c8bae17b9ab8">More...</a><br/></td></tr>
<tr class="separator:a3c013c2ed76ebc48c283c8bae17b9ab8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad0e4fa951d563740462d837bb6ddd7bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#ad0e4fa951d563740462d837bb6ddd7bb">__USAT</a>   __usat</td></tr>
<tr class="memdesc:ad0e4fa951d563740462d837bb6ddd7bb"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned Saturate. <a href="#ad0e4fa951d563740462d837bb6ddd7bb">More...</a><br/></td></tr>
<tr class="separator:ad0e4fa951d563740462d837bb6ddd7bb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad2a4e5d85d92189d574854b2fbfff057"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#ad2a4e5d85d92189d574854b2fbfff057">__get_CP</a>(cp, op1, Rt, CRn, CRm, op2)   do { register volatile uint32_t tmp <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a>("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)</td></tr>
<tr class="separator:ad2a4e5d85d92189d574854b2fbfff057"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5e4710ddc910c7feee1de7f118b84ad1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a5e4710ddc910c7feee1de7f118b84ad1">__set_CP</a>(cp, op1, Rt, CRn, CRm, op2)   do { register volatile uint32_t tmp <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a>("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)</td></tr>
<tr class="separator:a5e4710ddc910c7feee1de7f118b84ad1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a96a3cccabb5bcaf41115a5dfb3fc6723"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a96a3cccabb5bcaf41115a5dfb3fc6723">__get_CP64</a>(cp, op1, Rt, CRm)</td></tr>
<tr class="separator:a96a3cccabb5bcaf41115a5dfb3fc6723"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af23b5ae27930ef8d9f62a2cf19338003"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#af23b5ae27930ef8d9f62a2cf19338003">__set_CP64</a>(cp, op1, Rt, CRm)</td></tr>
<tr class="separator:af23b5ae27930ef8d9f62a2cf19338003"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga6a275172e274ea7ce6c22030d07c6c64"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPSCR.html#ga6a275172e274ea7ce6c22030d07c6c64">__get_FPSCR</a> (void)</td></tr>
<tr class="memdesc:ga6a275172e274ea7ce6c22030d07c6c64"><td class="mdescLeft"> </td><td class="mdescRight">Get FPSCR (Floating Point Status/Control) <a href="group__CMSIS__FPSCR.html#ga6a275172e274ea7ce6c22030d07c6c64">More...</a><br/></td></tr>
<tr class="separator:ga6a275172e274ea7ce6c22030d07c6c64"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga17c6ff443c52c74125fefef7de5fee1d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPSCR.html#ga17c6ff443c52c74125fefef7de5fee1d">__set_FPSCR</a> (uint32_t fpscr)</td></tr>
<tr class="memdesc:ga17c6ff443c52c74125fefef7de5fee1d"><td class="mdescLeft"> </td><td class="mdescRight">Set FPSCR (Floating Point Status/Control) <a href="group__CMSIS__FPSCR.html#ga17c6ff443c52c74125fefef7de5fee1d">More...</a><br/></td></tr>
<tr class="separator:ga17c6ff443c52c74125fefef7de5fee1d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0308d7d313bced36c3d1a4c2f9741186"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR.html#ga0308d7d313bced36c3d1a4c2f9741186">__get_CPSR</a> (void)</td></tr>
<tr class="memdesc:ga0308d7d313bced36c3d1a4c2f9741186"><td class="mdescLeft"> </td><td class="mdescRight">Get CPSR (Current Program Status Register) <a href="group__CMSIS__CPSR.html#ga0308d7d313bced36c3d1a4c2f9741186">More...</a><br/></td></tr>
<tr class="separator:ga0308d7d313bced36c3d1a4c2f9741186"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf87faa3453333bcac5667fb1ccfc7f61"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR.html#gaf87faa3453333bcac5667fb1ccfc7f61">__set_CPSR</a> (uint32_t cpsr)</td></tr>
<tr class="memdesc:gaf87faa3453333bcac5667fb1ccfc7f61"><td class="mdescLeft"> </td><td class="mdescRight">Set CPSR (Current Program Status Register) <a href="group__CMSIS__CPSR.html#gaf87faa3453333bcac5667fb1ccfc7f61">More...</a><br/></td></tr>
<tr class="separator:gaf87faa3453333bcac5667fb1ccfc7f61"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4712ef84455dfc73de4697e1c213b0ed"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a4712ef84455dfc73de4697e1c213b0ed">__get_mode</a> (void)</td></tr>
<tr class="memdesc:a4712ef84455dfc73de4697e1c213b0ed"><td class="mdescLeft"> </td><td class="mdescRight">Get Mode. <a href="#a4712ef84455dfc73de4697e1c213b0ed">More...</a><br/></td></tr>
<tr class="separator:a4712ef84455dfc73de4697e1c213b0ed"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a306b0a932918f2243a40d4e855503be2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a306b0a932918f2243a40d4e855503be2">__set_mode</a> (uint32_t mode)</td></tr>
<tr class="memdesc:a306b0a932918f2243a40d4e855503be2"><td class="mdescLeft"> </td><td class="mdescRight">Set Mode. <a href="#a306b0a932918f2243a40d4e855503be2">More...</a><br/></td></tr>
<tr class="separator:a306b0a932918f2243a40d4e855503be2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1473ba10f33f397118e434e9ad0c1514"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a1473ba10f33f397118e434e9ad0c1514">__get_SP</a> (void)</td></tr>
<tr class="memdesc:a1473ba10f33f397118e434e9ad0c1514"><td class="mdescLeft"> </td><td class="mdescRight">Get Stack Pointer. <a href="#a1473ba10f33f397118e434e9ad0c1514">More...</a><br/></td></tr>
<tr class="separator:a1473ba10f33f397118e434e9ad0c1514"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6af63cb939bd108aef1c0f12622350cb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SP.html#ga6af63cb939bd108aef1c0f12622350cb">__set_SP</a> (uint32_t stack)</td></tr>
<tr class="memdesc:ga6af63cb939bd108aef1c0f12622350cb"><td class="mdescLeft"> </td><td class="mdescRight">Set Stack Pointer. <a href="group__CMSIS__SP.html#ga6af63cb939bd108aef1c0f12622350cb">More...</a><br/></td></tr>
<tr class="separator:ga6af63cb939bd108aef1c0f12622350cb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a403dcb809998ee594da0908820155a42"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__armcc_8h.html#a403dcb809998ee594da0908820155a42">__get_SP_usr</a> (void)</td></tr>
<tr class="memdesc:a403dcb809998ee594da0908820155a42"><td class="mdescLeft"> </td><td class="mdescRight">Get USR/SYS Stack Pointer. <a href="#a403dcb809998ee594da0908820155a42">More...</a><br/></td></tr>
<tr class="separator:a403dcb809998ee594da0908820155a42"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabfe36eb17b6ae34633c7e155d132426e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SP.html#gabfe36eb17b6ae34633c7e155d132426e">__set_SP_usr</a> (uint32_t topOfProcStack)</td></tr>
<tr class="memdesc:gabfe36eb17b6ae34633c7e155d132426e"><td class="mdescLeft"> </td><td class="mdescRight">Set USR/SYS Stack Pointer. <a href="group__CMSIS__SP.html#gabfe36eb17b6ae34633c7e155d132426e">More...</a><br/></td></tr>
<tr class="separator:gabfe36eb17b6ae34633c7e155d132426e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadde57667b9f81c468a49268513624b90"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPEXC.html#gadde57667b9f81c468a49268513624b90">__get_FPEXC</a> (void)</td></tr>
<tr class="memdesc:gadde57667b9f81c468a49268513624b90"><td class="mdescLeft"> </td><td class="mdescRight">Get FPEXC (Floating Point Exception Control Register) <a href="group__CMSIS__FPEXC.html#gadde57667b9f81c468a49268513624b90">More...</a><br/></td></tr>
<tr class="separator:gadde57667b9f81c468a49268513624b90"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga14ba90beb9b4712454f35ac453c45f5d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPEXC.html#ga14ba90beb9b4712454f35ac453c45f5d">__set_FPEXC</a> (uint32_t fpexc)</td></tr>
<tr class="memdesc:ga14ba90beb9b4712454f35ac453c45f5d"><td class="mdescLeft"> </td><td class="mdescRight">Set FPEXC (Floating Point Exception Control Register) <a href="group__CMSIS__FPEXC.html#ga14ba90beb9b4712454f35ac453c45f5d">More...</a><br/></td></tr>
<tr class="separator:ga14ba90beb9b4712454f35ac453c45f5d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1e4728985ee8b4fa89cc01c032f69565"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__FPU__functions.html#ga1e4728985ee8b4fa89cc01c032f69565">__FPU_Enable</a> (void)</td></tr>
<tr class="memdesc:ga1e4728985ee8b4fa89cc01c032f69565"><td class="mdescLeft"> </td><td class="mdescRight">Enable Floating Point Unit. <a href="group__FPU__functions.html#ga1e4728985ee8b4fa89cc01c032f69565">More...</a><br/></td></tr>
<tr class="separator:ga1e4728985ee8b4fa89cc01c032f69565"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl class="section version"><dt>Version</dt><dd>V1.0.3 </dd></dl>
<dl class="section date"><dt>Date</dt><dd>15. May 2019 </dd></dl>
</div><h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a7f7b66103530fadcce226375af3c2c03"></a>
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<td class="memname">#define __CLREX   __clrex</td>
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<p>Removes the exclusive lock which is created by LDREX. </p>
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<td class="memname">#define __CLZ   __clz</td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl>
</div>
</div>
<a class="anchor" id="a6516fb12ab0dd45c734f8cef7d921af6"></a>
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<td class="memname">#define __COMPILER_BARRIER</td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td>   __memory_changed()</td>
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</div><div class="memdoc">
</div>
</div>
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<td class="memname">#define __FORCEINLINE   __forceinline</td>
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</div>
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<td class="memname">#define __get_CP</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">cp, </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">op1, </td>
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<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">Rt, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">CRn, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">CRm, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">op2 </td>
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<tr>
<td></td>
<td>)</td>
<td></td><td>   do { register volatile uint32_t tmp <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a>("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)</td>
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</div>
</div>
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<td class="memname">#define __get_CP64</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">cp, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">op1, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">Rt, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">CRm </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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</div><div class="memdoc">
</div>
</div>
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<td class="memname">#define __LDREXB</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">ptr</td><td>)</td>
<td>   _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")</td>
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<p>Executes a exclusive LDR instruction for 8 bit value. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>
</div>
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<td class="memname">#define __LDREXH</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">ptr</td><td>)</td>
<td>   _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")</td>
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<p>Executes a exclusive LDR instruction for 16 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>
</div>
</div>
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<td class="memname">#define __LDREXW</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">ptr</td><td>)</td>
<td>   _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")</td>
</tr>
</table>
</div><div class="memdoc">
<p>Executes a exclusive LDR instruction for 32 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>
</div>
</div>
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<td class="memname">#define __PACKED_STRUCT   __packed struct</td>
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</div>
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<td class="memname">#define __RBIT   __rbit</td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>
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</div>
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<td class="memname">#define __REV   __rev</td>
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<p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>
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</div>
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<td class="memname">#define __ROR   __ror</td>
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<p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value Reverse byte order (16 bit)</dd></dl>
<p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value Rotate Right in unsigned value (32 bit) </dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">op1</td><td>Value to rotate </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">op2</td><td>Number of Bits to rotate </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>
</div>
</div>
<a class="anchor" id="a5e4710ddc910c7feee1de7f118b84ad1"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __set_CP</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">cp, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">op1, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">Rt, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">CRn, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">CRm, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">op2 </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   do { register volatile uint32_t tmp <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a>("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="af23b5ae27930ef8d9f62a2cf19338003"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __set_CP64</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">cp, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">op1, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">Rt, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">CRm </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a3c013c2ed76ebc48c283c8bae17b9ab8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __SSAT   __ssat</td>
</tr>
</table>
</div><div class="memdoc">
<p>Saturates a signed value. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to (1..32) </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>
</div>
</div>
<a class="anchor" id="ab904513442afdf77d4f8c74f23cbb040"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __STATIC_FORCEINLINE   static __forceinline</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a503ba30a93e83963de38e5171fbbabce"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __STREXB</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">value, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">ptr </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")</td>
</tr>
</table>
</div><div class="memdoc">
<p>Executes a exclusive STR instruction for 8 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>
</div>
</div>
<a class="anchor" id="a63d19c6c7852ada9a1c1aab80e6294b1"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __STREXH</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">value, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">ptr </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")</td>
</tr>
</table>
</div><div class="memdoc">
<p>Executes a exclusive STR instruction for 16 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>
</div>
</div>
<a class="anchor" id="a0c3704e33e90ba0491cee56cfb553090"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __STREXW</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">value, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">ptr </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")</td>
</tr>
</table>
</div><div class="memdoc">
<p>Executes a exclusive STR instruction for 32 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>
</div>
</div>
<a class="anchor" id="ab71b66e5ce403158d3dee62a59f9175f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __UNALIGNED_UINT16_READ</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">addr</td><td>)</td>
<td>   (*((const __packed uint16_t *)(addr)))</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a5103fb373cae9837cc4a384be55dc87f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __UNALIGNED_UINT16_WRITE</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">addr, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">val </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   ((*((__packed uint16_t *)(addr))) = (val))</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a3b931f0b051b8c1a6377a3dcc7559b5e"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __UNALIGNED_UINT32_READ</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">addr</td><td>)</td>
<td>   (*((const __packed uint32_t *)(addr)))</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a203f593d140ed88b81bc189edc861110"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __UNALIGNED_UINT32_WRITE</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">addr, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">val </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   ((*((__packed uint32_t *)(addr))) = (val))</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ad0e4fa951d563740462d837bb6ddd7bb"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __USAT   __usat</td>
</tr>
</table>
</div><div class="memdoc">
<p>Saturates an unsigned value. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to (0..31) </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>
</div>
</div>
<a class="anchor" id="acdc36c1b3d3e16c17a73889b7d06d0d2"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define CMSIS_DEPRECATED   __attribute__((deprecated))</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="a4712ef84455dfc73de4697e1c213b0ed"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t __get_mode </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>Processor Mode </dd></dl>
</div>
</div>
<a class="anchor" id="a1473ba10f33f397118e434e9ad0c1514"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> uint32_t __get_SP </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>Stack Pointer </dd></dl>
</div>
</div>
<a class="anchor" id="a403dcb809998ee594da0908820155a42"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> uint32_t __get_SP_usr </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>USR/SYSStack Pointer </dd></dl>
</div>
</div>
<a class="anchor" id="a306b0a932918f2243a40d4e855503be2"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> void __set_mode </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>mode</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>Mode value to set </td></tr>
</table>
</dd>
</dl>
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<p>CMSIS compiler specific macros, functions, instructions.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab904513442afdf77d4f8c74f23cbb040"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a></td></tr>
<tr class="memdesc:gab904513442afdf77d4f8c74f23cbb040"><td class="mdescLeft"> </td><td class="mdescRight">Define a static function that should be always inlined by the compiler. <a href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">More...</a><br/></td></tr>
<tr class="separator:gab904513442afdf77d4f8c74f23cbb040"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4dbb70fab85207c27b581ecb6532b314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a></td></tr>
<tr class="memdesc:ga4dbb70fab85207c27b581ecb6532b314"><td class="mdescLeft"> </td><td class="mdescRight">Request smallest possible alignment for a structure. <a href="group__comp__cntrl__gr.html#ga4dbb70fab85207c27b581ecb6532b314">More...</a><br/></td></tr>
<tr class="separator:ga4dbb70fab85207c27b581ecb6532b314"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga27fd2ec6767ca1ab66d36b5cc0103268"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a></td></tr>
<tr class="memdesc:ga27fd2ec6767ca1ab66d36b5cc0103268"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned access of a uint32_t variable. <a href="group__comp__cntrl__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">More...</a><br/></td></tr>
<tr class="separator:ga27fd2ec6767ca1ab66d36b5cc0103268"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabe8693a7200e573101551d49a1772fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a></td></tr>
<tr class="memdesc:gabe8693a7200e573101551d49a1772fb9"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned read of a uint16_t variable. <a href="group__comp__cntrl__gr.html#gabe8693a7200e573101551d49a1772fb9">More...</a><br/></td></tr>
<tr class="separator:gabe8693a7200e573101551d49a1772fb9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadb9cd73446f7e11e92383cd327a23407"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gadb9cd73446f7e11e92383cd327a23407">__UNALIGNED_UINT16_WRITE</a></td></tr>
<tr class="memdesc:gadb9cd73446f7e11e92383cd327a23407"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned write of a uint16_t variable. <a href="group__comp__cntrl__gr.html#gadb9cd73446f7e11e92383cd327a23407">More...</a><br/></td></tr>
<tr class="separator:gadb9cd73446f7e11e92383cd327a23407"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga254322c344d954c9f829719a50a88e87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a></td></tr>
<tr class="memdesc:ga254322c344d954c9f829719a50a88e87"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned read of a uint32_t variable. <a href="group__comp__cntrl__gr.html#ga254322c344d954c9f829719a50a88e87">More...</a><br/></td></tr>
<tr class="separator:ga254322c344d954c9f829719a50a88e87"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabb2180285c417aa9120a360c51f64b4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__comp__cntrl__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a></td></tr>
<tr class="memdesc:gabb2180285c417aa9120a360c51f64b4b"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned write of a uint32_t variable. <a href="group__comp__cntrl__gr.html#gabb2180285c417aa9120a360c51f64b4b">More...</a><br/></td></tr>
<tr class="separator:gabb2180285c417aa9120a360c51f64b4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (32 bit) <a href="group__CMSIS__Core__InstructionInterface.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">More...</a><br/></td></tr>
<tr class="separator:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga926d702cf1de59d54f4e62ab8e3c8b8d"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga926d702cf1de59d54f4e62ab8e3c8b8d">__REV16</a> (uint16_t value)</td></tr>
<tr class="memdesc:ga926d702cf1de59d54f4e62ab8e3c8b8d"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <a href="group__CMSIS__Core__InstructionInterface.html#ga926d702cf1de59d54f4e62ab8e3c8b8d">More...</a><br/></td></tr>
<tr class="separator:ga926d702cf1de59d54f4e62ab8e3c8b8d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1ec006e6d79063363cb0c2a2e0b3adbe"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">__REVSH</a> (int32_t value)</td></tr>
<tr class="memdesc:ga1ec006e6d79063363cb0c2a2e0b3adbe"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <a href="group__CMSIS__Core__InstructionInterface.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">More...</a><br/></td></tr>
<tr class="separator:ga1ec006e6d79063363cb0c2a2e0b3adbe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae05c1a2dac5bb7a399420c804c3048ca"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gae05c1a2dac5bb7a399420c804c3048ca">__ROR</a> (uint32_t op1, uint32_t op2)</td></tr>
<tr class="memdesc:gae05c1a2dac5bb7a399420c804c3048ca"><td class="mdescLeft"> </td><td class="mdescRight">Rotate Right in unsigned value (32 bit) <a href="group__CMSIS__Core__InstructionInterface.html#gae05c1a2dac5bb7a399420c804c3048ca">More...</a><br/></td></tr>
<tr class="separator:gae05c1a2dac5bb7a399420c804c3048ca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad6f9f297f6b91a995ee199fbc796b863"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a> (uint32_t value)</td></tr>
<tr class="memdesc:gad6f9f297f6b91a995ee199fbc796b863"><td class="mdescLeft"> </td><td class="mdescRight">Reverse bit order of value. <a href="group__CMSIS__Core__InstructionInterface.html#gad6f9f297f6b91a995ee199fbc796b863">More...</a><br/></td></tr>
<tr class="separator:gad6f9f297f6b91a995ee199fbc796b863"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga90884c591ac5d73d6069334eba9d6c02"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga90884c591ac5d73d6069334eba9d6c02"><td class="mdescLeft"> </td><td class="mdescRight">Count leading zeros. <a href="group__CMSIS__Core__InstructionInterface.html#ga90884c591ac5d73d6069334eba9d6c02">More...</a><br/></td></tr>
<tr class="separator:ga90884c591ac5d73d6069334eba9d6c02"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl class="section version"><dt>Version</dt><dd>V1.00 </dd></dl>
<dl class="section date"><dt>Date</dt><dd>22. Feb 2017 </dd></dl>
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<a href="#define-members">Macros</a> |
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<div class="title">cmsis_cp15.h File Reference</div> </div>
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<p>CMSIS compiler specific macros, functions, instructions.
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Macros</h2></td></tr>
<tr class="memitem:ae6f92562f567fd8583d8ddd98cae46d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#ae6f92562f567fd8583d8ddd98cae46d5">__CMSIS_CP15_H</a></td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gae75d412bfd6fe873ade00b021aefcab3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">__get_ACTLR</a> (void)</td></tr>
<tr class="memdesc:gae75d412bfd6fe873ade00b021aefcab3"><td class="mdescLeft"> </td><td class="mdescRight">Get ACTLR. <a href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">More...</a><br/></td></tr>
<tr class="separator:gae75d412bfd6fe873ade00b021aefcab3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af0fd00dce8d7368f78c033e5f7fda9cd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#af0fd00dce8d7368f78c033e5f7fda9cd">__set_ACTLR</a> (uint32_t actlr)</td></tr>
<tr class="memdesc:af0fd00dce8d7368f78c033e5f7fda9cd"><td class="mdescLeft"> </td><td class="mdescRight">Set ACTLR. <a href="#af0fd00dce8d7368f78c033e5f7fda9cd">More...</a><br/></td></tr>
<tr class="separator:af0fd00dce8d7368f78c033e5f7fda9cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadb152ab7a893135695e608ecaa5b0c4e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR.html#gadb152ab7a893135695e608ecaa5b0c4e">__get_CPACR</a> (void)</td></tr>
<tr class="memdesc:gadb152ab7a893135695e608ecaa5b0c4e"><td class="mdescLeft"> </td><td class="mdescRight">Get CPACR. <a href="group__CMSIS__CPACR.html#gadb152ab7a893135695e608ecaa5b0c4e">More...</a><br/></td></tr>
<tr class="separator:gadb152ab7a893135695e608ecaa5b0c4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8bf7e1cfb0f28bc3bff3be7fec057668"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR.html#ga8bf7e1cfb0f28bc3bff3be7fec057668">__set_CPACR</a> (uint32_t cpacr)</td></tr>
<tr class="memdesc:ga8bf7e1cfb0f28bc3bff3be7fec057668"><td class="mdescLeft"> </td><td class="mdescRight">Set CPACR. <a href="group__CMSIS__CPACR.html#ga8bf7e1cfb0f28bc3bff3be7fec057668">More...</a><br/></td></tr>
<tr class="separator:ga8bf7e1cfb0f28bc3bff3be7fec057668"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9897e96a6ccb50199d4968fd45ab7962"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR.html#ga9897e96a6ccb50199d4968fd45ab7962">__get_DFSR</a> (void)</td></tr>
<tr class="memdesc:ga9897e96a6ccb50199d4968fd45ab7962"><td class="mdescLeft"> </td><td class="mdescRight">Get DFSR. <a href="group__CMSIS__DFSR.html#ga9897e96a6ccb50199d4968fd45ab7962">More...</a><br/></td></tr>
<tr class="separator:ga9897e96a6ccb50199d4968fd45ab7962"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga824a3e4ae371ef38641375f9fa4cc29c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR.html#ga824a3e4ae371ef38641375f9fa4cc29c">__set_DFSR</a> (uint32_t dfsr)</td></tr>
<tr class="memdesc:ga824a3e4ae371ef38641375f9fa4cc29c"><td class="mdescLeft"> </td><td class="mdescRight">Set DFSR. <a href="group__CMSIS__DFSR.html#ga824a3e4ae371ef38641375f9fa4cc29c">More...</a><br/></td></tr>
<tr class="separator:ga824a3e4ae371ef38641375f9fa4cc29c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9350226159749b673afd56a3b24953a0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR.html#ga9350226159749b673afd56a3b24953a0">__get_IFSR</a> (void)</td></tr>
<tr class="memdesc:ga9350226159749b673afd56a3b24953a0"><td class="mdescLeft"> </td><td class="mdescRight">Get IFSR. <a href="group__CMSIS__IFSR.html#ga9350226159749b673afd56a3b24953a0">More...</a><br/></td></tr>
<tr class="separator:ga9350226159749b673afd56a3b24953a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5bd9b703236cf2566eeed0ed59dda8a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR.html#ga5bd9b703236cf2566eeed0ed59dda8a6">__set_IFSR</a> (uint32_t ifsr)</td></tr>
<tr class="memdesc:ga5bd9b703236cf2566eeed0ed59dda8a6"><td class="mdescLeft"> </td><td class="mdescRight">Set IFSR. <a href="group__CMSIS__IFSR.html#ga5bd9b703236cf2566eeed0ed59dda8a6">More...</a><br/></td></tr>
<tr class="separator:ga5bd9b703236cf2566eeed0ed59dda8a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga450229b64b770e8524ed763f53ff62e2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR.html#ga450229b64b770e8524ed763f53ff62e2">__get_ISR</a> (void)</td></tr>
<tr class="memdesc:ga450229b64b770e8524ed763f53ff62e2"><td class="mdescLeft"> </td><td class="mdescRight">Get ISR. <a href="group__CMSIS__ISR.html#ga450229b64b770e8524ed763f53ff62e2">More...</a><br/></td></tr>
<tr class="separator:ga450229b64b770e8524ed763f53ff62e2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab0f00668bb0f6cbe3cc8b90535d66d8e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBAR.html#gab0f00668bb0f6cbe3cc8b90535d66d8e">__get_CBAR</a> (void)</td></tr>
<tr class="memdesc:gab0f00668bb0f6cbe3cc8b90535d66d8e"><td class="mdescLeft"> </td><td class="mdescRight">Get CBAR. <a href="group__CMSIS__CBAR.html#gab0f00668bb0f6cbe3cc8b90535d66d8e">More...</a><br/></td></tr>
<tr class="separator:gab0f00668bb0f6cbe3cc8b90535d66d8e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga678997bc01f6d8d48b1d407cec24809d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TTBR.html#ga678997bc01f6d8d48b1d407cec24809d">__get_TTBR0</a> (void)</td></tr>
<tr class="memdesc:ga678997bc01f6d8d48b1d407cec24809d"><td class="mdescLeft"> </td><td class="mdescRight">Get TTBR0. <a href="group__CMSIS__TTBR.html#ga678997bc01f6d8d48b1d407cec24809d">More...</a><br/></td></tr>
<tr class="separator:ga678997bc01f6d8d48b1d407cec24809d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad2ccad052f77c18897c5ceaaf307711e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TTBR.html#gad2ccad052f77c18897c5ceaaf307711e">__set_TTBR0</a> (uint32_t ttbr0)</td></tr>
<tr class="memdesc:gad2ccad052f77c18897c5ceaaf307711e"><td class="mdescLeft"> </td><td class="mdescRight">Set TTBR0. <a href="group__CMSIS__TTBR.html#gad2ccad052f77c18897c5ceaaf307711e">More...</a><br/></td></tr>
<tr class="separator:gad2ccad052f77c18897c5ceaaf307711e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga10278deb975c653555ee70178546aaa6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR.html#ga10278deb975c653555ee70178546aaa6">__get_DACR</a> (void)</td></tr>
<tr class="memdesc:ga10278deb975c653555ee70178546aaa6"><td class="mdescLeft"> </td><td class="mdescRight">Get DACR. <a href="group__CMSIS__DACR.html#ga10278deb975c653555ee70178546aaa6">More...</a><br/></td></tr>
<tr class="separator:ga10278deb975c653555ee70178546aaa6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga72e050de5b19cd6b683f6c234968b78b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR.html#ga72e050de5b19cd6b683f6c234968b78b">__set_DACR</a> (uint32_t dacr)</td></tr>
<tr class="memdesc:ga72e050de5b19cd6b683f6c234968b78b"><td class="mdescLeft"> </td><td class="mdescRight">Set DACR. <a href="group__CMSIS__DACR.html#ga72e050de5b19cd6b683f6c234968b78b">More...</a><br/></td></tr>
<tr class="separator:ga72e050de5b19cd6b683f6c234968b78b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf9b8e96ddd2e76c4475cf957600fd57a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR.html#gaf9b8e96ddd2e76c4475cf957600fd57a">__set_SCTLR</a> (uint32_t sctlr)</td></tr>
<tr class="memdesc:gaf9b8e96ddd2e76c4475cf957600fd57a"><td class="mdescLeft"> </td><td class="mdescRight">Set SCTLR. <a href="group__CMSIS__SCTLR.html#gaf9b8e96ddd2e76c4475cf957600fd57a">More...</a><br/></td></tr>
<tr class="separator:gaf9b8e96ddd2e76c4475cf957600fd57a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3070304d6180433c91c4e6daef3f3c73"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR.html#ga3070304d6180433c91c4e6daef3f3c73">__get_SCTLR</a> (void)</td></tr>
<tr class="memdesc:ga3070304d6180433c91c4e6daef3f3c73"><td class="mdescLeft"> </td><td class="mdescRight">Get SCTLR. <a href="group__CMSIS__SCTLR.html#ga3070304d6180433c91c4e6daef3f3c73">More...</a><br/></td></tr>
<tr class="separator:ga3070304d6180433c91c4e6daef3f3c73"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabe7491eac1652f740050bd905baea187"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187">__set_ACTRL</a> (uint32_t actrl)</td></tr>
<tr class="memdesc:gabe7491eac1652f740050bd905baea187"><td class="mdescLeft"> </td><td class="mdescRight">Set ACTRL. <a href="group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187">More...</a><br/></td></tr>
<tr class="separator:gabe7491eac1652f740050bd905baea187"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a41816284abd2ff7a2ea050c37ff5b5b0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#a41816284abd2ff7a2ea050c37ff5b5b0">__get_ACTRL</a> (void)</td></tr>
<tr class="memdesc:a41816284abd2ff7a2ea050c37ff5b5b0"><td class="mdescLeft"> </td><td class="mdescRight">Get ACTRL. <a href="#a41816284abd2ff7a2ea050c37ff5b5b0">More...</a><br/></td></tr>
<tr class="separator:a41816284abd2ff7a2ea050c37ff5b5b0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga05394b4cb9fb0ba1329ec6521c76e571"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MPIDR.html#ga05394b4cb9fb0ba1329ec6521c76e571">__get_MPIDR</a> (void)</td></tr>
<tr class="memdesc:ga05394b4cb9fb0ba1329ec6521c76e571"><td class="mdescLeft"> </td><td class="mdescRight">Get MPIDR. <a href="group__CMSIS__MPIDR.html#ga05394b4cb9fb0ba1329ec6521c76e571">More...</a><br/></td></tr>
<tr class="separator:ga05394b4cb9fb0ba1329ec6521c76e571"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8abf5c92597d8e7d403aa26d8246387c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__VBAR.html#ga8abf5c92597d8e7d403aa26d8246387c">__get_VBAR</a> (void)</td></tr>
<tr class="memdesc:ga8abf5c92597d8e7d403aa26d8246387c"><td class="mdescLeft"> </td><td class="mdescRight">Get VBAR. <a href="group__CMSIS__VBAR.html#ga8abf5c92597d8e7d403aa26d8246387c">More...</a><br/></td></tr>
<tr class="separator:ga8abf5c92597d8e7d403aa26d8246387c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga582f9a60f7b090ae5a4e8f60ef3b79f8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__VBAR.html#ga582f9a60f7b090ae5a4e8f60ef3b79f8">__set_VBAR</a> (uint32_t vbar)</td></tr>
<tr class="memdesc:ga582f9a60f7b090ae5a4e8f60ef3b79f8"><td class="mdescLeft"> </td><td class="mdescRight">Set VBAR. <a href="group__CMSIS__VBAR.html#ga582f9a60f7b090ae5a4e8f60ef3b79f8">More...</a><br/></td></tr>
<tr class="separator:ga582f9a60f7b090ae5a4e8f60ef3b79f8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3839224facf28080e73ac1bd6e356c30"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MVBAR.html#ga3839224facf28080e73ac1bd6e356c30">__get_MVBAR</a> (void)</td></tr>
<tr class="memdesc:ga3839224facf28080e73ac1bd6e356c30"><td class="mdescLeft"> </td><td class="mdescRight">Get MVBAR. <a href="group__CMSIS__MVBAR.html#ga3839224facf28080e73ac1bd6e356c30">More...</a><br/></td></tr>
<tr class="separator:ga3839224facf28080e73ac1bd6e356c30"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga73c9231bcf1669fb34a1ee3f8062ad09"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MVBAR.html#ga73c9231bcf1669fb34a1ee3f8062ad09">__set_MVBAR</a> (uint32_t mvbar)</td></tr>
<tr class="memdesc:ga73c9231bcf1669fb34a1ee3f8062ad09"><td class="mdescLeft"> </td><td class="mdescRight">Set MVBAR. <a href="group__CMSIS__MVBAR.html#ga73c9231bcf1669fb34a1ee3f8062ad09">More...</a><br/></td></tr>
<tr class="separator:ga73c9231bcf1669fb34a1ee3f8062ad09"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga66d2d5070c8577f95e1d2e2bcb3ad143"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTFRQ.html#ga66d2d5070c8577f95e1d2e2bcb3ad143">__set_CNTFRQ</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga66d2d5070c8577f95e1d2e2bcb3ad143"><td class="mdescLeft"> </td><td class="mdescRight">Set CNTFRQ. <a href="group__CMSIS__CNTFRQ.html#ga66d2d5070c8577f95e1d2e2bcb3ad143">More...</a><br/></td></tr>
<tr class="separator:ga66d2d5070c8577f95e1d2e2bcb3ad143"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4b6c8f8689077d9b57f65dcff910dbf8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTFRQ.html#ga4b6c8f8689077d9b57f65dcff910dbf8">__get_CNTFRQ</a> (void)</td></tr>
<tr class="memdesc:ga4b6c8f8689077d9b57f65dcff910dbf8"><td class="mdescLeft"> </td><td class="mdescRight">Get CNTFRQ. <a href="group__CMSIS__CNTFRQ.html#ga4b6c8f8689077d9b57f65dcff910dbf8">More...</a><br/></td></tr>
<tr class="separator:ga4b6c8f8689077d9b57f65dcff910dbf8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5cd55833483552e023c9b2ead0c97a02"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__TVAL.html#ga5cd55833483552e023c9b2ead0c97a02">__set_CNTP_TVAL</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga5cd55833483552e023c9b2ead0c97a02"><td class="mdescLeft"> </td><td class="mdescRight">Set CNTP_TVAL. <a href="group__CMSIS__CNTP__TVAL.html#ga5cd55833483552e023c9b2ead0c97a02">More...</a><br/></td></tr>
<tr class="separator:ga5cd55833483552e023c9b2ead0c97a02"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga94321d86e23339a3de6e48ae1b4e006d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__TVAL.html#ga94321d86e23339a3de6e48ae1b4e006d">__get_CNTP_TVAL</a> (void)</td></tr>
<tr class="memdesc:ga94321d86e23339a3de6e48ae1b4e006d"><td class="mdescLeft"> </td><td class="mdescRight">Get CNTP_TVAL. <a href="group__CMSIS__CNTP__TVAL.html#ga94321d86e23339a3de6e48ae1b4e006d">More...</a><br/></td></tr>
<tr class="separator:ga94321d86e23339a3de6e48ae1b4e006d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga42643f577dcc957d6928e170ce7a2d60"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTPCT.html#ga42643f577dcc957d6928e170ce7a2d60">__get_CNTPCT</a> (void)</td></tr>
<tr class="memdesc:ga42643f577dcc957d6928e170ce7a2d60"><td class="mdescLeft"> </td><td class="mdescRight">Get CNTPCT. <a href="group__CMSIS__CNTPCT.html#ga42643f577dcc957d6928e170ce7a2d60">More...</a><br/></td></tr>
<tr class="separator:ga42643f577dcc957d6928e170ce7a2d60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abfe82f8e7ef6edd48d21a545d3c79c3c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#abfe82f8e7ef6edd48d21a545d3c79c3c">__set_CNTP_CVAL</a> (uint64_t value)</td></tr>
<tr class="memdesc:abfe82f8e7ef6edd48d21a545d3c79c3c"><td class="mdescLeft"> </td><td class="mdescRight">Set CNTP_CVAL. <a href="#abfe82f8e7ef6edd48d21a545d3c79c3c">More...</a><br/></td></tr>
<tr class="separator:abfe82f8e7ef6edd48d21a545d3c79c3c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafc37057a481a5357fb9d35a003941d1d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CVAL.html#gafc37057a481a5357fb9d35a003941d1d">__get_CNTP_CVAL</a> (void)</td></tr>
<tr class="memdesc:gafc37057a481a5357fb9d35a003941d1d"><td class="mdescLeft"> </td><td class="mdescRight">Get CNTP_CVAL. <a href="group__CMSIS__CNTP__CVAL.html#gafc37057a481a5357fb9d35a003941d1d">More...</a><br/></td></tr>
<tr class="separator:gafc37057a481a5357fb9d35a003941d1d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga96a537cd4e121d58aa9f7d2bfccaa66d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CTL.html#ga96a537cd4e121d58aa9f7d2bfccaa66d">__set_CNTP_CTL</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga96a537cd4e121d58aa9f7d2bfccaa66d"><td class="mdescLeft"> </td><td class="mdescRight">Set CNTP_CTL. <a href="group__CMSIS__CNTP__CTL.html#ga96a537cd4e121d58aa9f7d2bfccaa66d">More...</a><br/></td></tr>
<tr class="separator:ga96a537cd4e121d58aa9f7d2bfccaa66d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaca4b93d7543b49c1d7e6b4e1c1ff3768"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CTL.html#gaca4b93d7543b49c1d7e6b4e1c1ff3768">__get_CNTP_CTL</a> (void)</td></tr>
<tr class="memdesc:gaca4b93d7543b49c1d7e6b4e1c1ff3768"><td class="mdescLeft"> </td><td class="mdescRight">Get CNTP_CTL register. <a href="group__CMSIS__CNTP__CTL.html#gaca4b93d7543b49c1d7e6b4e1c1ff3768">More...</a><br/></td></tr>
<tr class="separator:gaca4b93d7543b49c1d7e6b4e1c1ff3768"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafe73539914fa96265067bec49a3ed4ea"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TLB.html#gafe73539914fa96265067bec49a3ed4ea">__set_TLBIALL</a> (uint32_t value)</td></tr>
<tr class="memdesc:gafe73539914fa96265067bec49a3ed4ea"><td class="mdescLeft"> </td><td class="mdescRight">Set TLBIALL. <a href="group__CMSIS__TLB.html#gafe73539914fa96265067bec49a3ed4ea">More...</a><br/></td></tr>
<tr class="separator:gafe73539914fa96265067bec49a3ed4ea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa5a1bf5487bd00c61764ee2614bea3d4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html#gaa5a1bf5487bd00c61764ee2614bea3d4">__set_BPIALL</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaa5a1bf5487bd00c61764ee2614bea3d4"><td class="mdescLeft"> </td><td class="mdescRight">Set BPIALL. <a href="group__CMSIS__CBPM.html#gaa5a1bf5487bd00c61764ee2614bea3d4">More...</a><br/></td></tr>
<tr class="separator:gaa5a1bf5487bd00c61764ee2614bea3d4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaee63f9c620f6d37775f80667bc5f724d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html#gaee63f9c620f6d37775f80667bc5f724d">__set_ICIALLU</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaee63f9c620f6d37775f80667bc5f724d"><td class="mdescLeft"> </td><td class="mdescRight">Set ICIALLU. <a href="group__CMSIS__CBPM.html#gaee63f9c620f6d37775f80667bc5f724d">More...</a><br/></td></tr>
<tr class="separator:gaee63f9c620f6d37775f80667bc5f724d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa47448c89b3134f5e9fbb7ba0b69c7d9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html#gaa47448c89b3134f5e9fbb7ba0b69c7d9">__set_DCCMVAC</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaa47448c89b3134f5e9fbb7ba0b69c7d9"><td class="mdescLeft"> </td><td class="mdescRight">Set DCCMVAC. <a href="group__CMSIS__CBPM.html#gaa47448c89b3134f5e9fbb7ba0b69c7d9">More...</a><br/></td></tr>
<tr class="separator:gaa47448c89b3134f5e9fbb7ba0b69c7d9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga643b62f37449627ca2ec3de80c1b8abb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html#ga643b62f37449627ca2ec3de80c1b8abb">__set_DCIMVAC</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga643b62f37449627ca2ec3de80c1b8abb"><td class="mdescLeft"> </td><td class="mdescRight">Set DCIMVAC. <a href="group__CMSIS__CBPM.html#ga643b62f37449627ca2ec3de80c1b8abb">More...</a><br/></td></tr>
<tr class="separator:ga643b62f37449627ca2ec3de80c1b8abb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5a6dc4a371d0e5c5ea9f9a1dcea999ff"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html#ga5a6dc4a371d0e5c5ea9f9a1dcea999ff">__set_DCCIMVAC</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga5a6dc4a371d0e5c5ea9f9a1dcea999ff"><td class="mdescLeft"> </td><td class="mdescRight">Set DCCIMVAC. <a href="group__CMSIS__CBPM.html#ga5a6dc4a371d0e5c5ea9f9a1dcea999ff">More...</a><br/></td></tr>
<tr class="separator:ga5a6dc4a371d0e5c5ea9f9a1dcea999ff"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a14db4d16b3fc39943a94ef9fce2e4f16"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#a14db4d16b3fc39943a94ef9fce2e4f16">__set_CSSELR</a> (uint32_t value)</td></tr>
<tr class="memdesc:a14db4d16b3fc39943a94ef9fce2e4f16"><td class="mdescLeft"> </td><td class="mdescRight">Set CSSELR. <a href="#a14db4d16b3fc39943a94ef9fce2e4f16">More...</a><br/></td></tr>
<tr class="separator:a14db4d16b3fc39943a94ef9fce2e4f16"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a99c40d6a37940e66339191ce3fe68762"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#a99c40d6a37940e66339191ce3fe68762">__get_CSSELR</a> (void)</td></tr>
<tr class="memdesc:a99c40d6a37940e66339191ce3fe68762"><td class="mdescLeft"> </td><td class="mdescRight">Get CSSELR. <a href="#a99c40d6a37940e66339191ce3fe68762">More...</a><br/></td></tr>
<tr class="separator:a99c40d6a37940e66339191ce3fe68762"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a639d467f42fdad7a173f90568b697fc8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#acdc36c1b3d3e16c17a73889b7d06d0d2">CMSIS_DEPRECATED</a> <br class="typebreak"/>
<a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#a639d467f42fdad7a173f90568b697fc8">__set_CCSIDR</a> (uint32_t value)</td></tr>
<tr class="memdesc:a639d467f42fdad7a173f90568b697fc8"><td class="mdescLeft"> </td><td class="mdescRight">Set CCSIDR. <a href="#a639d467f42fdad7a173f90568b697fc8">More...</a><br/></td></tr>
<tr class="separator:a639d467f42fdad7a173f90568b697fc8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ace5e469919d7708bf00391a7bf425869"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#ace5e469919d7708bf00391a7bf425869">__get_CCSIDR</a> (void)</td></tr>
<tr class="memdesc:ace5e469919d7708bf00391a7bf425869"><td class="mdescLeft"> </td><td class="mdescRight">Get CCSIDR. <a href="#ace5e469919d7708bf00391a7bf425869">More...</a><br/></td></tr>
<tr class="separator:ace5e469919d7708bf00391a7bf425869"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abad99510b8a79835d5c9769c6e0a177b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#abad99510b8a79835d5c9769c6e0a177b">__get_CLIDR</a> (void)</td></tr>
<tr class="memdesc:abad99510b8a79835d5c9769c6e0a177b"><td class="mdescLeft"> </td><td class="mdescRight">Get CLIDR. <a href="#abad99510b8a79835d5c9769c6e0a177b">More...</a><br/></td></tr>
<tr class="separator:abad99510b8a79835d5c9769c6e0a177b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab1f9c335fd63529d9385f83b8d6cb43e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#ab1f9c335fd63529d9385f83b8d6cb43e">__set_DCISW</a> (uint32_t value)</td></tr>
<tr class="memdesc:ab1f9c335fd63529d9385f83b8d6cb43e"><td class="mdescLeft"> </td><td class="mdescRight">Set DCISW. <a href="#ab1f9c335fd63529d9385f83b8d6cb43e">More...</a><br/></td></tr>
<tr class="separator:ab1f9c335fd63529d9385f83b8d6cb43e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6c4b49c4e9366c823f6ee909cf446483"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#a6c4b49c4e9366c823f6ee909cf446483">__set_DCCSW</a> (uint32_t value)</td></tr>
<tr class="memdesc:a6c4b49c4e9366c823f6ee909cf446483"><td class="mdescLeft"> </td><td class="mdescRight">Set DCCSW. <a href="#a6c4b49c4e9366c823f6ee909cf446483">More...</a><br/></td></tr>
<tr class="separator:a6c4b49c4e9366c823f6ee909cf446483"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a40f09b50f1a4565adcae6825ad989f10"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="cmsis__cp15_8h.html#a40f09b50f1a4565adcae6825ad989f10">__set_DCCISW</a> (uint32_t value)</td></tr>
<tr class="memdesc:a40f09b50f1a4565adcae6825ad989f10"><td class="mdescLeft"> </td><td class="mdescRight">Set DCCISW. <a href="#a40f09b50f1a4565adcae6825ad989f10">More...</a><br/></td></tr>
<tr class="separator:a40f09b50f1a4565adcae6825ad989f10"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl class="section version"><dt>Version</dt><dd>V1.0.1 </dd></dl>
<dl class="section date"><dt>Date</dt><dd>07. Sep 2017 </dd></dl>
</div><h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ae6f92562f567fd8583d8ddd98cae46d5"></a>
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<td class="memname">#define __CMSIS_CP15_H</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t __get_ACTRL </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>Auxiliary Control Register value </dd></dl>
</div>
</div>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t __get_CCSIDR </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>CCSIDR Register value </dd></dl>
</div>
</div>
<a class="anchor" id="abad99510b8a79835d5c9769c6e0a177b"></a>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t __get_CLIDR </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>CLIDR Register value </dd></dl>
</div>
</div>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t __get_CSSELR </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>CSSELR Register value </dd></dl>
</div>
</div>
<a class="anchor" id="af0fd00dce8d7368f78c033e5f7fda9cd"></a>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_ACTLR </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>actlr</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">actlr</td><td>Auxiliary Control value to set </td></tr>
</table>
</dd>
</dl>
</div>
</div>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#acdc36c1b3d3e16c17a73889b7d06d0d2">CMSIS_DEPRECATED</a> <a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_CCSIDR </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000003">Deprecated:</a></b></dt><dd>CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. </dd></dl>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_CNTP_CVAL </td>
<td>(</td>
<td class="paramtype">uint64_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>CNTP_CVAL Register value to set </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="a14db4d16b3fc39943a94ef9fce2e4f16"></a>
<div class="memitem">
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<tr>
<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_CSSELR </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a40f09b50f1a4565adcae6825ad989f10"></a>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_DCCISW </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a6c4b49c4e9366c823f6ee909cf446483"></a>
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<div class="memproto">
<table class="memname">
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_DCCSW </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ab1f9c335fd63529d9385f83b8d6cb43e"></a>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __set_DCISW </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
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<p>CMSIS Cortex-A Core Peripheral Access Layer Header File.
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html">GICInterface_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html">Timer_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCNTP__CTL__Type.html">CNTP_CTL_Type</a></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:af6738f04c5c33edae09174f235ef3e14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af6738f04c5c33edae09174f235ef3e14">__CORE_CA_H_GENERIC</a></td></tr>
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<tr class="memdesc:ga519092cc80304900838f3d79a1a04e36"><td class="mdescLeft"> </td><td class="mdescRight">[31:16] CMSIS-Core(A) main version <a href="group__version__ctrl.html#ga519092cc80304900838f3d79a1a04e36">More...</a><br/></td></tr>
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<tr class="memdesc:gaca4690227a53e24645758cdab9a00cdf"><td class="mdescLeft"> </td><td class="mdescRight">[15:0] CMSIS-Core(A) sub version <a href="group__version__ctrl.html#gaca4690227a53e24645758cdab9a00cdf">More...</a><br/></td></tr>
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<tr class="memdesc:ga60199f17babba1ac0cf233e59043b23b"><td class="mdescLeft"> </td><td class="mdescRight">CMSIS-Core(A) version number. <a href="group__version__ctrl.html#ga60199f17babba1ac0cf233e59043b23b">More...</a><br/></td></tr>
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<tr class="memitem:af63697ed9952cc71e1225efe205f6cd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   volatile</td></tr>
<tr class="memdesc:af63697ed9952cc71e1225efe205f6cd3"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read only' permissions. <a href="#af63697ed9952cc71e1225efe205f6cd3">More...</a><br/></td></tr>
<tr class="separator:af63697ed9952cc71e1225efe205f6cd3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7e25d9380f9ef903923964322e71f2f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>   volatile</td></tr>
<tr class="memdesc:a7e25d9380f9ef903923964322e71f2f6"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'write only' permissions. <a href="#a7e25d9380f9ef903923964322e71f2f6">More...</a><br/></td></tr>
<tr class="separator:a7e25d9380f9ef903923964322e71f2f6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aec43007d9998a0a0e01faede4133d6be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a>   volatile</td></tr>
<tr class="memdesc:aec43007d9998a0a0e01faede4133d6be"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read / write' permissions. <a href="#aec43007d9998a0a0e01faede4133d6be">More...</a><br/></td></tr>
<tr class="separator:aec43007d9998a0a0e01faede4133d6be"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4cc1649793116d7c2d8afce7a4ffce43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>   volatile const</td></tr>
<tr class="memdesc:a4cc1649793116d7c2d8afce7a4ffce43"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read only' structure member permissions. <a href="#a4cc1649793116d7c2d8afce7a4ffce43">More...</a><br/></td></tr>
<tr class="separator:a4cc1649793116d7c2d8afce7a4ffce43"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0ea2009ed8fd9ef35b48708280fdb758"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>   volatile</td></tr>
<tr class="memdesc:a0ea2009ed8fd9ef35b48708280fdb758"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'write only' structure member permissions. <a href="#a0ea2009ed8fd9ef35b48708280fdb758">More...</a><br/></td></tr>
<tr class="separator:a0ea2009ed8fd9ef35b48708280fdb758"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab6caba5853a60a17e8e04499b52bf691"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a>   volatile</td></tr>
<tr class="memdesc:ab6caba5853a60a17e8e04499b52bf691"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read / write' structure member permissions. <a href="#ab6caba5853a60a17e8e04499b52bf691">More...</a><br/></td></tr>
<tr class="separator:ab6caba5853a60a17e8e04499b52bf691"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af7f66fda711fd46e157dbb6c1af88e04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04">RESERVED</a>(N, T)   T RESERVED##N;</td></tr>
<tr class="separator:af7f66fda711fd46e157dbb6c1af88e04"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaedc00ebe496885524daac4190742f84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">CPSR_N_Pos</a>   31U</td></tr>
<tr class="memdesc:gaaedc00ebe496885524daac4190742f84"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: N Position. <a href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">More...</a><br/></td></tr>
<tr class="separator:gaaedc00ebe496885524daac4190742f84"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6c4a636a3b5ec71e0f2eb021ac353544">CPSR_N_Msk</a>   (1UL << CPSR_N_Pos)</td></tr>
<tr class="memdesc:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: N Mask. <a href="group__CMSIS__CPSR__BITS.html#ga6c4a636a3b5ec71e0f2eb021ac353544">More...</a><br/></td></tr>
<tr class="separator:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">CPSR_Z_Pos</a>   30U</td></tr>
<tr class="memdesc:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Z Position. <a href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">More...</a><br/></td></tr>
<tr class="separator:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab091112988009fb8360b01c79d993f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gab091112988009fb8360b01c79d993f67">CPSR_Z_Msk</a>   (1UL << CPSR_Z_Pos)</td></tr>
<tr class="memdesc:gab091112988009fb8360b01c79d993f67"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Z Mask. <a href="group__CMSIS__CPSR__BITS.html#gab091112988009fb8360b01c79d993f67">More...</a><br/></td></tr>
<tr class="separator:gab091112988009fb8360b01c79d993f67"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8565df3cf054dc09506e1c0ea4790131"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">CPSR_C_Pos</a>   29U</td></tr>
<tr class="memdesc:ga8565df3cf054dc09506e1c0ea4790131"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: C Position. <a href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">More...</a><br/></td></tr>
<tr class="separator:ga8565df3cf054dc09506e1c0ea4790131"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3bc30b14b9b0bf113600eb882304244c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga3bc30b14b9b0bf113600eb882304244c">CPSR_C_Msk</a>   (1UL << CPSR_C_Pos)</td></tr>
<tr class="memdesc:ga3bc30b14b9b0bf113600eb882304244c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: C Mask. <a href="group__CMSIS__CPSR__BITS.html#ga3bc30b14b9b0bf113600eb882304244c">More...</a><br/></td></tr>
<tr class="separator:ga3bc30b14b9b0bf113600eb882304244c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5685fa5745113b4ff61181ee439bc2a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">CPSR_V_Pos</a>   28U</td></tr>
<tr class="memdesc:ga5685fa5745113b4ff61181ee439bc2a5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: V Position. <a href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">More...</a><br/></td></tr>
<tr class="separator:ga5685fa5745113b4ff61181ee439bc2a5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga9b9fe5c1da5e922cbff18215b70b4252">CPSR_V_Msk</a>   (1UL << CPSR_V_Pos)</td></tr>
<tr class="memdesc:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: V Mask. <a href="group__CMSIS__CPSR__BITS.html#ga9b9fe5c1da5e922cbff18215b70b4252">More...</a><br/></td></tr>
<tr class="separator:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">CPSR_Q_Pos</a>   27U</td></tr>
<tr class="memdesc:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Q Position. <a href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">More...</a><br/></td></tr>
<tr class="separator:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba36b1ac0438594afdc6eef220d2e146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaba36b1ac0438594afdc6eef220d2e146">CPSR_Q_Msk</a>   (1UL << CPSR_Q_Pos)</td></tr>
<tr class="memdesc:gaba36b1ac0438594afdc6eef220d2e146"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Q Mask. <a href="group__CMSIS__CPSR__BITS.html#gaba36b1ac0438594afdc6eef220d2e146">More...</a><br/></td></tr>
<tr class="separator:gaba36b1ac0438594afdc6eef220d2e146"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga450f3fff0642431fd3478a04b70c3d87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">CPSR_IT0_Pos</a>   25U</td></tr>
<tr class="memdesc:ga450f3fff0642431fd3478a04b70c3d87"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT0 Position. <a href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">More...</a><br/></td></tr>
<tr class="separator:ga450f3fff0642431fd3478a04b70c3d87"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga128366788d0f94d52fbe4610162c97e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga128366788d0f94d52fbe4610162c97e5">CPSR_IT0_Msk</a>   (3UL << CPSR_IT0_Pos)</td></tr>
<tr class="memdesc:ga128366788d0f94d52fbe4610162c97e5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT0 Mask. <a href="group__CMSIS__CPSR__BITS.html#ga128366788d0f94d52fbe4610162c97e5">More...</a><br/></td></tr>
<tr class="separator:ga128366788d0f94d52fbe4610162c97e5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6b49ddfb770143a51aa682b56be2e990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">CPSR_J_Pos</a>   24U</td></tr>
<tr class="memdesc:ga6b49ddfb770143a51aa682b56be2e990"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: J Position. <a href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">More...</a><br/></td></tr>
<tr class="separator:ga6b49ddfb770143a51aa682b56be2e990"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6b52a05ec2e95ade71b65090f19285c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b52a05ec2e95ade71b65090f19285c2">CPSR_J_Msk</a>   (1UL << CPSR_J_Pos)</td></tr>
<tr class="memdesc:ga6b52a05ec2e95ade71b65090f19285c2"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: J Mask. <a href="group__CMSIS__CPSR__BITS.html#ga6b52a05ec2e95ade71b65090f19285c2">More...</a><br/></td></tr>
<tr class="separator:ga6b52a05ec2e95ade71b65090f19285c2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga37aa76465f6c6055395790e74169d760"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">CPSR_GE_Pos</a>   16U</td></tr>
<tr class="memdesc:ga37aa76465f6c6055395790e74169d760"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: GE Position. <a href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">More...</a><br/></td></tr>
<tr class="separator:ga37aa76465f6c6055395790e74169d760"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9a3a6a87437892954cb37662ff27521a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga9a3a6a87437892954cb37662ff27521a">CPSR_GE_Msk</a>   (0xFUL << CPSR_GE_Pos)</td></tr>
<tr class="memdesc:ga9a3a6a87437892954cb37662ff27521a"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: GE Mask. <a href="group__CMSIS__CPSR__BITS.html#ga9a3a6a87437892954cb37662ff27521a">More...</a><br/></td></tr>
<tr class="separator:ga9a3a6a87437892954cb37662ff27521a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa2ab21d87052b439c06f058fb65036a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">CPSR_IT1_Pos</a>   10U</td></tr>
<tr class="memdesc:gaa2ab21d87052b439c06f058fb65036a5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT1 Position. <a href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">More...</a><br/></td></tr>
<tr class="separator:gaa2ab21d87052b439c06f058fb65036a5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga791263c8a9707795b5824dae5485cd39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga791263c8a9707795b5824dae5485cd39">CPSR_IT1_Msk</a>   (0x3FUL << CPSR_IT1_Pos)</td></tr>
<tr class="memdesc:ga791263c8a9707795b5824dae5485cd39"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT1 Mask. <a href="group__CMSIS__CPSR__BITS.html#ga791263c8a9707795b5824dae5485cd39">More...</a><br/></td></tr>
<tr class="separator:ga791263c8a9707795b5824dae5485cd39"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">CPSR_E_Pos</a>   9U</td></tr>
<tr class="memdesc:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: E Position. <a href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">More...</a><br/></td></tr>
<tr class="separator:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6661712dd33a50ce4a42e13bf72aa35b">CPSR_E_Msk</a>   (1UL << CPSR_E_Pos)</td></tr>
<tr class="memdesc:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: E Mask. <a href="group__CMSIS__CPSR__BITS.html#ga6661712dd33a50ce4a42e13bf72aa35b">More...</a><br/></td></tr>
<tr class="separator:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">CPSR_A_Pos</a>   8U</td></tr>
<tr class="memdesc:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: A Position. <a href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">More...</a><br/></td></tr>
<tr class="separator:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga002803fa282333e0ead5c9b4cf748cb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga002803fa282333e0ead5c9b4cf748cb1">CPSR_A_Msk</a>   (1UL << CPSR_A_Pos)</td></tr>
<tr class="memdesc:ga002803fa282333e0ead5c9b4cf748cb1"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: A Mask. <a href="group__CMSIS__CPSR__BITS.html#ga002803fa282333e0ead5c9b4cf748cb1">More...</a><br/></td></tr>
<tr class="separator:ga002803fa282333e0ead5c9b4cf748cb1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad1d9be2f731f5400fc87076ce3495e59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">CPSR_I_Pos</a>   7U</td></tr>
<tr class="memdesc:gad1d9be2f731f5400fc87076ce3495e59"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: I Position. <a href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">More...</a><br/></td></tr>
<tr class="separator:gad1d9be2f731f5400fc87076ce3495e59"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad9abe93ba1179e254a70e325cb1a5834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gad9abe93ba1179e254a70e325cb1a5834">CPSR_I_Msk</a>   (1UL << CPSR_I_Pos)</td></tr>
<tr class="memdesc:gad9abe93ba1179e254a70e325cb1a5834"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: I Mask. <a href="group__CMSIS__CPSR__BITS.html#gad9abe93ba1179e254a70e325cb1a5834">More...</a><br/></td></tr>
<tr class="separator:gad9abe93ba1179e254a70e325cb1a5834"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">CPSR_F_Pos</a>   6U</td></tr>
<tr class="memdesc:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: F Position. <a href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">More...</a><br/></td></tr>
<tr class="separator:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4df09481ffd9dfb17823a8e9895b1566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga4df09481ffd9dfb17823a8e9895b1566">CPSR_F_Msk</a>   (1UL << CPSR_F_Pos)</td></tr>
<tr class="memdesc:ga4df09481ffd9dfb17823a8e9895b1566"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: F Mask. <a href="group__CMSIS__CPSR__BITS.html#ga4df09481ffd9dfb17823a8e9895b1566">More...</a><br/></td></tr>
<tr class="separator:ga4df09481ffd9dfb17823a8e9895b1566"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa1134ff3e774b1354a43227b798a707c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">CPSR_T_Pos</a>   5U</td></tr>
<tr class="memdesc:gaa1134ff3e774b1354a43227b798a707c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: T Position. <a href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">More...</a><br/></td></tr>
<tr class="separator:gaa1134ff3e774b1354a43227b798a707c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga23ed422711cbd2f9a5dcbe6c05b2a720">CPSR_T_Msk</a>   (1UL << CPSR_T_Pos)</td></tr>
<tr class="memdesc:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: T Mask. <a href="group__CMSIS__CPSR__BITS.html#ga23ed422711cbd2f9a5dcbe6c05b2a720">More...</a><br/></td></tr>
<tr class="separator:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">CPSR_M_Pos</a>   0U</td></tr>
<tr class="memdesc:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Position. <a href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">More...</a><br/></td></tr>
<tr class="separator:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadce47959b814f70f802a139250daa04c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gadce47959b814f70f802a139250daa04c">CPSR_M_Msk</a>   (0x1FUL << CPSR_M_Pos)</td></tr>
<tr class="memdesc:gadce47959b814f70f802a139250daa04c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Mask. <a href="group__CMSIS__CPSR__BITS.html#gadce47959b814f70f802a139250daa04c">More...</a><br/></td></tr>
<tr class="separator:gadce47959b814f70f802a139250daa04c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e">CPSR_M_USR</a>   0x10U</td></tr>
<tr class="memdesc:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M User mode (PL0) <a href="group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e">More...</a><br/></td></tr>
<tr class="separator:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga868ef12e003f541f90a613ca7f6ada74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74">CPSR_M_FIQ</a>   0x11U</td></tr>
<tr class="memdesc:ga868ef12e003f541f90a613ca7f6ada74"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Fast Interrupt mode (PL1) <a href="group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74">More...</a><br/></td></tr>
<tr class="separator:ga868ef12e003f541f90a613ca7f6ada74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db">CPSR_M_IRQ</a>   0x12U</td></tr>
<tr class="memdesc:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Interrupt mode (PL1) <a href="group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db">More...</a><br/></td></tr>
<tr class="separator:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga5afcb85bd2968acc2b09cb9d99c531ad">CPSR_M_SVC</a>   0x13U</td></tr>
<tr class="memdesc:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Supervisor mode (PL1) <a href="group__CMSIS__CPSR__M.html#ga5afcb85bd2968acc2b09cb9d99c531ad">More...</a><br/></td></tr>
<tr class="separator:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga69d734db93f67899b4bffcf62f80f098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098">CPSR_M_MON</a>   0x16U</td></tr>
<tr class="memdesc:ga69d734db93f67899b4bffcf62f80f098"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Monitor mode (PL1) <a href="group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098">More...</a><br/></td></tr>
<tr class="separator:ga69d734db93f67899b4bffcf62f80f098"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa">CPSR_M_ABT</a>   0x17U</td></tr>
<tr class="memdesc:gac8c0a99a21ef256f5d3115595a845bfa"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Abort mode (PL1) <a href="group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa">More...</a><br/></td></tr>
<tr class="separator:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988">CPSR_M_HYP</a>   0x1AU</td></tr>
<tr class="memdesc:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Hypervisor mode (PL2) <a href="group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988">More...</a><br/></td></tr>
<tr class="separator:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef">CPSR_M_UND</a>   0x1BU</td></tr>
<tr class="memdesc:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Undefined mode (PL1) <a href="group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef">More...</a><br/></td></tr>
<tr class="separator:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa0a3996ce096cd205bce34f90b10912c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c">CPSR_M_SYS</a>   0x1FU</td></tr>
<tr class="memdesc:gaa0a3996ce096cd205bce34f90b10912c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M System mode (PL1) <a href="group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c">More...</a><br/></td></tr>
<tr class="separator:gaa0a3996ce096cd205bce34f90b10912c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>   30U</td></tr>
<tr class="memdesc:gab0a611e2359e04624379e1ddd4dc64b1"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Position. <a href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">More...</a><br/></td></tr>
<tr class="separator:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b">SCTLR_TE_Msk</a>   (1UL << SCTLR_TE_Pos)</td></tr>
<tr class="memdesc:ga4a68d6660c76951ada2541ceaf040b3b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b">More...</a><br/></td></tr>
<tr class="separator:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>   29U</td></tr>
<tr class="memdesc:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Position. <a href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">More...</a><br/></td></tr>
<tr class="separator:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957">SCTLR_AFE_Msk</a>   (1UL << SCTLR_AFE_Pos)</td></tr>
<tr class="memdesc:ga9016d6e50562d2584c1f1a95bde1e957"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957">More...</a><br/></td></tr>
<tr class="separator:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>   28U</td></tr>
<tr class="memdesc:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Position. <a href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">More...</a><br/></td></tr>
<tr class="separator:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab0481eb9812a4908601cb20c8ae84918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918">SCTLR_TRE_Msk</a>   (1UL << SCTLR_TRE_Pos)</td></tr>
<tr class="memdesc:gab0481eb9812a4908601cb20c8ae84918"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Mask. <a href="group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918">More...</a><br/></td></tr>
<tr class="separator:gab0481eb9812a4908601cb20c8ae84918"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>   27U</td></tr>
<tr class="memdesc:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Position. <a href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">More...</a><br/></td></tr>
<tr class="separator:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279">SCTLR_NMFI_Msk</a>   (1UL << SCTLR_NMFI_Pos)</td></tr>
<tr class="memdesc:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Mask. <a href="group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279">More...</a><br/></td></tr>
<tr class="separator:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0baec19421bd41277c5d8783c59942fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>   25U</td></tr>
<tr class="memdesc:ga0baec19421bd41277c5d8783c59942fa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Position. <a href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">More...</a><br/></td></tr>
<tr class="separator:ga0baec19421bd41277c5d8783c59942fa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044">SCTLR_EE_Msk</a>   (1UL << SCTLR_EE_Pos)</td></tr>
<tr class="memdesc:ga8d95cd61bc40dc77f8855f40c797d044"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044">More...</a><br/></td></tr>
<tr class="separator:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1372b569553a0740d881e24c0be7334f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>   24U</td></tr>
<tr class="memdesc:ga1372b569553a0740d881e24c0be7334f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Position. <a href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">More...</a><br/></td></tr>
<tr class="separator:ga1372b569553a0740d881e24c0be7334f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad94a7feadba850299a68c56e39c0b274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274">SCTLR_VE_Msk</a>   (1UL << SCTLR_VE_Pos)</td></tr>
<tr class="memdesc:gad94a7feadba850299a68c56e39c0b274"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Mask. <a href="group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274">More...</a><br/></td></tr>
<tr class="separator:gad94a7feadba850299a68c56e39c0b274"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa0431730d7ce929db03d8accee558e17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>   22U</td></tr>
<tr class="memdesc:gaa0431730d7ce929db03d8accee558e17"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Position. <a href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">More...</a><br/></td></tr>
<tr class="separator:gaa0431730d7ce929db03d8accee558e17"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f">SCTLR_U_Msk</a>   (1UL << SCTLR_U_Pos)</td></tr>
<tr class="memdesc:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Mask. <a href="group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f">More...</a><br/></td></tr>
<tr class="separator:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad88d563fa9a8b09fe36702a5329b0360"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>   21U</td></tr>
<tr class="memdesc:gad88d563fa9a8b09fe36702a5329b0360"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Position. <a href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">More...</a><br/></td></tr>
<tr class="separator:gad88d563fa9a8b09fe36702a5329b0360"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc">SCTLR_FI_Msk</a>   (1UL << SCTLR_FI_Pos)</td></tr>
<tr class="memdesc:ga316b80925b88fe3b88ec46a55655b0bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc">More...</a><br/></td></tr>
<tr class="separator:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>   20U</td></tr>
<tr class="memdesc:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Position. <a href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">More...</a><br/></td></tr>
<tr class="separator:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab834e64e0da7c2a98d747ce73252c199"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199">SCTLR_UWXN_Msk</a>   (1UL << SCTLR_UWXN_Pos)</td></tr>
<tr class="memdesc:gab834e64e0da7c2a98d747ce73252c199"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Mask. <a href="group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199">More...</a><br/></td></tr>
<tr class="separator:gab834e64e0da7c2a98d747ce73252c199"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf145654986fd6d014136580ad279d256"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>   19U</td></tr>
<tr class="memdesc:gaf145654986fd6d014136580ad279d256"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Position. <a href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">More...</a><br/></td></tr>
<tr class="separator:gaf145654986fd6d014136580ad279d256"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga510b03214d135f15ad3c5d41ec20a291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291">SCTLR_WXN_Msk</a>   (1UL << SCTLR_WXN_Pos)</td></tr>
<tr class="memdesc:ga510b03214d135f15ad3c5d41ec20a291"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291">More...</a><br/></td></tr>
<tr class="separator:ga510b03214d135f15ad3c5d41ec20a291"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>   17U</td></tr>
<tr class="memdesc:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Position. <a href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">More...</a><br/></td></tr>
<tr class="separator:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6830e9bf54a6b548f329ac047f59c179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179">SCTLR_HA_Msk</a>   (1UL << SCTLR_HA_Pos)</td></tr>
<tr class="memdesc:ga6830e9bf54a6b548f329ac047f59c179"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179">More...</a><br/></td></tr>
<tr class="separator:ga6830e9bf54a6b548f329ac047f59c179"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga86e5b78ba8f818061644688db75ddc64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>   14U</td></tr>
<tr class="memdesc:ga86e5b78ba8f818061644688db75ddc64"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Position. <a href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">More...</a><br/></td></tr>
<tr class="separator:ga86e5b78ba8f818061644688db75ddc64"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc">SCTLR_RR_Msk</a>   (1UL << SCTLR_RR_Pos)</td></tr>
<tr class="memdesc:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc">More...</a><br/></td></tr>
<tr class="separator:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>   13U</td></tr>
<tr class="memdesc:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Position. <a href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">More...</a><br/></td></tr>
<tr class="separator:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11">SCTLR_V_Msk</a>   (1UL << SCTLR_V_Pos)</td></tr>
<tr class="memdesc:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Mask. <a href="group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11">More...</a><br/></td></tr>
<tr class="separator:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>   12U</td></tr>
<tr class="memdesc:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Position. <a href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">More...</a><br/></td></tr>
<tr class="separator:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666">SCTLR_I_Msk</a>   (1UL << SCTLR_I_Pos)</td></tr>
<tr class="memdesc:gab3cc0744fb07127e3c0f18cba9d51666"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Mask. <a href="group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666">More...</a><br/></td></tr>
<tr class="separator:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa0eade648c9a34de891af0e6f47857dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>   11U</td></tr>
<tr class="memdesc:gaa0eade648c9a34de891af0e6f47857dd"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Position. <a href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">More...</a><br/></td></tr>
<tr class="separator:gaa0eade648c9a34de891af0e6f47857dd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga12a05acdcb8db6e99970f26206d3067c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c">SCTLR_Z_Msk</a>   (1UL << SCTLR_Z_Pos)</td></tr>
<tr class="memdesc:ga12a05acdcb8db6e99970f26206d3067c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c">More...</a><br/></td></tr>
<tr class="separator:ga12a05acdcb8db6e99970f26206d3067c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>   10U</td></tr>
<tr class="memdesc:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Position. <a href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">More...</a><br/></td></tr>
<tr class="separator:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae4074aefcf01786fe199c82e273271b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8">SCTLR_SW_Msk</a>   (1UL << SCTLR_SW_Pos)</td></tr>
<tr class="memdesc:gae4074aefcf01786fe199c82e273271b8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Mask. <a href="group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8">More...</a><br/></td></tr>
<tr class="separator:gae4074aefcf01786fe199c82e273271b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>   7U</td></tr>
<tr class="memdesc:ga5f185efbe1a9eb5738b2573f076a0859"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Position. <a href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">More...</a><br/></td></tr>
<tr class="separator:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6">SCTLR_B_Msk</a>   (1UL << SCTLR_B_Pos)</td></tr>
<tr class="memdesc:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6">More...</a><br/></td></tr>
<tr class="separator:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gace284f69e1a810957665adf0cb2e4b2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>   5U</td></tr>
<tr class="memdesc:gace284f69e1a810957665adf0cb2e4b2b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Position. <a href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">More...</a><br/></td></tr>
<tr class="separator:gace284f69e1a810957665adf0cb2e4b2b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac">SCTLR_CP15BEN_Msk</a>   (1UL << SCTLR_CP15BEN_Pos)</td></tr>
<tr class="memdesc:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac">More...</a><br/></td></tr>
<tr class="separator:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8a0394c5147b8212767087e3421deffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>   2U</td></tr>
<tr class="memdesc:ga8a0394c5147b8212767087e3421deffa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Position. <a href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">More...</a><br/></td></tr>
<tr class="separator:ga8a0394c5147b8212767087e3421deffa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2be72788d984153ded81711e20fd2d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33">SCTLR_C_Msk</a>   (1UL << SCTLR_C_Pos)</td></tr>
<tr class="memdesc:ga2be72788d984153ded81711e20fd2d33"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33">More...</a><br/></td></tr>
<tr class="separator:ga2be72788d984153ded81711e20fd2d33"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0d667a307e974515ebc15b5249f34146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>   1U</td></tr>
<tr class="memdesc:ga0d667a307e974515ebc15b5249f34146"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Position. <a href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">More...</a><br/></td></tr>
<tr class="separator:ga0d667a307e974515ebc15b5249f34146"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga678c919832272745678213e55211e741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741">SCTLR_A_Msk</a>   (1UL << SCTLR_A_Pos)</td></tr>
<tr class="memdesc:ga678c919832272745678213e55211e741"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Mask. <a href="group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741">More...</a><br/></td></tr>
<tr class="separator:ga678c919832272745678213e55211e741"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga88e34078fa8cf719aab6f53f138c9810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>   0U</td></tr>
<tr class="memdesc:ga88e34078fa8cf719aab6f53f138c9810"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Position. <a href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">More...</a><br/></td></tr>
<tr class="separator:ga88e34078fa8cf719aab6f53f138c9810"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf460824cdbf549bd914aa79762572e8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e">SCTLR_M_Msk</a>   (1UL << SCTLR_M_Pos)</td></tr>
<tr class="memdesc:gaf460824cdbf549bd914aa79762572e8e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Mask. <a href="group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e">More...</a><br/></td></tr>
<tr class="separator:gaf460824cdbf549bd914aa79762572e8e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5468e93550ce28af7114cbc1e19474c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">ACTLR_DDI_Pos</a>   28U</td></tr>
<tr class="memdesc:ga5468e93550ce28af7114cbc1e19474c0"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDI Position. <a href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">More...</a><br/></td></tr>
<tr class="separator:ga5468e93550ce28af7114cbc1e19474c0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaeee8e0fc7b28f2a405b234e7d2c7486e">ACTLR_DDI_Msk</a>   (1UL << ACTLR_DDI_Pos)</td></tr>
<tr class="memdesc:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDI Mask. <a href="group__CMSIS__ACTLR__BITS.html#gaeee8e0fc7b28f2a405b234e7d2c7486e">More...</a><br/></td></tr>
<tr class="separator:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">ACTLR_DBDI_Pos</a>   28U</td></tr>
<tr class="memdesc:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DBDI Position. <a href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">More...</a><br/></td></tr>
<tr class="separator:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0a3d58754927731758c53bd945ac35fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0a3d58754927731758c53bd945ac35fe">ACTLR_DBDI_Msk</a>   (1UL << ACTLR_DBDI_Pos)</td></tr>
<tr class="memdesc:ga0a3d58754927731758c53bd945ac35fe"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DBDI Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga0a3d58754927731758c53bd945ac35fe">More...</a><br/></td></tr>
<tr class="separator:ga0a3d58754927731758c53bd945ac35fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8c81a1e1522400322f215c52ca80d47d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">ACTLR_BTDIS_Pos</a>   18U</td></tr>
<tr class="memdesc:ga8c81a1e1522400322f215c52ca80d47d"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BTDIS Position. <a href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">More...</a><br/></td></tr>
<tr class="separator:ga8c81a1e1522400322f215c52ca80d47d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad48e0a1c1e59e6721547b45f37baa48b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad48e0a1c1e59e6721547b45f37baa48b">ACTLR_BTDIS_Msk</a>   (1UL << ACTLR_BTDIS_Pos)</td></tr>
<tr class="memdesc:gad48e0a1c1e59e6721547b45f37baa48b"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BTDIS Mask. <a href="group__CMSIS__ACTLR__BITS.html#gad48e0a1c1e59e6721547b45f37baa48b">More...</a><br/></td></tr>
<tr class="separator:gad48e0a1c1e59e6721547b45f37baa48b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">ACTLR_RSDIS_Pos</a>   17U</td></tr>
<tr class="memdesc:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RSDIS Position. <a href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">More...</a><br/></td></tr>
<tr class="separator:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8487babc3514e2bb8f3d524e5f80d95f">ACTLR_RSDIS_Msk</a>   (1UL << ACTLR_RSDIS_Pos)</td></tr>
<tr class="memdesc:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RSDIS Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga8487babc3514e2bb8f3d524e5f80d95f">More...</a><br/></td></tr>
<tr class="separator:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga120f5d653af52bd711c27c2495ce78f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">ACTLR_BP_Pos</a>   15U</td></tr>
<tr class="memdesc:ga120f5d653af52bd711c27c2495ce78f6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BP Position. <a href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">More...</a><br/></td></tr>
<tr class="separator:ga120f5d653af52bd711c27c2495ce78f6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga677211818d8a2c7b118115361fbef2e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga677211818d8a2c7b118115361fbef2e7">ACTLR_BP_Msk</a>   (3UL << ACTLR_BP_Pos)</td></tr>
<tr class="memdesc:ga677211818d8a2c7b118115361fbef2e7"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BP Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga677211818d8a2c7b118115361fbef2e7">More...</a><br/></td></tr>
<tr class="separator:ga677211818d8a2c7b118115361fbef2e7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">ACTLR_DDVM_Pos</a>   15U</td></tr>
<tr class="memdesc:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDVM Position. <a href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">More...</a><br/></td></tr>
<tr class="separator:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4565f2632e5c4be5e1d3eb90fa6f2ac6">ACTLR_DDVM_Msk</a>   (1UL << ACTLR_DDVM_Pos)</td></tr>
<tr class="memdesc:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDVM Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga4565f2632e5c4be5e1d3eb90fa6f2ac6">More...</a><br/></td></tr>
<tr class="separator:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga546f1f2bbf7344bad6522205257f17ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">ACTLR_L1PCTL_Pos</a>   13U</td></tr>
<tr class="memdesc:ga546f1f2bbf7344bad6522205257f17ae"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PCTL Position. <a href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">More...</a><br/></td></tr>
<tr class="separator:ga546f1f2bbf7344bad6522205257f17ae"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad701fa3ff69b89ba185b7482e81cb6fd">ACTLR_L1PCTL_Msk</a>   (3UL << ACTLR_L1PCTL_Pos)</td></tr>
<tr class="memdesc:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PCTL Mask. <a href="group__CMSIS__ACTLR__BITS.html#gad701fa3ff69b89ba185b7482e81cb6fd">More...</a><br/></td></tr>
<tr class="separator:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">ACTLR_RADIS_Pos</a>   12U</td></tr>
<tr class="memdesc:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RADIS Position. <a href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">More...</a><br/></td></tr>
<tr class="separator:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac6aea849e5320c0e93321d5d8b0c117c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gac6aea849e5320c0e93321d5d8b0c117c">ACTLR_RADIS_Msk</a>   (1UL << ACTLR_RADIS_Pos)</td></tr>
<tr class="memdesc:gac6aea849e5320c0e93321d5d8b0c117c"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RADIS Mask. <a href="group__CMSIS__ACTLR__BITS.html#gac6aea849e5320c0e93321d5d8b0c117c">More...</a><br/></td></tr>
<tr class="separator:gac6aea849e5320c0e93321d5d8b0c117c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf8b306b854ecd78110cf944d414644a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">ACTLR_L1RADIS_Pos</a>   12U</td></tr>
<tr class="memdesc:gaf8b306b854ecd78110cf944d414644a1"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1RADIS Position. <a href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">More...</a><br/></td></tr>
<tr class="separator:gaf8b306b854ecd78110cf944d414644a1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6aafd83ca6c02f705def8edc8c064c04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga6aafd83ca6c02f705def8edc8c064c04">ACTLR_L1RADIS_Msk</a>   (1UL << ACTLR_L1RADIS_Pos)</td></tr>
<tr class="memdesc:ga6aafd83ca6c02f705def8edc8c064c04"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1RADIS Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga6aafd83ca6c02f705def8edc8c064c04">More...</a><br/></td></tr>
<tr class="separator:ga6aafd83ca6c02f705def8edc8c064c04"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">ACTLR_DWBST_Pos</a>   11U</td></tr>
<tr class="memdesc:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DWBST Position. <a href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">More...</a><br/></td></tr>
<tr class="separator:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab948ab9af88a9357e2e383d948e9dc7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gab948ab9af88a9357e2e383d948e9dc7e">ACTLR_DWBST_Msk</a>   (1UL << ACTLR_DWBST_Pos)</td></tr>
<tr class="memdesc:gab948ab9af88a9357e2e383d948e9dc7e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DWBST Mask. <a href="group__CMSIS__ACTLR__BITS.html#gab948ab9af88a9357e2e383d948e9dc7e">More...</a><br/></td></tr>
<tr class="separator:gab948ab9af88a9357e2e383d948e9dc7e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">ACTLR_L2RADIS_Pos</a>   11U</td></tr>
<tr class="memdesc:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L2RADIS Position. <a href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">More...</a><br/></td></tr>
<tr class="separator:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad84b20f4f5d1979bb000a14a582cad12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad84b20f4f5d1979bb000a14a582cad12">ACTLR_L2RADIS_Msk</a>   (1UL << ACTLR_L2RADIS_Pos)</td></tr>
<tr class="memdesc:gad84b20f4f5d1979bb000a14a582cad12"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L2RADIS Mask. <a href="group__CMSIS__ACTLR__BITS.html#gad84b20f4f5d1979bb000a14a582cad12">More...</a><br/></td></tr>
<tr class="separator:gad84b20f4f5d1979bb000a14a582cad12"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">ACTLR_DODMBS_Pos</a>   10U</td></tr>
<tr class="memdesc:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DODMBS Position. <a href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">More...</a><br/></td></tr>
<tr class="separator:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga88a85e6310334edb190a6e9298ae98b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga88a85e6310334edb190a6e9298ae98b7">ACTLR_DODMBS_Msk</a>   (1UL << ACTLR_DODMBS_Pos)</td></tr>
<tr class="memdesc:ga88a85e6310334edb190a6e9298ae98b7"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DODMBS Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga88a85e6310334edb190a6e9298ae98b7">More...</a><br/></td></tr>
<tr class="separator:ga88a85e6310334edb190a6e9298ae98b7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8300a65b41aa3f5c69c7cc713c847749"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">ACTLR_PARITY_Pos</a>   9U</td></tr>
<tr class="memdesc:ga8300a65b41aa3f5c69c7cc713c847749"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: PARITY Position. <a href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">More...</a><br/></td></tr>
<tr class="separator:ga8300a65b41aa3f5c69c7cc713c847749"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadec8e5d68791dc4749bf3f075a3559fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gadec8e5d68791dc4749bf3f075a3559fb">ACTLR_PARITY_Msk</a>   (1UL << ACTLR_PARITY_Pos)</td></tr>
<tr class="memdesc:gadec8e5d68791dc4749bf3f075a3559fb"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: PARITY Mask. <a href="group__CMSIS__ACTLR__BITS.html#gadec8e5d68791dc4749bf3f075a3559fb">More...</a><br/></td></tr>
<tr class="separator:gadec8e5d68791dc4749bf3f075a3559fb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga633ee6b129f8668593687ab8537aeb7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">ACTLR_AOW_Pos</a>   8U</td></tr>
<tr class="memdesc:ga633ee6b129f8668593687ab8537aeb7f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: AOW Position. <a href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">More...</a><br/></td></tr>
<tr class="separator:ga633ee6b129f8668593687ab8537aeb7f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5ca6754c31f90c7e5d1822dddfb4135c">ACTLR_AOW_Msk</a>   (1UL << ACTLR_AOW_Pos)</td></tr>
<tr class="memdesc:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: AOW Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga5ca6754c31f90c7e5d1822dddfb4135c">More...</a><br/></td></tr>
<tr class="separator:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga17dcfbcdf5db82900354db5440699701"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">ACTLR_EXCL_Pos</a>   7U</td></tr>
<tr class="memdesc:ga17dcfbcdf5db82900354db5440699701"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: EXCL Position. <a href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">More...</a><br/></td></tr>
<tr class="separator:ga17dcfbcdf5db82900354db5440699701"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8b704419a7ed130ecbee00de9fd72d55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8b704419a7ed130ecbee00de9fd72d55">ACTLR_EXCL_Msk</a>   (1UL << ACTLR_EXCL_Pos)</td></tr>
<tr class="memdesc:ga8b704419a7ed130ecbee00de9fd72d55"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: EXCL Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga8b704419a7ed130ecbee00de9fd72d55">More...</a><br/></td></tr>
<tr class="separator:ga8b704419a7ed130ecbee00de9fd72d55"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">ACTLR_SMP_Pos</a>   6U</td></tr>
<tr class="memdesc:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: SMP Position. <a href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">More...</a><br/></td></tr>
<tr class="separator:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac6dcc315f6c4527434b9b0e4106771d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gac6dcc315f6c4527434b9b0e4106771d8">ACTLR_SMP_Msk</a>   (1UL << ACTLR_SMP_Pos)</td></tr>
<tr class="memdesc:gac6dcc315f6c4527434b9b0e4106771d8"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: SMP Mask. <a href="group__CMSIS__ACTLR__BITS.html#gac6dcc315f6c4527434b9b0e4106771d8">More...</a><br/></td></tr>
<tr class="separator:gac6dcc315f6c4527434b9b0e4106771d8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga104112fe1d88dde49635e9b0f9530306"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">ACTLR_WFLZM_Pos</a>   3U</td></tr>
<tr class="memdesc:ga104112fe1d88dde49635e9b0f9530306"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: WFLZM Position. <a href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">More...</a><br/></td></tr>
<tr class="separator:ga104112fe1d88dde49635e9b0f9530306"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae5a89cb553773b10e86a9c826f11179f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gae5a89cb553773b10e86a9c826f11179f">ACTLR_WFLZM_Msk</a>   (1UL << ACTLR_WFLZM_Pos)</td></tr>
<tr class="memdesc:gae5a89cb553773b10e86a9c826f11179f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: WFLZM Mask. <a href="group__CMSIS__ACTLR__BITS.html#gae5a89cb553773b10e86a9c826f11179f">More...</a><br/></td></tr>
<tr class="separator:gae5a89cb553773b10e86a9c826f11179f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">ACTLR_L1PE_Pos</a>   2U</td></tr>
<tr class="memdesc:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PE Position. <a href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">More...</a><br/></td></tr>
<tr class="separator:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga969c20495fe3e50e8c2a73454688a674"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga969c20495fe3e50e8c2a73454688a674">ACTLR_L1PE_Msk</a>   (1UL << ACTLR_L1PE_Pos)</td></tr>
<tr class="memdesc:ga969c20495fe3e50e8c2a73454688a674"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PE Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga969c20495fe3e50e8c2a73454688a674">More...</a><br/></td></tr>
<tr class="separator:ga969c20495fe3e50e8c2a73454688a674"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga89b1a661668534177bc9679149a692ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">ACTLR_FW_Pos</a>   0U</td></tr>
<tr class="memdesc:ga89b1a661668534177bc9679149a692ce"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: FW Position. <a href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">More...</a><br/></td></tr>
<tr class="separator:ga89b1a661668534177bc9679149a692ce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1">ACTLR_FW_Msk</a>   (1UL << ACTLR_FW_Pos)</td></tr>
<tr class="memdesc:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: FW Mask. <a href="group__CMSIS__ACTLR__BITS.html#ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1">More...</a><br/></td></tr>
<tr class="separator:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3acd342ab1e88bd4ad73f5670e7af163"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga3acd342ab1e88bd4ad73f5670e7af163">CPACR_ASEDIS_Pos</a>   31U</td></tr>
<tr class="memdesc:ga3acd342ab1e88bd4ad73f5670e7af163"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: ASEDIS Position. <a href="group__CMSIS__CPACR__BITS.html#ga3acd342ab1e88bd4ad73f5670e7af163">More...</a><br/></td></tr>
<tr class="separator:ga3acd342ab1e88bd4ad73f5670e7af163"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga46d28804bfa370b0dd4ac520a7a67609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga46d28804bfa370b0dd4ac520a7a67609">CPACR_ASEDIS_Msk</a>   (1UL << CPACR_ASEDIS_Pos)</td></tr>
<tr class="memdesc:ga46d28804bfa370b0dd4ac520a7a67609"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: ASEDIS Mask. <a href="group__CMSIS__CPACR__BITS.html#ga46d28804bfa370b0dd4ac520a7a67609">More...</a><br/></td></tr>
<tr class="separator:ga46d28804bfa370b0dd4ac520a7a67609"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6df0c4e805105285e63b0f0e992bd416"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga6df0c4e805105285e63b0f0e992bd416">CPACR_D32DIS_Pos</a>   30U</td></tr>
<tr class="memdesc:ga6df0c4e805105285e63b0f0e992bd416"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Position. <a href="group__CMSIS__CPACR__BITS.html#ga6df0c4e805105285e63b0f0e992bd416">More...</a><br/></td></tr>
<tr class="separator:ga6df0c4e805105285e63b0f0e992bd416"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga96266eb6bf35c3c3f22718bd06b12d79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga96266eb6bf35c3c3f22718bd06b12d79">CPACR_D32DIS_Msk</a>   (1UL << CPACR_D32DIS_Pos)</td></tr>
<tr class="memdesc:ga96266eb6bf35c3c3f22718bd06b12d79"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Mask. <a href="group__CMSIS__CPACR__BITS.html#ga96266eb6bf35c3c3f22718bd06b12d79">More...</a><br/></td></tr>
<tr class="separator:ga96266eb6bf35c3c3f22718bd06b12d79"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6866c97020fdba42f7c287433c58d77c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga6866c97020fdba42f7c287433c58d77c">CPACR_TRCDIS_Pos</a>   28U</td></tr>
<tr class="memdesc:ga6866c97020fdba42f7c287433c58d77c"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Position. <a href="group__CMSIS__CPACR__BITS.html#ga6866c97020fdba42f7c287433c58d77c">More...</a><br/></td></tr>
<tr class="separator:ga6866c97020fdba42f7c287433c58d77c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab5d6ec83339e755bd3e7eacb914edf37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#gab5d6ec83339e755bd3e7eacb914edf37">CPACR_TRCDIS_Msk</a>   (1UL << CPACR_D32DIS_Pos)</td></tr>
<tr class="memdesc:gab5d6ec83339e755bd3e7eacb914edf37"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Mask. <a href="group__CMSIS__CPACR__BITS.html#gab5d6ec83339e755bd3e7eacb914edf37">More...</a><br/></td></tr>
<tr class="separator:gab5d6ec83339e755bd3e7eacb914edf37"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga77dc035e6d16dee8f5cf53b36b86cfaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga77dc035e6d16dee8f5cf53b36b86cfaf">CPACR_CP_Pos_</a>(n)   (n*2U)</td></tr>
<tr class="memdesc:ga77dc035e6d16dee8f5cf53b36b86cfaf"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: CPn Position. <a href="group__CMSIS__CPACR__BITS.html#ga77dc035e6d16dee8f5cf53b36b86cfaf">More...</a><br/></td></tr>
<tr class="separator:ga77dc035e6d16dee8f5cf53b36b86cfaf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7c87723442baa681a80de8f644eda1a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga7c87723442baa681a80de8f644eda1a2">CPACR_CP_Msk_</a>(n)   (3UL << CPACR_CP_Pos_(n))</td></tr>
<tr class="memdesc:ga7c87723442baa681a80de8f644eda1a2"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: CPn Mask. <a href="group__CMSIS__CPACR__BITS.html#ga7c87723442baa681a80de8f644eda1a2">More...</a><br/></td></tr>
<tr class="separator:ga7c87723442baa681a80de8f644eda1a2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd03f590b34b809438eaa3df4af2e7db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__CP.html#gabd03f590b34b809438eaa3df4af2e7db">CPACR_CP_NA</a>   0U</td></tr>
<tr class="memdesc:gabd03f590b34b809438eaa3df4af2e7db"><td class="mdescLeft"> </td><td class="mdescRight">CPACR CPn field: Access denied. <a href="group__CMSIS__CPACR__CP.html#gabd03f590b34b809438eaa3df4af2e7db">More...</a><br/></td></tr>
<tr class="separator:gabd03f590b34b809438eaa3df4af2e7db"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8602342c0bad80f3a36d3bdee7418a46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__CP.html#ga8602342c0bad80f3a36d3bdee7418a46">CPACR_CP_PL1</a>   1U</td></tr>
<tr class="memdesc:ga8602342c0bad80f3a36d3bdee7418a46"><td class="mdescLeft"> </td><td class="mdescRight">CPACR CPn field: Accessible from PL1 only. <a href="group__CMSIS__CPACR__CP.html#ga8602342c0bad80f3a36d3bdee7418a46">More...</a><br/></td></tr>
<tr class="separator:ga8602342c0bad80f3a36d3bdee7418a46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeaa29f06a74fadc7245d6bd183bad11b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__CP.html#gaeaa29f06a74fadc7245d6bd183bad11b">CPACR_CP_FA</a>   3U</td></tr>
<tr class="memdesc:gaeaa29f06a74fadc7245d6bd183bad11b"><td class="mdescLeft"> </td><td class="mdescRight">CPACR CPn field: Full access. <a href="group__CMSIS__CPACR__CP.html#gaeaa29f06a74fadc7245d6bd183bad11b">More...</a><br/></td></tr>
<tr class="separator:gaeaa29f06a74fadc7245d6bd183bad11b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac1c7d8f30e77bd1fe395d6e9a5a63a3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gac1c7d8f30e77bd1fe395d6e9a5a63a3e">DFSR_CM_Pos</a>   13U</td></tr>
<tr class="memdesc:gac1c7d8f30e77bd1fe395d6e9a5a63a3e"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: CM Position. <a href="group__CMSIS__DFSR__BITS.html#gac1c7d8f30e77bd1fe395d6e9a5a63a3e">More...</a><br/></td></tr>
<tr class="separator:gac1c7d8f30e77bd1fe395d6e9a5a63a3e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga91cf285dc43beda62ae72f043e83238c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga91cf285dc43beda62ae72f043e83238c">DFSR_CM_Msk</a>   (1UL << DFSR_CM_Pos)</td></tr>
<tr class="memdesc:ga91cf285dc43beda62ae72f043e83238c"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: CM Mask. <a href="group__CMSIS__DFSR__BITS.html#ga91cf285dc43beda62ae72f043e83238c">More...</a><br/></td></tr>
<tr class="separator:ga91cf285dc43beda62ae72f043e83238c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8cc8dcb1b3a971a13b0575bf9083acf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga8cc8dcb1b3a971a13b0575bf9083acf5">DFSR_Ext_Pos</a>   12U</td></tr>
<tr class="memdesc:ga8cc8dcb1b3a971a13b0575bf9083acf5"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Ext Position. <a href="group__CMSIS__DFSR__BITS.html#ga8cc8dcb1b3a971a13b0575bf9083acf5">More...</a><br/></td></tr>
<tr class="separator:ga8cc8dcb1b3a971a13b0575bf9083acf5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad3a97b4eb87f45df8ae539e59592f21b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gad3a97b4eb87f45df8ae539e59592f21b">DFSR_Ext_Msk</a>   (1UL << DFSR_Ext_Pos)</td></tr>
<tr class="memdesc:gad3a97b4eb87f45df8ae539e59592f21b"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Ext Mask. <a href="group__CMSIS__DFSR__BITS.html#gad3a97b4eb87f45df8ae539e59592f21b">More...</a><br/></td></tr>
<tr class="separator:gad3a97b4eb87f45df8ae539e59592f21b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga410420633e9ba47cdd1ae2d3df146866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga410420633e9ba47cdd1ae2d3df146866">DFSR_WnR_Pos</a>   11U</td></tr>
<tr class="memdesc:ga410420633e9ba47cdd1ae2d3df146866"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: WnR Position. <a href="group__CMSIS__DFSR__BITS.html#ga410420633e9ba47cdd1ae2d3df146866">More...</a><br/></td></tr>
<tr class="separator:ga410420633e9ba47cdd1ae2d3df146866"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabfbf482895e7620fe6727b54378c0f2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gabfbf482895e7620fe6727b54378c0f2a">DFSR_WnR_Msk</a>   (1UL << DFSR_WnR_Pos)</td></tr>
<tr class="memdesc:gabfbf482895e7620fe6727b54378c0f2a"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: WnR Mask. <a href="group__CMSIS__DFSR__BITS.html#gabfbf482895e7620fe6727b54378c0f2a">More...</a><br/></td></tr>
<tr class="separator:gabfbf482895e7620fe6727b54378c0f2a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3faee10970931cadf7ff16069ce65a1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga3faee10970931cadf7ff16069ce65a1a">DFSR_FS1_Pos</a>   10U</td></tr>
<tr class="memdesc:ga3faee10970931cadf7ff16069ce65a1a"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS1 Position. <a href="group__CMSIS__DFSR__BITS.html#ga3faee10970931cadf7ff16069ce65a1a">More...</a><br/></td></tr>
<tr class="separator:ga3faee10970931cadf7ff16069ce65a1a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6540a3ca5b2dcf8f81bb37fbdbe9d746"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga6540a3ca5b2dcf8f81bb37fbdbe9d746">DFSR_FS1_Msk</a>   (1UL << DFSR_FS1_Pos)</td></tr>
<tr class="memdesc:ga6540a3ca5b2dcf8f81bb37fbdbe9d746"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS1 Mask. <a href="group__CMSIS__DFSR__BITS.html#ga6540a3ca5b2dcf8f81bb37fbdbe9d746">More...</a><br/></td></tr>
<tr class="separator:ga6540a3ca5b2dcf8f81bb37fbdbe9d746"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga10f7b48c4f128c9be07c377bb60cfa7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga10f7b48c4f128c9be07c377bb60cfa7a">DFSR_LPAE_Pos</a>   9U</td></tr>
<tr class="memdesc:ga10f7b48c4f128c9be07c377bb60cfa7a"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: LPAE Position. <a href="group__CMSIS__DFSR__BITS.html#ga10f7b48c4f128c9be07c377bb60cfa7a">More...</a><br/></td></tr>
<tr class="separator:ga10f7b48c4f128c9be07c377bb60cfa7a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga104bfa1e333340616fdbdc804948276f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga104bfa1e333340616fdbdc804948276f">DFSR_LPAE_Msk</a>   (1UL << DFSR_LPAE_Pos)</td></tr>
<tr class="memdesc:ga104bfa1e333340616fdbdc804948276f"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: LPAE Mask. <a href="group__CMSIS__DFSR__BITS.html#ga104bfa1e333340616fdbdc804948276f">More...</a><br/></td></tr>
<tr class="separator:ga104bfa1e333340616fdbdc804948276f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac5a7afc43963dbc429792fb5a1569e15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gac5a7afc43963dbc429792fb5a1569e15">DFSR_Domain_Pos</a>   4U</td></tr>
<tr class="memdesc:gac5a7afc43963dbc429792fb5a1569e15"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Domain Position. <a href="group__CMSIS__DFSR__BITS.html#gac5a7afc43963dbc429792fb5a1569e15">More...</a><br/></td></tr>
<tr class="separator:gac5a7afc43963dbc429792fb5a1569e15"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga59949776e069a5af7231ef63156f17cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga59949776e069a5af7231ef63156f17cf">DFSR_Domain_Msk</a>   (0xFUL << DFSR_Domain_Pos)</td></tr>
<tr class="memdesc:ga59949776e069a5af7231ef63156f17cf"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Domain Mask. <a href="group__CMSIS__DFSR__BITS.html#ga59949776e069a5af7231ef63156f17cf">More...</a><br/></td></tr>
<tr class="separator:ga59949776e069a5af7231ef63156f17cf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae5d9bc62e71693bd9dc2a84bb4c82082"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gae5d9bc62e71693bd9dc2a84bb4c82082">DFSR_FS0_Pos</a>   0U</td></tr>
<tr class="memdesc:gae5d9bc62e71693bd9dc2a84bb4c82082"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS0 Position. <a href="group__CMSIS__DFSR__BITS.html#gae5d9bc62e71693bd9dc2a84bb4c82082">More...</a><br/></td></tr>
<tr class="separator:gae5d9bc62e71693bd9dc2a84bb4c82082"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga23b688e81c0378b5cd75acb53896bb5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga23b688e81c0378b5cd75acb53896bb5e">DFSR_FS0_Msk</a>   (0xFUL << DFSR_FS0_Pos)</td></tr>
<tr class="memdesc:ga23b688e81c0378b5cd75acb53896bb5e"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS0 Mask. <a href="group__CMSIS__DFSR__BITS.html#ga23b688e81c0378b5cd75acb53896bb5e">More...</a><br/></td></tr>
<tr class="separator:ga23b688e81c0378b5cd75acb53896bb5e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacb6fae1908b12c4900e2cdcc320c6c11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gacb6fae1908b12c4900e2cdcc320c6c11">DFSR_STATUS_Pos</a>   0U</td></tr>
<tr class="memdesc:gacb6fae1908b12c4900e2cdcc320c6c11"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: STATUS Position. <a href="group__CMSIS__DFSR__BITS.html#gacb6fae1908b12c4900e2cdcc320c6c11">More...</a><br/></td></tr>
<tr class="separator:gacb6fae1908b12c4900e2cdcc320c6c11"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7541052737038d737fd9fe00b9815140"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga7541052737038d737fd9fe00b9815140">DFSR_STATUS_Msk</a>   (0x3FUL << DFSR_STATUS_Pos)</td></tr>
<tr class="memdesc:ga7541052737038d737fd9fe00b9815140"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: STATUS Mask. <a href="group__CMSIS__DFSR__BITS.html#ga7541052737038d737fd9fe00b9815140">More...</a><br/></td></tr>
<tr class="separator:ga7541052737038d737fd9fe00b9815140"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafb3d593ec56834b6a265744efd6340a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">IFSR_ExT_Pos</a>   12U</td></tr>
<tr class="memdesc:gafb3d593ec56834b6a265744efd6340a8"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: ExT Position. <a href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">More...</a><br/></td></tr>
<tr class="separator:gafb3d593ec56834b6a265744efd6340a8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab0083a1d82b370a7e5208e39267bda22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gab0083a1d82b370a7e5208e39267bda22">IFSR_ExT_Msk</a>   (1UL << IFSR_ExT_Pos)</td></tr>
<tr class="memdesc:gab0083a1d82b370a7e5208e39267bda22"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: ExT Mask. <a href="group__CMSIS__IFSR__BITS.html#gab0083a1d82b370a7e5208e39267bda22">More...</a><br/></td></tr>
<tr class="separator:gab0083a1d82b370a7e5208e39267bda22"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>   10U</td></tr>
<tr class="memdesc:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS1 Position. <a href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">More...</a><br/></td></tr>
<tr class="separator:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga6fc93a02fbd1c968c70786a84428fca6">IFSR_FS1_Msk</a>   (1UL << IFSR_FS1_Pos)</td></tr>
<tr class="memdesc:ga6fc93a02fbd1c968c70786a84428fca6"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS1 Mask. <a href="group__CMSIS__IFSR__BITS.html#ga6fc93a02fbd1c968c70786a84428fca6">More...</a><br/></td></tr>
<tr class="separator:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4">IFSR_LPAE_Pos</a>   9U</td></tr>
<tr class="memdesc:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: LPAE Position. <a href="group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4">More...</a><br/></td></tr>
<tr class="separator:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga20639ca32a866d7b021e455b7a5d24c6">IFSR_LPAE_Msk</a>   (0x1UL << IFSR_LPAE_Pos)</td></tr>
<tr class="memdesc:ga20639ca32a866d7b021e455b7a5d24c6"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: LPAE Mask. <a href="group__CMSIS__IFSR__BITS.html#ga20639ca32a866d7b021e455b7a5d24c6">More...</a><br/></td></tr>
<tr class="separator:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga487c29da2f2d648f149c4346f3093f72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">IFSR_FS0_Pos</a>   0U</td></tr>
<tr class="memdesc:ga487c29da2f2d648f149c4346f3093f72"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS0 Position. <a href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">More...</a><br/></td></tr>
<tr class="separator:ga487c29da2f2d648f149c4346f3093f72"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaa17676ff0276b0fe93f92010fe35f6b8">IFSR_FS0_Msk</a>   (0xFUL << IFSR_FS0_Pos)</td></tr>
<tr class="memdesc:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS0 Mask. <a href="group__CMSIS__IFSR__BITS.html#gaa17676ff0276b0fe93f92010fe35f6b8">More...</a><br/></td></tr>
<tr class="separator:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">IFSR_STATUS_Pos</a>   0U</td></tr>
<tr class="memdesc:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: STATUS Position. <a href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">More...</a><br/></td></tr>
<tr class="separator:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">IFSR_STATUS_Msk</a>   (0x3FUL << IFSR_STATUS_Pos)</td></tr>
<tr class="memdesc:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: STATUS Mask. <a href="group__CMSIS__IFSR__BITS.html#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">More...</a><br/></td></tr>
<tr class="separator:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaecf0a2cb278bfd27e0da4ab8126d98af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#gaecf0a2cb278bfd27e0da4ab8126d98af">ISR_A_Pos</a>   13U</td></tr>
<tr class="memdesc:gaecf0a2cb278bfd27e0da4ab8126d98af"><td class="mdescLeft"> </td><td class="mdescRight">ISR: A Position. <a href="group__CMSIS__ISR__BITS.html#gaecf0a2cb278bfd27e0da4ab8126d98af">More...</a><br/></td></tr>
<tr class="separator:gaecf0a2cb278bfd27e0da4ab8126d98af"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8c6d55d243da46ed7ca05c3941316c8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#ga8c6d55d243da46ed7ca05c3941316c8d">ISR_A_Msk</a>   (1UL << ISR_A_Pos)</td></tr>
<tr class="memdesc:ga8c6d55d243da46ed7ca05c3941316c8d"><td class="mdescLeft"> </td><td class="mdescRight">ISR: A Mask. <a href="group__CMSIS__ISR__BITS.html#ga8c6d55d243da46ed7ca05c3941316c8d">More...</a><br/></td></tr>
<tr class="separator:ga8c6d55d243da46ed7ca05c3941316c8d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9f51d4217c1394e52f5223a6cd382136"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#ga9f51d4217c1394e52f5223a6cd382136">ISR_I_Pos</a>   12U</td></tr>
<tr class="memdesc:ga9f51d4217c1394e52f5223a6cd382136"><td class="mdescLeft"> </td><td class="mdescRight">ISR: I Position. <a href="group__CMSIS__ISR__BITS.html#ga9f51d4217c1394e52f5223a6cd382136">More...</a><br/></td></tr>
<tr class="separator:ga9f51d4217c1394e52f5223a6cd382136"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7b756c9a406d7dd0a86891656908e98c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#ga7b756c9a406d7dd0a86891656908e98c">ISR_I_Msk</a>   (1UL << ISR_I_Pos)</td></tr>
<tr class="memdesc:ga7b756c9a406d7dd0a86891656908e98c"><td class="mdescLeft"> </td><td class="mdescRight">ISR: I Mask. <a href="group__CMSIS__ISR__BITS.html#ga7b756c9a406d7dd0a86891656908e98c">More...</a><br/></td></tr>
<tr class="separator:ga7b756c9a406d7dd0a86891656908e98c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad8654422bb59e22fb7f1321eeef1b81d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#gad8654422bb59e22fb7f1321eeef1b81d">ISR_F_Pos</a>   11U</td></tr>
<tr class="memdesc:gad8654422bb59e22fb7f1321eeef1b81d"><td class="mdescLeft"> </td><td class="mdescRight">ISR: F Position. <a href="group__CMSIS__ISR__BITS.html#gad8654422bb59e22fb7f1321eeef1b81d">More...</a><br/></td></tr>
<tr class="separator:gad8654422bb59e22fb7f1321eeef1b81d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac2efaf413c81afab4265515160f6700c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#gac2efaf413c81afab4265515160f6700c">ISR_F_Msk</a>   (1UL << ISR_F_Pos)</td></tr>
<tr class="memdesc:gac2efaf413c81afab4265515160f6700c"><td class="mdescLeft"> </td><td class="mdescRight">ISR: F Mask. <a href="group__CMSIS__ISR__BITS.html#gac2efaf413c81afab4265515160f6700c">More...</a><br/></td></tr>
<tr class="separator:gac2efaf413c81afab4265515160f6700c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2c014e929b74e6ded5e89a74903ce975"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__BITS.html#ga2c014e929b74e6ded5e89a74903ce975">DACR_D_Pos_</a>(n)   (2U*n)</td></tr>
<tr class="memdesc:ga2c014e929b74e6ded5e89a74903ce975"><td class="mdescLeft"> </td><td class="mdescRight">DACR: Dn Position. <a href="group__CMSIS__DACR__BITS.html#ga2c014e929b74e6ded5e89a74903ce975">More...</a><br/></td></tr>
<tr class="separator:ga2c014e929b74e6ded5e89a74903ce975"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga41b90c8a7338fbe5e5b06be083ba22fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__BITS.html#ga41b90c8a7338fbe5e5b06be083ba22fe">DACR_D_Msk_</a>(n)   (3UL << DACR_D_Pos_(n))</td></tr>
<tr class="memdesc:ga41b90c8a7338fbe5e5b06be083ba22fe"><td class="mdescLeft"> </td><td class="mdescRight">DACR: Dn Mask. <a href="group__CMSIS__DACR__BITS.html#ga41b90c8a7338fbe5e5b06be083ba22fe">More...</a><br/></td></tr>
<tr class="separator:ga41b90c8a7338fbe5e5b06be083ba22fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga281ebf97decb4ef4f7b1e5c4285c45ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__Dn.html#ga281ebf97decb4ef4f7b1e5c4285c45ab">DACR_Dn_NOACCESS</a>   0U</td></tr>
<tr class="memdesc:ga281ebf97decb4ef4f7b1e5c4285c45ab"><td class="mdescLeft"> </td><td class="mdescRight">DACR Dn field: No access. <a href="group__CMSIS__DACR__Dn.html#ga281ebf97decb4ef4f7b1e5c4285c45ab">More...</a><br/></td></tr>
<tr class="separator:ga281ebf97decb4ef4f7b1e5c4285c45ab"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac76e6128758cd64a9fa92487ec49441b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__Dn.html#gac76e6128758cd64a9fa92487ec49441b">DACR_Dn_CLIENT</a>   1U</td></tr>
<tr class="memdesc:gac76e6128758cd64a9fa92487ec49441b"><td class="mdescLeft"> </td><td class="mdescRight">DACR Dn field: Client. <a href="group__CMSIS__DACR__Dn.html#gac76e6128758cd64a9fa92487ec49441b">More...</a><br/></td></tr>
<tr class="separator:gac76e6128758cd64a9fa92487ec49441b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabbf27724d67055138bf7abdb651e9732"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__Dn.html#gabbf27724d67055138bf7abdb651e9732">DACR_Dn_MANAGER</a>   3U</td></tr>
<tr class="memdesc:gabbf27724d67055138bf7abdb651e9732"><td class="mdescLeft"> </td><td class="mdescRight">DACR Dn field: Manager. <a href="group__CMSIS__DACR__Dn.html#gabbf27724d67055138bf7abdb651e9732">More...</a><br/></td></tr>
<tr class="separator:gabbf27724d67055138bf7abdb651e9732"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)</td></tr>
<tr class="memdesc:a286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a bit field value for use in a register bit range. <a href="#a286e3b913dbd236c7f48ea70c8821f4e">More...</a><br/></td></tr>
<tr class="separator:a286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)</td></tr>
<tr class="memdesc:a139b6e261c981f014f386927ca4a8444"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a register value to extract a bit filed value. <a href="#a139b6e261c981f014f386927ca4a8444">More...</a><br/></td></tr>
<tr class="separator:a139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3b08fba5b9be921c8a971231f75f8764"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga3b08fba5b9be921c8a971231f75f8764">L2C_310</a>   ((<a class="el" href="structL2C__310__TypeDef.html">L2C_310_TypeDef</a> *)<a class="el" href="ARMCA9_8h.html#a5ce89d9feb78e20a4034f025eec392b4">L2C_310_BASE</a>)</td></tr>
<tr class="memdesc:ga3b08fba5b9be921c8a971231f75f8764"><td class="mdescLeft"> </td><td class="mdescRight">L2C_310 register set access pointer. <a href="group__L2__cache__functions.html#ga3b08fba5b9be921c8a971231f75f8764">More...</a><br/></td></tr>
<tr class="separator:ga3b08fba5b9be921c8a971231f75f8764"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga82e193c0016a9377274756b2673464a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>   ((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a> *) <a class="el" href="ARMCA9_8h.html#a5cc9c031f86d3fcb7efcbe2fce4cd552">GIC_DISTRIBUTOR_BASE</a> )</td></tr>
<tr class="memdesc:ga82e193c0016a9377274756b2673464a6"><td class="mdescLeft"> </td><td class="mdescRight">GIC Distributor register set access pointer. <a href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">More...</a><br/></td></tr>
<tr class="separator:ga82e193c0016a9377274756b2673464a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga31a083dbdc5cb84178dbf184286180e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>   ((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a> *) <a class="el" href="ARMCA9_8h.html#adc560f42c09a0a3ce5dcc4aa898209ca">GIC_INTERFACE_BASE</a> )</td></tr>
<tr class="memdesc:ga31a083dbdc5cb84178dbf184286180e3"><td class="mdescLeft"> </td><td class="mdescRight">GIC Interface register set access pointer. <a href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">More...</a><br/></td></tr>
<tr class="separator:ga31a083dbdc5cb84178dbf184286180e3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaaf976e808e92970c4853195f46f86aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gaaaf976e808e92970c4853195f46f86aa">PTIM</a>   ((<a class="el" href="structTimer__Type.html">Timer_Type</a> *) <a class="el" href="ARMCA9_8h.html#a251f8c6600afee0dddf950c7a41d4723">TIMER_BASE</a> )</td></tr>
<tr class="memdesc:gaaaf976e808e92970c4853195f46f86aa"><td class="mdescLeft"> </td><td class="mdescRight">Timer register struct. <a href="group__PTM__timer__functions.html#gaaaf976e808e92970c4853195f46f86aa">More...</a><br/></td></tr>
<tr class="separator:gaaaf976e808e92970c4853195f46f86aa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a647b0a71258678d75aed0aadd5801612"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a647b0a71258678d75aed0aadd5801612">GIC_SetSecurity</a>   <a class="el" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a></td></tr>
<tr class="separator:a647b0a71258678d75aed0aadd5801612"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aea0bba954f8c3b032cf9a6540277ddef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aea0bba954f8c3b032cf9a6540277ddef">GIC_GetSecurity</a>   <a class="el" href="core__ca_8h.html#ae161d7a866cb61f92b808ae98fa7c812">GIC_GetGroup</a></td></tr>
<tr class="separator:aea0bba954f8c3b032cf9a6540277ddef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4ab4ff3ff904df46da18f5532ceb1e89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga4ab4ff3ff904df46da18f5532ceb1e89">SECTION_DESCRIPTOR</a>   (0x2)</td></tr>
<tr class="separator:ga4ab4ff3ff904df46da18f5532ceb1e89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a16f225cca51a80c5cf1c9c002cfd2dba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a16f225cca51a80c5cf1c9c002cfd2dba">SECTION_MASK</a>   (0xFFFFFFFC)</td></tr>
<tr class="separator:a16f225cca51a80c5cf1c9c002cfd2dba"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3052ba3d97ad157189a6c6fce15b1b6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3052ba3d97ad157189a6c6fce15b1b6a">SECTION_TEXCB_MASK</a>   (0xFFFF8FF3)</td></tr>
<tr class="separator:a3052ba3d97ad157189a6c6fce15b1b6a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa77545190c32bb2f4d2d86e41552daef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaa77545190c32bb2f4d2d86e41552daef">SECTION_B_SHIFT</a>   (2)</td></tr>
<tr class="separator:gaa77545190c32bb2f4d2d86e41552daef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae0b3a2eccc4f9c249e928d359c43c20c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gae0b3a2eccc4f9c249e928d359c43c20c">SECTION_C_SHIFT</a>   (3)</td></tr>
<tr class="separator:gae0b3a2eccc4f9c249e928d359c43c20c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad84432cb37ae093f7609f8f29f42c1f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gad84432cb37ae093f7609f8f29f42c1f4">SECTION_TEX0_SHIFT</a>   (12)</td></tr>
<tr class="separator:gad84432cb37ae093f7609f8f29f42c1f4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga531cafc5eca8ade67a6fb83b35f8520e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga531cafc5eca8ade67a6fb83b35f8520e">SECTION_TEX1_SHIFT</a>   (13)</td></tr>
<tr class="separator:ga531cafc5eca8ade67a6fb83b35f8520e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8a6d854746a9c0049f9a91188092a55f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga8a6d854746a9c0049f9a91188092a55f">SECTION_TEX2_SHIFT</a>   (14)</td></tr>
<tr class="separator:ga8a6d854746a9c0049f9a91188092a55f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a83cb551c9fa708e33082c682be614334"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a83cb551c9fa708e33082c682be614334">SECTION_XN_MASK</a>   (0xFFFFFFEF)</td></tr>
<tr class="separator:a83cb551c9fa708e33082c682be614334"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6cdc2db0ca695fd1191305a13e66c0a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga6cdc2db0ca695fd1191305a13e66c0a7">SECTION_XN_SHIFT</a>   (4)</td></tr>
<tr class="separator:ga6cdc2db0ca695fd1191305a13e66c0a7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a90a30c02512cbea24791212af9f2cd9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a90a30c02512cbea24791212af9f2cd9f">SECTION_DOMAIN_MASK</a>   (0xFFFFFE1F)</td></tr>
<tr class="separator:a90a30c02512cbea24791212af9f2cd9f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga70cc38b984789323feecd97033a66757"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga70cc38b984789323feecd97033a66757">SECTION_DOMAIN_SHIFT</a>   (5)</td></tr>
<tr class="separator:ga70cc38b984789323feecd97033a66757"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad32d146d84a9d7f964f28f1dadc98bcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad32d146d84a9d7f964f28f1dadc98bcb">SECTION_P_MASK</a>   (0xFFFFFDFF)</td></tr>
<tr class="separator:ad32d146d84a9d7f964f28f1dadc98bcb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8f27fa21cb70abad114374f33a562988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga8f27fa21cb70abad114374f33a562988">SECTION_P_SHIFT</a>   (9)</td></tr>
<tr class="separator:ga8f27fa21cb70abad114374f33a562988"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a725efc96ea9aa940fefcf013bce6ca8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a725efc96ea9aa940fefcf013bce6ca8c">SECTION_AP_MASK</a>   (0xFFFF73FF)</td></tr>
<tr class="separator:a725efc96ea9aa940fefcf013bce6ca8c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga274fa608581b227182ce92adec4597b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga274fa608581b227182ce92adec4597b5">SECTION_AP_SHIFT</a>   (10)</td></tr>
<tr class="separator:ga274fa608581b227182ce92adec4597b5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1b8b0d00bfc7cbeed67b82db26d98195"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1b8b0d00bfc7cbeed67b82db26d98195">SECTION_AP2_SHIFT</a>   (15)</td></tr>
<tr class="separator:ga1b8b0d00bfc7cbeed67b82db26d98195"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a42d3645aad501af4ef447186c01685b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a42d3645aad501af4ef447186c01685b7">SECTION_S_MASK</a>   (0xFFFEFFFF)</td></tr>
<tr class="separator:a42d3645aad501af4ef447186c01685b7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga83a5fc538dad79161b122fb164d630fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga83a5fc538dad79161b122fb164d630fe">SECTION_S_SHIFT</a>   (16)</td></tr>
<tr class="separator:ga83a5fc538dad79161b122fb164d630fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a01ceacdb3888d7cddcfeccfea9eb3658"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a01ceacdb3888d7cddcfeccfea9eb3658">SECTION_NG_MASK</a>   (0xFFFDFFFF)</td></tr>
<tr class="separator:a01ceacdb3888d7cddcfeccfea9eb3658"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7af8adbf033d0a5c7b0889dd085041d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga7af8adbf033d0a5c7b0889dd085041d1">SECTION_NG_SHIFT</a>   (17)</td></tr>
<tr class="separator:ga7af8adbf033d0a5c7b0889dd085041d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a057533871fa1af6db7a27b39d976ac95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a057533871fa1af6db7a27b39d976ac95">SECTION_NS_MASK</a>   (0xFFF7FFFF)</td></tr>
<tr class="separator:a057533871fa1af6db7a27b39d976ac95"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga502d55a107c909e15be282d8fbe4a8ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga502d55a107c909e15be282d8fbe4a8ce">SECTION_NS_SHIFT</a>   (19)</td></tr>
<tr class="separator:ga502d55a107c909e15be282d8fbe4a8ce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga82cb818cf0bcf9431ed9d0b52a39fe14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga82cb818cf0bcf9431ed9d0b52a39fe14">PAGE_L1_DESCRIPTOR</a>   (0x1)</td></tr>
<tr class="separator:ga82cb818cf0bcf9431ed9d0b52a39fe14"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9fe764cc3a117a9ab93a301de8bceed1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9fe764cc3a117a9ab93a301de8bceed1">PAGE_L1_MASK</a>   (0xFFFFFFFC)</td></tr>
<tr class="separator:a9fe764cc3a117a9ab93a301de8bceed1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaefb20807cde04ea9fee6b197602348cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaefb20807cde04ea9fee6b197602348cf">PAGE_L2_4K_DESC</a>   (0x2)</td></tr>
<tr class="separator:gaefb20807cde04ea9fee6b197602348cf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abd292694d0155e3b0d4c12895a6c8fa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#abd292694d0155e3b0d4c12895a6c8fa6">PAGE_L2_4K_MASK</a>   (0xFFFFFFFD)</td></tr>
<tr class="separator:abd292694d0155e3b0d4c12895a6c8fa6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf38d8149733ba83690fd04ac1204bde1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaf38d8149733ba83690fd04ac1204bde1">PAGE_L2_64K_DESC</a>   (0x1)</td></tr>
<tr class="separator:gaf38d8149733ba83690fd04ac1204bde1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab3a82626ee70e38285852a1128b75c7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab3a82626ee70e38285852a1128b75c7a">PAGE_L2_64K_MASK</a>   (0xFFFFFFFC)</td></tr>
<tr class="separator:ab3a82626ee70e38285852a1128b75c7a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a234fceea67b5d6c41b0875852d86cc70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a234fceea67b5d6c41b0875852d86cc70">PAGE_4K_TEXCB_MASK</a>   (0xFFFFFE33)</td></tr>
<tr class="separator:a234fceea67b5d6c41b0875852d86cc70"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga295b3b39fa6f7da3650a94551e28218b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga295b3b39fa6f7da3650a94551e28218b">PAGE_4K_B_SHIFT</a>   (2)</td></tr>
<tr class="separator:ga295b3b39fa6f7da3650a94551e28218b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga17ad8e75e5987a1f98adfc783640b75f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga17ad8e75e5987a1f98adfc783640b75f">PAGE_4K_C_SHIFT</a>   (3)</td></tr>
<tr class="separator:ga17ad8e75e5987a1f98adfc783640b75f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8069f8882920692467749cc65f50e1f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga8069f8882920692467749cc65f50e1f8">PAGE_4K_TEX0_SHIFT</a>   (6)</td></tr>
<tr class="separator:ga8069f8882920692467749cc65f50e1f8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac0db1e472f79b641d0e51e4faa6e7e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gac0db1e472f79b641d0e51e4faa6e7e08">PAGE_4K_TEX1_SHIFT</a>   (7)</td></tr>
<tr class="separator:gac0db1e472f79b641d0e51e4faa6e7e08"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0e5c586a7e1928c7efa95e0d5f26e981"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga0e5c586a7e1928c7efa95e0d5f26e981">PAGE_4K_TEX2_SHIFT</a>   (8)</td></tr>
<tr class="separator:ga0e5c586a7e1928c7efa95e0d5f26e981"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a666e7d1971403995104586f35d56590b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a666e7d1971403995104586f35d56590b">PAGE_64K_TEXCB_MASK</a>   (0xFFFF8FF3)</td></tr>
<tr class="separator:a666e7d1971403995104586f35d56590b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaedc4abb2636443389128258bd74ce0bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaedc4abb2636443389128258bd74ce0bd">PAGE_64K_B_SHIFT</a>   (2)</td></tr>
<tr class="separator:gaedc4abb2636443389128258bd74ce0bd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc1ce8b3d369d1e054fabf87514c4cd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gabc1ce8b3d369d1e054fabf87514c4cd6">PAGE_64K_C_SHIFT</a>   (3)</td></tr>
<tr class="separator:gabc1ce8b3d369d1e054fabf87514c4cd6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab4d67a1d5aa37623272abe4db32677ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gab4d67a1d5aa37623272abe4db32677ec">PAGE_64K_TEX0_SHIFT</a>   (12)</td></tr>
<tr class="separator:gab4d67a1d5aa37623272abe4db32677ec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9c910152d27ce0a1552e3bb3c88782a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga9c910152d27ce0a1552e3bb3c88782a6">PAGE_64K_TEX1_SHIFT</a>   (13)</td></tr>
<tr class="separator:ga9c910152d27ce0a1552e3bb3c88782a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8ec4dcea202b5ebc15419f7410a6c0b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga8ec4dcea202b5ebc15419f7410a6c0b0">PAGE_64K_TEX2_SHIFT</a>   (14)</td></tr>
<tr class="separator:ga8ec4dcea202b5ebc15419f7410a6c0b0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa488ef0c274f8ae125f61129745b1629"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa488ef0c274f8ae125f61129745b1629">PAGE_TEXCB_MASK</a>   (0xFFFF8FF3)</td></tr>
<tr class="separator:aa488ef0c274f8ae125f61129745b1629"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3a660cdbc121e6510ed815fcb5bc8a44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga3a660cdbc121e6510ed815fcb5bc8a44">PAGE_B_SHIFT</a>   (2)</td></tr>
<tr class="separator:ga3a660cdbc121e6510ed815fcb5bc8a44"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad9fc2f0cbe58ae4f1afea3cf9817b450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gad9fc2f0cbe58ae4f1afea3cf9817b450">PAGE_C_SHIFT</a>   (3)</td></tr>
<tr class="separator:gad9fc2f0cbe58ae4f1afea3cf9817b450"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5833dc0a939f8d33299d8c8995a06589"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga5833dc0a939f8d33299d8c8995a06589">PAGE_TEX_SHIFT</a>   (12)</td></tr>
<tr class="separator:ga5833dc0a939f8d33299d8c8995a06589"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a522f61b0d301d6f69c33a629e1699c7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a522f61b0d301d6f69c33a629e1699c7e">PAGE_XN_4K_MASK</a>   (0xFFFFFFFE)</td></tr>
<tr class="separator:a522f61b0d301d6f69c33a629e1699c7e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9be26955f4a44c54008c55de61652539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga9be26955f4a44c54008c55de61652539">PAGE_XN_4K_SHIFT</a>   (0)</td></tr>
<tr class="separator:ga9be26955f4a44c54008c55de61652539"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae0445cb4d6dc78359074cbb2776e3b5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae0445cb4d6dc78359074cbb2776e3b5c">PAGE_XN_64K_MASK</a>   (0xFFFF7FFF)</td></tr>
<tr class="separator:ae0445cb4d6dc78359074cbb2776e3b5c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab34b65fbaaec1287daef459071c5c5c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gab34b65fbaaec1287daef459071c5c5c9">PAGE_XN_64K_SHIFT</a>   (15)</td></tr>
<tr class="separator:gab34b65fbaaec1287daef459071c5c5c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0a48a4e79188149fbe886a698b6d9cb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0a48a4e79188149fbe886a698b6d9cb4">PAGE_DOMAIN_MASK</a>   (0xFFFFFE1F)</td></tr>
<tr class="separator:a0a48a4e79188149fbe886a698b6d9cb4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gade787969e64896d0c8fe554f6aa1bc9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gade787969e64896d0c8fe554f6aa1bc9e">PAGE_DOMAIN_SHIFT</a>   (5)</td></tr>
<tr class="separator:gade787969e64896d0c8fe554f6aa1bc9e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a604f4f13fcb78ff08d65ef4a1a3f7933"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a604f4f13fcb78ff08d65ef4a1a3f7933">PAGE_P_MASK</a>   (0xFFFFFDFF)</td></tr>
<tr class="separator:a604f4f13fcb78ff08d65ef4a1a3f7933"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga46a63dfcf084d48ccf27987bab48417a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga46a63dfcf084d48ccf27987bab48417a">PAGE_P_SHIFT</a>   (9)</td></tr>
<tr class="separator:ga46a63dfcf084d48ccf27987bab48417a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af7d3ee23adcaf9221967791f0e64d830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af7d3ee23adcaf9221967791f0e64d830">PAGE_AP_MASK</a>   (0xFFFFFDCF)</td></tr>
<tr class="separator:af7d3ee23adcaf9221967791f0e64d830"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafed0cfe8a8ab67fe26e961b876db13a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gafed0cfe8a8ab67fe26e961b876db13a3">PAGE_AP_SHIFT</a>   (4)</td></tr>
<tr class="separator:gafed0cfe8a8ab67fe26e961b876db13a3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad2d3cf0695c98dc2c4e37ebeb9235b2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gad2d3cf0695c98dc2c4e37ebeb9235b2c">PAGE_AP2_SHIFT</a>   (9)</td></tr>
<tr class="separator:gad2d3cf0695c98dc2c4e37ebeb9235b2c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac44cd885615a54131c372abfdc2d5c66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac44cd885615a54131c372abfdc2d5c66">PAGE_S_MASK</a>   (0xFFFFFBFF)</td></tr>
<tr class="separator:ac44cd885615a54131c372abfdc2d5c66"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1d9a3ed8dfa64aba257e2273d2613bce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1d9a3ed8dfa64aba257e2273d2613bce">PAGE_S_SHIFT</a>   (10)</td></tr>
<tr class="separator:ga1d9a3ed8dfa64aba257e2273d2613bce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:add5d44ba746fe4d17d8b06a1086aa853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#add5d44ba746fe4d17d8b06a1086aa853">PAGE_NG_MASK</a>   (0xFFFFF7FF)</td></tr>
<tr class="separator:add5d44ba746fe4d17d8b06a1086aa853"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1d9196f2dd260244a4ad7e5b70b0e4c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1d9196f2dd260244a4ad7e5b70b0e4c7">PAGE_NG_SHIFT</a>   (11)</td></tr>
<tr class="separator:ga1d9196f2dd260244a4ad7e5b70b0e4c7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a618b1432615c3242f53360d4364c5797"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a618b1432615c3242f53360d4364c5797">PAGE_NS_MASK</a>   (0xFFFFFFF7)</td></tr>
<tr class="separator:a618b1432615c3242f53360d4364c5797"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga49740f5181adebe63b11c68db731bb0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga49740f5181adebe63b11c68db731bb0f">PAGE_NS_SHIFT</a>   (3)</td></tr>
<tr class="separator:ga49740f5181adebe63b11c68db731bb0f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8e51cfa91c0b6bbf1df1cff0bde44836"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga8e51cfa91c0b6bbf1df1cff0bde44836">OFFSET_1M</a>   (0x00100000)</td></tr>
<tr class="separator:ga8e51cfa91c0b6bbf1df1cff0bde44836"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf19b9fb664a06a41562176a51c66fcff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaf19b9fb664a06a41562176a51c66fcff">OFFSET_64K</a>   (0x00010000)</td></tr>
<tr class="separator:gaf19b9fb664a06a41562176a51c66fcff"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga121c645cdc91018720ceaf1d021fcd89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga121c645cdc91018720ceaf1d021fcd89">OFFSET_4K</a>   (0x00001000)</td></tr>
<tr class="separator:ga121c645cdc91018720ceaf1d021fcd89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba92665a24bc2ba8c49b9a0881c9df8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaba92665a24bc2ba8c49b9a0881c9df8a">DESCRIPTOR_FAULT</a>   (0x00000000)</td></tr>
<tr class="separator:gaba92665a24bc2ba8c49b9a0881c9df8a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga220aab449cf3716723979d06666c2ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga220aab449cf3716723979d06666c2ebf">section_normal</a>(descriptor_l1, region)</td></tr>
<tr class="separator:ga220aab449cf3716723979d06666c2ebf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a470b88645153aad94b09485f3108c641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a470b88645153aad94b09485f3108c641">section_normal_nc</a>(descriptor_l1, region)</td></tr>
<tr class="separator:a470b88645153aad94b09485f3108c641"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad598239f9bb9b6ae2bec8278305640b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gad598239f9bb9b6ae2bec8278305640b4">section_normal_cod</a>(descriptor_l1, region)</td></tr>
<tr class="separator:gad598239f9bb9b6ae2bec8278305640b4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf95fa76d8f0f7ccfd2ebc00860af4f1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaf95fa76d8f0f7ccfd2ebc00860af4f1d">section_normal_ro</a>(descriptor_l1, region)</td></tr>
<tr class="separator:gaf95fa76d8f0f7ccfd2ebc00860af4f1d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1f2ce84e6ec5c150a2ffc05092ea6d0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1f2ce84e6ec5c150a2ffc05092ea6d0e">section_normal_rw</a>(descriptor_l1, region)</td></tr>
<tr class="separator:ga1f2ce84e6ec5c150a2ffc05092ea6d0e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf77ecb86097e6e8cf5f6c7bb9d2740c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaf77ecb86097e6e8cf5f6c7bb9d2740c9">section_so</a>(descriptor_l1, region)</td></tr>
<tr class="separator:gaf77ecb86097e6e8cf5f6c7bb9d2740c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1f66b52e152895af070514528763c272"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1f66b52e152895af070514528763c272">section_device_ro</a>(descriptor_l1, region)</td></tr>
<tr class="separator:ga1f66b52e152895af070514528763c272"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga33c6ad1fc06648fe50f8b21554c9bccb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga33c6ad1fc06648fe50f8b21554c9bccb">section_device_rw</a>(descriptor_l1, region)</td></tr>
<tr class="separator:ga33c6ad1fc06648fe50f8b21554c9bccb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafe66b1515bf7d251a9a3218162637a22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gafe66b1515bf7d251a9a3218162637a22">page4k_device_rw</a>(descriptor_l1, descriptor_l2, region)</td></tr>
<tr class="separator:gafe66b1515bf7d251a9a3218162637a22"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6c8c84bdeebf350d97eb3a99bd11845f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga6c8c84bdeebf350d97eb3a99bd11845f">page64k_device_rw</a>(descriptor_l1, descriptor_l2, region)</td></tr>
<tr class="separator:ga6c8c84bdeebf350d97eb3a99bd11845f"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:gab184b824a6d7cb728bd46c6abcd0c21a"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a">mmu_region_size_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21aacb7227be6a36b93e485b62e3acddae51">SECTION</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21aa99ce0ce05e9c418dc6bddcc47b2fa05a">PAGE_4k</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21aafc53512bbf834739fcb97ad1c0f444fc">PAGE_64k</a>
<br/>
}</td></tr>
<tr class="separator:gab184b824a6d7cb728bd46c6abcd0c21a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga83ac8de9263f89879079da521e86d5f2"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2">mmu_memory_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a50d1448013c6f17125caee18aa418af7">NORMAL</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a28b8a7b4b6c2a98af7cf438255207174">DEVICE</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a9b78345535e6af3288cc69a572338808">SHARED_DEVICE</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a765e5cbb28da82e4d8f7e94fce32a7e0">NON_SHARED_DEVICE</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a0a4d347de23312717e6e57b04f0b014e">STRONGLY_ORDERED</a>
<br/>
}</td></tr>
<tr class="separator:ga83ac8de9263f89879079da521e86d5f2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga11c86b7b193efb2c59b6a2179a02f584"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584a61a625191f7d288011e20bf2104ee151">NON_CACHEABLE</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584a23294b86e8dbf6ff0fa98b678e8fd667">WB_WA</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584ab044987527e64a06f65aa6f2ae0e4e7e">WT</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584aca2e70f575679d6f3e2e340d1ede4f13">WB_NO_WA</a>
<br/>
}</td></tr>
<tr class="separator:ga11c86b7b193efb2c59b6a2179a02f584"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga06d94c0eaa22d713636acaff81485409"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409">mmu_ecc_check_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409a48ce2ec8ec49f0167a7d571081a9301f">ECC_DISABLED</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409af0e84d9540ed9d79f01caad9841d414d">ECC_ENABLED</a>
<br/>
}</td></tr>
<tr class="separator:ga06d94c0eaa22d713636acaff81485409"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2fe1157deda82e66b9a1b19772309b63"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63">mmu_execute_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63a887d2cbfd9131de5cc3745731421b34b">EXECUTE</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63ad1d1eabb1b07ce896d5308a1144cf87a">NON_EXECUTE</a>
<br/>
}</td></tr>
<tr class="separator:ga2fe1157deda82e66b9a1b19772309b63"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga04160605fbe20914c8ef020430684a30"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30">mmu_global_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30afde1bb5ef04b28059e61df449501f1c0">GLOBAL</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30a611c091f2869100296a98915a19ee018">NON_GLOBAL</a>
<br/>
}</td></tr>
<tr class="separator:ga04160605fbe20914c8ef020430684a30"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab884a11fa8d094573ab77fb1c0f8d8a7"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7">mmu_shared_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7a4a237208271e450df0a72c07169683b4">NON_SHARED</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7a9c46e16a4ab019339596acadeefc8c53">SHARED</a>
<br/>
}</td></tr>
<tr class="separator:gab884a11fa8d094573ab77fb1c0f8d8a7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac3d277641df9fb3bb3b555e2e79dd639"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639">mmu_secure_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639aa9dea2ba3f45f7d12b274eb6ab7d28d9">SECURE</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639a9e08ca26fdda38ef731f13e4f058ef6f">NON_SECURE</a>
<br/>
}</td></tr>
<tr class="separator:gac3d277641df9fb3bb3b555e2e79dd639"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2ee598252f996e4f96640b096291d280"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> { <br/>
  <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280a4c66cd69a45985317939a53d820fb9da">NO_ACCESS</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280aec2497e0c8af01c04bec31ec0d1d7847">RW</a>,
<br/>
  <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280acb9be765f361bb7efb9073730aac92c6">READ</a>
<br/>
}</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gaff8a4966eff1ada5cba80f2b689446db"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gaff8a4966eff1ada5cba80f2b689446db">L1C_EnableCaches</a> (void)</td></tr>
<tr class="memdesc:gaff8a4966eff1ada5cba80f2b689446db"><td class="mdescLeft"> </td><td class="mdescRight">Enable Caches by setting I and C bits in SCTLR register. <a href="group__L1__cache__functions.html#gaff8a4966eff1ada5cba80f2b689446db">More...</a><br/></td></tr>
<tr class="separator:gaff8a4966eff1ada5cba80f2b689446db"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga320ef6fd1dd65f2f82e64c096a4994a6">L1C_DisableCaches</a> (void)</td></tr>
<tr class="memdesc:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="mdescLeft"> </td><td class="mdescRight">Disable Caches by clearing I and C bits in SCTLR register. <a href="group__L1__cache__functions.html#ga320ef6fd1dd65f2f82e64c096a4994a6">More...</a><br/></td></tr>
<tr class="separator:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa5fb36b4496e64472849f7811970c581"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gaa5fb36b4496e64472849f7811970c581">L1C_EnableBTAC</a> (void)</td></tr>
<tr class="memdesc:gaa5fb36b4496e64472849f7811970c581"><td class="mdescLeft"> </td><td class="mdescRight">Enable Branch Prediction by setting Z bit in SCTLR register. <a href="group__L1__cache__functions.html#gaa5fb36b4496e64472849f7811970c581">More...</a><br/></td></tr>
<tr class="separator:gaa5fb36b4496e64472849f7811970c581"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gab8695cf1f4a7f3789b93c41dc4eeb51d">L1C_DisableBTAC</a> (void)</td></tr>
<tr class="memdesc:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="mdescLeft"> </td><td class="mdescRight">Disable Branch Prediction by clearing Z bit in SCTLR register. <a href="group__L1__cache__functions.html#gab8695cf1f4a7f3789b93c41dc4eeb51d">More...</a><br/></td></tr>
<tr class="separator:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad0d732293be6a928db184b59aadc1979"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gad0d732293be6a928db184b59aadc1979">L1C_InvalidateBTAC</a> (void)</td></tr>
<tr class="memdesc:gad0d732293be6a928db184b59aadc1979"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate entire branch predictor array. <a href="group__L1__cache__functions.html#gad0d732293be6a928db184b59aadc1979">More...</a><br/></td></tr>
<tr class="separator:gad0d732293be6a928db184b59aadc1979"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac932810cfe83f087590859010972645e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gac932810cfe83f087590859010972645e">L1C_InvalidateICacheAll</a> (void)</td></tr>
<tr class="memdesc:gac932810cfe83f087590859010972645e"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate the whole instruction cache. <a href="group__L1__cache__functions.html#gac932810cfe83f087590859010972645e">More...</a><br/></td></tr>
<tr class="separator:gac932810cfe83f087590859010972645e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga9eb6f0a7c9c04cc49efd964eb59ba26f">L1C_CleanDCacheMVA</a> (void *va)</td></tr>
<tr class="memdesc:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="mdescLeft"> </td><td class="mdescRight">Clean data cache line by address. <a href="group__L1__cache__functions.html#ga9eb6f0a7c9c04cc49efd964eb59ba26f">More...</a><br/></td></tr>
<tr class="separator:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9209853937940991daf70edd6bc633fe"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga9209853937940991daf70edd6bc633fe">L1C_InvalidateDCacheMVA</a> (void *va)</td></tr>
<tr class="memdesc:ga9209853937940991daf70edd6bc633fe"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate data cache line by address. <a href="group__L1__cache__functions.html#ga9209853937940991daf70edd6bc633fe">More...</a><br/></td></tr>
<tr class="separator:ga9209853937940991daf70edd6bc633fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7646a5e01b529566968f393e485f46a2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga7646a5e01b529566968f393e485f46a2">L1C_CleanInvalidateDCacheMVA</a> (void *va)</td></tr>
<tr class="memdesc:ga7646a5e01b529566968f393e485f46a2"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate data cache by address. <a href="group__L1__cache__functions.html#ga7646a5e01b529566968f393e485f46a2">More...</a><br/></td></tr>
<tr class="separator:ga7646a5e01b529566968f393e485f46a2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a35988a42567ca868bffd0b6171021ecb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a35988a42567ca868bffd0b6171021ecb">__log2_up</a> (uint32_t n)</td></tr>
<tr class="memdesc:a35988a42567ca868bffd0b6171021ecb"><td class="mdescLeft"> </td><td class="mdescRight">Calculate log2 rounded up. <a href="#a35988a42567ca868bffd0b6171021ecb">More...</a><br/></td></tr>
<tr class="separator:a35988a42567ca868bffd0b6171021ecb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5ace5c651cf18aaa7659e1fbe6e77988"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5ace5c651cf18aaa7659e1fbe6e77988">__L1C_MaintainDCacheSetWay</a> (uint32_t level, uint32_t maint)</td></tr>
<tr class="memdesc:a5ace5c651cf18aaa7659e1fbe6e77988"><td class="mdescLeft"> </td><td class="mdescRight">Apply cache maintenance to given cache level. <a href="#a5ace5c651cf18aaa7659e1fbe6e77988">More...</a><br/></td></tr>
<tr class="separator:a5ace5c651cf18aaa7659e1fbe6e77988"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga30d7632156a30a3b75064f6d15b8f850"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga30d7632156a30a3b75064f6d15b8f850">L1C_CleanInvalidateCache</a> (uint32_t op)</td></tr>
<tr class="memdesc:ga30d7632156a30a3b75064f6d15b8f850"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. <a href="group__L1__cache__functions.html#ga30d7632156a30a3b75064f6d15b8f850">More...</a><br/></td></tr>
<tr class="separator:ga30d7632156a30a3b75064f6d15b8f850"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga722ceb077e491bb4befcfbb3aee9b20b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#acdc36c1b3d3e16c17a73889b7d06d0d2">CMSIS_DEPRECATED</a> <br class="typebreak"/>
<a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga722ceb077e491bb4befcfbb3aee9b20b">__L1C_CleanInvalidateCache</a> (uint32_t op)</td></tr>
<tr class="memdesc:ga722ceb077e491bb4befcfbb3aee9b20b"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. <a href="group__L1__cache__functions.html#ga722ceb077e491bb4befcfbb3aee9b20b">More...</a><br/></td></tr>
<tr class="separator:ga722ceb077e491bb4befcfbb3aee9b20b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae895f75c4f3539058232f555d79e5df3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gae895f75c4f3539058232f555d79e5df3">L1C_InvalidateDCacheAll</a> (void)</td></tr>
<tr class="memdesc:gae895f75c4f3539058232f555d79e5df3"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate the whole data cache. <a href="group__L1__cache__functions.html#gae895f75c4f3539058232f555d79e5df3">More...</a><br/></td></tr>
<tr class="separator:gae895f75c4f3539058232f555d79e5df3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga70359d824bf26f376e3d7cb9c787da27"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga70359d824bf26f376e3d7cb9c787da27">L1C_CleanDCacheAll</a> (void)</td></tr>
<tr class="memdesc:ga70359d824bf26f376e3d7cb9c787da27"><td class="mdescLeft"> </td><td class="mdescRight">Clean the whole data cache. <a href="group__L1__cache__functions.html#ga70359d824bf26f376e3d7cb9c787da27">More...</a><br/></td></tr>
<tr class="separator:ga70359d824bf26f376e3d7cb9c787da27"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga92b5babf7317abe3815f61a2731735c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga92b5babf7317abe3815f61a2731735c3">L1C_CleanInvalidateDCacheAll</a> (void)</td></tr>
<tr class="memdesc:ga92b5babf7317abe3815f61a2731735c3"><td class="mdescLeft"> </td><td class="mdescRight">Clean and invalidate the whole data cache. <a href="group__L1__cache__functions.html#ga92b5babf7317abe3815f61a2731735c3">More...</a><br/></td></tr>
<tr class="separator:ga92b5babf7317abe3815f61a2731735c3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga164c59c55e2d18bf8a94dc91c0f4ce68"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga164c59c55e2d18bf8a94dc91c0f4ce68">L2C_Sync</a> (void)</td></tr>
<tr class="memdesc:ga164c59c55e2d18bf8a94dc91c0f4ce68"><td class="mdescLeft"> </td><td class="mdescRight">Cache Sync operation by writing CACHE_SYNC register. <a href="group__L2__cache__functions.html#ga164c59c55e2d18bf8a94dc91c0f4ce68">More...</a><br/></td></tr>
<tr class="separator:ga164c59c55e2d18bf8a94dc91c0f4ce68"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga75af64212e1d3d0b3ade860c365e95b3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga75af64212e1d3d0b3ade860c365e95b3">L2C_GetID</a> (void)</td></tr>
<tr class="memdesc:ga75af64212e1d3d0b3ade860c365e95b3"><td class="mdescLeft"> </td><td class="mdescRight">Read cache controller cache ID from CACHE_ID register. <a href="group__L2__cache__functions.html#ga75af64212e1d3d0b3ade860c365e95b3">More...</a><br/></td></tr>
<tr class="separator:ga75af64212e1d3d0b3ade860c365e95b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0c334fa25720d77e78cfa187bdf833be"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga0c334fa25720d77e78cfa187bdf833be">L2C_GetType</a> (void)</td></tr>
<tr class="memdesc:ga0c334fa25720d77e78cfa187bdf833be"><td class="mdescLeft"> </td><td class="mdescRight">Read cache controller cache type from CACHE_TYPE register. <a href="group__L2__cache__functions.html#ga0c334fa25720d77e78cfa187bdf833be">More...</a><br/></td></tr>
<tr class="separator:ga0c334fa25720d77e78cfa187bdf833be"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5b0ea2db52d137b5531ce568479c9d17"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga5b0ea2db52d137b5531ce568479c9d17">L2C_InvAllByWay</a> (void)</td></tr>
<tr class="memdesc:ga5b0ea2db52d137b5531ce568479c9d17"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate all cache by way. <a href="group__L2__cache__functions.html#ga5b0ea2db52d137b5531ce568479c9d17">More...</a><br/></td></tr>
<tr class="separator:ga5b0ea2db52d137b5531ce568479c9d17"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd0a9b10926537fa283c0bb30d54abc7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#gabd0a9b10926537fa283c0bb30d54abc7">L2C_CleanInvAllByWay</a> (void)</td></tr>
<tr class="memdesc:gabd0a9b10926537fa283c0bb30d54abc7"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate all cache by way. <a href="group__L2__cache__functions.html#gabd0a9b10926537fa283c0bb30d54abc7">More...</a><br/></td></tr>
<tr class="separator:gabd0a9b10926537fa283c0bb30d54abc7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga720c36b4cd1d6c070ed0d2c49cffd7e1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga720c36b4cd1d6c070ed0d2c49cffd7e1">L2C_Enable</a> (void)</td></tr>
<tr class="memdesc:ga720c36b4cd1d6c070ed0d2c49cffd7e1"><td class="mdescLeft"> </td><td class="mdescRight">Enable Level 2 Cache. <a href="group__L2__cache__functions.html#ga720c36b4cd1d6c070ed0d2c49cffd7e1">More...</a><br/></td></tr>
<tr class="separator:ga720c36b4cd1d6c070ed0d2c49cffd7e1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga66767e7f30f52d72de72231b2d6abd34"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga66767e7f30f52d72de72231b2d6abd34">L2C_Disable</a> (void)</td></tr>
<tr class="memdesc:ga66767e7f30f52d72de72231b2d6abd34"><td class="mdescLeft"> </td><td class="mdescRight">Disable Level 2 Cache. <a href="group__L2__cache__functions.html#ga66767e7f30f52d72de72231b2d6abd34">More...</a><br/></td></tr>
<tr class="separator:ga66767e7f30f52d72de72231b2d6abd34"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4cf213e72c97776def35ab8223face82"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga4cf213e72c97776def35ab8223face82">L2C_InvPa</a> (void *pa)</td></tr>
<tr class="memdesc:ga4cf213e72c97776def35ab8223face82"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate cache by physical address. <a href="group__L2__cache__functions.html#ga4cf213e72c97776def35ab8223face82">More...</a><br/></td></tr>
<tr class="separator:ga4cf213e72c97776def35ab8223face82"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga242f6fa13f33e7d5cdd7d92935d52f5f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga242f6fa13f33e7d5cdd7d92935d52f5f">L2C_CleanPa</a> (void *pa)</td></tr>
<tr class="memdesc:ga242f6fa13f33e7d5cdd7d92935d52f5f"><td class="mdescLeft"> </td><td class="mdescRight">Clean cache by physical address. <a href="group__L2__cache__functions.html#ga242f6fa13f33e7d5cdd7d92935d52f5f">More...</a><br/></td></tr>
<tr class="separator:ga242f6fa13f33e7d5cdd7d92935d52f5f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaff11c6afa9eaacb4cdfcfe5c36f57eb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#gaaff11c6afa9eaacb4cdfcfe5c36f57eb">L2C_CleanInvPa</a> (void *pa)</td></tr>
<tr class="memdesc:gaaff11c6afa9eaacb4cdfcfe5c36f57eb"><td class="mdescLeft"> </td><td class="mdescRight">Clean and invalidate cache by physical address. <a href="group__L2__cache__functions.html#gaaff11c6afa9eaacb4cdfcfe5c36f57eb">More...</a><br/></td></tr>
<tr class="separator:gaaff11c6afa9eaacb4cdfcfe5c36f57eb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0f44df6823e90178183257e096e5cac6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6">GIC_EnableDistributor</a> (void)</td></tr>
<tr class="memdesc:ga0f44df6823e90178183257e096e5cac6"><td class="mdescLeft"> </td><td class="mdescRight">Enable the interrupt distributor using the GIC's CTLR register. <a href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6">More...</a><br/></td></tr>
<tr class="separator:ga0f44df6823e90178183257e096e5cac6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga363311538d4a4d750197b9936505d466"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga363311538d4a4d750197b9936505d466">GIC_DisableDistributor</a> (void)</td></tr>
<tr class="memdesc:ga363311538d4a4d750197b9936505d466"><td class="mdescLeft"> </td><td class="mdescRight">Disable the interrupt distributor using the GIC's CTLR register. <a href="group__GIC__functions.html#ga363311538d4a4d750197b9936505d466">More...</a><br/></td></tr>
<tr class="separator:ga363311538d4a4d750197b9936505d466"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a> (void)</td></tr>
<tr class="memdesc:ga7d93d39736ef5e379e6511430ee6e75f"><td class="mdescLeft"> </td><td class="mdescRight">Read the GIC's TYPER register. <a href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">More...</a><br/></td></tr>
<tr class="separator:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6">GIC_DistributorImplementer</a> (void)</td></tr>
<tr class="memdesc:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="mdescLeft"> </td><td class="mdescRight">Reads the GIC's IIDR register. <a href="group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6">More...</a><br/></td></tr>
<tr class="separator:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t cpu_target)</td></tr>
<tr class="memdesc:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="mdescLeft"> </td><td class="mdescRight">Sets the GIC's ITARGETSR register for the given interrupt. <a href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">More...</a><br/></td></tr>
<tr class="separator:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafccf881f9517592f30489bcabcb738a8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gafccf881f9517592f30489bcabcb738a8"><td class="mdescLeft"> </td><td class="mdescRight">Read the GIC's ITARGETSR register. <a href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">More...</a><br/></td></tr>
<tr class="separator:gafccf881f9517592f30489bcabcb738a8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce">GIC_EnableInterface</a> (void)</td></tr>
<tr class="memdesc:ga758e5600d7f891e4f2f551bb45d07fce"><td class="mdescLeft"> </td><td class="mdescRight">Enable the CPU's interrupt interface. <a href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce">More...</a><br/></td></tr>
<tr class="separator:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0605877ad627c1f4320e518725fd103e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e">GIC_DisableInterface</a> (void)</td></tr>
<tr class="memdesc:ga0605877ad627c1f4320e518725fd103e"><td class="mdescLeft"> </td><td class="mdescRight">Disable the CPU's interrupt interface. <a href="group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e">More...</a><br/></td></tr>
<tr class="separator:ga0605877ad627c1f4320e518725fd103e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a> (void)</td></tr>
<tr class="memdesc:gafc08bbc58b25fef0d24003313fd16eb8"><td class="mdescLeft"> </td><td class="mdescRight">Read the CPU's IAR register. <a href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">More...</a><br/></td></tr>
<tr class="separator:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac23f090f572a058b4a737f6613ded9cd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gac23f090f572a058b4a737f6613ded9cd"><td class="mdescLeft"> </td><td class="mdescRight">Writes the given interrupt number to the CPU's EOIR register. <a href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">More...</a><br/></td></tr>
<tr class="separator:gac23f090f572a058b4a737f6613ded9cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaeba215d9c4ec3599e0a168800288c3f3"><td class="mdescLeft"> </td><td class="mdescRight">Enables the given interrupt using GIC's ISENABLER register. <a href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">More...</a><br/></td></tr>
<tr class="separator:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abcd7d576ea634b1a708db9fda95d09df"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#abcd7d576ea634b1a708db9fda95d09df">GIC_GetEnableIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:abcd7d576ea634b1a708db9fda95d09df"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt enable status using GIC's ISENABLER register. <a href="#abcd7d576ea634b1a708db9fda95d09df">More...</a><br/></td></tr>
<tr class="separator:abcd7d576ea634b1a708db9fda95d09df"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2102399d255690c0674209a6faeec13d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga2102399d255690c0674209a6faeec13d"><td class="mdescLeft"> </td><td class="mdescRight">Disables the given interrupt using GIC's ICENABLER register. <a href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">More...</a><br/></td></tr>
<tr class="separator:ga2102399d255690c0674209a6faeec13d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab726a01df6ee9a480cc73910a06ddfb7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab726a01df6ee9a480cc73910a06ddfb7">GIC_GetPendingIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ab726a01df6ee9a480cc73910a06ddfb7"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt pending status from GIC's ISPENDR register. <a href="#ab726a01df6ee9a480cc73910a06ddfb7">More...</a><br/></td></tr>
<tr class="separator:ab726a01df6ee9a480cc73910a06ddfb7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga18fbddf7f3594df141c97f61a71da47c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga18fbddf7f3594df141c97f61a71da47c"><td class="mdescLeft"> </td><td class="mdescRight">Sets the given interrupt as pending using GIC's ISPENDR register. <a href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">More...</a><br/></td></tr>
<tr class="separator:ga18fbddf7f3594df141c97f61a71da47c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="mdescLeft"> </td><td class="mdescRight">Clears the given interrupt from being pending using GIC's ICPENDR register. <a href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">More...</a><br/></td></tr>
<tr class="separator:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5dffcd04b18d2c3ee5a410e185ce5108"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5dffcd04b18d2c3ee5a410e185ce5108">GIC_SetConfiguration</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t int_config)</td></tr>
<tr class="memdesc:a5dffcd04b18d2c3ee5a410e185ce5108"><td class="mdescLeft"> </td><td class="mdescRight">Sets the interrupt configuration using GIC's ICFGR register. <a href="#a5dffcd04b18d2c3ee5a410e185ce5108">More...</a><br/></td></tr>
<tr class="separator:a5dffcd04b18d2c3ee5a410e185ce5108"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a43cfac7327b49e2a89d63abc99b6b06a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a43cfac7327b49e2a89d63abc99b6b06a">GIC_GetConfiguration</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:a43cfac7327b49e2a89d63abc99b6b06a"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt configuration from the GIC's ICFGR register. <a href="#a43cfac7327b49e2a89d63abc99b6b06a">More...</a><br/></td></tr>
<tr class="separator:a43cfac7327b49e2a89d63abc99b6b06a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga27b9862b58290276851ec669cabf0f71"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
<tr class="memdesc:ga27b9862b58290276851ec669cabf0f71"><td class="mdescLeft"> </td><td class="mdescRight">Set the priority for the given interrupt in the GIC's IPRIORITYR register. <a href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">More...</a><br/></td></tr>
<tr class="separator:ga27b9862b58290276851ec669cabf0f71"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga397048004654f792649742f95bf8ae67"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga397048004654f792649742f95bf8ae67"><td class="mdescLeft"> </td><td class="mdescRight">Read the current interrupt priority from GIC's IPRIORITYR register. <a href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">More...</a><br/></td></tr>
<tr class="separator:ga397048004654f792649742f95bf8ae67"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (uint32_t priority)</td></tr>
<tr class="memdesc:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="mdescLeft"> </td><td class="mdescRight">Set the interrupt priority mask using CPU's PMR register. <a href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">More...</a><br/></td></tr>
<tr class="separator:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a> (void)</td></tr>
<tr class="memdesc:ga2c5f9e5637560fc9d5c29d772580a728"><td class="mdescLeft"> </td><td class="mdescRight">Read the current interrupt priority mask from CPU's PMR register. <a href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">More...</a><br/></td></tr>
<tr class="separator:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (uint32_t binary_point)</td></tr>
<tr class="memdesc:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="mdescLeft"> </td><td class="mdescRight">Configures the group priority and subpriority split point using CPU's BPR register. <a href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">More...</a><br/></td></tr>
<tr class="separator:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa7046d8206ddd4696716726e68f85906"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a> (void)</td></tr>
<tr class="memdesc:gaa7046d8206ddd4696716726e68f85906"><td class="mdescLeft"> </td><td class="mdescRight">Read the current group priority and subpriority split point from CPU's BPR register. <a href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">More...</a><br/></td></tr>
<tr class="separator:gaa7046d8206ddd4696716726e68f85906"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f">GIC_GetIRQStatus</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="mdescLeft"> </td><td class="mdescRight">Get the status for a given interrupt. <a href="group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f">More...</a><br/></td></tr>
<tr class="separator:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9">GIC_SendSGI</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t target_list, uint32_t filter_list)</td></tr>
<tr class="memdesc:ga2de8850780af26e802ee4cc43e9da6e9"><td class="mdescLeft"> </td><td class="mdescRight">Generate a software interrupt using GIC's SGIR register. <a href="group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9">More...</a><br/></td></tr>
<tr class="separator:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1">GIC_GetHighPendingIRQ</a> (void)</td></tr>
<tr class="memdesc:ga8bb27e1bab132a8df44190adb996c2a1"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. <a href="group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1">More...</a><br/></td></tr>
<tr class="separator:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50">GIC_GetInterfaceId</a> (void)</td></tr>
<tr class="memdesc:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="mdescLeft"> </td><td class="mdescRight">Provides information about the implementer and revision of the CPU interface. <a href="group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50">More...</a><br/></td></tr>
<tr class="separator:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab875d63dc51a75149802945bb00e2695"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t group)</td></tr>
<tr class="memdesc:ab875d63dc51a75149802945bb00e2695"><td class="mdescLeft"> </td><td class="mdescRight">Set the interrupt group from the GIC's IGROUPR register. <a href="#ab875d63dc51a75149802945bb00e2695">More...</a><br/></td></tr>
<tr class="separator:ab875d63dc51a75149802945bb00e2695"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae161d7a866cb61f92b808ae98fa7c812"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae161d7a866cb61f92b808ae98fa7c812">GIC_GetGroup</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ae161d7a866cb61f92b808ae98fa7c812"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt group from the GIC's IGROUPR register. <a href="#ae161d7a866cb61f92b808ae98fa7c812">More...</a><br/></td></tr>
<tr class="separator:ae161d7a866cb61f92b808ae98fa7c812"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1">GIC_DistInit</a> (void)</td></tr>
<tr class="memdesc:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the interrupt distributor. <a href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1">More...</a><br/></td></tr>
<tr class="separator:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9">GIC_CPUInterfaceInit</a> (void)</td></tr>
<tr class="memdesc:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the CPU's interrupt interface. <a href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9">More...</a><br/></td></tr>
<tr class="separator:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a> (void)</td></tr>
<tr class="memdesc:ga818881f69aae3eef6eb996bee6f6c63e"><td class="mdescLeft"> </td><td class="mdescRight">Initialize and enable the GIC. <a href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">More...</a><br/></td></tr>
<tr class="separator:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac09f09327fde6a6adffe0e6298eaa1db"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gac09f09327fde6a6adffe0e6298eaa1db">PL1_SetCounterFrequency</a> (uint32_t value)</td></tr>
<tr class="memdesc:gac09f09327fde6a6adffe0e6298eaa1db"><td class="mdescLeft"> </td><td class="mdescRight">Configures the frequency the timer shall run at. <a href="group__PL1__timer__functions.html#gac09f09327fde6a6adffe0e6298eaa1db">More...</a><br/></td></tr>
<tr class="separator:gac09f09327fde6a6adffe0e6298eaa1db"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae4edcfbdaf901a59a81d1fbf9845d9f7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gae4edcfbdaf901a59a81d1fbf9845d9f7">PL1_SetLoadValue</a> (uint32_t value)</td></tr>
<tr class="memdesc:gae4edcfbdaf901a59a81d1fbf9845d9f7"><td class="mdescLeft"> </td><td class="mdescRight">Sets the reset value of the timer. <a href="group__PL1__timer__functions.html#gae4edcfbdaf901a59a81d1fbf9845d9f7">More...</a><br/></td></tr>
<tr class="separator:gae4edcfbdaf901a59a81d1fbf9845d9f7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8a212e9457005edfb9f14afbf937ebf9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#ga8a212e9457005edfb9f14afbf937ebf9">PL1_GetCurrentValue</a> (void)</td></tr>
<tr class="memdesc:ga8a212e9457005edfb9f14afbf937ebf9"><td class="mdescLeft"> </td><td class="mdescRight">Get the current counter value. <a href="group__PL1__timer__functions.html#ga8a212e9457005edfb9f14afbf937ebf9">More...</a><br/></td></tr>
<tr class="separator:ga8a212e9457005edfb9f14afbf937ebf9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac66bd336d2353f70aa8ebfc73aa3fc43"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gac66bd336d2353f70aa8ebfc73aa3fc43">PL1_GetCurrentPhysicalValue</a> (void)</td></tr>
<tr class="memdesc:gac66bd336d2353f70aa8ebfc73aa3fc43"><td class="mdescLeft"> </td><td class="mdescRight">Get the current physical counter value. <a href="group__PL1__timer__functions.html#gac66bd336d2353f70aa8ebfc73aa3fc43">More...</a><br/></td></tr>
<tr class="separator:gac66bd336d2353f70aa8ebfc73aa3fc43"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab34067824971064a829e17b791070643"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gab34067824971064a829e17b791070643">PL1_SetPhysicalCompareValue</a> (uint64_t value)</td></tr>
<tr class="memdesc:gab34067824971064a829e17b791070643"><td class="mdescLeft"> </td><td class="mdescRight">Set the physical compare value. <a href="group__PL1__timer__functions.html#gab34067824971064a829e17b791070643">More...</a><br/></td></tr>
<tr class="separator:gab34067824971064a829e17b791070643"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga341ae7d1ae29f4dc5dae6310fa453164"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#ga341ae7d1ae29f4dc5dae6310fa453164">PL1_GetPhysicalCompareValue</a> (void)</td></tr>
<tr class="memdesc:ga341ae7d1ae29f4dc5dae6310fa453164"><td class="mdescLeft"> </td><td class="mdescRight">Get the physical compare value. <a href="group__PL1__timer__functions.html#ga341ae7d1ae29f4dc5dae6310fa453164">More...</a><br/></td></tr>
<tr class="separator:ga341ae7d1ae29f4dc5dae6310fa453164"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2e2ea7eac12a90c6243000172bf774e1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#ga2e2ea7eac12a90c6243000172bf774e1">PL1_SetControl</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga2e2ea7eac12a90c6243000172bf774e1"><td class="mdescLeft"> </td><td class="mdescRight">Configure the timer by setting the control value. <a href="group__PL1__timer__functions.html#ga2e2ea7eac12a90c6243000172bf774e1">More...</a><br/></td></tr>
<tr class="separator:ga2e2ea7eac12a90c6243000172bf774e1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf7fda3fe3452565fbe46cb0ea53a9f8a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gaf7fda3fe3452565fbe46cb0ea53a9f8a">PL1_GetControl</a> (void)</td></tr>
<tr class="memdesc:gaf7fda3fe3452565fbe46cb0ea53a9f8a"><td class="mdescLeft"> </td><td class="mdescRight">Get the control value. <a href="group__PL1__timer__functions.html#gaf7fda3fe3452565fbe46cb0ea53a9f8a">More...</a><br/></td></tr>
<tr class="separator:gaf7fda3fe3452565fbe46cb0ea53a9f8a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga30516fed24977be8eecf3efd8b6a2fea"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#ga30516fed24977be8eecf3efd8b6a2fea">PTIM_SetLoadValue</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga30516fed24977be8eecf3efd8b6a2fea"><td class="mdescLeft"> </td><td class="mdescRight">Set the load value to timers LOAD register. <a href="group__PTM__timer__functions.html#ga30516fed24977be8eecf3efd8b6a2fea">More...</a><br/></td></tr>
<tr class="separator:ga30516fed24977be8eecf3efd8b6a2fea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacca3bf92e93c69e538ff4618317f7bfa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gacca3bf92e93c69e538ff4618317f7bfa">PTIM_GetLoadValue</a> (void)</td></tr>
<tr class="memdesc:gacca3bf92e93c69e538ff4618317f7bfa"><td class="mdescLeft"> </td><td class="mdescRight">Get the load value from timers LOAD register. <a href="group__PTM__timer__functions.html#gacca3bf92e93c69e538ff4618317f7bfa">More...</a><br/></td></tr>
<tr class="separator:gacca3bf92e93c69e538ff4618317f7bfa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a323bf405e32846a7e57344935e51de66"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a323bf405e32846a7e57344935e51de66">PTIM_SetCurrentValue</a> (uint32_t value)</td></tr>
<tr class="memdesc:a323bf405e32846a7e57344935e51de66"><td class="mdescLeft"> </td><td class="mdescRight">Set current counter value from its COUNTER register. <a href="#a323bf405e32846a7e57344935e51de66">More...</a><br/></td></tr>
<tr class="separator:a323bf405e32846a7e57344935e51de66"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaccd88ab7931c379817f71d7c0183586"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gaaccd88ab7931c379817f71d7c0183586">PTIM_GetCurrentValue</a> (void)</td></tr>
<tr class="memdesc:gaaccd88ab7931c379817f71d7c0183586"><td class="mdescLeft"> </td><td class="mdescRight">Get current counter value from timers COUNTER register. <a href="group__PTM__timer__functions.html#gaaccd88ab7931c379817f71d7c0183586">More...</a><br/></td></tr>
<tr class="separator:gaaccd88ab7931c379817f71d7c0183586"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaabc1dba029389fe0e2a6297952df7972"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gaabc1dba029389fe0e2a6297952df7972">PTIM_SetControl</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaabc1dba029389fe0e2a6297952df7972"><td class="mdescLeft"> </td><td class="mdescRight">Configure the timer using its CONTROL register. <a href="group__PTM__timer__functions.html#gaabc1dba029389fe0e2a6297952df7972">More...</a><br/></td></tr>
<tr class="separator:gaabc1dba029389fe0e2a6297952df7972"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga34f0ceea142a4be1479cb552bf8bc4d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#ga34f0ceea142a4be1479cb552bf8bc4d1">PTIM_GetControl</a> (void)</td></tr>
<tr class="separator:ga34f0ceea142a4be1479cb552bf8bc4d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2c3f9f942e8a08630562f35802dbe942"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a2c3f9f942e8a08630562f35802dbe942">PTIM_GetEventFlag</a> (void)</td></tr>
<tr class="separator:a2c3f9f942e8a08630562f35802dbe942"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga59dca62df390bc4bce18559fc7d28578"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#ga59dca62df390bc4bce18559fc7d28578">PTIM_ClearEventFlag</a> (void)</td></tr>
<tr class="separator:ga59dca62df390bc4bce18559fc7d28578"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9132cbfe3b2367de3db27daf4cc82ad7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga9132cbfe3b2367de3db27daf4cc82ad7">MMU_XNSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63">mmu_execute_Type</a> xn)</td></tr>
<tr class="memdesc:ga9132cbfe3b2367de3db27daf4cc82ad7"><td class="mdescLeft"> </td><td class="mdescRight">Set section execution-never attribute. <a href="group__MMU__functions.html#ga9132cbfe3b2367de3db27daf4cc82ad7">More...</a><br/></td></tr>
<tr class="separator:ga9132cbfe3b2367de3db27daf4cc82ad7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd88f4c41b74365c38209692785287d0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gabd88f4c41b74365c38209692785287d0">MMU_DomainSection</a> (uint32_t *descriptor_l1, uint8_t domain)</td></tr>
<tr class="memdesc:gabd88f4c41b74365c38209692785287d0"><td class="mdescLeft"> </td><td class="mdescRight">Set section domain. <a href="group__MMU__functions.html#gabd88f4c41b74365c38209692785287d0">More...</a><br/></td></tr>
<tr class="separator:gabd88f4c41b74365c38209692785287d0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3577aec23189228c9f95abba50c3716d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga3577aec23189228c9f95abba50c3716d">MMU_PSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409">mmu_ecc_check_Type</a> p_bit)</td></tr>
<tr class="memdesc:ga3577aec23189228c9f95abba50c3716d"><td class="mdescLeft"> </td><td class="mdescRight">Set section parity check. <a href="group__MMU__functions.html#ga3577aec23189228c9f95abba50c3716d">More...</a><br/></td></tr>
<tr class="separator:ga3577aec23189228c9f95abba50c3716d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga946866c84a72690c385ee07545bf8145"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga946866c84a72690c385ee07545bf8145">MMU_APSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> user, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> priv, uint32_t afe)</td></tr>
<tr class="memdesc:ga946866c84a72690c385ee07545bf8145"><td class="mdescLeft"> </td><td class="mdescRight">Set section access privileges. <a href="group__MMU__functions.html#ga946866c84a72690c385ee07545bf8145">More...</a><br/></td></tr>
<tr class="separator:ga946866c84a72690c385ee07545bf8145"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga29ea426394746cdd6a4b4c14164ec6b9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga29ea426394746cdd6a4b4c14164ec6b9">MMU_SharedSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7">mmu_shared_Type</a> s_bit)</td></tr>
<tr class="memdesc:ga29ea426394746cdd6a4b4c14164ec6b9"><td class="mdescLeft"> </td><td class="mdescRight">Set section shareability. <a href="group__MMU__functions.html#ga29ea426394746cdd6a4b4c14164ec6b9">More...</a><br/></td></tr>
<tr class="separator:ga29ea426394746cdd6a4b4c14164ec6b9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3ca22117a7f2d3c4d1cd1bf832cc4d2f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga3ca22117a7f2d3c4d1cd1bf832cc4d2f">MMU_GlobalSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30">mmu_global_Type</a> g_bit)</td></tr>
<tr class="memdesc:ga3ca22117a7f2d3c4d1cd1bf832cc4d2f"><td class="mdescLeft"> </td><td class="mdescRight">Set section Global attribute. <a href="group__MMU__functions.html#ga3ca22117a7f2d3c4d1cd1bf832cc4d2f">More...</a><br/></td></tr>
<tr class="separator:ga3ca22117a7f2d3c4d1cd1bf832cc4d2f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga84a5a15ee353d70a9b904e3814bd94d8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga84a5a15ee353d70a9b904e3814bd94d8">MMU_SecureSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639">mmu_secure_Type</a> s_bit)</td></tr>
<tr class="memdesc:ga84a5a15ee353d70a9b904e3814bd94d8"><td class="mdescLeft"> </td><td class="mdescRight">Set section Security attribute. <a href="group__MMU__functions.html#ga84a5a15ee353d70a9b904e3814bd94d8">More...</a><br/></td></tr>
<tr class="separator:ga84a5a15ee353d70a9b904e3814bd94d8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab0e0fed40d998757147beb8fcf05a890"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gab0e0fed40d998757147beb8fcf05a890">MMU_XNPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63">mmu_execute_Type</a> xn, <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a">mmu_region_size_Type</a> page)</td></tr>
<tr class="memdesc:gab0e0fed40d998757147beb8fcf05a890"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page execution-never attribute. <a href="group__MMU__functions.html#gab0e0fed40d998757147beb8fcf05a890">More...</a><br/></td></tr>
<tr class="separator:gab0e0fed40d998757147beb8fcf05a890"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga45f5389cb1351bb2806a38ac8c32d416"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga45f5389cb1351bb2806a38ac8c32d416">MMU_DomainPage</a> (uint32_t *descriptor_l1, uint8_t domain)</td></tr>
<tr class="memdesc:ga45f5389cb1351bb2806a38ac8c32d416"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page domain. <a href="group__MMU__functions.html#ga45f5389cb1351bb2806a38ac8c32d416">More...</a><br/></td></tr>
<tr class="separator:ga45f5389cb1351bb2806a38ac8c32d416"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab15289c416609cd56dde816b39a4cea4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gab15289c416609cd56dde816b39a4cea4">MMU_PPage</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409">mmu_ecc_check_Type</a> p_bit)</td></tr>
<tr class="memdesc:gab15289c416609cd56dde816b39a4cea4"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page parity check. <a href="group__MMU__functions.html#gab15289c416609cd56dde816b39a4cea4">More...</a><br/></td></tr>
<tr class="separator:gab15289c416609cd56dde816b39a4cea4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac7c88d4d613350059b4d77814ea2c7a0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gac7c88d4d613350059b4d77814ea2c7a0">MMU_APPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> user, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> priv, uint32_t afe)</td></tr>
<tr class="memdesc:gac7c88d4d613350059b4d77814ea2c7a0"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page access privileges. <a href="group__MMU__functions.html#gac7c88d4d613350059b4d77814ea2c7a0">More...</a><br/></td></tr>
<tr class="separator:gac7c88d4d613350059b4d77814ea2c7a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaa19560532778e4fdc667e56fd2dd378"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gaaa19560532778e4fdc667e56fd2dd378">MMU_SharedPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7">mmu_shared_Type</a> s_bit)</td></tr>
<tr class="memdesc:gaaa19560532778e4fdc667e56fd2dd378"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page shareability. <a href="group__MMU__functions.html#gaaa19560532778e4fdc667e56fd2dd378">More...</a><br/></td></tr>
<tr class="separator:gaaa19560532778e4fdc667e56fd2dd378"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga14dfeaf8983de57521aaa66c19dd43c9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga14dfeaf8983de57521aaa66c19dd43c9">MMU_GlobalPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30">mmu_global_Type</a> g_bit)</td></tr>
<tr class="memdesc:ga14dfeaf8983de57521aaa66c19dd43c9"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page Global attribute. <a href="group__MMU__functions.html#ga14dfeaf8983de57521aaa66c19dd43c9">More...</a><br/></td></tr>
<tr class="separator:ga14dfeaf8983de57521aaa66c19dd43c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2c1887ed6aaff0a51e3effc3db595c94"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga2c1887ed6aaff0a51e3effc3db595c94">MMU_SecurePage</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639">mmu_secure_Type</a> s_bit)</td></tr>
<tr class="memdesc:ga2c1887ed6aaff0a51e3effc3db595c94"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page Security attribute. <a href="group__MMU__functions.html#ga2c1887ed6aaff0a51e3effc3db595c94">More...</a><br/></td></tr>
<tr class="separator:ga2c1887ed6aaff0a51e3effc3db595c94"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga353d3d794bcd1b35b3b5aeb73d6feb08"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga353d3d794bcd1b35b3b5aeb73d6feb08">MMU_MemorySection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2">mmu_memory_Type</a> mem, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> outer, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> inner)</td></tr>
<tr class="memdesc:ga353d3d794bcd1b35b3b5aeb73d6feb08"><td class="mdescLeft"> </td><td class="mdescRight">Set Section memory attributes. <a href="group__MMU__functions.html#ga353d3d794bcd1b35b3b5aeb73d6feb08">More...</a><br/></td></tr>
<tr class="separator:ga353d3d794bcd1b35b3b5aeb73d6feb08"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9a2946f7c93bcb05cdd20be691a54b8c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga9a2946f7c93bcb05cdd20be691a54b8c">MMU_MemoryPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2">mmu_memory_Type</a> mem, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> outer, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> inner, <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a">mmu_region_size_Type</a> page)</td></tr>
<tr class="memdesc:ga9a2946f7c93bcb05cdd20be691a54b8c"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page memory attributes. <a href="group__MMU__functions.html#ga9a2946f7c93bcb05cdd20be691a54b8c">More...</a><br/></td></tr>
<tr class="separator:ga9a2946f7c93bcb05cdd20be691a54b8c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4f21eee79309cf8cde694d0d7e1205bd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga4f21eee79309cf8cde694d0d7e1205bd">MMU_GetSectionDescriptor</a> (uint32_t *descriptor, <a class="el" href="structmmu__region__attributes__Type.html">mmu_region_attributes_Type</a> reg)</td></tr>
<tr class="memdesc:ga4f21eee79309cf8cde694d0d7e1205bd"><td class="mdescLeft"> </td><td class="mdescRight">Create a L1 section descriptor. <a href="group__MMU__functions.html#ga4f21eee79309cf8cde694d0d7e1205bd">More...</a><br/></td></tr>
<tr class="separator:ga4f21eee79309cf8cde694d0d7e1205bd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa2fcfb63c7019665b8a352d54f55d740"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gaa2fcfb63c7019665b8a352d54f55d740">MMU_GetPageDescriptor</a> (uint32_t *descriptor, uint32_t *descriptor2, <a class="el" href="structmmu__region__attributes__Type.html">mmu_region_attributes_Type</a> reg)</td></tr>
<tr class="memdesc:gaa2fcfb63c7019665b8a352d54f55d740"><td class="mdescLeft"> </td><td class="mdescRight">Create a L1 and L2 4k/64k page descriptor. <a href="group__MMU__functions.html#gaa2fcfb63c7019665b8a352d54f55d740">More...</a><br/></td></tr>
<tr class="separator:gaa2fcfb63c7019665b8a352d54f55d740"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaff28ea191391cbbd389d74327961753"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gaaff28ea191391cbbd389d74327961753">MMU_TTSection</a> (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)</td></tr>
<tr class="memdesc:gaaff28ea191391cbbd389d74327961753"><td class="mdescLeft"> </td><td class="mdescRight">Create a 1MB Section. <a href="group__MMU__functions.html#gaaff28ea191391cbbd389d74327961753">More...</a><br/></td></tr>
<tr class="separator:gaaff28ea191391cbbd389d74327961753"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga823cca9649a28bab8a90f8bd9bb92d83"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga823cca9649a28bab8a90f8bd9bb92d83">MMU_TTPage4k</a> (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)</td></tr>
<tr class="memdesc:ga823cca9649a28bab8a90f8bd9bb92d83"><td class="mdescLeft"> </td><td class="mdescRight">Create a 4k page entry. <a href="group__MMU__functions.html#ga823cca9649a28bab8a90f8bd9bb92d83">More...</a><br/></td></tr>
<tr class="separator:ga823cca9649a28bab8a90f8bd9bb92d83"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga48c509501f94a3f7316e79f8ccd34184"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga48c509501f94a3f7316e79f8ccd34184">MMU_TTPage64k</a> (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)</td></tr>
<tr class="memdesc:ga48c509501f94a3f7316e79f8ccd34184"><td class="mdescLeft"> </td><td class="mdescRight">Create a 64k page entry. <a href="group__MMU__functions.html#ga48c509501f94a3f7316e79f8ccd34184">More...</a><br/></td></tr>
<tr class="separator:ga48c509501f94a3f7316e79f8ccd34184"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga63334cbd77d310d078eb226c7542b96b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga63334cbd77d310d078eb226c7542b96b">MMU_Enable</a> (void)</td></tr>
<tr class="memdesc:ga63334cbd77d310d078eb226c7542b96b"><td class="mdescLeft"> </td><td class="mdescRight">Enable MMU. <a href="group__MMU__functions.html#ga63334cbd77d310d078eb226c7542b96b">More...</a><br/></td></tr>
<tr class="separator:ga63334cbd77d310d078eb226c7542b96b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2a2badd06531e04f559b97fdb2aea154"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga2a2badd06531e04f559b97fdb2aea154">MMU_Disable</a> (void)</td></tr>
<tr class="memdesc:ga2a2badd06531e04f559b97fdb2aea154"><td class="mdescLeft"> </td><td class="mdescRight">Disable MMU. <a href="group__MMU__functions.html#ga2a2badd06531e04f559b97fdb2aea154">More...</a><br/></td></tr>
<tr class="separator:ga2a2badd06531e04f559b97fdb2aea154"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9de65bea1cabf73dc4302e0e727cc8c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga9de65bea1cabf73dc4302e0e727cc8c3">MMU_InvalidateTLB</a> (void)</td></tr>
<tr class="memdesc:ga9de65bea1cabf73dc4302e0e727cc8c3"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate entire unified TLB. <a href="group__MMU__functions.html#ga9de65bea1cabf73dc4302e0e727cc8c3">More...</a><br/></td></tr>
<tr class="separator:ga9de65bea1cabf73dc4302e0e727cc8c3"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl class="section version"><dt>Version</dt><dd>V1.0.2 </dd></dl>
<dl class="section date"><dt>Date</dt><dd>12. November 2018 </dd></dl>
</div><h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="add5658d95f6b79934202e6fbf1795b12"></a>
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<td class="memname">#define __CORE_CA_H_DEPENDANT</td>
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<td class="memname">#define __CORE_CA_H_GENERIC</td>
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</div>
</div>
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<td class="memname">#define __FPU_PRESENT   0U</td>
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</div>
</div>
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<td class="memname">#define __FPU_USED   0U</td>
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</div>
</div>
<a class="anchor" id="a6690a7e24ea0ec4b36a8fb077d01a820"></a>
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<td class="memname">#define __GIC_PRESENT   1U</td>
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</div>
</div>
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<td class="memname">#define __I   volatile</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a4cc1649793116d7c2d8afce7a4ffce43"></a>
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<td class="memname">#define __IM   volatile const</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="aec43007d9998a0a0e01faede4133d6be"></a>
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<td class="memname">#define __IO   volatile</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ab6caba5853a60a17e8e04499b52bf691"></a>
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<td class="memname">#define __IOM   volatile</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a7e25d9380f9ef903923964322e71f2f6"></a>
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<td class="memname">#define __O   volatile</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a0ea2009ed8fd9ef35b48708280fdb758"></a>
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<td class="memname">#define __OM   volatile</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a0e57ca9f1bc10c2de05d383d2c76267a"></a>
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<td class="memname">#define __TIM_PRESENT   1U</td>
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<td class="memname">#define _FLD2VAL</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">field, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">value </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)</td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">field</td><td>Name of the register bit field. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value of register. This parameter is interpreted as an uint32_t type. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Masked and shifted bit field value. </dd></dl>
</div>
</div>
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<td class="memname">#define _VAL2FLD</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">field, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">value </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)</td>
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</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">field</td><td>Name of the register bit field. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value of the bit field. This parameter is interpreted as an uint32_t type. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Masked and shifted value. </dd></dl>
</div>
</div>
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<td class="memname">#define GIC_GetSecurity   <a class="el" href="core__ca_8h.html#ae161d7a866cb61f92b808ae98fa7c812">GIC_GetGroup</a></td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a647b0a71258678d75aed0aadd5801612"></a>
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<td class="memname">#define GIC_SetSecurity   <a class="el" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a></td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a234fceea67b5d6c41b0875852d86cc70"></a>
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<td class="memname">#define PAGE_4K_TEXCB_MASK   (0xFFFFFE33)</td>
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</div>
</div>
<a class="anchor" id="a666e7d1971403995104586f35d56590b"></a>
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<td class="memname">#define PAGE_64K_TEXCB_MASK   (0xFFFF8FF3)</td>
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</table>
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</div>
</div>
<a class="anchor" id="af7d3ee23adcaf9221967791f0e64d830"></a>
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<td class="memname">#define PAGE_AP_MASK   (0xFFFFFDCF)</td>
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</div>
</div>
<a class="anchor" id="a0a48a4e79188149fbe886a698b6d9cb4"></a>
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<td class="memname">#define PAGE_DOMAIN_MASK   (0xFFFFFE1F)</td>
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</div>
<a class="anchor" id="a9fe764cc3a117a9ab93a301de8bceed1"></a>
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<td class="memname">#define PAGE_L1_MASK   (0xFFFFFFFC)</td>
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<a class="anchor" id="abd292694d0155e3b0d4c12895a6c8fa6"></a>
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<td class="memname">#define PAGE_L2_4K_MASK   (0xFFFFFFFD)</td>
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</table>
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</div>
</div>
<a class="anchor" id="ab3a82626ee70e38285852a1128b75c7a"></a>
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<td class="memname">#define PAGE_L2_64K_MASK   (0xFFFFFFFC)</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="add5d44ba746fe4d17d8b06a1086aa853"></a>
<div class="memitem">
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<td class="memname">#define PAGE_NG_MASK   (0xFFFFF7FF)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a618b1432615c3242f53360d4364c5797"></a>
<div class="memitem">
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<td class="memname">#define PAGE_NS_MASK   (0xFFFFFFF7)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a604f4f13fcb78ff08d65ef4a1a3f7933"></a>
<div class="memitem">
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<td class="memname">#define PAGE_P_MASK   (0xFFFFFDFF)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ac44cd885615a54131c372abfdc2d5c66"></a>
<div class="memitem">
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<td class="memname">#define PAGE_S_MASK   (0xFFFFFBFF)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="aa488ef0c274f8ae125f61129745b1629"></a>
<div class="memitem">
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<td class="memname">#define PAGE_TEXCB_MASK   (0xFFFF8FF3)</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a522f61b0d301d6f69c33a629e1699c7e"></a>
<div class="memitem">
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<td class="memname">#define PAGE_XN_4K_MASK   (0xFFFFFFFE)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ae0445cb4d6dc78359074cbb2776e3b5c"></a>
<div class="memitem">
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<td class="memname">#define PAGE_XN_64K_MASK   (0xFFFF7FFF)</td>
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</table>
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</div>
</div>
<a class="anchor" id="af7f66fda711fd46e157dbb6c1af88e04"></a>
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<td class="memname">#define RESERVED</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">N, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">T </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td>   T RESERVED##N;</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a725efc96ea9aa940fefcf013bce6ca8c"></a>
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<td class="memname">#define SECTION_AP_MASK   (0xFFFF73FF)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a90a30c02512cbea24791212af9f2cd9f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define SECTION_DOMAIN_MASK   (0xFFFFFE1F)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a16f225cca51a80c5cf1c9c002cfd2dba"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_MASK   (0xFFFFFFFC)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a01ceacdb3888d7cddcfeccfea9eb3658"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_NG_MASK   (0xFFFDFFFF)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a470b88645153aad94b09485f3108c641"></a>
<div class="memitem">
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<td class="memname">#define section_normal_nc</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">descriptor_l1, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">region </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a057533871fa1af6db7a27b39d976ac95"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_NS_MASK   (0xFFF7FFFF)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ad32d146d84a9d7f964f28f1dadc98bcb"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_P_MASK   (0xFFFFFDFF)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a42d3645aad501af4ef447186c01685b7"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_S_MASK   (0xFFFEFFFF)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a3052ba3d97ad157189a6c6fce15b1b6a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_TEXCB_MASK   (0xFFFF8FF3)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a83cb551c9fa708e33082c682be614334"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define SECTION_XN_MASK   (0xFFFFFFEF)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="a5ace5c651cf18aaa7659e1fbe6e77988"></a>
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<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __L1C_MaintainDCacheSetWay </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>level</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>maint</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">level</td><td>cache level to be maintained </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">maint</td><td>0 - invalidate, 1 - clean, otherwise - invalidate and clean </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="a35988a42567ca868bffd0b6171021ecb"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint8_t __log2_up </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>n</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<ul>
<li>log(0) => 0</li>
<li>log(1) => 0</li>
<li>log(2) => 1</li>
<li>log(3) => 2</li>
<li>log(4) => 2</li>
<li>log(5) => 3 : :</li>
<li>log(16) => 4</li>
<li>log(32) => 5 : : <dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">n</td><td>input value parameter </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>log2(n) </dd></dl>
</li>
</ul>
</div>
</div>
<a class="anchor" id="a43cfac7327b49e2a89d63abc99b6b06a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetConfiguration </td>
<td>(</td>
<td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to acquire the configuration for. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered </dd></dl>
</div>
</div>
<a class="anchor" id="abcd7d576ea634b1a708db9fda95d09df"></a>
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<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetEnableIRQ </td>
<td>(</td>
<td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - interrupt is not enabled, 1 - interrupt is enabled. </dd></dl>
</div>
</div>
<a class="anchor" id="ae161d7a866cb61f92b808ae98fa7c812"></a>
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<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetGroup </td>
<td>(</td>
<td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - Group 0, 1 - Group 1 </dd></dl>
</div>
</div>
<a class="anchor" id="ab726a01df6ee9a480cc73910a06ddfb7"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetPendingIRQ </td>
<td>(</td>
<td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - interrupt is not pending, 1 - interrupt is pendig. </dd></dl>
</div>
</div>
<a class="anchor" id="a5dffcd04b18d2c3ee5a410e185ce5108"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetConfiguration </td>
<td>(</td>
<td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>int_config</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be configured. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">int_config</td><td>Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ab875d63dc51a75149802945bb00e2695"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetGroup </td>
<td>(</td>
<td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>group</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">group</td><td>Interrupt group number: 0 - Group 0, 1 - Group 1 </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="a2c3f9f942e8a08630562f35802dbe942"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t PTIM_GetEventFlag </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>ref <a class="el" href="structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4" title="Offset: 0x008 (R/W) Private Timer Control Register. ">Timer_Type::CONTROL</a> Get the event flag in timers ISR register. </p>
<dl class="section return"><dt>Returns</dt><dd>0 - flag is not set, 1- flag is set </dd></dl>
</div>
</div>
<a class="anchor" id="a323bf405e32846a7e57344935e51de66"></a>
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void PTIM_SetCurrentValue </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>value</em></td><td>)</td>
<td></td>
</tr>
</table>
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<p>CMSIS Cortex-A Core Peripheral Access Layer Header File.
<a href="#details">More...</a></p>
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Macros</h2></td></tr>
<tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)</td></tr>
<tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a bit field value for assigning the result to a peripheral register. <a href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">More...</a><br/></td></tr>
<tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)</td></tr>
<tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft"> </td><td class="mdescRight">Extract from a peripheral register value the a bit field value. <a href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">More...</a><br/></td></tr>
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<dt><a class="anchor" id="_deprecated000002"></a>Global <a class="el" href="group__L1__cache__functions.html#ga722ceb077e491bb4befcfbb3aee9b20b">__L1C_CleanInvalidateCache</a> (uint32_t op)</dt>
<dd>Use generic L1C_CleanInvalidateCache instead. </dd>
<dt><a class="anchor" id="_deprecated000003"></a>Global <a class="el" href="cmsis__cp15_8h.html#a639d467f42fdad7a173f90568b697fc8">__set_CCSIDR</a> (uint32_t value)</dt>
<dd>CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. </dd>
<dt><a class="anchor" id="_deprecated000001"></a>Global <a class="el" href="group__comp__cntrl__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a> </dt>
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<div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p>
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<li><a class="el" href="device_h_pg.html#irqn_defs">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
<li><a class="el" href="device_h_pg.html#config_perifs">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
<li><a class="el" href="device_h_pg.html#access_perifs">Device Peripheral Access Layer</a> definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
<li><b>Access Functions for Peripherals (optioal)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
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<h1><a class="anchor" id="irqn_defs"></a>
Interrupt Number Definition</h1>
<h1><a class="anchor" id="config_perifs"></a>
Configuration of the Processor and Core Peripherals</h1>
<h1><a class="anchor" id="access_perifs"></a>
Device Peripheral Access Layer</h1>
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p>
<ul>
<li><a class="el" href="device_h_pg.html#irqn_defs">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
<li><a class="el" href="device_h_pg.html#config_perifs">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
<li><a class="el" href="device_h_pg.html#access_perifs">Device Peripheral Access Layer</a> definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
<li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
</ul>
<p><a href="Modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</p>
<h1><a class="anchor" id="interrupt_number_sec"></a>
Interrupt Number Definition</h1>
<p><a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the enumeration <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device. For devices implementing an Arm GIC these are defined as:</p>
<ul>
<li>IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.</li>
<li>IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.</li>
<li>IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.</li>
<li>IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.</li>
</ul>
<p><b>Example:</b> </p>
<p>The following example shows the extension of the interrupt vector table for Cortex-A9 class device.</p>
<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div>
<div class="line">{</div>
<div class="line"><span class="comment">/****** SGI Interrupts Numbers ****************************************/</span></div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a> = 0, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b">SGI1_IRQn</a> = 1,</div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07">SGI2_IRQn</a> = 2,</div>
<div class="line"> : :</div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321">SGI15_IRQn</a> = 15,</div>
<div class="line"></div>
<div class="line"><span class="comment">/****** Cortex-A9 Processor Exceptions Numbers ****************************************/</span></div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a69c74fffb53f9a8739613443943a94c3">GlobalTimer_IRQn</a> = 27, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249">PrivTimer_IRQn</a> = 29, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8aeb45b2fc32150bf94ecf305ee223f28f">PrivWatchdog_IRQn</a> = 30, </div>
<div class="line"><span class="comment">/****** Platform Exceptions Numbers ***************************************************/</span></div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a3f04766f3177f0152623a86e39ccef06">Watchdog_IRQn</a> = 32, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8adffcd012ea2c7bf76124965d8506df72">Timer0_IRQn</a> = 34, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ad0611a4c93162877ed3eb622f49e14a3">Timer1_IRQn</a> = 35, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8abdd513b1533957e93fe0d7f26024d28e">RTClock_IRQn</a> = 36, </div>
<div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ae9122b85b58f7c24033a8515615a7b74">UART0_IRQn</a> = 37, </div>
<div class="line"> : :</div>
<div class="line"> : :</div>
<div class="line">} <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>;</div>
</div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a>
Configuration of the Processor and Core Peripherals</h1>
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> configures the Cortex-A processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_<cpu>.h</b>.</p>
<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__CORTEX_A </td><td>5, 7, 9 </td><td>(n/a) </td><td>Core type number </td></tr>
<tr>
<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if an FPU is present or not </td></tr>
<tr>
<td>__GIC_PRESENT </td><td>0 ..1 </td><td>Defines if an GIC is present or not </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__TIM_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a private timer is present or not </td></tr>
<tr>
<td>__L2C_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a level 2 cache controller is present or not </td></tr>
</table>
<p><b>Example</b> </p>
<p>The following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CA_REV 0x0000U </span></div>
<div class="line"><span class="preprocessor">#define __CORTEX_A 9U </span></div>
<div class="line"><span class="preprocessor">#define __FPU_PRESENT 1U </span></div>
<div class="line"><span class="preprocessor">#define __GIC_PRESENT 1U </span></div>
<div class="line"><span class="preprocessor">#define __TIM_PRESENT 0U </span></div>
<div class="line"><span class="preprocessor">#define __L2C_PRESENT 0U </span></div>
<div class="line"><span class="preprocessor">:</span></div>
<div class="line"><span class="preprocessor"></span>:</div>
<div class="line"><span class="preprocessor">#include "<a class="code" href="core__ca_8h.html">core_ca.h</a>"</span> <span class="comment">/* Cortex-A processor and core peripherals */</span></div>
</div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a>
CMSIS Version and Processor Information</h1>
<p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-Core-A and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> to verify a minimum version or ensure that the right processor core is used.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CA_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS Core main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CA_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS Core sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CA_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS Core version number */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><h1><a class="anchor" id="device_access"></a>
Device Peripheral Access Layer</h1>
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains for each peripheral:</p>
<ul>
<li>Register Layout Typedef</li>
<li>Base Address</li>
<li>Access Definitions</li>
</ul>
<p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p>
<h1><a class="anchor" id="device_h_sec"></a>
Device.h Template File</h1>
<p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p>
<pre class="fragment">/**************************************************************************//**
* @file <Device>.h
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
* @version V1.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */
#define <Device>_H
#ifdef __cplusplus
extern "C" {
#endif
/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment */
/** @addtogroup <Vendor>
* @{
*/
/* ToDo: replace '<Device>' with device name; add your doxyGen comment */
/** @addtogroup <Device>
* @{
*/
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum IRQn
{
/* ======================================= ARM Cortex-A Specific Interrupt Numbers ========================================= */
/* Software Generated Interrupts */
SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */
SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */
SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */
SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */
SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */
SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */
SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */
SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */
SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */
SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */
SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */
SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */
SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */
SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */
SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */
SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */
/* Private Peripheral Interrupts */
VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */
HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */
VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */
Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */
SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */
NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */
Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */
/* Shared Peripheral Interrupts */
/* ToDo: add here your device specific external interrupt numbers */
<DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the Arm Cortex-A Processor and Core Peripherals ============================ */
/* ToDo: set the defines according your Device */
/* ToDo: define the correct core revision
5U if your device is a CORTEX-A5 device
7U if your device is a CORTEX-A7 device
9U if your device is a CORTEX-A9 device */
#define __CORTEX_A #U /*!< Cortex-A# Core */
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
/* ToDo: define the correct core features for the <Device> */
#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */
#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */
#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */
#define __L2C_PRESENT 1U /*!< Set to 1 if L2C is present */
/** @} */ /* End of group Configuration_of_CMSIS */
/* ToDo: include the correct core_ca#.h file
core_ca5.h if your device is a CORTEX-A5 device
core_ca7.h if your device is a CORTEX-A7 device
core_ca9.h if your device is a CORTEX-A9 device */
#include <core_ca#.h> /*!< Arm Cortex-A# processor and core peripherals */
/* ToDo: include your system_<Device>.h file
replace '<Device>' with your device name */
#include "system_<Device>.h" /*!< <Device> System */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* ToDo: add here your device specific peripheral access structure typedefs
following is an example for a timer */
/* =========================================================================================================================== */
/* ================ TMR ================ */
/* =========================================================================================================================== */
/**
* @brief Timer (TMR)
*/
typedef struct
{ /*!< (@ 0x40000000) TIM Structure */
__IOM uint32_t TimerLoad; /*!< (@ 0x00000004) Timer Load */
__IM uint32_t TimerValue; /*!< (@ 0x00000008) Timer Counter Current Value */
__IOM uint32_t TimerControl; /*!< (@ 0x0000000C) Timer Control */
__OM uint32_t TimerIntClr; /*!< (@ 0x00000010) Timer Interrupt Clear */
__IM uint32_t TimerRIS; /*!< (@ 0x00000014) Timer Raw Interrupt Status */
__IM uint32_t TimerMIS; /*!< (@ 0x00000018) Timer Masked Interrupt Status */
__IM uint32_t RESERVED[1];
__IOM uint32_t TimerBGLoad; /*!< (@ 0x00000020) Background Load Register */
} <DeviceAbbreviation>_TMR_TypeDef;
/*@}*/ /* end of group <Device>_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/* ToDo: add here your device peripherals base addresses
following is an example for timer */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
/* Peripheral and SRAM base address */
#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
/* Peripheral memory map */
#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */
#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */
#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/* ToDo: add here your device peripherals pointer definitions
following is an example for timer */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
/** @} */ /* End of group <Device> */
/** @} */ /* End of group <Vendor> */
#ifdef __cplusplus
}
#endif
#endif /* <Device>_H */
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padding-left: 2px;
padding-right: 2px;
color: #3A568E;
}
div.dynheader {
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border-bottom: 1px solid #A7B8DA;
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border:solid 1px #C1CDE5;
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margin:0px;
padding:0px;
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{
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float:left;
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background-color: #F9FAFC;
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padding: 5px 5px 5px 10px;
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{
margin-left: 0px;
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dl.note
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font-weight: bold;
color: gray;
cursor: pointer;
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user-select: none;
}
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margin-bottom: 4px;
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cursor: default;
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max-width: 80%;
opacity: 0.9;
padding: 1ex 1em 1em;
position: absolute;
z-index: 2147483647;
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color: grey;
font-style: italic;
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font-weight: bold;
}
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margin: 0px;
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margin: 0px -11px;
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left: 50%;
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border-width: 10px;
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}
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border-left-color: #ffffff;
border-width: 10px;
top: 50%;
margin-top: -10px;
}
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border-left-color: #808080;
border-width: 11px;
top: 50%;
margin-top: -11px;
}
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right: 100%;
}
#powerTip.w:after {
border-right-color: #ffffff;
border-width: 10px;
top: 50%;
margin-top: -10px;
}
#powerTip.w:before {
border-right-color: #808080;
border-width: 11px;
top: 50%;
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{
#top { display: none; }
#side-nav { display: none; }
#nav-path { display: none; }
body { overflow:visible; }
h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }
.summary { display: none; }
.memitem { page-break-inside: avoid; }
#doc-content
{
margin-left:0 !important;
height:auto !important;
width:auto !important;
overflow:inherit;
display:inline;
}
}
| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/doxygen.css | CSS | apache-2.0 | 23,935 |
function toggleVisibility(linkObj)
{
var base = $(linkObj).attr('id');
var summary = $('#'+base+'-summary');
var content = $('#'+base+'-content');
var trigger = $('#'+base+'-trigger');
var src=$(trigger).attr('src');
if (content.is(':visible')===true) {
content.hide();
summary.show();
$(linkObj).addClass('closed').removeClass('opened');
$(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');
} else {
content.show();
summary.hide();
$(linkObj).removeClass('closed').addClass('opened');
$(trigger).attr('src',src.substring(0,src.length-10)+'open.png');
}
return false;
}
function updateStripes()
{
$('table.directory tr').
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}
function toggleLevel(level)
{
$('table.directory tr').each(function(){
var l = this.id.split('_').length-1;
var i = $('#img'+this.id.substring(3));
var a = $('#arr'+this.id.substring(3));
if (l<level+1) {
i.attr('src','ftv2folderopen.png');
a.attr('src','ftv2mnode.png');
$(this).show();
} else if (l==level+1) {
i.attr('src','ftv2folderclosed.png');
a.attr('src','ftv2pnode.png');
$(this).show();
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$(this).hide();
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});
updateStripes();
}
function toggleFolder(id)
{
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var currentRow = $('#row_'+id);
var currentRowImages = currentRow.find("img");
//All rows after the clicked row
var rows = currentRow.nextAll("tr");
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var childRows = rows.filter(function() {
var re = new RegExp('^row_'+id+'\\d+_$', "i"); //only one sub
return this.id.match(re);
});
//First row is visible we are HIDING
if (childRows.filter(':first').is(':visible')===true) {
currentRowImages.filter("[id^=arr]").attr('src', 'ftv2pnode.png');
currentRowImages.filter("[id^=img]").attr('src', 'ftv2folderclosed.png');
rows.filter("[id^=row_"+id+"]").hide();
} else { //We are SHOWING
//All sub images
var childImages = childRows.find("img");
var childImg = childImages.filter("[id^=img]");
var childArr = childImages.filter("[id^=arr]");
currentRow.find("[id^=arr]").attr('src', 'ftv2mnode.png'); //open row
currentRow.find("[id^=img]").attr('src', 'ftv2folderopen.png'); //open row
childImg.attr('src','ftv2folderclosed.png'); //children closed
childArr.attr('src','ftv2pnode.png'); //children closed
childRows.show(); //show all children
}
updateStripes();
}
function toggleInherit(id)
{
var rows = $('tr.inherit.'+id);
var img = $('tr.inherit_header.'+id+' img');
var src = $(img).attr('src');
if (rows.filter(':first').is(':visible')===true) {
rows.css('display','none');
$(img).attr('src',src.substring(0,src.length-8)+'closed.png');
} else {
rows.css('display','table-row'); // using show() causes jump in firefox
$(img).attr('src',src.substring(0,src.length-10)+'open.png');
}
}
| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/dynsections.js | JavaScript | apache-2.0 | 2,983 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<title>File List</title>
<title>CMSIS-Core (Cortex-A): File List</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<link href="cmsis.css" rel="stylesheet" type="text/css" />
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<script type="text/javascript" src="printComponentTabs.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
$(document).ready(initResizable);
$(window).load(resizeHeight);
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<link href="search/search.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="search/search.js"></script>
<script type="text/javascript">
$(document).ready(function() { searchBox.OnSelectItem(0); });
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<tbody>
<tr style="height: 46px;">
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
<td style="padding-left: 0.5em;">
<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
</div>
<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
</td>
</tr>
</tbody>
</table>
</div>
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<div id="CMSISnav" class="tabs1">
<ul class="tablist">
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var searchBox = new SearchBox("searchBox", "search",false,'Search');
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<div id="navrow1" class="tabs">
<ul class="tablist">
<li><a href="index.html"><span>Main Page</span></a></li>
<li><a href="pages.html"><span>Usage and Description</span></a></li>
<li><a href="modules.html"><span>Reference</span></a></li>
<li>
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<span class="left">
<img id="MSearchSelect" src="search/mag_sel.png"
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<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
<li>A
: <a class="el" href="unionCPSR__Type.html#a8dc2435a7c376c9b8dfdd9748c091458">CPSR_Type</a>
, <a class="el" href="unionISR__Type.html#ad4dfcb37f30162fd57c4402ae99ca49e">ISR_Type</a>
, <a class="el" href="unionSCTLR__Type.html#a078edcb9c3fc8b46b8cf382ad249bb79">SCTLR_Type</a>
</li>
<li>ABPR
: <a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">GICInterface_Type</a>
</li>
<li>ADDRESS_FILTER_END
: <a class="el" href="structL2C__310__TypeDef.html#a956e7653f25ae52ac9534eb0e1d94c8c">L2C_310_TypeDef</a>
</li>
<li>ADDRESS_FILTER_START
: <a class="el" href="structL2C__310__TypeDef.html#ae3f752040cdfcabd337b3f0359216b11">L2C_310_TypeDef</a>
</li>
<li>AEOIR
: <a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">GICInterface_Type</a>
</li>
<li>AFE
: <a class="el" href="unionSCTLR__Type.html#ae5a729bf64a6de4cbfa42c1a7d254535">SCTLR_Type</a>
</li>
<li>AHPPIR
: <a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">GICInterface_Type</a>
</li>
<li>AIAR
: <a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">GICInterface_Type</a>
</li>
<li>AOW
: <a class="el" href="unionACTLR__Type.html#a3f235030777fe4e20477063df416b515">ACTLR_Type</a>
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: <a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">GICInterface_Type</a>
</li>
<li>ASEDIS
: <a class="el" href="unionCPACR__Type.html#a792fabd71db2311eefbc9b896db37986">CPACR_Type</a>
</li>
<li>AUX_CNT
: <a class="el" href="structL2C__310__TypeDef.html#a4f7bc7277a5baa1d804913e41b8200be">L2C_310_TypeDef</a>
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 <span id="projectnumber">Version 1.1.4</span>
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<li><a href="functions_t.html#index_t"><span>t</span></a></li>
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<li><a href="functions_v.html#index_v"><span>v</span></a></li>
<li><a href="functions_w.html#index_w"><span>w</span></a></li>
<li><a href="functions_x.html#index_x"><span>x</span></a></li>
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<li>b
: <a class="el" href="unionACTLR__Type.html#ac953059faa3a1139f8787d87f58a875d">ACTLR_Type</a>
, <a class="el" href="unionCNTP__CTL__Type.html#afdd6b14cdb03e4e694ec7db8163916b0">CNTP_CTL_Type</a>
, <a class="el" href="unionCPACR__Type.html#a7aa1870fa74e00241618df136e04141f">CPACR_Type</a>
, <a class="el" href="unionCPSR__Type.html#a2e735da6b6156874d12aaceb2017da06">CPSR_Type</a>
, <a class="el" href="unionISR__Type.html#ad01f116d61c2ae79c2469a38a0b2f497">ISR_Type</a>
</li>
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: <a class="el" href="unionSCTLR__Type.html#a805ee3324a333d7a77d9f0d8f0fac9a7">SCTLR_Type</a>
</li>
<li>b
: <a class="el" href="unionSCTLR__Type.html#a21ec59a37644281456a5f607450951d8">SCTLR_Type</a>
</li>
<li>BP
: <a class="el" href="unionACTLR__Type.html#ac8ac735e3001442e581ae37e773b5929">ACTLR_Type</a>
</li>
<li>BPR
: <a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">GICInterface_Type</a>
</li>
<li>BTDIS
: <a class="el" href="unionACTLR__Type.html#ad1a121373ae8df19f6d11bde3b3ba9c9">ACTLR_Type</a>
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<li><a href="functions_s.html#index_s"><span>s</span></a></li>
<li><a href="functions_t.html#index_t"><span>t</span></a></li>
<li><a href="functions_u.html#index_u"><span>u</span></a></li>
<li><a href="functions_v.html#index_v"><span>v</span></a></li>
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<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
<li>C
: <a class="el" href="unionCPSR__Type.html#aa967d0e42ed00bd886b2c6df6f49a7e2">CPSR_Type</a>
, <a class="el" href="unionSCTLR__Type.html#a122a4dde5ab1a27855ddad88bb3f9f78">SCTLR_Type</a>
</li>
<li>CACHE_ID
: <a class="el" href="structL2C__310__TypeDef.html#a87833c2acdf685d6ad6d0811f45677d7">L2C_310_TypeDef</a>
</li>
<li>CACHE_SYNC
: <a class="el" href="structL2C__310__TypeDef.html#ab9b9d1842b5d9e828a6825533ab80c0f">L2C_310_TypeDef</a>
</li>
<li>CACHE_TYPE
: <a class="el" href="structL2C__310__TypeDef.html#af19e1fd8a729834557884232c9e50bd2">L2C_310_TypeDef</a>
</li>
<li>CLEAN_INV_LINE_INDEX_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a2adcc6bff9e527be24076d197368a962">L2C_310_TypeDef</a>
</li>
<li>CLEAN_INV_LINE_PA
: <a class="el" href="structL2C__310__TypeDef.html#a61615f4a4ac97d5d278000a35100d795">L2C_310_TypeDef</a>
</li>
<li>CLEAN_INV_WAY
: <a class="el" href="structL2C__310__TypeDef.html#ae27fc13cf14eae85ad7ed2c86fd30f6c">L2C_310_TypeDef</a>
</li>
<li>CLEAN_LINE_INDEX_WAY
: <a class="el" href="structL2C__310__TypeDef.html#ac79d3397741a3ae8566c878b45d30970">L2C_310_TypeDef</a>
</li>
<li>CLEAN_LINE_PA
: <a class="el" href="structL2C__310__TypeDef.html#a400d9ededaf12a5193e01d7235f3d65d">L2C_310_TypeDef</a>
</li>
<li>CLEAN_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a0e6d40fb25420d5cac5be15ad2662e2c">L2C_310_TypeDef</a>
</li>
<li>CLRSPI_NSR
: <a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">GICDistributor_Type</a>
</li>
<li>CLRSPI_SR
: <a class="el" href="structGICDistributor__Type.html#ab487e4a8684b8a77357c6c20cf71dead">GICDistributor_Type</a>
</li>
<li>CM
: <a class="el" href="unionDFSR__Type.html#a38562a26cc210ea4c39c6b951c4a5b62">DFSR_Type</a>
</li>
<li>CONTROL
: <a class="el" href="structL2C__310__TypeDef.html#a491a4ed1ecdcdf784b180fa13ef46f2f">L2C_310_TypeDef</a>
, <a class="el" href="structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4">Timer_Type</a>
</li>
<li>COUNTER
: <a class="el" href="structTimer__Type.html#ac933977724591e6ca87d91848fc7a6b6">Timer_Type</a>
</li>
<li>CP0
: <a class="el" href="unionCPACR__Type.html#a1a29bc40d708ac1a43153b11f60b8195">CPACR_Type</a>
</li>
<li>CP1
: <a class="el" href="unionCPACR__Type.html#acb2055cdbdf2a6c9b8279dc6f7cbc624">CPACR_Type</a>
</li>
<li>CP10
: <a class="el" href="unionCPACR__Type.html#a0275dc6b0eb9f906ebc5c6431b03dc4e">CPACR_Type</a>
</li>
<li>CP11
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<li>CP12
: <a class="el" href="unionCPACR__Type.html#a68d69635225dd479d3035cc51b4c40ce">CPACR_Type</a>
</li>
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: <a class="el" href="unionCPACR__Type.html#a45d9be266fc37a6ff9f31c2bef897f90">CPACR_Type</a>
</li>
<li>CP15BEN
: <a class="el" href="unionSCTLR__Type.html#a98b55213f3bf0a8bd4f1db90512238de">SCTLR_Type</a>
</li>
<li>CP2
: <a class="el" href="unionCPACR__Type.html#a2553fcdfd94ffc09407db9da9db9d586">CPACR_Type</a>
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: <a class="el" href="unionCPACR__Type.html#af245b8dabfea0bf7dc06f5d4de7bfa79">CPACR_Type</a>
</li>
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: <a class="el" href="unionCPACR__Type.html#a6424b7a81a440217aab8e51e4b623adb">CPACR_Type</a>
</li>
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: <a class="el" href="unionCPACR__Type.html#ad5c0b15cd6a01a6f1db398e020809573">CPACR_Type</a>
</li>
<li>CP6
: <a class="el" href="unionCPACR__Type.html#ad898cab7c89a07b80068d141ced869e3">CPACR_Type</a>
</li>
<li>CP7
: <a class="el" href="unionCPACR__Type.html#a12002991719fb1af7a5db9a73deb323d">CPACR_Type</a>
</li>
<li>CP8
: <a class="el" href="unionCPACR__Type.html#a5a6f694264518a813bdbc202ff47664f">CPACR_Type</a>
</li>
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: <a class="el" href="unionCPACR__Type.html#a4de69636eb450fcc3f5f3e4a19a869f5">CPACR_Type</a>
</li>
<li>CPENDSGIR
: <a class="el" href="structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b">GICDistributor_Type</a>
</li>
<li>CTLR
: <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">GICDistributor_Type</a>
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</div><!-- doc-content -->
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/functions_c.html | HTML | apache-2.0 | 12,648 |
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<li><a href="functions_p.html#index_p"><span>p</span></a></li>
<li><a href="functions_q.html#index_q"><span>q</span></a></li>
<li><a href="functions_r.html#index_r"><span>r</span></a></li>
<li><a href="functions_s.html#index_s"><span>s</span></a></li>
<li><a href="functions_t.html#index_t"><span>t</span></a></li>
<li><a href="functions_u.html#index_u"><span>u</span></a></li>
<li><a href="functions_v.html#index_v"><span>v</span></a></li>
<li><a href="functions_w.html#index_w"><span>w</span></a></li>
<li><a href="functions_x.html#index_x"><span>x</span></a></li>
<li><a href="functions_z.html#index_z"><span>z</span></a></li>
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<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div>
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: <a class="el" href="unionACTLR__Type.html#a19e5f8f1a2ad8634619399b4eb50a449">ACTLR_Type</a>
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: <a class="el" href="structL2C__310__TypeDef.html#a996a2a5c1f311a6f3555844adc28e7f4">L2C_310_TypeDef</a>
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<li>DIR
: <a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">GICInterface_Type</a>
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: <a class="el" href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">ACTLR_Type</a>
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<li>Domain
: <a class="el" href="unionDFSR__Type.html#a38982c7088a4069f8a4b347f5eb400e9">DFSR_Type</a>
</li>
<li>domain
: <a class="el" href="structmmu__region__attributes__Type.html#a94158b710d212b8ca8105d78a910db39">mmu_region_attributes_Type</a>
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: <a class="el" href="unionACTLR__Type.html#ad8faaa57629f258c6eba678ba8efc9da">ACTLR_Type</a>
</li>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/functions_d.html | HTML | apache-2.0 | 10,793 |
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<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
<li>E
: <a class="el" href="unionCPSR__Type.html#a96bd175ed9927279dba40e76259dcfa7">CPSR_Type</a>
</li>
<li>e_t
: <a class="el" href="structmmu__region__attributes__Type.html#a7883ad6e464090150b175a54c68f592e">mmu_region_attributes_Type</a>
</li>
<li>EE
: <a class="el" href="unionSCTLR__Type.html#af868e042d01b612649539c151f1aaea5">SCTLR_Type</a>
</li>
<li>ENABLE
: <a class="el" href="unionCNTP__CTL__Type.html#a3b7426f99d1ecdacd172999b4d04b210">CNTP_CTL_Type</a>
</li>
<li>EOIR
: <a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">GICInterface_Type</a>
</li>
<li>EVENT_CONTROL
: <a class="el" href="structL2C__310__TypeDef.html#a2bc6f09ea83f8d3c966558598a098995">L2C_310_TypeDef</a>
</li>
<li>EVENT_COUNTER0_CONF
: <a class="el" href="structL2C__310__TypeDef.html#a1c78032b2b237ee968d6758bddc915ba">L2C_310_TypeDef</a>
</li>
<li>EVENT_COUNTER1_CONF
: <a class="el" href="structL2C__310__TypeDef.html#a4465c7dd7b45f8f35acde8c6e28cbd17">L2C_310_TypeDef</a>
</li>
<li>EXCL
: <a class="el" href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">ACTLR_Type</a>
</li>
<li>ExT
: <a class="el" href="unionDFSR__Type.html#aede34079d030df1977646c155a90f445">DFSR_Type</a>
, <a class="el" href="unionIFSR__Type.html#aee6fed7525c5125e637acc8e957c8d0f">IFSR_Type</a>
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<li><a href="functions_r.html#index_r"><span>r</span></a></li>
<li><a href="functions_s.html#index_s"><span>s</span></a></li>
<li><a href="functions_t.html#index_t"><span>t</span></a></li>
<li><a href="functions_u.html#index_u"><span>u</span></a></li>
<li><a href="functions_v.html#index_v"><span>v</span></a></li>
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<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
<li>F
: <a class="el" href="unionCPSR__Type.html#a20bbf5d5ba32cae380b7f181cf306f9e">CPSR_Type</a>
, <a class="el" href="unionISR__Type.html#ae691a856f7de0f301c60521a7a779dc2">ISR_Type</a>
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: <a class="el" href="unionSCTLR__Type.html#afe77b6c5d73e64d4ef3c5dc5ce2692dc">SCTLR_Type</a>
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: <a class="el" href="unionDFSR__Type.html#af29edf59ecfd29848b69e2bbfb7f3082">DFSR_Type</a>
, <a class="el" href="unionIFSR__Type.html#a9f9ae1ffa89d33e90159eec5c4b7cd6a">IFSR_Type</a>
</li>
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: <a class="el" href="unionDFSR__Type.html#a869658f432d5e213b8cd55e8e58d1f56">DFSR_Type</a>
, <a class="el" href="unionIFSR__Type.html#adb493acf17881eaf09a2e8629ee2243e">IFSR_Type</a>
</li>
<li>FW
: <a class="el" href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">ACTLR_Type</a>
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<h3><a class="anchor" id="index_g"></a>- g -</h3><ul>
<li>g_t
: <a class="el" href="structmmu__region__attributes__Type.html#a51f1a2a77db791b2bdf012f86605adfc">mmu_region_attributes_Type</a>
</li>
<li>GE
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<li><a href="functions_t.html#index_t"><span>t</span></a></li>
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<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div>
<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
<li>HA
: <a class="el" href="unionSCTLR__Type.html#aba2a8aac3478cdc34428af7b9726d97f">SCTLR_Type</a>
</li>
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: <a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">GICInterface_Type</a>
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 <span id="projectnumber">Version 1.1.4</span>
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<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div>
<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
<li>I
: <a class="el" href="unionCPSR__Type.html#a0d277e8b4d2147137407f526aa9e3214">CPSR_Type</a>
, <a class="el" href="unionISR__Type.html#ad83ba976f1764c7d3a7954c073c39c22">ISR_Type</a>
, <a class="el" href="unionSCTLR__Type.html#a0a4ed1a41f25a191cf4a500401c3c5db">SCTLR_Type</a>
</li>
<li>IAR
: <a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">GICInterface_Type</a>
</li>
<li>ICACTIVER
: <a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">GICDistributor_Type</a>
</li>
<li>ICENABLER
: <a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">GICDistributor_Type</a>
</li>
<li>ICFGR
: <a class="el" href="structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5">GICDistributor_Type</a>
</li>
<li>ICPENDR
: <a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">GICDistributor_Type</a>
</li>
<li>IGROUPR
: <a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">GICDistributor_Type</a>
</li>
<li>IGRPMODR
: <a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor_Type</a>
</li>
<li>IIDR
: <a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">GICDistributor_Type</a>
, <a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">GICInterface_Type</a>
</li>
<li>IMASK
: <a class="el" href="unionCNTP__CTL__Type.html#a07e23afbd292bcb84f15ea27ae2c157d">CNTP_CTL_Type</a>
</li>
<li>inner_norm_t
: <a class="el" href="structmmu__region__attributes__Type.html#a2088aadb7aa8e9b0d91d2dbad564bf33">mmu_region_attributes_Type</a>
</li>
<li>INST_LOCK_0_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a50ed69958acada08cce2c93b609097ad">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_1_WAY
: <a class="el" href="structL2C__310__TypeDef.html#acba26dcc19591924d2ad088a0b8302fa">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_2_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a98c744b09e490fa49beb452ddbc29ffd">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_3_WAY
: <a class="el" href="structL2C__310__TypeDef.html#aca5cecc05dae56be40cb1b0852b78490">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_4_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a0a54ef3839f09715962f7cc04879d6b8">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_5_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a9464799ec7797bacade9eacd4703bad2">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_6_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a990118c9674df74beb6879b3f6dbcbc6">L2C_310_TypeDef</a>
</li>
<li>INST_LOCK_7_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a6240652959732fbb74bbee91d4b487d0">L2C_310_TypeDef</a>
</li>
<li>INTERRUPT_CLEAR
: <a class="el" href="structL2C__310__TypeDef.html#a43116dfea74e77e870fd790189a403ec">L2C_310_TypeDef</a>
</li>
<li>INTERRUPT_MASK
: <a class="el" href="structL2C__310__TypeDef.html#a7c8ff2c17c6f3eb0d951e4cd193fd8e4">L2C_310_TypeDef</a>
</li>
<li>INV_LINE_PA
: <a class="el" href="structL2C__310__TypeDef.html#a1e7c5255e61ce785f2fd5c767178c098">L2C_310_TypeDef</a>
</li>
<li>INV_WAY
: <a class="el" href="structL2C__310__TypeDef.html#a78853d391272ff835025e8382c3c88d2">L2C_310_TypeDef</a>
</li>
<li>IPRIORITYR
: <a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">GICDistributor_Type</a>
</li>
<li>IROUTER
: <a class="el" href="structGICDistributor__Type.html#a73e0c679e5f45710deea474ab0d39cdb">GICDistributor_Type</a>
</li>
<li>ISACTIVER
: <a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">GICDistributor_Type</a>
</li>
<li>ISENABLER
: <a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">GICDistributor_Type</a>
</li>
<li>ISPENDR
: <a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">GICDistributor_Type</a>
</li>
<li>ISR
: <a class="el" href="structTimer__Type.html#ace17db6ca92940b030ad2ccbc674877e">Timer_Type</a>
</li>
<li>ISTATUS
: <a class="el" href="unionCNTP__CTL__Type.html#acb2f8900c7f6960443df47c1f2f2add3">CNTP_CTL_Type</a>
</li>
<li>IT0
: <a class="el" href="unionCPSR__Type.html#a5299532c92c92babc22517a433686b95">CPSR_Type</a>
</li>
<li>IT1
: <a class="el" href="unionCPSR__Type.html#a8bdd87822e3c00b3742c94a42b0654b9">CPSR_Type</a>
</li>
<li>ITARGETSR
: <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">GICDistributor_Type</a>
</li>
</ul>
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