code stringlengths 1 1.05M | repo_name stringlengths 6 83 | path stringlengths 3 242 | language stringclasses 222
values | license stringclasses 20
values | size int64 1 1.05M |
|---|---|---|---|---|---|
/**************************************************************************//**
* @file core_armv81mml.h
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
* @version V1.4.0
* @date 15. April 2020
******************************************************************************/
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_ARMV81MML_H_GENERIC
#define __CORE_ARMV81MML_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_ARMV81MML
@{
*/
#include "cmsis_version.h"
/* CMSIS ARMV81MML definitions */
#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
__ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (81U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#error Legacy Arm Compiler does not support Armv8.1-M target architecture.
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV81MML_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_ARMV81MML_H_DEPENDANT
#define __CORE_ARMV81MML_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __ARMv81MML_REV
#define __ARMv81MML_REV 0x0000U
#warning "__ARMv81MML_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#if __FPU_PRESENT != 0U
#ifndef __FPU_DP
#define __FPU_DP 0U
#warning "__FPU_DP not defined in device header file; using default!"
#endif
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 0U
#warning "__ICACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __PMU_PRESENT
#define __PMU_PRESENT 0U
#warning "__PMU_PRESENT not defined in device header file; using default!"
#endif
#if __PMU_PRESENT != 0U
#ifndef __PMU_NUM_EVENTCNT
#define __PMU_NUM_EVENTCNT 2U
#warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
#elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2)
#error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
#endif
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DSP_PRESENT
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group ARMv81MML */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED6[580U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/* SCB Non-Secure Access Control Register Definitions */
#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
/* SCB Debug Feature Register 0 Definitions */
#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
/* SCB RAS Fault Status Register Definitions */
#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
uint32_t RESERVED6[3U];
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Stimulus Port Register Definitions */
#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
uint32_t RESERVED32[934U];
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
uint32_t RESERVED33[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[809U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
uint32_t RESERVED4[4U];
__IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
/* TPI Periodic Synchronization Control Register Definitions */
#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
/* TPI Software Lock Status Register Definitions */
#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
\brief Type definitions for the Performance Monitoring Unit (PMU)
@{
*/
/**
\brief Structure type to access the Performance Monitoring Unit (PMU).
*/
typedef struct
{
__IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
#if __PMU_NUM_EVENTCNT<31
uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
#endif
__IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
uint32_t RESERVED1[224];
__IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
#if __PMU_NUM_EVENTCNT<31
uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
#endif
__IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
uint32_t RESERVED3[480];
__IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
uint32_t RESERVED4[7];
__IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
uint32_t RESERVED5[7];
__IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
uint32_t RESERVED6[7];
__IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
uint32_t RESERVED7[7];
__IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
uint32_t RESERVED8[7];
__IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
uint32_t RESERVED9[7];
__IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
uint32_t RESERVED10[79];
__IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
uint32_t RESERVED12[4];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
__IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
uint32_t RESERVED14[3];
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
__IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
} PMU_Type;
/** \brief PMU Event Counter Registers (0-30) Definitions */
#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
/** \brief PMU Count Enable Set Register Definitions */
#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
/** \brief PMU Count Enable Clear Register Definitions */
#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
/** \brief PMU Interrupt Enable Set Register Definitions */
#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
/** \brief PMU Interrupt Enable Clear Register Definitions */
#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
/** \brief PMU Overflow Flag Status Set Register Definitions */
#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
/** \brief PMU Overflow Flag Status Clear Register Definitions */
#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
/** \brief PMU Software Increment Counter */
#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
/** \brief PMU Control Register Definitions */
#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
/** \brief PMU Type Register Definitions */
#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
/** \brief PMU Authentication Status Register Definitions */
#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
/*@} end of group CMSIS_PMU */
#endif
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
__IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
__IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
__IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
uint32_t RESERVED0[1];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#else
uint32_t RESERVED0[3];
#endif
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/* Secure Fault Status Register Definitions */
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
/* Media and VFP Feature Register 0 Definitions */
#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
/* Media and VFP Feature Register 1 Definitions */
#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
/* Media and VFP Feature Register 2 Definitions */
#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
/*@} end of group CMSIS_FPU */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
__OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Set Clear Exception and Monitor Control Register Definitions */
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
__OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
#define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
#define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Priority Grouping (non-secure)
\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB_NS->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB_NS->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping (non-secure)
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
{
return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## PMU functions and events #################################### */
#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
#include "pmu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
{
return 2U; /* Double + Single precision FPU */
}
else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## MVE functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_MveFunctions MVE Functions
\brief Function that provides MVE type.
@{
*/
/**
\brief get MVE type
\details returns the MVE type
\returns
- \b 0: No Vector Extension (MVE)
- \b 1: Integer Vector Extension (MVE-I)
- \b 2: Floating-point Vector Extension (MVE-F)
*/
__STATIC_INLINE uint32_t SCB_GetMVEType(void)
{
const uint32_t mvfr1 = FPU->MVFR1;
if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
{
return 2U;
}
else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
{
return 1U;
}
else
{
return 0U;
}
}
/*@} end of CMSIS_Core_MveFunctions */
/* ########################## Cache functions #################################### */
#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
(defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
#include "cachel1_armv7.h"
#endif
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV81MML_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_armv81mml.h | C | apache-2.0 | 276,180 |
/**************************************************************************//**
* @file core_armv8mbl.h
* @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
* @version V5.1.0
* @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_ARMV8MBL_H_GENERIC
#define __CORE_ARMV8MBL_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_ARMv8MBL
@{
*/
#include "cmsis_version.h"
/* CMSIS definitions */
#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
__ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (2U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV8MBL_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_ARMV8MBL_H_DEPENDANT
#define __CORE_ARMV8MBL_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __ARMv8MBL_REV
#define __ARMv8MBL_REV 0x0000U
#warning "__ARMv8MBL_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __ETM_PRESENT
#define __ETM_PRESENT 0U
#warning "__ETM_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MTB_PRESENT
#define __MTB_PRESENT 0U
#warning "__MTB_PRESENT not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group ARMv8MBL */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
uint32_t RESERVED0[6U];
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[809U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
uint32_t RESERVED4[4U];
__IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI Periodic Synchronization Control Register Definitions */
#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
/* TPI Software Lock Status Register Definitions */
#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
uint32_t RESERVED0[7U];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 1U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#endif
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
If VTOR is not present address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_armv8mbl.h | C | apache-2.0 | 115,004 |
/**************************************************************************//**
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
* @version V5.2.1
* @date 19. August 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_ARMV8MML_H_GENERIC
#define __CORE_ARMV8MML_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_ARMv8MML
@{
*/
#include "cmsis_version.h"
/* CMSIS Armv8MML definitions */
#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
__ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (80U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV8MML_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_ARMV8MML_H_DEPENDANT
#define __CORE_ARMV8MML_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __ARMv8MML_REV
#define __ARMv8MML_REV 0x0000U
#warning "__ARMv8MML_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DSP_PRESENT
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group ARMv8MML */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED6[580U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/* SCB Non-Secure Access Control Register Definitions */
#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
uint32_t RESERVED6[4U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Stimulus Port Register Definitions */
#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
uint32_t RESERVED32[934U];
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
uint32_t RESERVED33[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[809U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
uint32_t RESERVED4[4U];
__IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI Periodic Synchronization Control Register Definitions */
#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
/* TPI Software Lock Status Register Definitions */
#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
__IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
__IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
__IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
uint32_t RESERVED0[1];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#else
uint32_t RESERVED0[3];
#endif
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/* Secure Fault Status Register Definitions */
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
/* Media and VFP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and VFP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/* Media and VFP Feature Register 2 Definitions */
#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
/*@} end of group CMSIS_FPU */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Priority Grouping (non-secure)
\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB_NS->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB_NS->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping (non-secure)
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
{
return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
{
return 2U; /* Double + Single precision FPU */
}
else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## Cache functions #################################### */
#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
(defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
#include "cachel1_armv7.h"
#endif
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_ARMV8MML_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_armv8mml.h | C | apache-2.0 | 182,696 |
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.8
* @date 21. August 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm0.h | C | apache-2.0 | 41,643 |
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V5.0.9
* @date 21. August 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
#define MPU_TYPE_RALIASES 1U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
If VTOR is not present address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
#else
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
#endif
/* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
#else
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
#endif
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm0plus.h | C | apache-2.0 | 49,877 |
/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm1.h | C | apache-2.0 | 42,626 |
/**************************************************************************//**
* @file core_cm23.h
* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
* @version V5.1.0
* @date 11. February 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_CM23_H_GENERIC
#define __CORE_CM23_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M23
@{
*/
#include "cmsis_version.h"
/* CMSIS definitions */
#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
__CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (23U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM23_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM23_H_DEPENDANT
#define __CORE_CM23_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM23_REV
#define __CM23_REV 0x0000U
#warning "__CM23_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __ETM_PRESENT
#define __ETM_PRESENT 0U
#warning "__ETM_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MTB_PRESENT
#define __MTB_PRESENT 0U
#warning "__MTB_PRESENT not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M23 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
uint32_t RESERVED0[6U];
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
__IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
__IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration Test FIFO Test Data 0 Register Definitions */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
/* TPI Integration Test ATB Control Register 2 Register Definitions */
#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
/* TPI Integration Test FIFO Test Data 1 Register Definitions */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
/* TPI Integration Test ATB Control Register 0 Definitions */
#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
uint32_t RESERVED0[7U];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 1U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#endif
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
If VTOR is not present address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM23_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm23.h | C | apache-2.0 | 121,556 |
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V5.1.1
* @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M3
@{
*/
#include "cmsis_version.h"
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
__CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (3U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV
#define __CM3_REV 0x0200U
#warning "__CM3_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#else
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
#else
uint32_t RESERVED1[1U];
#endif
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
#endif
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M3 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM3_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm3.h | C | apache-2.0 | 109,532 |
/**************************************************************************//**
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
* @version V5.2.1
* @date 19. August 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_CM33_H_GENERIC
#define __CORE_CM33_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M33
@{
*/
#include "cmsis_version.h"
/* CMSIS CM33 definitions */
#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
__CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (33U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined (__ARM_FP)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined (__ARMVFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined (__TI_VFP_SUPPORT__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined (__FPU_VFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM33_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM33_H_DEPENDANT
#define __CORE_CM33_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM33_REV
#define __CM33_REV 0x0000U
#warning "__CM33_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DSP_PRESENT
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M33 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED6[580U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/* SCB Non-Secure Access Control Register Definitions */
#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
uint32_t RESERVED6[4U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Stimulus Port Register Definitions */
#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
uint32_t RESERVED32[934U];
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
uint32_t RESERVED33[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
__IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
__IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration Test FIFO Test Data 0 Register Definitions */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
/* TPI Integration Test ATB Control Register 2 Register Definitions */
#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
/* TPI Integration Test FIFO Test Data 1 Register Definitions */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
/* TPI Integration Test ATB Control Register 0 Definitions */
#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
__IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
__IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
__IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
uint32_t RESERVED0[1];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#else
uint32_t RESERVED0[3];
#endif
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/* Secure Fault Status Register Definitions */
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
/* Media and VFP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and VFP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/* Media and VFP Feature Register 2 Definitions */
#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
/*@} end of group CMSIS_FPU */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Priority Grouping (non-secure)
\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB_NS->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB_NS->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping (non-secure)
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
{
return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
{
return 2U; /* Double + Single precision FPU */
}
else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM33_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm33.h | C | apache-2.0 | 189,029 |
/**************************************************************************//**
* @file core_cm35p.h
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
* @version V1.1.1
* @date 19. August 2020
******************************************************************************/
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_CM35P_H_GENERIC
#define __CORE_CM35P_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M35P
@{
*/
#include "cmsis_version.h"
/* CMSIS CM35P definitions */
#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
__CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (35U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined (__ARM_FP)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined (__ARMVFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined (__TI_VFP_SUPPORT__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined (__FPU_VFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM35P_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM35P_H_DEPENDANT
#define __CORE_CM35P_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM35P_REV
#define __CM35P_REV 0x0000U
#warning "__CM35P_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DSP_PRESENT
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M35P */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED6[580U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/* SCB Non-Secure Access Control Register Definitions */
#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
uint32_t RESERVED6[4U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Stimulus Port Register Definitions */
#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
uint32_t RESERVED32[934U];
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
uint32_t RESERVED33[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
__IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
__IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration Test FIFO Test Data 0 Register Definitions */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
/* TPI Integration Test ATB Control Register 2 Register Definitions */
#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
/* TPI Integration Test FIFO Test Data 1 Register Definitions */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
/* TPI Integration Test ATB Control Register 0 Definitions */
#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
__IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
__IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
__IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
uint32_t RESERVED0[1];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#else
uint32_t RESERVED0[3];
#endif
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/* Secure Fault Status Register Definitions */
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
/* Media and VFP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and VFP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/* Media and VFP Feature Register 2 Definitions */
#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
/*@} end of group CMSIS_FPU */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Priority Grouping (non-secure)
\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB_NS->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB_NS->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping (non-secure)
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
{
return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
{
return 2U; /* Double + Single precision FPU */
}
else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM35P_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm35p.h | C | apache-2.0 | 189,046 |
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V5.1.1
* @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM4_H_GENERIC
#define __CORE_CM4_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M4
@{
*/
#include "cmsis_version.h"
/* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
__CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (4U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM4_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM4_H_DEPENDANT
#define __CORE_CM4_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM4_REV
#define __CM4_REV 0x0000U
#warning "__CM4_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M4 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
/* Media and FP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and FP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/* Media and FP Feature Register 2 Definitions */
#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
/*@} end of group CMSIS_FPU */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M4 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM4_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm4.h | C | apache-2.0 | 120,978 |
/**************************************************************************//**
* @file core_cm55.h
* @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
* @version V1.1.0
* @date 15. April 2020
******************************************************************************/
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_CM55_H_GENERIC
#define __CORE_CM55_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_CM55
@{
*/
#include "cmsis_version.h"
/* CMSIS CM55 definitions */
#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \
__CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (55U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#error Legacy Arm Compiler does not support Armv8.1-M target architecture.
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#if defined(__ARM_FEATURE_DSP)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
#define __DSP_USED 1U
#else
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
#define __DSP_USED 0U
#endif
#else
#define __DSP_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM55_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM55_H_DEPENDANT
#define __CORE_CM55_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM55_REV
#define __CM55_REV 0x0000U
#warning "__CM55_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#if __FPU_PRESENT != 0U
#ifndef __FPU_DP
#define __FPU_DP 0U
#warning "__FPU_DP not defined in device header file; using default!"
#endif
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 0U
#warning "__ICACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __PMU_PRESENT
#define __PMU_PRESENT 0U
#warning "__PMU_PRESENT not defined in device header file; using default!"
#endif
#if __PMU_PRESENT != 0U
#ifndef __PMU_NUM_EVENTCNT
#define __PMU_NUM_EVENTCNT 8U
#warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
#elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)
#error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
#endif
#endif
#ifndef __SAUREGION_PRESENT
#define __SAUREGION_PRESENT 0U
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DSP_PRESENT
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M55 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core SAU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[16U];
__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[16U];
__IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[16U];
__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[16U];
__IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[16U];
__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
uint32_t RESERVED5[16U];
__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED6[580U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/* SCB Non-Secure Access Control Register Definitions */
#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
/* SCB Debug Feature Register 0 Definitions */
#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
/* SCB RAS Fault Status Register Definitions */
#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
uint32_t RESERVED6[3U];
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Stimulus Port Register Definitions */
#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
uint32_t RESERVED1[1U];
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
uint32_t RESERVED3[1U];
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED4[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
uint32_t RESERVED5[1U];
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED6[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
uint32_t RESERVED7[1U];
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED8[1U];
__IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
uint32_t RESERVED9[1U];
__IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
uint32_t RESERVED10[1U];
__IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
uint32_t RESERVED11[1U];
__IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
uint32_t RESERVED12[1U];
__IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
uint32_t RESERVED13[1U];
__IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
uint32_t RESERVED14[1U];
__IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
uint32_t RESERVED15[1U];
__IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
uint32_t RESERVED16[1U];
__IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
uint32_t RESERVED17[1U];
__IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
uint32_t RESERVED18[1U];
__IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
uint32_t RESERVED19[1U];
__IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
uint32_t RESERVED20[1U];
__IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
uint32_t RESERVED21[1U];
__IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
uint32_t RESERVED22[1U];
__IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
uint32_t RESERVED23[1U];
__IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
uint32_t RESERVED24[1U];
__IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
uint32_t RESERVED25[1U];
__IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
uint32_t RESERVED26[1U];
__IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
uint32_t RESERVED27[1U];
__IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
uint32_t RESERVED28[1U];
__IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
uint32_t RESERVED29[1U];
__IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
uint32_t RESERVED30[1U];
__IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
uint32_t RESERVED31[1U];
__IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
uint32_t RESERVED32[934U];
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
uint32_t RESERVED33[1U];
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
uint32_t RESERVED3[809U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
uint32_t RESERVED4[4U];
__IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
/* TPI Periodic Synchronization Control Register Definitions */
#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
/* TPI Software Lock Status Register Definitions */
#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
\brief Type definitions for the Performance Monitoring Unit (PMU)
@{
*/
/**
\brief Structure type to access the Performance Monitoring Unit (PMU).
*/
typedef struct
{
__IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
#if __PMU_NUM_EVENTCNT<31
uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
#endif
__IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
uint32_t RESERVED1[224];
__IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
#if __PMU_NUM_EVENTCNT<31
uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
#endif
__IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
uint32_t RESERVED3[480];
__IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
uint32_t RESERVED4[7];
__IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
uint32_t RESERVED5[7];
__IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
uint32_t RESERVED6[7];
__IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
uint32_t RESERVED7[7];
__IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
uint32_t RESERVED8[7];
__IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
uint32_t RESERVED9[7];
__IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
uint32_t RESERVED10[79];
__IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
uint32_t RESERVED12[4];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
__IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
uint32_t RESERVED14[3];
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
__IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
} PMU_Type;
/** \brief PMU Event Counter Registers (0-30) Definitions */
#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
/** \brief PMU Count Enable Set Register Definitions */
#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
/** \brief PMU Count Enable Clear Register Definitions */
#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
/** \brief PMU Interrupt Enable Set Register Definitions */
#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
/** \brief PMU Interrupt Enable Clear Register Definitions */
#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
/** \brief PMU Overflow Flag Status Set Register Definitions */
#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
/** \brief PMU Overflow Flag Status Clear Register Definitions */
#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
/** \brief PMU Software Increment Counter */
#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
/** \brief PMU Control Register Definitions */
#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
/** \brief PMU Type Register Definitions */
#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
/** \brief PMU Authentication Status Register Definitions */
#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
/*@} end of group CMSIS_PMU */
#endif
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
__IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
__IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
__IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
uint32_t RESERVED0[1];
union {
__IOM uint32_t MAIR[2];
struct {
__IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
__IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
};
};
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
/* MPU Region Limit Address Register Definitions */
#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
/* MPU Memory Attribute Indirection Register 0 Definitions */
#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
/* MPU Memory Attribute Indirection Register 1 Definitions */
#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
/*@} end of group CMSIS_MPU */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SAU Security Attribution Unit (SAU)
\brief Type definitions for the Security Attribution Unit (SAU)
@{
*/
/**
\brief Structure type to access the Security Attribution Unit (SAU).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
#else
uint32_t RESERVED0[3];
#endif
__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
} SAU_Type;
/* SAU Control Register Definitions */
#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
/* SAU Type Register Definitions */
#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
/* SAU Region Number Register Definitions */
#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
/* SAU Region Base Address Register Definitions */
#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
/* SAU Region Limit Address Register Definitions */
#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
/* Secure Fault Status Register Definitions */
#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
/*@} end of group CMSIS_SAU */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
/* Media and VFP Feature Register 0 Definitions */
#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
/* Media and VFP Feature Register 1 Definitions */
#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
/* Media and VFP Feature Register 2 Definitions */
#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
/*@} end of group CMSIS_FPU */
/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
__OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
/* Debug Set Clear Exception and Monitor Control Register Definitions */
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
/* Debug Authentication Control Register Definitions */
#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
/* Debug Security Control and Status Register Definitions */
#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DCB Debug Control Block
\brief Type definitions for the Debug Control Block Registers
@{
*/
/**
\brief Structure type to access the Debug Control Block Registers (DCB).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
__OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
} DCB_Type;
/* DHCSR, Debug Halting Control and Status Register Definitions */
#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
/* DCRSR, Debug Core Register Select Register Definitions */
#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
/* DCRDR, Debug Core Register Data Register Definitions */
#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
/* DEMCR, Debug Exception and Monitor Control Register Definitions */
#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
/* DAUTHCTRL, Debug Authentication Control Register Definitions */
#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
/* DSCSR, Debug Security Control and Status Register Definitions */
#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
/*@} end of group CMSIS_DCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DIB Debug Identification Block
\brief Type definitions for the Debug Identification Block Registers
@{
*/
/**
\brief Structure type to access the Debug Identification Block Registers (DIB).
*/
typedef struct
{
__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
__IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
__IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
__IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
} DIB_Type;
/* DLAR, SCS Software Lock Access Register Definitions */
#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
/* DLSR, SCS Software Lock Status Register Definitions */
#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
/* DDEVARCH, SCS Device Architecture Register Definitions */
#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
/* DDEVTYPE, SCS Device Type Register Definitions */
#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
/*@} end of group CMSIS_DIB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
#define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
#define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
#define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
#define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
#define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
#define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
#define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
#define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
#define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
#endif
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Special LR values for Secure/Non-Secure call handling and exception handling */
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#else
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
#endif
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Interrupt Target State
\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
\return 1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Target State
\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Clear Interrupt Target State
\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 if interrupt is assigned to Secure
1 if interrupt is assigned to Non Secure
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Priority Grouping (non-secure)
\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB_NS->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB_NS->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping (non-secure)
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
{
return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt (non-secure)
\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status (non-secure)
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt (non-secure)
\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Pending Interrupt (non-secure)
\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt (non-secure)
\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt (non-secure)
\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt (non-secure)
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority (non-secure)
\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every non-secure processor exception.
*/
__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority (non-secure)
\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv8.h"
#endif
/* ########################## PMU functions and events #################################### */
#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
#include "pmu_armv8.h"
/**
\brief Cortex-M55 PMU events
\note Architectural PMU events can be found in pmu_armv8.h
*/
#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */
#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */
#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */
#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */
#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */
#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/
#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */
#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */
#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */
#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */
#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */
#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */
#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */
#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
{
return 2U; /* Double + Single precision FPU */
}
else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## MVE functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_MveFunctions MVE Functions
\brief Function that provides MVE type.
@{
*/
/**
\brief get MVE type
\details returns the MVE type
\returns
- \b 0: No Vector Extension (MVE)
- \b 1: Integer Vector Extension (MVE-I)
- \b 2: Floating-point Vector Extension (MVE-F)
*/
__STATIC_INLINE uint32_t SCB_GetMVEType(void)
{
const uint32_t mvfr1 = FPU->MVFR1;
if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
{
return 2U;
}
else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
{
return 1U;
}
else
{
return 0U;
}
}
/*@} end of CMSIS_Core_MveFunctions */
/* ########################## Cache functions #################################### */
#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
(defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
#include "cachel1_armv7.h"
#endif
/* ########################## SAU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SAUFunctions SAU Functions
\brief Functions that configure the SAU.
@{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Enable SAU
\details Enables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Enable(void)
{
SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
}
/**
\brief Disable SAU
\details Disables the Security Attribution Unit (SAU).
*/
__STATIC_INLINE void TZ_SAU_Disable(void)
{
SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_SAUFunctions */
/* ################################## Debug Control function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DCBFunctions Debug Control Functions
\brief Functions that access the Debug Control Block.
@{
*/
/**
\brief Set Debug Authentication Control Register
\details writes to Debug Authentication Control register.
\param [in] value value to be writen.
*/
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
{
__DSB();
__ISB();
DCB->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register
\details Reads Debug Authentication Control register.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
{
return (DCB->DAUTHCTRL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Set Debug Authentication Control Register (non-secure)
\details writes to non-secure Debug Authentication Control register when in secure state.
\param [in] value value to be writen
*/
__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
{
__DSB();
__ISB();
DCB_NS->DAUTHCTRL = value;
__DSB();
__ISB();
}
/**
\brief Get Debug Authentication Control Register (non-secure)
\details Reads non-secure Debug Authentication Control register when in secure state.
\return Debug Authentication Control Register.
*/
__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
{
return (DCB_NS->DAUTHCTRL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## Debug Identification function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
\brief Functions that access the Debug Identification Block.
@{
*/
/**
\brief Get Debug Authentication Status Register
\details Reads Debug Authentication Status register.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
{
return (DIB->DAUTHSTATUS);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief Get Debug Authentication Status Register (non-secure)
\details Reads non-secure Debug Authentication Status register when in secure state.
\return Debug Authentication Status Register.
*/
__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
{
return (DIB_NS->DAUTHSTATUS);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*@} end of CMSIS_Core_DCBFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
\brief System Tick Configuration (non-secure)
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM55_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm55.h | C | apache-2.0 | 278,432 |
/**************************************************************************//**
* @file core_cm7.h
* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
* @version V5.1.4
* @date 19. August 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM7_H_GENERIC
#define __CORE_CM7_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M7
@{
*/
#include "cmsis_version.h"
/* CMSIS CM7 definitions */
#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
__CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (7U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM7_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM7_H_DEPENDANT
#define __CORE_CM7_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM7_REV
#define __CM7_REV 0x0000U
#warning "__CM7_REV not defined in device header file; using default!"
#endif
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 0U
#warning "__ICACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DTCM_PRESENT
#define __DTCM_PRESENT 0U
#warning "__DTCM_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M7 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
- Core FPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
#define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[1U];
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
uint32_t RESERVED3[93U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
uint32_t RESERVED7[5U];
__IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
__IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
__IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
__IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
__IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
uint32_t RESERVED8[1U];
__IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/* Instruction Tightly-Coupled Memory Control Register Definitions */
#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
/* Data Tightly-Coupled Memory Control Register Definitions */
#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
/* AHBP Control Register Definitions */
#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
/* L1 Cache Control Register Definitions */
#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
/* AHBS Control Register Definitions */
#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
/* Auxiliary Bus Fault Status Register Definitions */
#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
uint32_t RESERVED3[981U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU)
\brief Type definitions for the Floating Point Unit (FPU)
@{
*/
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
__IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
__IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
/* Media and FP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and FP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/* Media and FP Feature Register 2 Definitions */
#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
/*@} end of group CMSIS_FPU */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
__DSB();
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = SCB->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
{
return 2U; /* Double + Single precision FPU */
}
else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ########################## Cache functions #################################### */
#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
(defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
#include "cachel1_armv7.h"
#endif
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM7_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_cm7.h | C | apache-2.0 | 138,683 |
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V5.0.7
* @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC000
@{
*/
#include "cmsis_version.h"
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the SC000 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_sc000.h | C | apache-2.0 | 46,562 |
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
* @version V5.0.9
* @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC300_H_GENERIC
#define __CORE_SC300_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC3000
@{
*/
#include "cmsis_version.h"
/* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
__SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (300U) /*!< Cortex secure core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC300_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC300_H_DEPENDANT
#define __CORE_SC300_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC300_REV
#define __SC300_REV 0x0000U
#warning "__SC300_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 1U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC300 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
uint32_t RESERVED1[129U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15U];
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\brief Type definitions for the Data Watchpoint and Trace (DWT)
@{
*/
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
__IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
__IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
uint32_t RESERVED0[1U];
__IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
__IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
__IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
uint32_t RESERVED1[1U];
__IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
__IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
__IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
uint32_t RESERVED2[1U];
__IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
__IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
__IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
} DWT_Type;
/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
\brief Type definitions for the Trace Port Interface (TPI)
@{
*/
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
__IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Type definitions for the Core Debug Registers
@{
*/
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M3 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions ITM Functions
\brief Functions that access the ITM debug interface.
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
}
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
return (0); /* no character available */
}
else
{
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC300_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/core_sc300.h | C | apache-2.0 | 108,524 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file csi_core_cmsis.h
* @brief Header File for csi_core
* @version V1.0
* @date 12. June 2020
******************************************************************************/
#ifndef _CSI_CORE_CMSIS_H_
#define _CSI_CORE_CMSIS_H_
#include <stddef.h>
#include <cmsis_gcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Processor Interrupt Numbers ------------------------------ */
Interrupt0_IRQn = 0,
Interrupt1_IRQn = 1,
Interrupt2_IRQn = 2,
Interrupt3_IRQn = 3,
Interrupt4_IRQn = 4,
Interrupt5_IRQn = 5,
Interrupt6_IRQn = 6,
Interrupt7_IRQn = 7,
Interrupt8_IRQn = 8,
Interrupt9_IRQn = 9
/* Interrupts 10 .. 31 are left out */
} IRQn_Type;
#if defined(__CPU_CORTEXM0__)
#define __CM0_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 0U /* no MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include <../../CMSIS/Core/Include/core_cm0.h>
#elif defined(__CPU_CORTEXM0PLUS__)
#define __CM0PLUS_REV 0x0001U /* Core revision r0p1 */
#define __MPU_PRESENT 0U /* no MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include <core_cm0plus.h>
#elif defined(__CPU_CORTEXM1__)
#define __CM1_REV 0x0100U /* Core revision r1p0 */
#define __MPU_PRESENT 0U /* no MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include <core_cm1.h>
#elif defined(__CPU_CORTEXM23__)
#define __CM23_REV 0x0100U /* Core revision r1p0 */
#define __SAUREGION_PRESENT 0U /* SAU regions are not present */
#define __MPU_PRESENT 1U /* MPU is present */
#define __VTOR_PRESENT 1U /* VTOR is present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include <core_cm23.h>
#elif defined(__CPU_CORTEXM33__)
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#define __DSP_PRESENT 0U /* no DSP extension present */
#include <core_cm33.h>
#elif defined(__CPU_CORTEXM35P__)
#define __CM35P_REV 0x0000U /* Core revision r0p0 */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#define __DSP_PRESENT 0U /* no DSP extension present */
#include <core_cm35p.h>
#elif defined(__CPU_CORTEXM3__)
#define __CM3_REV 0x0201U /* Core revision r2p1 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include <core_cm3.h>
#elif defined(__CPU_CORTEXM4__)
#define __CM4_REV 0x0001U /* Core revision r0p1 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#include <core_cm4.h>
#elif defined(__CPU_CORTEXM55__)
#define __CM55_REV 0x0001U /* Core revision r0p1 */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __MPU_PRESENT 1U /* MPU present */
#define __FPU_PRESENT 1U /* FPU present */
#define __FPU_DP 1U /* double precision FPU */
#define __DSP_PRESENT 1U /* DSP extension present */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __PMU_PRESENT 1U /* PMU present */
#define __PMU_NUM_EVENTCNT 8U /* PMU Event Counters */
#define __ICACHE_PRESENT 1U /* Instruction Cache present */
#define __DCACHE_PRESENT 1U /* Data Cache present */
#include <core_cm55.h>
#elif defined(__CPU_CORTEXM7__)
#define __CM7_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#define __FPU_DP 0U /* unused */
#define __ICACHE_PRESENT 1U /* Instruction Cache present */
#define __DCACHE_PRESENT 1U /* Data Cache present */
#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
#include <core_cm7.h>
#endif
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
return SysTick_Config(ticks);
}
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return SysTick->LOAD;
}
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return SysTick->VAL;
}
__STATIC_INLINE void csi_coret_clear_irq(void)
{
}
#ifdef __GNUC__
#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline
__STATIC_INLINE size_t csi_irq_save(void)
{
uint32_t result;
result = __get_PRIMASK();
__disable_irq();
return (result);
}
__STATIC_INLINE void csi_irq_restore(size_t irq_state)
{
__set_PRIMASK(irq_state);
}
#else
static inline __asm size_t csi_irq_save(void)
{
MRS R0, PRIMASK
CPSID I
BX LR
return 0;
}
static inline __asm void csi_irq_restore(size_t irq_state)
{
MSR PRIMASK, R0
BX LR
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CSI_CORE_H_ */
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/csi_core_cmsis.h | C | apache-2.0 | 8,382 |
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.2
* @date 25. May 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/mpu_armv7.h | C | apache-2.0 | 11,722 |
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.2
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/mpu_armv8.h | C | apache-2.0 | 11,360 |
/******************************************************************************
* @file pmu_armv8.h
* @brief CMSIS PMU API for Armv8.1-M PMU
* @version V1.0.1
* @date 15. April 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_PMU_ARMV8_H
#define ARM_PMU_ARMV8_H
/**
* \brief PMU Events
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
* */
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
/** \brief PMU Functions */
__STATIC_INLINE void ARM_PMU_Enable(void);
__STATIC_INLINE void ARM_PMU_Disable(void);
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
/**
\brief Set event to count for PMU eventer counter
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
/**
\brief Enable counters
\param [in] mask Counters to enable
\note Enables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
PMU->CNTENSET = mask;
}
/**
\brief Disable counters
\param [in] mask Counters to enable
\note Disables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
PMU->CNTENCLR = mask;
}
/**
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
return PMU->CCNTR;
}
/**
\brief Read event counter
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
}
/**
\brief Read counter overflow status
\return Counter overflow status bits for the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
return PMU->OVSSET;
}
/**
\brief Clear counter overflow status
\param [in] mask Counter overflow status bits to clear
\note Clears overflow status bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
PMU->OVSCLR = mask;
}
/**
\brief Enable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to set
\note Sets overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
PMU->INTENSET = mask;
}
/**
\brief Disable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to clear
\note Clears overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
PMU->INTENCLR = mask;
}
/**
\brief Software increment event counter
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
PMU->SWINC = mask;
}
#endif
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/pmu_armv8.h | C | apache-2.0 | 22,786 |
/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H
| YifuLiu/AliOS-Things | components/csi/CMSIS/Core/Include/tz_context.h | C | apache-2.0 | 2,687 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_801.h
* @brief CSI 801 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_801_H_GENERIC
#define __CORE_801_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck801
@{
*/
/* CSI CK801 definitions */
#define __CK801_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK801_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK801_CSI_VERSION ((__CK801_CSI_VERSION_MAIN << 16U) | \
__CK801_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x01U) /*!< CK80X Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK801_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK801_H_DEPENDANT
#define __CORE_CK801_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK801_REV
#define __CK801_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK801 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 1.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t Size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 1; /*!< bit: 6 Reserved */
uint32_t base_addr: 25; /*!< bit: 7..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 7U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0x1FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 4; /*!< bit: 0.. 3 Reserved */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 11; /*!< bit: 5..15 Reserved */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[15U];
__IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[15U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[15U];
__IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[15U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[15U];
__IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[15U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[15U];
__IOM uint32_t ICSR[1U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[15U];
__IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[63U];
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[504U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
uint32_t RESERVED1;
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED2[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK801 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
VIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
VIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
VIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
VIC->ISSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
VIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
VIC->ICSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return Interrput status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
return ((uint32_t)(((VIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
return ((uint32_t)(((VIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
VIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
VIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
return ((uint32_t)(((VIC->IWER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wakeup Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
VIC->IWER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
VIC->IWDR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
return ((uint32_t)(((VIC->IABR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vecter threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
PrioThreshold &= 0xFFU;
VIC->IPTR = 0x80000000U | ((VectThreshold & 0xFFU) << 8U) | ((PrioThreshold << (8U - __VIC_PRIO_BITS)) & 0xFFU);
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 32) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 32) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
(void)IRQn;
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_128B = 0x6,
REGION_SIZE_256B = 0x7,
REGION_SIZE_512B = 0x8,
REGION_SIZE_1KB = 0x9,
REGION_SIZE_2KB = 0xA,
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0x3FFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_128B) {
pacr.w &= ~(((1u << (size -6)) - 1) << 7);
}
pacr.b.Size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
/*@} end of Old Interfaces */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_801_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_801.h | C | apache-2.0 | 46,789 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_802.h
* @brief CSI 802 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_802_H_GENERIC
#define __CORE_802_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck802
@{
*/
/* CSI CK802 definitions */
#define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \
__CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x02U) /*!< CK80X Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK802_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK802_H_DEPENDANT
#define __CORE_CK802_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK802_REV
#define __CK802_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK802 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 3; /*!< bit: 24..26 Reserved */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 5; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 1; /*!< bit: 6 Reserved */
uint32_t base_addr: 25; /*!< bit: 7..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 7U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0x1FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 4; /*!< bit: 0.. 3 Reserved */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
uint32_t RESERVED1;
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED2[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK802 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
#ifdef CONFIG_SYSTEM_SECURE
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
#endif
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
PrioThreshold &= 0xFFU;
VIC->IPTR = 0x80000000U | ((VectThreshold & 0xFFU) << 8U) | ((PrioThreshold << (8U - __VIC_PRIO_BITS)) & 0xFFU);
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk & (~CACHE_CER_CFIG_Msk)); /* enable all Cache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
\param [in] index cache scope index (0, 1, 2, 3).
\param [in] baseAddr base address must be aligned with size.
\param [in] size \ref CACHE Register Definitions. cache scope size.
\param [in] enable enable or disable cache scope.
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/*@} end of CSI_core_DebugFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_128B = 0x6,
REGION_SIZE_256B = 0x7,
REGION_SIZE_512B = 0x8,
REGION_SIZE_1KB = 0x9,
REGION_SIZE_2KB = 0xA,
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
if (idx > 7) {
return;
}
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0x3FFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_128B) {
pacr.w &= ~(((1u << (size -6)) - 1) << 7);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define HAD_SendChar(ch) csi_had_send_char(ch)
#define HAD_ReceiveChar() csi_had_receive_char()
#define HAD_CheckChar() csi_had_check_char()
/*@} end of Old Interfaces */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_802_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_802.h | C | apache-2.0 | 63,768 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_803.h
* @brief CSI 803 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_803_H_GENERIC
#define __CORE_803_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck803
@{
*/
/* CSI CK803 definitions */
#define __CK803_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK803_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK803_CSI_VERSION ((__CK803_CSI_VERSION_MAIN << 16U) | \
__CK803_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x03U) /*!< CK80X Core */
#endif
/* __FPU_USED indicates whether an FPU is used or not. */
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK803_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK803_H_DEPENDANT
#define __CORE_CK803_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK803_REV
#define __CK803_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK803 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
uint32_t SV: 1; /*!< bit: 25 Stacked valid */
uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_BE_Pos 1U /*!< CHR: BE Position */
#define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
#define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
#define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
#define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
#define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
#define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
uint32_t RESERVED1;
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED2[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK803 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
PrioThreshold &= 0xFFU;
VIC->IPTR = 0x80000000U | ((VectThreshold & 0xFFU) << 8U) | ((PrioThreshold << (8U - __VIC_PRIO_BITS)) & 0xFFU);
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
\param [in] index cache scope index (0, 1, 2, 3).
\param [in] baseAddr base address must be aligned with size.
\param [in] size \ref CACHE Register Definitions. cache scope size.
\param [in] enable enable or disable cache scope.
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define SCB_EnableICache() csi_icache_enable()
#define SCB_DisableICache() csi_icache_disable()
#define SCB_InvalidateICache() csi_icache_invalid()
#define SCB_EnableDCache() csi_dcache_enable()
#define SCB_DisableDCache() csi_dcache_disable()
#define SCB_InvalidateDCache() csi_dcache_invalid()
#define SCB_CleanDCache() csi_dcache_clean()
#define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
#define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
#define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
#define SCB_EnableCacheProfile() csi_cache_enable_profile()
#define SCB_DisableCacheProfile() csi_cache_disable_profile()
#define SCB_ResetCacheProfile() csi_cache_reset_profile()
#define SCB_CacheAccessTime() csi_cache_get_access_time()
#define SCB_CacheMissTime() csi_cache_get_miss_time()
#define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
#define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
#define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
#define SCB_CleanCache() csi_dcache_clean()
#define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
#define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
#define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_803_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_803.h | C | apache-2.0 | 67,514 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_804.h
* @brief CSI 804 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_804_H_GENERIC
#define __CORE_804_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck804
@{
*/
/* CSI CK804 definitions */
#define __CK804_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK804_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK804_CSI_VERSION ((__CK804_CSI_VERSION_MAIN << 16U) | \
__CK804_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x03U) /*!< CK80X Core */
#endif
/* __FPU_USED indicates whether an FPU is used or not. */
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK804_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK804_H_DEPENDANT
#define __CORE_CK804_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK804_REV
#define __CK804_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK804 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
uint32_t SV: 1; /*!< bit: 25 Stacked valid */
uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_BE_Pos 1U /*!< CHR: BE Position */
#define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
#define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
#define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
#define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
#define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
#define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
uint32_t RESERVED1;
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED2[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK804 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
PrioThreshold &= 0xFFU;
VIC->IPTR = 0x80000000U | ((VectThreshold & 0xFFU) << 8U) | ((PrioThreshold << (8U - __VIC_PRIO_BITS)) & 0xFFU);
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
\param [in] index cache scope index (0, 1, 2, 3).
\param [in] baseAddr base address must be aligned with size.
\param [in] size \ref CACHE Register Definitions. cache scope size.
\param [in] enable enable or disable cache scope.
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define SCB_EnableICache() csi_icache_enable()
#define SCB_DisableICache() csi_icache_disable()
#define SCB_InvalidateICache() csi_icache_invalid()
#define SCB_EnableDCache() csi_dcache_enable()
#define SCB_DisableDCache() csi_dcache_disable()
#define SCB_InvalidateDCache() csi_dcache_invalid()
#define SCB_CleanDCache() csi_dcache_clean()
#define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
#define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
#define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
#define SCB_EnableCacheProfile() csi_cache_enable_profile()
#define SCB_DisableCacheProfile() csi_cache_disable_profile()
#define SCB_ResetCacheProfile() csi_cache_reset_profile()
#define SCB_CacheAccessTime() csi_cache_get_access_time()
#define SCB_CacheMissTime() csi_cache_get_miss_time()
#define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
#define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
#define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
#define SCB_CleanCache() csi_dcache_clean()
#define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
#define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
#define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_804_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_804.h | C | apache-2.0 | 67,515 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_805.h
* @brief CSI 805 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_805_H_GENERIC
#define __CORE_805_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck805
@{
*/
/* CSI CK805 definitions */
#define __CK805_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK805_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK805_CSI_VERSION ((__CK805_CSI_VERSION_MAIN << 16U) | \
__CK805_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x03U) /*!< CK80X Core */
#endif
/* __FPU_USED indicates whether an FPU is used or not. */
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK805_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK805_H_DEPENDANT
#define __CORE_CK805_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK805_REV
#define __CK805_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK805 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
uint32_t SV: 1; /*!< bit: 25 Stacked valid */
uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_BE_Pos 1U /*!< CHR: BE Position */
#define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
#define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
#define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
#define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
#define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_DCEN_Pos 0U /*!< CACHE CER: DCEN Position */
#define CACHE_CER_DCEN_Msk (0x1UL << CACHE_CER_DCEN_Pos) /*!< CACHE CER: DCEN Mask */
#define CACHE_CER_ICEN_Pos 1U /*!< CACHE CER: ICEN Position */
#define CACHE_CER_ICEN_Msk (0x1UL << CACHE_CER_ICEN_Pos) /*!< CACHE CER: ICEN Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
#define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
#define CACHE_CIR_D_INV_Pos 0U /*!< CACHE CIR: D_INV Position */
#define CACHE_CIR_D_INV_Msk (0x1UL << CACHE_CIR_D_INV_Pos) /*!< CACHE CIR: D_INV Mask */
#define CACHE_CIR_I_INV_Pos 1U /*!< CACHE CIR: I_INV Position */
#define CACHE_CIR_I_INV_Msk (0x1UL << CACHE_CIR_I_INV_Pos) /*!< CACHE CIR: I_INV Mask */
#define CACHE_CIR_D_CLR_Pos 2U /*!< CACHE CIR: D_CLR Position */
#define CACHE_CIR_D_CLR_Msk (0x1UL << CACHE_CIR_D_CLR_Pos) /*!< CACHE CIR: D_CLR Mask */
#define CACHE_CIR_LINE_MODE_Pos 3U /*!< CACHE CIR: LINE_MODE Position */
#define CACHE_CIR_LINE_MODE_Msk (0x1UL << CACHE_CIR_LINE_MODE_Pos) /*!< CACHE CIR: LINE_MODE Mask */
#define CACHE_CIR_OP_ADDR_Pos 4U /*!< CACHE CIR: OP_ADDR Position */
#define CACHE_CIR_OP_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_OP_ADDR_Pos) /*!< CACHE CIR: OP_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
uint32_t RESERVED1;
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED2[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK805 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
PrioThreshold &= 0xFFU;
VIC->IPTR = 0x80000000U | ((VectThreshold & 0xFFU) << 8U) | ((PrioThreshold << (8U - __VIC_PRIO_BITS)) & 0xFFU);
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_I_INV_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_ICEN_Msk); /* enable icache Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_ICEN_Msk); /* disable icache */
CACHE->CIR = CACHE_CIR_I_INV_Msk; /* invalidate icache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_I_INV_Msk; /* invalidate icache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_INV_Msk; /* invalidate dcache */
CACHE->CER |= (uint32_t)(CACHE_CER_DCEN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk); /* enable dcache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_DCEN_Msk; /* disable dcache */
CACHE->CIR = CACHE_CIR_D_INV_Msk; /* invalidate dcache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_INV_Msk; /* invalidate dcache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_CLR_Msk; /* clean dcache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_CLR_Msk | CACHE_CIR_D_INV_Msk; /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_OP_ADDR_Msk;
int32_t linesize = 16;
op_addr |= (CACHE_CIR_D_INV_Msk | CACHE_CIR_LINE_MODE_Msk);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_OP_ADDR_Msk;
int32_t linesize = 16;
op_addr |= (CACHE_CIR_D_CLR_Msk | CACHE_CIR_LINE_MODE_Msk);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_OP_ADDR_Msk;
int32_t linesize = 16;
op_addr |= (CACHE_CIR_D_CLR_Msk | CACHE_CIR_D_INV_Msk | CACHE_CIR_LINE_MODE_Msk);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
\param [in] index cache scope index (0, 1, 2, 3).
\param [in] baseAddr base address must be aligned with size.
\param [in] size \ref CACHE Register Definitions. cache scope size.
\param [in] enable enable or disable cache scope.
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define SCB_EnableICache() csi_icache_enable()
#define SCB_DisableICache() csi_icache_disable()
#define SCB_InvalidateICache() csi_icache_invalid()
#define SCB_EnableDCache() csi_dcache_enable()
#define SCB_DisableDCache() csi_dcache_disable()
#define SCB_InvalidateDCache() csi_dcache_invalid()
#define SCB_CleanDCache() csi_dcache_clean()
#define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
#define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
#define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
#define SCB_EnableCacheProfile() csi_cache_enable_profile()
#define SCB_DisableCacheProfile() csi_cache_disable_profile()
#define SCB_ResetCacheProfile() csi_cache_reset_profile()
#define SCB_CacheAccessTime() csi_cache_get_access_time()
#define SCB_CacheMissTime() csi_cache_get_miss_time()
#define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
#define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
#define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
#define SCB_CleanCache() csi_dcache_clean()
#define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
#define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
#define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_805_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_805.h | C | apache-2.0 | 67,159 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck807.h
* @brief CSI CK807 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK807_H_GENERIC
#define __CORE_CK807_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK807
@{
*/
/* CSI CK807 definitions */
#define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
__CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK807
#define __CK807 (0x07U) /*!< CK807 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK807_H_DEPENDANT
#define __CORE_CK807_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK807_REV
#define __CK807_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK807 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK807 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t NX0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t NX1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t NX2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t NX3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t NX4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t NX5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t NX6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t NX7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_NX7_Pos 7U /*!< CAPR: NX7 Position */
#define CAPR_NX7_Msk (0x1UL << CAPR_NX7_Pos) /*!< CAPR: NX7 Mask */
#define CAPR_NX6_Pos 6U /*!< CAPR: NX6 Position */
#define CAPR_NX6_Msk (0x1UL << CAPR_NX6_Pos) /*!< CAPR: NX6 Mask */
#define CAPR_NX5_Pos 5U /*!< CAPR: NX5 Position */
#define CAPR_NX5_Msk (0x1UL << CAPR_NX5_Pos) /*!< CAPR: NX5 Mask */
#define CAPR_NX4_Pos 4U /*!< CAPR: NX4 Position */
#define CAPR_NX4_Msk (0x1UL << CAPR_NX4_Pos) /*!< CAPR: NX4 Mask */
#define CAPR_NX3_Pos 3U /*!< CAPR: NX3 Position */
#define CAPR_NX3_Msk (0x1UL << CAPR_NX3_Pos) /*!< CAPR: NX3 Mask */
#define CAPR_NX2_Pos 2U /*!< CAPR: NX2 Position */
#define CAPR_NX2_Msk (0x1UL << CAPR_NX2_Pos) /*!< CAPR: NX2 Mask */
#define CAPR_NX1_Pos 1U /*!< CAPR: NX1 Position */
#define CAPR_NX1_Msk (0x1UL << CAPR_NX1_Pos) /*!< CAPR: NX1 Mask */
#define CAPR_NX0_Pos 0U /*!< CAPR: NX0 Position */
#define CAPR_NX0_Msk (0x1UL << CAPR_NX0_Pos) /*!< CAPR: NX0 Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR1, CR<16,0>)
*/
typedef union {
struct {
uint32_t NX8: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t NX9: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t NX10: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t NX11: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t NX12: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t NX13: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t NX14: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t NX15: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP8: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP9: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP10: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP11: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP12: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP13: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP14: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP15: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S8: 1; /*!< bit: 24 Security property settings */
uint32_t S9: 1; /*!< bit: 25 Security property settings */
uint32_t S10: 1; /*!< bit: 26 Security property settings */
uint32_t S11: 1; /*!< bit: 27 Security property settings */
uint32_t S12: 1; /*!< bit: 28 Security property settings */
uint32_t S13: 1; /*!< bit: 29 Security property settings */
uint32_t S14: 1; /*!< bit: 30 Security property settings */
uint32_t S15: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR1_Type;
/* CAPR1 Register Definitions */
#define CAPR1_S15_Pos 31U /*!< CAPR1: S15 Position */
#define CAPR1_S15_Msk (1UL << CAPR1_S15_Pos) /*!< CAPR1: S15 Mask */
#define CAPR1_S14_Pos 30U /*!< CAPR1: S14 Position */
#define CAPR1_S14_Msk (1UL << CAPR1_S14_Pos) /*!< CAPR1: S14 Mask */
#define CAPR1_S13_Pos 29U /*!< CAPR1: S13 Position */
#define CAPR1_S13_Msk (1UL << CAPR1_S13_Pos) /*!< CAPR1: S13 Mask */
#define CAPR1_S12_Pos 28U /*!< CAPR1: S12 Position */
#define CAPR1_S12_Msk (1UL << CAPR1_S12_Pos) /*!< CAPR1: S12 Mask */
#define CAPR1_S11_Pos 27U /*!< CAPR1: S11 Position */
#define CAPR1_S11_Msk (1UL << CAPR1_S11_Pos) /*!< CAPR1: S11 Mask */
#define CAPR1_S10_Pos 26U /*!< CAPR1: S10 Position */
#define CAPR1_S10_Msk (1UL << CAPR1_S10_Pos) /*!< CAPR1: S10 Mask */
#define CAPR1_S9_Pos 25U /*!< CAPR1: S9 Position */
#define CAPR1_S9_Msk (1UL << CAPR1_S9_Pos) /*!< CAPR1: S9 Mask */
#define CAPR1_S8_Pos 24U /*!< CAPR1: S8 Position */
#define CAPR1_S8_Msk (1UL << CAPR1_S8_Pos) /*!< CAPR1: S8 Mask */
#define CAPR1_AP15_Pos 22U /*!< CAPR1: AP15 Position */
#define CAPR1_AP15_Msk (0x3UL << CAPR1_AP15_Pos) /*!< CAPR1: AP15 Mask */
#define CAPR1_AP14_Pos 20U /*!< CAPR1: AP14 Position */
#define CAPR1_AP14_Msk (0x3UL << CAPR1_AP14_Pos) /*!< CAPR1: AP14 Mask */
#define CAPR1_AP13_Pos 18U /*!< CAPR1: AP13 Position */
#define CAPR1_AP13_Msk (0x3UL << CAPR1_AP13_Pos) /*!< CAPR1: AP13 Mask */
#define CAPR1_AP12_Pos 16U /*!< CAPR1: AP12 Position */
#define CAPR1_AP12_Msk (0x3UL << CAPR1_AP12_Pos) /*!< CAPR1: AP12 Mask */
#define CAPR1_AP11_Pos 14U /*!< CAPR1: AP11 Position */
#define CAPR1_AP11_Msk (0x3UL << CAPR1_AP11_Pos) /*!< CAPR1: AP11 Mask */
#define CAPR1_AP10_Pos 12U /*!< CAPR1: AP10 Position */
#define CAPR1_AP10_Msk (0x3UL << CAPR1_AP10_Pos) /*!< CAPR1: AP10 Mask */
#define CAPR1_AP9_Pos 10U /*!< CAPR1: AP9 Position */
#define CAPR1_AP9_Msk (0x3UL << CAPR1_AP9_Pos) /*!< CAPR1: AP9 Mask */
#define CAPR1_AP8_Pos 8U /*!< CAPR1: AP8 Position */
#define CAPR1_AP8_Msk (0x3UL << CAPR1_AP8_Pos) /*!< CAPR1: AP8 Mask */
#define CAPR1_NX15_Pos 7U /*!< CAPR1: NX15 Position */
#define CAPR1_NX15_Msk (0x1UL << CAPR1_NX15_Pos) /*!< CAPR1: NX15 Mask */
#define CAPR1_NX14_Pos 6U /*!< CAPR1: NX14 Position */
#define CAPR1_NX14_Msk (0x1UL << CAPR1_NX14_Pos) /*!< CAPR1: NX14 Mask */
#define CAPR1_NX13_Pos 5U /*!< CAPR1: NX13 Position */
#define CAPR1_NX13_Msk (0x1UL << CAPR1_NX13_Pos) /*!< CAPR1: NX13 Mask */
#define CAPR1_NX12_Pos 4U /*!< CAPR1: NX12 Position */
#define CAPR1_NX12_Msk (0x1UL << CAPR1_NX12_Pos) /*!< CAPR1: NX12 Mask */
#define CAPR1_NX11_Pos 3U /*!< CAPR1: NX11 Position */
#define CAPR1_NX11_Msk (0x1UL << CAPR1_NX11_Pos) /*!< CAPR1: NX11 Mask */
#define CAPR1_NX10_Pos 2U /*!< CAPR1: NX10 Position */
#define CAPR1_NX10_Msk (0x1UL << CAPR1_NX10_Pos) /*!< CAPR1: NX10 Mask */
#define CAPR1_NX9_Pos 1U /*!< CAPR1: NX9 Position */
#define CAPR1_NX9_Msk (0x1UL << CAPR1_NX9_Pos) /*!< CAPR1: NX9 Mask */
#define CAPR1_NX8_Pos 0U /*!< CAPR1: NX8 Position */
#define CAPR1_NX8_Msk (0x1UL << CAPR1_NX8_Pos) /*!< CAPR1: NX8 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t base_addr: 26; /*!< bit: 6..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 6U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0x3FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 4; /*!< bit: 0.. 3 Protected area index value */
uint32_t _reserved0: 28; /*!< bit: 2..28 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for accessing protection area selection register(ATTR0,CR<26,0>).
*/
typedef union {
struct {
uint32_t Attr0_reserved: 1; /*!< bit: 0 Reserved */
uint32_t Attr0_B: 1; /*!< bit: 1 Bufferable attribute setting */
uint32_t Attr0_SO: 1; /*!< bit: 2 Strong-Order attribute setting */
uint32_t Attr0_C: 1; /*!< bit: 3 Cacheable attribute setting */
uint32_t Attr1_reserved: 1; /*!< bit: 4 Reserved */
uint32_t Attr1_B: 1; /*!< bit: 5 Bufferable attribute setting */
uint32_t Attr1_SO: 1; /*!< bit: 6 Strong-Order attribute setting */
uint32_t Attr1_C: 1; /*!< bit: 7 Cacheable attribute setting */
uint32_t Attr2_reserved: 1; /*!< bit: 8 Reserved */
uint32_t Attr2_B: 1; /*!< bit: 9 Bufferable attribute setting */
uint32_t Attr2_SO: 1; /*!< bit: 10 Strong-Order attribute setting */
uint32_t Attr2_C: 1; /*!< bit: 11 Bufferable attribute setting */
uint32_t Attr3_reserved: 1; /*!< bit: 12 Reserved */
uint32_t Attr3_B: 1; /*!< bit: 13 Bufferable attribute setting */
uint32_t Attr3_SO: 1; /*!< bit: 14 Strong-Order attribute setting */
uint32_t Attr3_C: 1; /*!< bit: 15 Bufferable attribute setting */
uint32_t Attr4_reserved: 1; /*!< bit: 16 Reserved */
uint32_t Attr4_B: 1; /*!< bit: 17 Bufferable attribute setting */
uint32_t Attr4_SO: 1; /*!< bit: 18 Strong-Order attribute setting */
uint32_t Attr4_C: 1; /*!< bit: 19 Bufferable attribute setting */
uint32_t Attr5_reserved: 1; /*!< bit: 20 Reserved */
uint32_t Attr5_B: 1; /*!< bit: 21 Bufferable attribute setting */
uint32_t Attr5_SO: 1; /*!< bit: 22 Strong-Order attribute setting */
uint32_t Attr5_C: 1; /*!< bit: 23 Bufferable attribute setting */
uint32_t Attr6_reserved: 1; /*!< bit: 24 Reserved */
uint32_t Attr6_B: 1; /*!< bit: 25 Bufferable attribute setting */
uint32_t Attr6_SO: 1; /*!< bit: 26 Strong-Order attribute setting */
uint32_t Attr6_C: 1; /*!< bit: 27 Bufferable attribute setting */
uint32_t Attr7_reserved: 1; /*!< bit: 28 Reserved */
uint32_t Attr7_B: 1; /*!< bit: 29 Bufferable attribute setting */
uint32_t Attr7_SO: 1; /*!< bit: 30 Strong-Order attribute setting */
uint32_t Attr7_C: 1; /*!< bit: 31 Bufferable attribute setting */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ATTR0_Type;
/* ATTR0 Register Definitions */
#define ATTR0_RESERVED_Pos 0U /*!< ATTR0: RESERVED Position */
#define ATTR0_RESERVED_Msk (0x1UL << ATTR0_RESERVED_Pos) /*!< ATTR0: RESERVED Mask */
#define ATTR0_B_Pos 1U /*!< ATTR0: BUFFERABLE Position */
#define ATTR0_B_Msk (0x1UL << ATTR0_B_Pos) /*!< ATTR0: BUFFERABLE Mask */
#define ATTR0_SO_Pos 2U /*!< ATTR0: STRONG-ORDER Position */
#define ATTR0_SO_Msk (0x1UL << ATTR0_SO_Pos) /*!< ATTR0: STRONG-ORDER Mask */
#define ATTR0_C_Pos 3U /*!< ATTR0: CACHEABLE Position */
#define ATTR0_C_Msk (0x1UL << ATTR0_C_Pos) /*!< ATTR0: CACHEABLE Mask */
#define ATTR1_RESERVED_Pos 4U /*!< ATTR1: RESERVED Position */
#define ATTR1_RESERVED_Msk (0x1UL << ATTR1_RESERVED_Pos) /*!< ATTR1: RESERVED Mask */
#define ATTR1_B_Pos 5U /*!< ATTR1: BUFFERABLE Position */
#define ATTR1_B_Msk (0x1UL << ATTR1_B_Pos) /*!< ATTR1: BUFFERABLE Mask */
#define ATTR1_SO_Pos 6U /*!< ATTR1: STRONG-ORDER Position */
#define ATTR1_SO_Msk (0x1UL << ATTR1_SO_Pos) /*!< ATTR1: STRONG-ORDER Mask */
#define ATTR1_C_Pos 7U /*!< ATTR1: CACHEABLE Position */
#define ATTR1_C_Msk (0x1UL << ATTR1_C_Pos) /*!< ATTR1: CACHEABLE Mask */
#define ATTR2_RESERVED_Pos 8U /*!< ATTR2: RESERVED Position */
#define ATTR2_RESERVED_Msk (0x1UL << ATTR2_RESERVED_Pos) /*!< ATTR2: RESERVED Mask */
#define ATTR2_B_Pos 9U /*!< ATTR2: BUFFERABLE Position */
#define ATTR2_B_Msk (0x1UL << ATTR2_B_Pos) /*!< ATTR2: BUFFERABLE Mask */
#define ATTR2_SO_Pos 10U /*!< ATTR2: STRONG-ORDER Position */
#define ATTR2_SO_Msk (0x1UL << ATTR2_SO_Pos) /*!< ATTR2: STRONG-ORDER Mask */
#define ATTR2_C_Pos 11U /*!< ATTR2: CACHEABLE Position */
#define ATTR2_C_Msk (0x1UL << ATTR2_C_Pos) /*!< ATTR2: CACHEABLE Mask */
#define ATTR3_RESERVED_Pos 12U /*!< ATTR3: RESERVED Position */
#define ATTR3_RESERVED_Msk (0x1UL << ATTR3_RESERVED_Pos) /*!< ATTR3: RESERVED Mask */
#define ATTR3_B_Pos 13U /*!< ATTR3: BUFFERABLE Position */
#define ATTR3_B_Msk (0x1UL << ATTR3_B_Pos) /*!< ATTR3: BUFFERABLE Mask */
#define ATTR3_SO_Pos 14U /*!< ATTR3: STRONG-ORDER Position */
#define ATTR3_SO_Msk (0x1UL << ATTR3_SO_Pos) /*!< ATTR3: STRONG-ORDER Mask */
#define ATTR3_C_Pos 15U /*!< ATTR3: CACHEABLE Position */
#define ATTR3_C_Msk (0x1UL << ATTR3_C_Pos) /*!< ATTR3: CACHEABLE Mask */
#define ATTR4_RESERVED_Pos 16U /*!< ATTR4: RESERVED Position */
#define ATTR4_RESERVED_Msk (0x1UL << ATTR4_RESERVED_Pos) /*!< ATTR4: RESERVED Mask */
#define ATTR4_B_Pos 17U /*!< ATTR4: BUFFERABLE Position */
#define ATTR4_B_Msk (0x1UL << ATTR4_B_Pos) /*!< ATTR4: BUFFERABLE Mask */
#define ATTR4_SO_Pos 18U /*!< ATTR4: STRONG-ORDER Position */
#define ATTR4_SO_Msk (0x1UL << ATTR4_SO_Pos /*!< ATTR4: STRONG-ORDER Mask */
#define ATTR4_C_Pos 19U /*!< ATTR4: CACHEABLE Position */
#define ATTR4_C_Msk (0x1UL << ATTR4_C_Pos) /*!< ATTR4: CACHEABLE Mask */
#define ATTR5_RESERVED_Pos 20U /*!< ATTR5: RESERVED Position */
#define ATTR5_RESERVED_Msk (0x1UL << ATTR5_RESERVED_Pos) /*!< ATTR5: RESERVED Mask */
#define ATTR5_B_Pos 21U /*!< ATTR5: BUFFERABLE Position */
#define ATTR5_B_Msk (0x1UL << ATTR5_B_Pos) /*!< ATTR5: BUFFERABLE Mask */
#define ATTR5_SO_Pos 22U /*!< ATTR5: STRONG-ORDER Position */
#define ATTR5_SO_Msk (0x1UL << ATTR5_SO_Pos) /*!< ATTR5: STRONG-ORDER Mask */
#define ATTR5_C_Pos 23U /*!< ATTR5: CACHEABLE Position */
#define ATTR5_C_Msk (0x1UL << ATTR5_C_Pos) /*!< ATTR5: CACHEABLE Mask */
#define ATTR6_RESERVED_Pos 24U /*!< ATTR6: RESERVED Position */
#define ATTR6_RESERVED_Msk (0x1UL << ATTR6_RESERVED_Pos) /*!< ATTR6: RESERVED Mask */
#define ATTR6_B_Pos 25U /*!< ATTR6: BUFFERABLE Position */
#define ATTR6_B_Msk (0x1UL << ATTR6_B_Pos) /*!< ATTR6: BUFFERABLE Mask */
#define ATTR6_SO_Pos 26U /*!< ATTR6: STRONG-ORDER Position */
#define ATTR6_SO_Msk (0x1UL << ATTR6_SO_Pos) /*!< ATTR6: STRONG-ORDER Mask */
#define ATTR6_C_Pos 27U /*!< ATTR6: CACHEABLE Position */
#define ATTR6_C_Msk (0x1UL << ATTR6_C_Pos) /*!< ATTR6: CACHEABLE Mask */
#define ATTR7_RESERVED_Pos 28U /*!< ATTR7: RESERVED Position */
#define ATTR7_RESERVED_Msk (0x1UL << ATTR7_RESERVED_Pos) /*!< ATTR7: RESERVED Mask */
#define ATTR7_B_Pos 29U /*!< ATTR7: BUFFERABLE Position */
#define ATTR7_B_Msk (0x1UL << ATTR7_B_Pos) /*!< ATTR7: BUFFERABLE Mask */
#define ATTR7_SO_Pos 30U /*!< ATTR7: STRONG-ORDER Position */
#define ATTR7_SO_Msk (0x1UL << ATTR7_SO_Pos) /*!< ATTR7: STRONG-ORDER Mask */
#define ATTR7_C_Pos 31U /*!< ATTR7: CACHEABLE Position */
#define ATTR7_C_Msk (0x1UL << ATTR7_C_Pos) /*!< ATTR7: CACHEABLE Mask */
/**
\brief Consortium definition for accessing protection area selection register(ATTR1,CR<27,0>).
*/
typedef union {
struct {
uint32_t Attr8_reserved: 1; /*!< bit: 0 Reserved */
uint32_t Attr8_B: 1; /*!< bit: 1 Bufferable attribute setting */
uint32_t Attr8_SO: 1; /*!< bit: 2 Strong-Order attribute setting */
uint32_t Attr8_C: 1; /*!< bit: 3 Cacheable attribute setting */
uint32_t Attr9_reserved: 1; /*!< bit: 4 Reserved */
uint32_t Attr9_B: 1; /*!< bit: 5 Bufferable attribute setting */
uint32_t Attr9_SO: 1; /*!< bit: 6 Strong-Order attribute setting */
uint32_t Attr9_C: 1; /*!< bit: 7 Cacheable attribute setting */
uint32_t Attr10_reserved: 1; /*!< bit: 8 Reserved */
uint32_t Attr10_B: 1; /*!< bit: 9 Bufferable attribute setting */
uint32_t Attr10_SO: 1; /*!< bit: 10 Strong-Order attribute setting */
uint32_t Attr10_C: 1; /*!< bit: 11 Bufferable attribute setting */
uint32_t Attr11_reserved: 1; /*!< bit: 12 Reserved */
uint32_t Attr11_B: 1; /*!< bit: 13 Bufferable attribute setting */
uint32_t Attr11_SO: 1; /*!< bit: 14 Strong-Order attribute setting */
uint32_t Attr11_C: 1; /*!< bit: 15 Bufferable attribute setting */
uint32_t Attr12_reserved: 1; /*!< bit: 16 Reserved */
uint32_t Attr12_B: 1; /*!< bit: 17 Bufferable attribute setting */
uint32_t Attr12_SO: 1; /*!< bit: 18 Strong-Order attribute setting */
uint32_t Attr12_C: 1; /*!< bit: 19 Bufferable attribute setting */
uint32_t Attr13_reserved: 1; /*!< bit: 20 Reserved */
uint32_t Attr13_B: 1; /*!< bit: 21 Bufferable attribute setting */
uint32_t Attr13_SO: 1; /*!< bit: 22 Strong-Order attribute setting */
uint32_t Attr13_C: 1; /*!< bit: 23 Bufferable attribute setting */
uint32_t Attr14_reserved: 1; /*!< bit: 24 Reserved */
uint32_t Attr14_B: 1; /*!< bit: 25 Bufferable attribute setting */
uint32_t Attr14_SO: 1; /*!< bit: 26 Strong-Order attribute setting */
uint32_t Attr14_C: 1; /*!< bit: 27 Bufferable attribute setting */
uint32_t Attr15_reserved: 1; /*!< bit: 28 Reserved */
uint32_t Attr15_B: 1; /*!< bit: 29 Bufferable attribute setting */
uint32_t Attr15_SO: 1; /*!< bit: 30 Strong-Order attribute setting */
uint32_t Attr15_C: 1; /*!< bit: 31 Bufferable attribute setting */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ATTR1_Type;
/* ATTR0 Register Definitions */
#define ATTR8_RESERVED_Pos 0U /*!< ATTR8: RESERVED Position */
#define ATTR8_RESERVED_Msk (0x1UL << ATTR8_RESERVED_Pos) /*!< ATTR8: RESERVED Mask */
#define ATTR8_B_Pos 1U /*!< ATTR8: BUFFERABLE Position */
#define ATTR8_B_Msk (0x1UL << ATTR8_B_Pos) /*!< ATTR8: BUFFERABLE Mask */
#define ATTR8_SO_Pos 2U /*!< ATTR8: STRONG-ORDER Position */
#define ATTR8_SO_Msk (0x1UL << ATTR8_SO_Pos) /*!< ATTR8: STRONG-ORDER Mask */
#define ATTR8_C_Pos 3U /*!< ATTR8: CACHEABLE Position */
#define ATTR8_C_Msk (0x1UL << ATTR8_C_Pos) /*!< ATTR8: CACHEABLE Mask */
#define ATTR9_RESERVED_Pos 4U /*!< ATTR9: RESERVED Position */
#define ATTR9_RESERVED_Msk (0x1UL << ATTR9_RESERVED_Pos) /*!< ATTR9: RESERVED Mask */
#define ATTR9_B_Pos 5U /*!< ATTR9: BUFFERABLE Position */
#define ATTR9_B_Msk (0x1UL << ATTR9_B_Pos) /*!< ATTR9: BUFFERABLE Mask */
#define ATTR9_SO_Pos 6U /*!< ATTR9: STRONG-ORDER Position */
#define ATTR9_SO_Msk (0x1UL << ATTR9_SO_Pos) /*!< ATTR9: STRONG-ORDER Mask */
#define ATTR9_C_Pos 7U /*!< ATTR9: CACHEABLE Position */
#define ATTR9_C_Msk (0x1UL << ATTR9_C_Pos) /*!< ATTR9: CACHEABLE Mask */
#define ATTR10_RESERVED_Pos 8U /*!< ATTR10: RESERVED Position */
#define ATTR10_RESERVED_Msk (0x1UL << ATTR10_RESERVED_Pos) /*!< ATTR10: RESERVED Mask */
#define ATTR10_B_Pos 9U /*!< ATTR10: BUFFERABLE Position */
#define ATTR10_B_Msk (0x1UL << ATTR10_B_Pos) /*!< ATTR10: BUFFERABLE Mask */
#define ATTR10_SO_Pos 10U /*!< ATTR10: STRONG-ORDER Position */
#define ATTR10_SO_Msk (0x1UL << ATTR10_SO_Pos) /*!< ATTR10: STRONG-ORDER Mask */
#define ATTR10_C_Pos 11U /*!< ATTR10: CACHEABLE Position */
#define ATTR10_C_Msk (0x1UL << ATTR10_C_Pos) /*!< ATTR10: CACHEABLE Mask */
#define ATTR11_RESERVED_Pos 12U /*!< ATTR11: RESERVED Position */
#define ATTR11_RESERVED_Msk (0x1UL << ATTR11_RESERVED_Pos) /*!< ATTR11: RESERVED Mask */
#define ATTR11_B_Pos 13U /*!< ATTR11: BUFFERABLE Position */
#define ATTR11_B_Msk (0x1UL << ATTR11_B_Pos) /*!< ATTR11: BUFFERABLE Mask */
#define ATTR11_SO_Pos 14U /*!< ATTR11: STRONG-ORDER Position */
#define ATTR11_SO_Msk (0x1UL << ATTR11_SO_Pos) /*!< ATTR11: STRONG-ORDER Mask */
#define ATTR11_C_Pos 15U /*!< ATTR11: CACHEABLE Position */
#define ATTR11_C_Msk (0x1UL << ATTR11_C_Pos) /*!< ATTR11: CACHEABLE Mask */
#define ATTR12_RESERVED_Pos 16U /*!< ATTR12: RESERVED Position */
#define ATTR12_RESERVED_Msk (0x1UL << ATTR12_RESERVED_Pos) /*!< ATTR12: RESERVED Mask */
#define ATTR12_B_Pos 17U /*!< ATTR12: BUFFERABLE Position */
#define ATTR12_B_Msk (0x1UL << ATTR12_B_Pos) /*!< ATTR12: BUFFERABLE Mask */
#define ATTR12_SO_Pos 18U /*!< ATTR12: STRONG-ORDER Position */
#define ATTR12_SO_Msk (0x1UL << ATTR12_SO_Pos /*!< ATTR12: STRONG-ORDER Mask */
#define ATTR12_C_Pos 19U /*!< ATTR12: CACHEABLE Position */
#define ATTR12_C_Msk (0x1UL << ATTR12_C_Pos) /*!< ATTR12: CACHEABLE Mask */
#define ATTR13_RESERVED_Pos 20U /*!< ATTR13: RESERVED Position */
#define ATTR13_RESERVED_Msk (0x1UL << ATTR13_RESERVED_Pos) /*!< ATTR13: RESERVED Mask */
#define ATTR13_B_Pos 21U /*!< ATTR13: BUFFERABLE Position */
#define ATTR13_B_Msk (0x1UL << ATTR13_B_Pos) /*!< ATTR13: BUFFERABLE Mask */
#define ATTR13_SO_Pos 22U /*!< ATTR13: STRONG-ORDER Position */
#define ATTR13_SO_Msk (0x1UL << ATTR13_SO_Pos) /*!< ATTR13: STRONG-ORDER Mask */
#define ATTR13_C_Pos 23U /*!< ATTR13: CACHEABLE Position */
#define ATTR13_C_Msk (0x1UL << ATTR13_C_Pos) /*!< ATTR13: CACHEABLE Mask */
#define ATTR14_RESERVED_Pos 24U /*!< ATTR14: RESERVED Position */
#define ATTR14_RESERVED_Msk (0x1UL << ATTR14_RESERVED_Pos) /*!< ATTR14: RESERVED Mask */
#define ATTR14_B_Pos 25U /*!< ATTR14: BUFFERABLE Position */
#define ATTR14_B_Msk (0x1UL << ATTR14_B_Pos) /*!< ATTR14: BUFFERABLE Mask */
#define ATTR14_SO_Pos 26U /*!< ATTR14: STRONG-ORDER Position */
#define ATTR14_SO_Msk (0x1UL << ATTR14_SO_Pos) /*!< ATTR14: STRONG-ORDER Mask */
#define ATTR14_C_Pos 27U /*!< ATTR14: CACHEABLE Position */
#define ATTR14_C_Msk (0x1UL << ATTR14_C_Pos) /*!< ATTR14: CACHEABLE Mask */
#define ATTR15_RESERVED_Pos 28U /*!< ATTR15: RESERVED Position */
#define ATTR15_RESERVED_Msk (0x1UL << ATTR15_RESERVED_Pos) /*!< ATTR15: RESERVED Mask */
#define ATTR15_B_Pos 29U /*!< ATTR15: BUFFERABLE Position */
#define ATTR15_B_Msk (0x1UL << ATTR15_B_Pos) /*!< ATTR15: BUFFERABLE Mask */
#define ATTR15_SO_Pos 30U /*!< ATTR15: STRONG-ORDER Position */
#define ATTR15_SO_Msk (0x1UL << ATTR15_SO_Pos) /*!< ATTR15: STRONG-ORDER Mask */
#define ATTR15_C_Pos 31U /*!< ATTR15: CACHEABLE Position */
#define ATTR15_C_Msk (0x1UL << ATTR15_C_Pos) /*!< ATTR15: CACHEABLE Mask */
/* CCR2 Register Definitions */
#define CCR2_CRECC_Pos 7U /*!< CCR2: CRECC Position */
#define CCR2_CRECC_Msk (0x1UL << CCR2_CRECC_Pos) /*!< CCR2: CRECC Mask */
#define CCR2_ECC_Pos 6U /*!< CCR2: ECC Position */
#define CCR2_ECC_Msk (0x1UL << CCR2_ECC_Pos) /*!< CCR2: ECC Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_tcm_register
\defgroup CSI_TCM
\brief Type definitions for the tcm Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(ITCMCR,CR<22,1>).
*/
typedef union {
struct {
uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */
uint32_t _reserved0: 1; /*!< bit: 1 Reserved */
uint32_t SIF: 1; /*!< bit: 2 Slave interface access ITCM */
uint32_t _reserved1: 1; /*!< bit: 3 Reserved */
uint32_t Size: 4; /*!< bit: 4..7 Size of ITCM */
uint32_t _reserved2: 1; /*!< bit: 8 Reserved */
uint32_t Delay: 1; /*!< bit: 9 The time from access ITCM to data come back. */
uint32_t _reserved3: 2; /*!< bit: 10..11 Reserved */
uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ITCMCR_Type;
#define ITCMCR_Base_Address_Pos 12U /*!< ITCMCR: Base_Address Position */
#define ITCMCR_Base_Address_Msk (0xfffffUL << ITCMCR_Base_Address_Pos) /*!< ITCMCR: Base_Address Mask */
#define ITCMCR_Delay_Pos 9U /*!< ITCMCR: Delay Position */
#define ITCMCR_Delay_Msk (0x1UL << ITCMCR_Delay_Pos) /*!< ITCMCR: Delay Mask */
#define ITCMCR_Size_Pos 4U /*!< ITCMCR: Size Position */
#define ITCMCR_Size_Msk (0xfUL << ITCMCR_Size_Pos) /*!< ITCMCR: Size Mask */
#define ITCMCR_SIF_Pos 2U /*!< ITCMCR: SIF Position */
#define ITCMCR_SIF_Msk (0x1UL << ITCMCR_SIF_Pos) /*!< ITCMCR: SIF Mask */
#define ITCMCR_EN_Pos 0U /*!< ITCMCR: EN Position */
#define ITCMCR_EN_Msk (0x1UL << ITCMCR_EN_Pos) /*!< ITCMCR: EN Mask */
/**
\brief Consortium definition for accessing protection area selection register(DTCMCR,CR<23,1>).
*/
typedef union {
struct {
uint32_t EN: 1; /*!< bit: 0 Data Tightly-Coupled Memory enable */
uint32_t _reserved0: 1; /*!< bit: 1 Reserved */
uint32_t SIF: 1; /*!< bit: 2 Slave interface access DTCM */
uint32_t _reserved1: 1; /*!< bit: 3 Reserved */
uint32_t Size: 4; /*!< bit: 4..7 Size of DTCM */
uint32_t _reserved2: 1; /*!< bit: 8 Reserved */
uint32_t Delay: 1; /*!< bit: 9 The time from access DTCM to data come back.*/
uint32_t _reserved3: 2; /*!< bit: 10..11 Reserved */
uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} DTCMCR_Type;
#define DTCMCR_Base_Address_Pos 12U /*!< DTCMCR: Base_Address Position */
#define DTCMCR_Base_Address_Msk (0xfffffUL << DTCMCR_Base_Address_Pos) /*!< DTCMCR: Base_Address Mask */
#define DTCMCR_Delay_Pos 9U /*!< DTCMCR: Delay Position */
#define DTCMCR_Delay_Msk (0x1UL << DTCMCR_Delay_Pos) /*!< DTCMCR: Delay Mask */
#define DTCMCR_Size_Pos 4U /*!< DTCMCR: Size Position */
#define DTCMCR_Size_Msk (0xfUL << DTCMCR_Size_Pos) /*!< DTCMCR: Size Mask */
#define DTCMCR_SIF_Pos 2U /*!< DTCMCR: SIF Position */
#define DTCMCR_SIF_Msk (0x1UL << DTCMCR_SIF_Pos) /*!< DTCMCR: SIF Mask */
#define DTCMCR_EN_Pos 0U /*!< DTCMCR: EN Position */
#define DTCMCR_EN_Msk (0x1UL << DTCMCR_EN_Pos) /*!< DTCMCR: EN Mask */
/*@} end of group CSI_TCM_bitfield */
/**
\ingroup CSI_ECC_register
\defgroup CSI_ECC
\brief Type definitions for the ECC Registers
@{
*/
typedef union {
struct {
uint32_t Index: 17; /*!< bit: 0..16 RAM index */
uint32_t _reserved0: 1; /*!< bit: 2..23 Reserved */
uint32_t Way: 2; /*!< bit: 18..19 ICACHE/DCACHE WAY */
uint32_t _reserved1: 2; /*!< bit: 20..21 Reserved */
uint32_t RAMID: 8; /*!< bit: 22..29 ECC RAM ID */
uint32_t ERR_TYPE: 2; /*!< bit: 30..31 ECC ERR TYPE */
} b;
uint32_t w;
} ERRLC_Type;
#define ERRLC_ERR_TYPE_Pos 30U /*!< ERRLC: ERR_TYPE Position */
#define ERRLC_ERR_TYPE_Msk (0x3UL << ERRLC_ERR_TYPE_Pos) /*!< ERRLC: ERR_TYPE Mask */
#define ERRLC_RAMID_Pos 22U /*!< ERRLC: RAMID Position */
#define ERRLC_RAMID_Msk (0xFFUL << ERRLC_RAMID_Pos) /*!< ERRLC: RAMID Mask */
#define ERRLC_Way_Pos 18U /*!< ERRLC: Way Position */
#define ERRLC_Way_Msk (0x3UL << ERRLC_Way_Pos) /*!< ERRLC: Way Mask */
#define ERRLC_Index_Pos 0U /*!< ERRLC: Index Position */
#define ERRLC_Index_Msk (0x1FFFFUL << ERRLC_Index_Pos) /*!< ERRLC: Index Mask */
typedef union {
struct {
uint32_t INJ_EN: 1; /*!< bit: 0 ECC inject enable */
uint32_t ERR_TYPE: 1; /*!< bit: 1 ECC error type */
uint32_t _reserved0: 22; /*!< bit: 2..23 Reserved */
uint32_t RAMID: 8; /*!< bit: 24..31 ECC RAMID */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ERRINJCR_Type;
#define ERRINJCR_RAMID_Pos 24U /*!< ERRINJCR: RAMID Position */
#define ERRINJCR_RAMID_Msk (0xFFUL << ERRINJCR_RAMID_Pos) /*!< ERRINJCR: RAMID Mask */
#define ERRINJCR_ERR_TYPE_Pos 1U /*!< ERRINJCR: ERR_TYPE Position */
#define ERRINJCR_ERR_TYPE_Msk (0x1UL << ERRINJCR_ERR_TYPE_Pos) /*!< ERRINJCR: ERR_TYPE Mask */
#define ERRINJCR_INJ_EN_Pos 0U /*!< ERRINJCR: INJ_EN Position */
#define ERRINJCR_INJ_EN_Msk (0x1UL << ERRINJCR_INJ_EN_Pos) /*!< ERRINJCR: INJ_EN Mask */
/*@} end of group CSI_ECC_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_128B = 0x6,
REGION_SIZE_256B = 0x7,
REGION_SIZE_512B = 0x8,
REGION_SIZE_1KB = 0x9,
REGION_SIZE_2KB = 0xA,
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1;
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1;
uint32_t c: 1; /* cacheable */
uint32_t so: 1;
uint32_t b: 1;
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
uint32_t op_idx;
if (idx > 15) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
ATTR0_Type reg_attr;
if (idx <= 7) {
capr.w = __get_CAPR();
reg_attr.w = __get_ATTR0();
op_idx = idx;
} else {
capr.w = __get_CAPR1();
reg_attr.w = __get_ATTR1();
op_idx = idx - 8;
}
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.w = (base_addr & PACR_BASE_ADDR_Msk) | (size << PACR_SIZE_Pos);
pacr.w &= ~(((1u << (size - 6)) - 1) << 7);
pacr.b.E = enable;
prsr.b.RID = idx;
__set_PRSR(prsr.w);
capr.w &= ~((0x1 << op_idx) | (0x3 << (op_idx * 2 + 8)) | (0x1 << (op_idx + 24)));
capr.w = (capr.w | (attr.nx << op_idx) | (attr.ap << (op_idx * 2 + 8)) | (attr.s << (op_idx + 24)));
reg_attr.w &= ~(0x7 << (op_idx << 2));
reg_attr.w |= ((attr.c | (attr.so << 1) | (attr.b << 2)) << (op_idx << 2));
if (idx <= 7) {
__set_CAPR(capr.w);
__set_ATTR0(reg_attr.w);
} else {
__set_CAPR1(capr.w);
__set_ATTR1(reg_attr.w);
}
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 15) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 15) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MPUFunctions */
/* ########################## TCM functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_TCMFunctions TCM Functions
\brief Functions that configure TCM.
@{
*/
/**
\brief Enable ITCM
\details Turns on ITCM
*/
__STATIC_INLINE void csi_itcm_enable (void)
{
__set_ITCMCR(__get_ITCMCR() | ITCMCR_EN_Msk);
}
/**
\brief Enable DTCM
\details Turns on DTCM
*/
__STATIC_INLINE void csi_dtcm_enable (void)
{
__set_DTCMCR(__get_DTCMCR() | DTCMCR_EN_Msk);
}
/**
\brief Enable ITCM
\details Turns on ITCM
*/
__STATIC_INLINE void csi_itcm_disable (void)
{
__set_ITCMCR(__get_ITCMCR() & (~ITCMCR_EN_Msk));
}
/**
\brief Enable DTCM
\details Turns on DTCM
*/
__STATIC_INLINE void csi_dtcm_disable (void)
{
__set_DTCMCR(__get_DTCMCR() & (~DTCMCR_EN_Msk));
}
/**
\brief Enable ITCM slave interface access
\details Enable ITCM slave interface access
*/
__STATIC_INLINE void csi_itcm_enable_slave_access(void)
{
__set_ITCMCR(__get_ITCMCR() | ITCMCR_SIF_Msk);
}
/**
\brief Disable ITCM slave interface access
\details Disable ITCM slave interface access
*/
__STATIC_INLINE void csi_itcm_disable_slave_access(void)
{
__set_ITCMCR(__get_ITCMCR() & (~ITCMCR_SIF_Msk));
}
/**
\brief Enable DTCM slave interface access
\details Enable DTCM slave interface access
*/
__STATIC_INLINE void csi_dtcm_enable_slave_access(void)
{
__set_DTCMCR(__get_DTCMCR() | DTCMCR_SIF_Msk);
}
/**
\brief Disable DTCM slave interface access
\details Disable DTCM slave interface access
*/
__STATIC_INLINE void csi_dtcm_disable_slave_access(void)
{
__set_DTCMCR(__get_DTCMCR() & (~DTCMCR_SIF_Msk));
}
/**
\brief Get ITCM Size
\details Get ITCM Size
\return ITCM size (bytes).
*/
__STATIC_INLINE uint32_t csi_itcm_get_size(void)
{
ITCMCR_Type sizemask;
uint32_t ret;
sizemask.w = __get_ITCMCR();
ret = sizemask.b.Size;
return (1 << ret) << 10;
}
/**
\brief Get DTCM Size
\details Get DTCM Size
\return DTCM size (bytes).
*/
__STATIC_INLINE uint32_t csi_dtcm_get_size(void)
{
DTCMCR_Type sizemask;
uint32_t ret;
sizemask.w = __get_DTCMCR();
ret = sizemask.b.Size;
return (1 << ret) << 10;
}
/**
\brief Get ITCM Delay
\details Get ITCM Delay
\return delay time.
*/
__STATIC_INLINE uint32_t csi_itcm_get_delay(void)
{
ITCMCR_Type delaymask;
uint32_t ret;
delaymask.w = __get_ITCMCR();
ret = delaymask.b.Delay;
return ret;
}
/**
\brief Get DTCM Delay
\details Get DTCM Delay
\return delay time.
*/
__STATIC_INLINE uint32_t csi_dtcm_get_delay(void)
{
DTCMCR_Type delaymask;
uint32_t ret;
delaymask.w = __get_DTCMCR();
ret = delaymask.b.Delay;
return ret;
}
/**
\brief Set ITCM Base Address
\details Set ITCM Base Address
\param [in] base_addr itcm base address.
*/
__STATIC_INLINE void csi_itcm_set_base_addr(uint32_t base_addr)
{
__set_ITCMCR((__get_ITCMCR() & (~ITCMCR_Base_Address_Msk)) | (base_addr & ITCMCR_Base_Address_Msk));
}
/**
\brief Set DTCM Base Address
\details Set DTCM Base Address
\param [in] base_addr dtcm base address.
*/
__STATIC_INLINE void csi_dtcm_set_base_addr(uint32_t base_addr)
{
__set_DTCMCR((__get_DTCMCR() & (~DTCMCR_Base_Address_Msk)) | (base_addr & DTCMCR_Base_Address_Msk));
}
/*@} end of CSI_Core_TCMFunctions */
/* ########################## ECC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_ECCFunctions ECC Functions
\brief Functions that configure ECC.
@{
*/
typedef enum {
ECC_ERROR_CORRECTABLE = 0,
ECC_ERROR_FATAL = 1
} ecc_error_type_e;
typedef enum {
ECC_DTCM_RAM = 0,
ECC_ITCM_RAM = 1,
ECC_DCACHE_DATA_RAM = 4,
ECC_DCACHE_TAG_RAM = 5,
ECC_ICACHE_DATA_RAM = 6,
ECC_ICACHE_TAG_RAM = 7
} ecc_ramid_e;
typedef struct {
uint32_t erraddr;
uint32_t index;
uint8_t way;
ecc_ramid_e ramid: 8;
ecc_error_type_e err_type: 8;
} ecc_error_info_t;
/**
\brief Enable ECC
\details Turns on ECC
*/
__STATIC_INLINE void csi_ecc_enable (void)
{
__set_CCR2(__get_CCR2() | CCR2_ECC_Msk);
}
/**
\brief Disable ECC
\details Turns off ECC
*/
__STATIC_INLINE void csi_ecc_disable (void)
{
__set_CCR2(__get_CCR2() & ~CCR2_ECC_Msk);
}
/**
\brief Enable ECC error fix function
\details Turns on ECC error fix function
*/
__STATIC_INLINE void csi_ecc_enable_error_fix (void)
{
__set_CCR2(__get_CCR2() | CCR2_CRECC_Msk);
}
/**
\brief Disable ECC error fix function
\details Turns off ECC error fix function
*/
__STATIC_INLINE void csi_ecc_disable_error_fix (void)
{
__set_CCR2(__get_CCR2() & ~CCR2_CRECC_Msk);
}
/**
\brief Inject ECC error
\details Inject ECC error
\param [in] type ECC error type.
\param [in] ramid ECC ram id.
*/
__STATIC_INLINE void csi_ecc_inject_error(ecc_error_type_e type, ecc_ramid_e ramid)
{
ERRINJCR_Type errinjcr;
errinjcr.b.ERR_TYPE = type;
errinjcr.b.RAMID = (1U << ramid);
errinjcr.b.INJ_EN = 1U;
errinjcr.b._reserved0 = 0;
__set_ERRINJCR(errinjcr.w);
}
/**
\brief Get ECC error info
\details Inject ECC error info
\param [out] info ECC error info
*/
__STATIC_INLINE void csi_ecc_get_error_info(ecc_error_info_t *info)
{
ERRLC_Type errlc;
if (info != NULL) {
errlc.w = __get_ERRLC();
info->erraddr = __get_ERRADDR();
info->index = errlc.b.Index;
info->way = errlc.b.Way;
info->ramid = 31 - __FF1(errlc.b.RAMID);
info->err_type = errlc.b.ERR_TYPE;
}
}
/*@} end of CSI_Core_ECCFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_807.h | C | apache-2.0 | 96,525 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck810.h
* @brief CSI CK810 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK810_H_GENERIC
#define __CORE_CK810_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK810
@{
*/
/* CSI CK810 definitions */
#define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
__CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK810
#define __CK810 (0x0aU) /*!< CK810 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK810_H_DEPENDANT
#define __CORE_CK810_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK810_REV
#define __CK810_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK810 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK810 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
#define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
#define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_810.h | C | apache-2.0 | 35,443 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck610.h
* @brief CSI CK610 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK610_H_GENERIC
#define __CORE_CK610_H_GENERIC
#include <stdint.h>
#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck610
@{
*/
/* CSI CK610 definitions */
#define __CK610_CSI_VERSION_MAIN (0x01U) /*!< [31:16] CSI HAL main version */
#define __CK610_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK610_CSI_VERSION ((__CK610_CSI_VERSION_MAIN << 16U) | \
__CK610_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#define __CK610 (0x01U) /*!< CK610 Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK610_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK610_H_DEPENDANT
#define __CORE_CK610_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK610_REV
#define __CK610_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK610 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core MGU Register
- Core MMU Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK610 processor based devices.
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t CPID: 4; /*!< bit: 24..27 Number of processor currently running */
uint32_t _reserved3: 3; /*!< bit: 28..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_CPID_Pos 24U /*!< PSR: CPID Position */
#define PSR_CPID_Msk (0xFUL << PSR_CPID_Pos) /*!< PSR: CPID Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0..1 Memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Endian mode */
uint32_t DE: 1; /*!< bit: 3 Endian mode */
uint32_t WB: 1; /*!< bit: 4 Endian mode */
uint32_t RS: 1; /*!< bit: 5 Endian mode */
uint32_t Z: 1; /*!< bit: 6 Endian mode */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 The clock ratio of the system and the processor */
uint32_t _reserved0: 21; /*!< bit: 11..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x7UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_Z_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_RS_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_WB_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_DE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_IE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t C0: 1; /*!< bit: 0 Cacheable setting */
uint32_t C1: 1; /*!< bit: 1 Cacheable setting */
uint32_t C2: 1; /*!< bit: 2 Cacheable setting */
uint32_t C3: 1; /*!< bit: 3 Cacheable setting */
uint32_t _reserved0: 4; /*!< bit: 4.. 7 Reserved */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 2; /*!< bit: 0.. 1 Protected area index value */
uint32_t _reserved0: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CP15_CR0).
*/
typedef union {
struct {
uint32_t Index: 10;
uint32_t _reserved: 20;
uint32_t TF: 1;
uint32_t P: 1;
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
*/
typedef union {
struct {
uint32_t G: 1;
uint32_t V: 1;
uint32_t D: 1;
uint32_t C: 3;
uint32_t PFN: 20;
uint32_t _reserved: 6;
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 6 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x7UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
*/
typedef union {
struct {
uint32_t ASID :8;
uint32_t _reserved :4;
uint32_t VPN :20;
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
*/
typedef union {
struct {
uint32_t _reserved0: 13;
uint32_t page_mask: 12;
uint32_t _reserved1: 7;
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
*/
typedef union {
struct {
uint32_t ASID: 8;
uint32_t _reserved: 17;
uint32_t TLBINV_INDEX: 1;
uint32_t TLBINV_ALL: 1;
uint32_t TLBINV: 1;
uint32_t TLBWR: 1;
uint32_t TLBWI: 1;
uint32_t TLBR: 1;
uint32_t TLBP: 1;
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEL_Type mel;
MEH_Type meh;
uint32_t vaddr_bit = 0;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
pgmask.w = __FF1(__get_MPR());
vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
meh.b.ASID = asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
} else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type mpr;
mpr.w = __get_MPR();
mpr.b.page_mask = size;
__set_MPR(mpr.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t c: 1; /* cacheable */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 3) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 3) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 3) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/*@} */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK610_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_ck610.h | C | apache-2.0 | 35,730 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck801.h
* @brief CSI CK801 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK801_H_GENERIC
#define __CORE_CK801_H_GENERIC
#include <core_801.h>
#endif /* __CORE_CK801_H_DEPENDANT */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_ck801.h | C | apache-2.0 | 526 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck802.h
* @brief CSI CK802 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK802_H_GENERIC
#define __CORE_CK802_H_GENERIC
#include <core_802.h>
#endif /* __CORE_CK802_H_DEPENDANT */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_ck802.h | C | apache-2.0 | 526 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck803.h
* @brief CSI CK803 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK803_H_GENERIC
#define __CORE_CK803_H_GENERIC
#include <core_803.h>
#endif /* __CORE_CK803_H_DEPENDANT */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_ck803.h | C | apache-2.0 | 526 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck807.h
* @brief CSI CK807 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK807_H_GENERIC
#define __CORE_CK807_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK807
@{
*/
/* CSI CK807 definitions */
#define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
__CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK807
#define __CK807 (0x07U) /*!< CK807 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK807_H_DEPENDANT
#define __CORE_CK807_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK807_REV
#define __CK807_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK807 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK807 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_ck807.h | C | apache-2.0 | 33,217 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck810.h
* @brief CSI CK810 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK810_H_GENERIC
#define __CORE_CK810_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK810
@{
*/
/* CSI CK810 definitions */
#define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
__CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK810
#define __CK810 (0x0aU) /*!< CK810 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK810_H_DEPENDANT
#define __CORE_CK810_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK810_REV
#define __CK810_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK810 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK810 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
#define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
#define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_ck810.h | C | apache-2.0 | 33,885 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_rv32.h
* @brief CSI RV32 Core Peripheral Access Layer Header File
* @version V1.0
* @date 01. Sep 2018
******************************************************************************/
#ifndef __CORE_RV32_H_GENERIC
#define __CORE_RV32_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup RV32
@{
*/
#ifndef __RV32
#define __RV32 (0x01U)
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_RV32_H_DEPENDANT
#define __CORE_RV32_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __RV32_REV
#define __RV32_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_rv32_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK802 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core CLIC Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC)
\brief Type definitions for the CLIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */
__IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */
__IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */
__IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */
} CLIC_INT_Control;
typedef struct {
__IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */
__IM uint32_t CLICINFO;
__IOM uint32_t MINTTHRESH;
uint32_t RESERVED[1021];
CLIC_INT_Control CLICINT[4096];
} CLIC_Type;
#define CLIC_INFO_CLICINTCTLBITS_Pos 21U
#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos)
#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */
#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */
#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */
#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */
#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */
#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */
#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */
#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */
#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */
#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */
#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */
#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */
#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */
#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */
/*@} end of group CSI_CLIC */
/**
\ingroup CSI_core_register
\defgroup CSI_PMP Physical Memory Protection (PMP)
\brief Type definitions for the PMP Registers
@{
*/
#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
typedef enum {
REGION_SIZE_4B = -1,
REGION_SIZE_8B = 0,
REGION_SIZE_16B = 1,
REGION_SIZE_32B = 2,
REGION_SIZE_64B = 3,
REGION_SIZE_128B = 4,
REGION_SIZE_256B = 5,
REGION_SIZE_512B = 6,
REGION_SIZE_1KB = 7,
REGION_SIZE_2KB = 8,
REGION_SIZE_4KB = 9,
REGION_SIZE_8KB = 10,
REGION_SIZE_16KB = 11,
REGION_SIZE_32KB = 12,
REGION_SIZE_64KB = 13,
REGION_SIZE_128KB = 14,
REGION_SIZE_256KB = 15,
REGION_SIZE_512KB = 16,
REGION_SIZE_1MB = 17,
REGION_SIZE_2MB = 18,
REGION_SIZE_4MB = 19,
REGION_SIZE_8MB = 20,
REGION_SIZE_16MB = 21,
REGION_SIZE_32MB = 22,
REGION_SIZE_64MB = 23,
REGION_SIZE_128MB = 24,
REGION_SIZE_256MB = 25,
REGION_SIZE_512MB = 26,
REGION_SIZE_1GB = 27,
REGION_SIZE_2GB = 28,
REGION_SIZE_4GB = 29,
REGION_SIZE_8GB = 30,
REGION_SIZE_16GB = 31
} region_size_e;
typedef enum {
ADDRESS_MATCHING_TOR = 1,
ADDRESS_MATCHING_NAPOT = 3
} address_matching_e;
typedef struct {
uint32_t r: 1; /* readable enable */
uint32_t w: 1; /* writeable enable */
uint32_t x: 1; /* execable enable */
address_matching_e a: 2; /* address matching mode */
uint32_t reserved: 2; /* reserved */
uint32_t l: 1; /* lock enable */
} mpu_region_attr_t;
/*@} end of group CSI_PMP */
/* CACHE Register Definitions */
#define CACHE_MHCR_L0BTB_Pos 12U /*!< CACHE MHCR: L0BTB Position */
#define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */
#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */
#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */
#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */
#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */
#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */
#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */
#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */
#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */
#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */
#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */
#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */
#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */
#define CACHE_INV_ADDR_Pos 5U
#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos)
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM unsigned long long MTIMECMP; /*!< Offset: 0x000 (R/W) Timer compare register */
uint32_t RESERVED[8187];
__IM unsigned long long MTIME; /*!< Offset: 0x7FFC (R) Timer current register */
} CORET_Type;
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK802 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (0xE4004000UL) /*!< CORET Base Address */
#define CLIC_BASE (0xE0000000UL) /*!< CLIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk;
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk;
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk);
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk);
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk;
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk;
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits);
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
vectors[IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
return (uint32_t)vectors[IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ########################## PMP functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_PMPFunctions PMP Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
uint8_t pmpxcfg = 0;
uint32_t addr = 0;
if (idx > 15) {
return;
}
if (!enable) {
attr.a = 0;
}
if (attr.a == ADDRESS_MATCHING_TOR) {
addr = base_addr >> 2;
} else {
if (size == REGION_SIZE_4B) {
addr = base_addr >> 2;
attr.a = 2;
} else {
addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1);
}
}
__set_PMPADDRx(idx, addr);
pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) |
(attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) |
(attr.l << PMP_PMPCFG_L_Pos);
__set_PMPxCFG(idx, pmpxcfg);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
__set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk));
}
/*@} end of CSI_Core_PMPFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
CORET->MTIMECMP = CORET->MTIME + ticks;
return (0UL);
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->MTIMECMP & 0xFFFFFFFF;
}
/**
\brief get CORE timer reload high value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_loadh(void)
{
return (CORET->MTIMECMP >> 32) & 0xFFFFFFFF;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->MTIME & 0xFFFFFFFF;
}
/**
\brief get CORE timer counter high value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_valueh(void)
{
return (CORET->MTIME >> 32) & 0xFFFFFFFF;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
__ICACHE_IALL();
cache = __get_MHCR();
cache |= CACHE_MHCR_IE_Msk;
__set_MHCR(cache);
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache |= ~CACHE_MHCR_IE_Msk; /* disable icache */
__set_MHCR(cache);
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all dcache */
cache = __get_MHCR();
cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */
__set_MHCR(cache);
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
__set_MHCR(cache);
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CALL(); /* clean all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CIALL(); /* clean and inv all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t)addr;
int32_t linesize = 32;
__DSB();
while (op_size > 0) {
__DCACHE_IPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk;
int32_t linesize = 32;
__DSB();
while (op_size > 0) {
__DCACHE_CPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t) addr;
int32_t linesize = 32;
__DSB();
while (op_size > 0) {
__DCACHE_CIPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
;
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return 0;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return 0;
}
/*@} end of CSI_Core_CacheFunctions */
/*@} end of CSI_core_DebugFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_MSTATUS();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_MSTATUS(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_rv32.h | C | apache-2.0 | 34,050 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_rv32.h
* @brief CSI RV32 Core Peripheral Access Layer Header File
* @version V1.0
* @date 01. Sep 2018
******************************************************************************/
#ifndef __CORE_RV32_H_GENERIC
#define __CORE_RV32_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup RV32
@{
*/
#ifndef __RV32
#define __RV32 (0x01U)
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_RV32_H_DEPENDANT
#define __CORE_RV32_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __RV32_REV
#define __RV32_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_rv32_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK802 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core CLIC Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC)
\brief Type definitions for the CLIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint8_t INTIP[1024U]; /*!< Offset: 0x000 (R/W) Interrupt set pending register */
__IOM uint8_t INTIE[1024U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
__IOM uint8_t INTCFG[768U]; /*!< Offset: 0x000 (R/W) Interrupt configure register */
__IOM uint8_t CLICCFG; /*!< Offset: 0x000 (R/W) CLIC configure register */
} CLIC_Type;
#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */
#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */
#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */
#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */
#define CLIC_INTCFG_PRIO_Pos 6U /*!< CLIC INTCFG: INTCFG Position */
#define CLIC_INTCFG_PRIO_Msk (0x1UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */
#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */
#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */
#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */
#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */
/*@} end of group CSI_CLIC */
/**
\ingroup CSI_core_register
\defgroup CSI_PMP Physical Memory Protection (PMP)
\brief Type definitions for the PMP Registers
@{
*/
#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
typedef enum {
REGION_SIZE_4B = -1,
REGION_SIZE_8B = 0,
REGION_SIZE_16B = 1,
REGION_SIZE_32B = 2,
REGION_SIZE_64B = 3,
REGION_SIZE_128B = 4,
REGION_SIZE_256B = 5,
REGION_SIZE_512B = 6,
REGION_SIZE_1KB = 7,
REGION_SIZE_2KB = 8,
REGION_SIZE_4KB = 9,
REGION_SIZE_8KB = 10,
REGION_SIZE_16KB = 11,
REGION_SIZE_32KB = 12,
REGION_SIZE_64KB = 13,
REGION_SIZE_128KB = 14,
REGION_SIZE_256KB = 15,
REGION_SIZE_512KB = 16,
REGION_SIZE_1MB = 17,
REGION_SIZE_2MB = 18,
REGION_SIZE_4MB = 19,
REGION_SIZE_8MB = 20,
REGION_SIZE_16MB = 21,
REGION_SIZE_32MB = 22,
REGION_SIZE_64MB = 23,
REGION_SIZE_128MB = 24,
REGION_SIZE_256MB = 25,
REGION_SIZE_512MB = 26,
REGION_SIZE_1GB = 27,
REGION_SIZE_2GB = 28,
REGION_SIZE_4GB = 29,
REGION_SIZE_8GB = 30,
REGION_SIZE_16GB = 31
} region_size_e;
typedef enum {
ADDRESS_MATCHING_TOR = 1,
ADDRESS_MATCHING_NAPOT = 3
} address_matching_e;
typedef struct {
uint32_t r: 1; /* readable enable */
uint32_t w: 1; /* writeable enable */
uint32_t x: 1; /* execable enable */
address_matching_e a: 2; /* address matching mode */
uint32_t reserved: 2; /* reserved */
uint32_t l: 1; /* lock enable */
} mpu_region_attr_t;
/*@} end of group CSI_PMP */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_WCFIG_Pos 3U /*!< CACHE CER: WCFIG Position */
#define CACHE_CER_WCFIG_Msk (0x1UL << CACHE_CER_WCFIG_Pos) /*!< CACHE CER: WCFIG Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_CS_Pos 31U /*!< CACHE CER: CS Position */
#define CACHE_CER_CS_Msk (0x1UL << CACHE_CER_CS_Pos) /*!< CACHE CER: CS Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK802 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define CLIC_BASE (TCIP_BASE + 0x0100UL) /*!< CLIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
CLIC->INTIE[IRQn] |= CLIC_INTIE_IE_Msk;
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
CLIC->INTIE[IRQn] &= ~CLIC_INTIE_IE_Msk;
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
CLIC->INTIE[IRQn] |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
CLIC->INTIE[IRQn] &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->INTIE[IRQn] & CLIC_INTIE_IE_Msk);
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->INTIP[IRQn] & CLIC_INTIP_IP_Msk);
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
CLIC->INTIP[IRQn] |= CLIC_INTIP_IP_Msk;
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
CLIC->INTIP[IRQn] &= ~CLIC_INTIP_IP_Msk;
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
CLIC->INTCFG[IRQn] = (CLIC->INTCFG[IRQn] & (~CLIC_INTCFG_PRIO_Msk)) | (priority << CLIC_INTCFG_PRIO_Pos);
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return CLIC->INTCFG[IRQn] >> CLIC_INTCFG_PRIO_Pos;
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ########################## PMP functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_PMPFunctions PMP Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
uint8_t pmpxcfg = 0;
uint32_t addr = 0;
if (idx > 15) {
return;
}
if (!enable) {
attr.a = 0;
}
if (attr.a == ADDRESS_MATCHING_TOR) {
addr = base_addr >> 2;
} else {
if (size == REGION_SIZE_4B) {
addr = base_addr >> 2;
attr.a = 2;
} else {
addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1);
}
}
__set_PMPADDRx(idx, addr);
pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) |
(attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) |
(attr.l << PMP_PMPCFG_L_Pos);
__set_PMPxCFG(idx, pmpxcfg);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
__set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk));
}
/*@} end of CSI_Core_PMPFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/*@} end of CSI_core_DebugFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_MSTATUS();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_MSTATUS(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/core_rv32_old.h | C | apache-2.0 | 42,882 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_gcc.h
* @brief CSI Header File for GCC.
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef _CSI_GCC_H_
#define _CSI_GCC_H_
#include <stdlib.h>
#include <stdint.h>
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
#ifndef __ALWAYS_STATIC_INLINE
#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by setting the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("psrset ie");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by clearing the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("psrclr ie");
}
/**
\brief Get PSR
\details Returns the content of the PSR Register.
\return PSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PSR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, psr" : "=r"(result));
return (result);
}
/**
\brief Set PSR
\details Writes the given value to the PSR Register.
\param [in] psr PSR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PSR(uint32_t psr)
{
__ASM volatile("mtcr %0, psr" : : "r"(psr));
}
/**
\brief Get SP
\details Returns the content of the SP Register.
\return SP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("mov %0, sp" : "=r"(result));
return (result);
}
/**
\brief Set SP
\details Writes the given value to the SP Register.
\param [in] sp SP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp)
{
__ASM volatile("mov sp, %0" : : "r"(sp): "sp");
}
/**
\brief Get Int SP
\details Returns the content of the Int SP Register.
\return Int SP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_Int_SP(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<15, 1>" : "=r"(result));
return (result);
}
/**
\brief Set Int SP
\details Writes the given value to the Int SP Register.
\param [in] sp Int SP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_Int_SP(uint32_t sp)
{
__ASM volatile("mtcr %0, cr<15, 1>" : : "r"(sp));
}
/**
\brief Get VBR Register
\details Returns the content of the VBR Register.
\return VBR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_VBR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, vbr" : "=r"(result));
return (result);
}
/**
\brief Set VBR
\details Writes the given value to the VBR Register.
\param [in] vbr VBR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_VBR(uint32_t vbr)
{
__ASM volatile("mtcr %0, vbr" : : "r"(vbr));
}
/**
\brief Get EPC Register
\details Returns the content of the EPC Register.
\return EPC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_EPC(void)
{
uint32_t result;
__ASM volatile("mfcr %0, epc" : "=r"(result));
return (result);
}
/**
\brief Set EPC
\details Writes the given value to the EPC Register.
\param [in] epc EPC Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_EPC(uint32_t epc)
{
__ASM volatile("mtcr %0, epc" : : "r"(epc));
}
/**
\brief Get EPSR
\details Returns the content of the EPSR Register.
\return EPSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_EPSR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, epsr" : "=r"(result));
return (result);
}
/**
\brief Set EPSR
\details Writes the given value to the EPSR Register.
\param [in] epsr EPSR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_EPSR(uint32_t epsr)
{
__ASM volatile("mtcr %0, epsr" : : "r"(epsr));
}
/**
\brief Get CPUID Register
\details Returns the content of the CPUID Register.
\return CPUID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CPUID(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr13" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<13, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Get CCR
\details Returns the current value of the CCR.
\return CCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CCR(void)
{
register uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr18\n" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<18, 0>\n" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CCR
\details Assigns the given value to the CCR.
\param [in] ccr CCR value to set
*/
__ALWAYS_STATIC_INLINE void __set_CCR(uint32_t ccr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr18\n" : : "r"(ccr));
#else
__ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr));
#endif
}
/**
\brief Get CCR2
\details Returns the current value of the CCR2.
\return CCR2 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CCR2(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<31, 0>\n" : "=r"(result));
return (result);
}
/**
\brief Set CCR2
\details Assigns the given value to the CCR2.
\param [in] ccr2 CCR2 value to set
*/
__ALWAYS_STATIC_INLINE void __set_CCR2(uint32_t ccr2)
{
__ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(ccr2));
}
/**
\brief Get DCSR
\details Returns the content of the DCSR Register.
\return DCSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_DCSR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr14" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<14, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set DCSR
\details Writes the given value to the DCSR Register.
\param [in] dcsr DCSR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_DCSR(uint32_t dcsr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr14" : : "r"(dcsr));
#else
__ASM volatile("mtcr %0, cr<14, 0>" : : "r"(dcsr));
#endif
}
/**
\brief Get CFR
\details Returns the content of the CFR Register.
\return CFR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CFR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr17" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<17, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CFR
\details Writes the given value to the CFR Register.
\param [in] cfr CFR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_CFR(uint32_t cfr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr17" : : "r"(cfr));
#else
__ASM volatile("mtcr %0, cr<17, 0>" : : "r"(cfr));
#endif
}
/**
\brief Get CIR
\details Returns the content of the CIR Register.
\return CIR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CIR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr22" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<22, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CIR
\details Writes the given value to the CIR Register.
\param [in] cir CIR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_CIR(uint32_t cir)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr22" : : "r"(cir));
#else
__ASM volatile("mtcr %0, cr<22, 0>" : : "r"(cir));
#endif
}
/**
\brief Get ERRLC
\details Returns the current value of the ERRLC.
\return ERRLC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRLC(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<6, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRLC
\details Assigns the given value to the ERRLC.
\param [in] errlc ERRLC value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRLC(uint32_t errlc)
{
__ASM volatile("mtcr %0, cr<6, 1>\n" : : "r"(errlc));
}
/**
\brief Get ERRADDR
\details Returns the current value of the ERRADDR.
\return ERRADDR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRADDR(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<7, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRADDR
\details Assigns the given value to the ERRADDR.
\param [in] erraddr ERRADDR value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRADDR(uint32_t erraddr)
{
__ASM volatile("mtcr %0, cr<7, 1>\n" : : "r"(erraddr));
}
/**
\brief Get ERRSTS
\details Returns the current value of the ERRSTS.
\return ERRSTS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRSTS(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<8, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRSTS
\details Assigns the given value to the ERRSTS.
\param [in] errsts ERRSTS value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRSTS(uint32_t errsts)
{
__ASM volatile("mtcr %0, cr<8, 1>\n" : : "r"(errsts));
}
/**
\brief Get ERRINJCR
\details Returns the current value of the ERRINJCR.
\return ERRINJCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCR(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<9, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRINJCR
\details Assigns the given value to the ERRINJCR.
\param [in] errinjcr ERRINJCR value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRINJCR(uint32_t errinjcr)
{
__ASM volatile("mtcr %0, cr<9, 1>\n" : : "r"(errinjcr));
}
/**
\brief Get ERRINJCNT
\details Returns the current value of the ERRINJCNT.
\return ERRINJCNT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCNT(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<10, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRINJCNT
\details Assigns the given value to the ERRINJCNT.
\param [in] errinjcnt ERRINJCNT value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRJCNT(uint32_t errinjcnt)
{
__ASM volatile("mtcr %0, cr<10, 1>\n" : : "r"(errinjcnt));
}
/**
\brief Get ITCMCR
\details Returns the content of the ITCMCR Register.
\return ITCMCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ITCMCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<22, 1>" : "=r"(result));
return (result);
}
/**
\brief Set ITCMCR
\details Writes the given value to the ITCMCR Register.
\param [in] itcmcr ITCMCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_ITCMCR(uint32_t itcmcr)
{
__ASM volatile("mtcr %0, cr<22, 1>" : : "r"(itcmcr));
}
/**
\brief Get DTCMCR
\details Returns the content of the DTCMCR Register.
\return DTCMCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_DTCMCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<23, 1>" : "=r"(result));
return (result);
}
/**
\brief Set DTCMCR
\details Writes the given value to the DTCMCR Register.
\param [in] dtcmcr DTCMCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_DTCMCR(uint32_t dtcmcr)
{
__ASM volatile("mtcr %0, cr<23, 1>" : : "r"(dtcmcr));
}
/**
\brief Get CINDEX
\details Returns the current value of the CINDEX.
\return CINDEX Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CINDEX(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<26, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set CINDEX
\details Assigns the given value to the CINDEX.
\param [in] cindex CINDEX value to set
*/
__ALWAYS_STATIC_INLINE void __set_CINDEX(uint32_t cindex)
{
__ASM volatile("mtcr %0, cr<26, 1>\n" : : "r"(cindex));
}
/**
\brief Get CDATAx
\details Returns the current value of the CDATAx.
\return CDATAx Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CDATA0(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<27, 1>\n" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_CDATA1(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<28, 1>\n" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_CDATA2(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<29, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set CDATAx
\details Assigns the given value to the CDATAx.
\param [in] cdata CDATAx value to set
*/
__ALWAYS_STATIC_INLINE void __set_CDATA0(uint32_t cdata)
{
__ASM volatile("mtcr %0, cr<27, 1>\n" : : "r"(cdata));
}
__ALWAYS_STATIC_INLINE void __set_CDATA1(uint32_t cdata)
{
__ASM volatile("mtcr %0, cr<28, 1>\n" : : "r"(cdata));
}
__ALWAYS_STATIC_INLINE void __set_CDATA2(uint32_t cdata)
{
__ASM volatile("mtcr %0, cr<29, 1>\n" : : "r"(cdata));
}
/**
\brief Get CINS
\details Returns the current value of the CINS.
\return CINS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CINS(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<31, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set CINS
\details Assigns the given value to the CINS.
\param [in] cins CINS value to set
*/
__ALWAYS_STATIC_INLINE void __set_CINS(uint32_t cins)
{
__ASM volatile("mtcr %0, cr<31, 1>\n" : : "r"(cins));
}
/**
\brief Get CAPR
\details Returns the current value of the CAPR.
\return CAPR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CAPR(void)
{
register uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr19\n" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<19, 0>\n" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CAPR
\details Assigns the given value to the CAPR.
\param [in] capr CAPR value to set
*/
__ALWAYS_STATIC_INLINE void __set_CAPR(uint32_t capr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr19\n" : : "r"(capr));
#else
__ASM volatile("mtcr %0, cr<19, 0>\n" : : "r"(capr));
#endif
}
/**
\brief Get CAPR1
\details Returns the current value of the CAPR1.
\return CAPR1 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CAPR1(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<16, 0>\n" : "=r"(result));
return (result);
}
/**
\brief Set CAPR1
\details Assigns the given value to the CAPR1.
\param [in] capr1 CAPR1 value to set
*/
__ALWAYS_STATIC_INLINE void __set_CAPR1(uint32_t capr1)
{
__ASM volatile("mtcr %0, cr<16, 0>\n" : : "r"(capr1));
}
/**
\brief Set PACR
\details Assigns the given value to the PACR.
\param [in] pacr PACR value to set
*/
__ALWAYS_STATIC_INLINE void __set_PACR(uint32_t pacr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr20\n" : : "r"(pacr));
#else
__ASM volatile("mtcr %0, cr<20, 0>\n" : : "r"(pacr));
#endif
}
/**
\brief Get PACR
\details Returns the current value of PACR.
\return PACR value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PACR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr20" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<20, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set PRSR
\details Assigns the given value to the PRSR.
\param [in] prsr PRSR value to set
*/
__ALWAYS_STATIC_INLINE void __set_PRSR(uint32_t prsr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr21\n" : : "r"(prsr));
#else
__ASM volatile("mtcr %0, cr<21, 0>\n" : : "r"(prsr));
#endif
}
/**
\brief Get PRSR
\details Returns the current value of PRSR.
\return PRSR value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PRSR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr21" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<21, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set ATTR0
\details Assigns the given value to the ATTR0.
\param [in] attr0 ATTR0 value to set
*/
__ALWAYS_STATIC_INLINE void __set_ATTR0(uint32_t attr0)
{
__ASM volatile("mtcr %0, cr<26, 0>\n" : : "r"(attr0));
}
/**
\brief Get ATTR0
\details Returns the current value of ATTR0.
\return ATTR0 value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ATTR0(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<26, 0>" : "=r"(result));
return (result);
}
/**
\brief Set ATTR1
\details Assigns the given value to the ATTR1.
\param [in] attr0 ATTR1 value to set
*/
__ALWAYS_STATIC_INLINE void __set_ATTR1(uint32_t attr1)
{
__ASM volatile("mtcr %0, cr<27, 0>\n" : : "r"(attr1));
}
/**
\brief Get ATTR1
\details Returns the current value of ATTR1.
\return ATTR1 value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ATTR1(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<27, 0>" : "=r"(result));
return (result);
}
/**
\brief Get user sp
\details Returns the current value of user r14.
\return UR14 value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_UR14(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mov %0, sp" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<14, 1>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set UR14
\details Assigns the given value to the UR14.
\param [in] ur14 UR14 value to set
*/
__ALWAYS_STATIC_INLINE void __set_UR14(uint32_t ur14)
{
#ifdef __CK610
__ASM volatile("mov sp, %0" : "=r"(ur14));
#else
__ASM volatile("mtcr %0, cr<14, 1>\n" : : "r"(ur14));
#endif
}
/**
\brief Get CHR Register
\details Returns the content of the CHR Register.
\return CHR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CHR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<31, 0>\n" :"=r"(result));
return (result);
}
/**
\brief Set CHR
\details Assigns the given value to the CHR.
\param [in] chr CHR value to set
*/
__ALWAYS_STATIC_INLINE void __set_CHR(uint32_t chr)
{
__ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(chr));
}
/**
\brief Get HINT
\details Returns the content of the HINT Register.
\return HINT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_HINT(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr<30, 0>" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<31, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set HINT
\details Writes the given value to the HINT Register.
\param [in] hint HINT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_HINT(uint32_t hint)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr<30, 0>" : "=r"(hint));
#else
__ASM volatile("mtcr %0, cr<31, 0>" : : "r"(hint));
#endif
}
/**
\brief Get MIR
\details Returns the content of the MIR Register.
\return MIR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr0" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<0, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MIR
\details Writes the given value to the MIR Register.
\param [in] mir MIR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MIR(uint32_t mir)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr0" : : "b"(mir));
#else
__ASM volatile("mtcr %0, cr<0, 15>" : : "r"(mir));
#endif
}
/**
\brief Get MEL0
\details Returns the content of the MEL0 Register.
\return MEL0 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEL0(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr2" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<2, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MEL0
\details Writes the given value to the MEL0 Register.
\param [in] mel0 MEL0 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEL0(uint32_t mel0)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr2" : : "b"(mel0));
#else
__ASM volatile("mtcr %0, cr<2, 15>" : : "r"(mel0));
#endif
}
/**
\brief Get MEL1
\details Returns the content of the MEL1 Register.
\return MEL1 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEL1(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr3" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<3, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MEL1
\details Writes the given value to the MEL1 Register.
\param [in] mel1 MEL1 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEL1(uint32_t mel1)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr3" : : "b"(mel1));
#else
__ASM volatile("mtcr %0, cr<3, 15>" : : "r"(mel1));
#endif
}
/**
\brief Get MEH
\details Returns the content of the MEH Register.
\return MEH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEH(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr4" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<4, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MEH
\details Writes the given value to the MEH Register.
\param [in] meh MEH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEH(uint32_t meh)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr4" : : "b"(meh));
#else
__ASM volatile("mtcr %0, cr<4, 15>" : : "r"(meh));
#endif
}
/**
\brief Get MPR
\details Returns the content of the MPR Register.
\return MPR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MPR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr6" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<6, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MPR
\details Writes the given value to the MPR Register.
\param [in] mpr MPR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MPR(uint32_t mpr)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr6" : : "b"(mpr));
#else
__ASM volatile("mtcr %0, cr<6, 15>" : : "r"(mpr));
#endif
}
/**
\brief Get MCIR
\details Returns the content of the MCIR Register.
\return MCIR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCIR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr8" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<8, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MCIR
\details Writes the given value to the MCIR Register.
\param [in] mcir MCIR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MCIR(uint32_t mcir)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr8" : : "b"(mcir));
#else
__ASM volatile("mtcr %0, cr<8, 15>" : : "r"(mcir));
#endif
}
/**
\brief Get MPGD
\details Returns the content of the MPGD Register.
\return MPGD Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MPGD(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr29" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<29, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MPGD
\details Writes the given value to the MPGD Register.
\param [in] mpgd MPGD Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MPGD(uint32_t mpgd)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr29" : : "b"(mpgd));
#else
__ASM volatile("mtcr %0, cr<29, 15>" : : "r"(mpgd));
#endif
}
/**
\brief Get MSA0
\details Returns the content of the MSA0 Register.
\return MSA0 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSA0(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr30" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<30, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MSA0
\details Writes the given value to the MSA0 Register.
\param [in] msa0 MSA0 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSA0(uint32_t msa0)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr30" : : "b"(msa0));
#else
__ASM volatile("mtcr %0, cr<30, 15>" : : "r"(msa0));
#endif
}
/**
\brief Get MSA1
\details Returns the content of the MSA1 Register.
\return MSA1 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSA1(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr31" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<31, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MSA1
\details Writes the given value to the MSA1 Register.
\param [in] msa1 MSA1 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSA1(uint32_t msa1)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr31" : : "b"(msa1));
#else
__ASM volatile("mtcr %0, cr<31, 15>" : : "r"(msa1));
#endif
}
/**
\brief Enable interrupts and exceptions
\details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_excp_irq(void)
{
__ASM volatile("psrset ee, ie");
}
/**
\brief Disable interrupts and exceptions
\details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_excp_irq(void)
{
__ASM volatile("psrclr ee, ie");
}
/**
\brief Get GSR
\details Returns the content of the GSR Register.
\return GSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_GSR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr12" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<12, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Get GCR
\details Returns the content of the GCR Register.
\return GCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_GCR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr11" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<11, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set GCR
\details Writes the given value to the GCR Register.
\param [in] gcr GCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_GCR(uint32_t gcr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr11" : : "r"(gcr));
#else
__ASM volatile("mtcr %0, cr<11, 0>" : : "r"(gcr));
#endif
}
/**
\brief Get WSSR
\details Returns the content of the WSSR Register, must be accessed in TEE
\return WSSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_WSSR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<0, 3>" : "=r"(result));
return (result);
}
/**
\brief Get WRCR
\details Returns the content of the WRCR Register, must be accessed in TEE
\return WRCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_WRCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<1, 3>" : "=r"(result));
return (result);
}
/**
\brief Set WRCR
\details Writes the given value to the WRCR Register, must be accessed in TEE
\param [in] wrcr WRCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_WRCR(uint32_t wrcr)
{
__ASM volatile("mtcr %0, cr<1, 3>" : : "r"(wrcr));
}
/**
\brief Get DCR
\details Returns the content of the DCR Register, must be accessed in TEE
\return DCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_DCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<8, 3>" : "=r"(result));
return (result);
}
/**
\brief Set DCR
\details Writes the given value to the DCR Register, must be accessed in TEE
\param [in] dcr DCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_DCR(uint32_t dcr)
{
__ASM volatile("mtcr %0, cr<8, 3>" : : "r"(dcr));
}
/**
\brief Get PCR
\details Returns the content of the PCR Register, must be accessed in TEE
\return PCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<9, 3>" : "=r"(result));
return (result);
}
/**
\brief Set PCR
\details Writes the given value to the PCR Register, must be accessed in TEE
\param [in] pcr PCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PCR(uint32_t pcr)
{
__ASM volatile("mtcr %0, cr<9, 3>" : : "r"(pcr));
}
/**
\brief Get EBR
\details Returns the content of the EBR Register.
\return EBR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_EBR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<1, 1>" : "=r"(result));
return (result);
}
/**
\brief Set EBR
\details Writes the given value to the EBR Register.
\param [in] ebr EBR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_EBR(uint32_t ebr)
{
__ASM volatile("mtcr %0, cr<1, 1>" : : "r"(ebr));
}
/*@} end of CSI_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CSI_Core_InstructionInterface CSI Core Instruction Interface
Access to dedicated instructions
@{
*/
#define __CSI_GCC_OUT_REG(r) "=r" (r)
#define __CSI_GCC_USE_REG(r) "r" (r)
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__ALWAYS_STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
__ALWAYS_STATIC_INLINE void __WFI(void)
{
__ASM volatile("wait");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __WAIT(void)
{
__ASM volatile("wait");
}
/**
\brief Doze For Interrupt
\details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __DOZE(void)
{
__ASM volatile("doze");
}
/**
\brief Stop For Interrupt
\details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __STOP(void)
{
__ASM volatile("stop");
}
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__ALWAYS_STATIC_INLINE void __ISB(void)
{
__ASM volatile("sync"::: "memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("sync"::: "memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__ALWAYS_STATIC_INLINE void __DMB(void)
{
__ASM volatile("sync"::: "memory");
}
/**
\brief Search from the highest bit that the very first bit which's value is 1.
\param [in] value Value to bit search.
\return if the highest bit' value is 1, return 0, and if lowest bit's value is 1, return 31, otherwise return 32.
*/
#if !defined(__CK610) || !(__CK80X == 1)
__ALWAYS_STATIC_INLINE uint32_t __FF0(uint32_t value)
{
uint32_t ret;
__ASM volatile("ff0 %0, %1" : "=r"(ret) : "r"(value));
return ret;
}
#endif
/**
\brief Search from the highest bit that the very first bit which's value is 0.
\param [in] value Value to bit search.
\return if the highest bit' value is 0, return 0, and if lowest bit's value is 0, return 31, otherwise return 32.
*/
#if !(__CK80X == 1)
__ALWAYS_STATIC_INLINE uint32_t __FF1(uint32_t value)
{
uint32_t ret;
#if !defined (__CK610)
__ASM volatile("ff1 %0, %1" : "=r"(ret) : "r"(value));
#else
ret = value;
__ASM volatile("ff1 %0" : "=r"(ret):);
#endif
return ret;
}
#endif
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value)
{
return __builtin_bswap32(value);
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
#if (__CK80X >= 2)
__ASM volatile("revh %0, %1" : __CSI_GCC_OUT_REG(result) : __CSI_GCC_USE_REG(value));
#else
result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) |
((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8);
#endif
return (result);
}
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value)
{
return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8));
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
*/
__ALWAYS_STATIC_INLINE void __BKPT(void)
{
__ASM volatile("bkpt");
}
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if (__CK80X >= 0x03U)
__ASM volatile("brev %0, %1" : "=r"(result) : "r"(value));
#else
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return (result);
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
/**
\details This function saturates a signed value.
\param [in] x Value to be saturated
\param [in] y Bit position to saturate to [1..32]
\return Saturated value.
*/
__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
{
int32_t posMax, negMin;
uint32_t i;
posMax = 1;
for (i = 0; i < (y - 1); i++) {
posMax = posMax * 2;
}
if (x > 0) {
posMax = (posMax - 1);
if (x > posMax) {
x = posMax;
}
// x &= (posMax * 2 + 1);
} else {
negMin = -posMax;
if (x < negMin) {
x = negMin;
}
// x &= (posMax * 2 - 1);
}
return (x);
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Unsigned Saturate for internal use
\details Saturates an unsigned value, should not call directly.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Rotate Right with Extend
\details This function moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\note carry input will always 0.
\param [in] op1 Value to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1)
{
#if (__CK80X >= 2)
uint32_t res = 0;
__ASM volatile("bgeni t0, 31\n\t"
"lsri %0, 1\n\t"
"movt %1, t0\n\t"
"or %1, %1, %0\n\t"
: "=r"(op1), "=r"(res): "0"(op1), "1"(res): "t0");
return res;
#else
uint32_t res = 0;
__ASM volatile("movi r7, 0\n\t"
"bseti r7, 31\n\t"
"lsri %0, 1\n\t"
"bf 1f\n\t"
"mov %1, r7\n\t"
"1:\n\t"
"or %1, %1, %0\n\t"
: "=r"(op1), "=r"(res): "0"(op1), "1"(res): "r7");
return res;
#endif
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] addr Pointer to location
\return value of type uint8_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
//#warning "__LDRBT"
__ASM volatile("ldb %0, (%1, 0)" : "=r"(result) : "r"(addr));
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] addr Pointer to location
\return value of type uint16_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
//#warning "__LDRHT"
__ASM volatile("ldh %0, (%1, 0)" : "=r"(result) : "r"(addr));
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] addr Pointer to location
\return value of type uint32_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
//#warning "__LDRT"
__ASM volatile("ldw %0, (%1, 0)" : "=r"(result) : "r"(addr));
return (result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
//#warning "__STRBT"
__ASM volatile("stb %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
//#warning "__STRHT"
__ASM volatile("sth %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
//#warning "__STRT"
__ASM volatile("stw %1, (%0, 0)" :: "r"(addr), "r"(value) : "memory");
}
/*@}*/ /* end of group CSI_Core_InstructionInterface */
/* ########################## FPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type, always 0.
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__ALWAYS_STATIC_INLINE uint32_t __get_FPUType(void)
{
//FIXME:
return 0;
}
/*@} end of CSI_Core_FpuFunctions */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics
Access to dedicated SIMD instructions \n
Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
@{
*/
/**
\brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16]
of val2 levitated with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be left-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for left-shifting val2. Value range [0..31].
\return the combination of halfwords.
\remark
res[15:0] = val1[15:0] \n
res[31:16] = val2[31:16] << val3
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000));
}
/**
\brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0]
of val2 right-shifted with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be right-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for right-shifting val2. Value range [1..32].
\return the combination of halfwords.
\remark
res[15:0] = val2[15:0] >> val3 \n
res[31:16] = val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF));
}
/**
\brief Dual 16-bit signed saturate.
\details This function saturates a signed value.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:\n
the signed saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the signed saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF;
s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturate.
\details This function enables you to saturate two signed 16-bit values to a selected unsigned range.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the saturation of the two signed 16-bit values, as non-negative values:
the saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF;
s = __IUSAT(((x) >> 16), y) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit saturating addition.
\details This function enables you to perform four 8-bit integer additions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating addition.
\details This function enables you to perform four unsigned 8-bit integer additions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed addition.
\details This function performs four 8-bit signed integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition.
\details This function performs four unsigned 8-bit integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit saturating subtract.
\details This function enables you to perform four 8-bit integer subtractions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating subtraction.
\details This function enables you to perform four unsigned 8-bit integer subtractions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed subtraction.
\details This function enables you to perform four 8-bit signed integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtract.
\details This function enables you to perform four 8-bit unsigned integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences together, returning the result as a single unsigned integer.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n
The sum is returned as a single unsigned integer.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
*/
__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return (u + t + s + r);
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences to a 32-bit accumulate operand.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\param [in] sum accumulation value.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:
the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n
res[31:0] = sum[31:0] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
{
int32_t r, s, t, u;
#ifdef __cplusplus
r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#else
r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#endif
return (u + t + s + r + sum);
}
/**
\brief Dual 16-bit saturating addition.
\details This function enables you to perform two 16-bit integer arithmetic additions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition.
\details This function enables you to perform two unsigned 16-bit integer additions, saturating
the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition.
\details This function enables you to perform two 16-bit signed integer additions.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition
\details This function enables you to perform two 16-bit unsigned integer additions.
\param [in] x first two 16-bit summands for each addition.
\param [in] y second two 16-bit summands for each addition.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition with halved results.
\details This function enables you to perform two signed 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition with halved results.
\details This function enables you to perform two unsigned 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition with halved results.
\details This function enables you to perform four unsigned 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit saturating subtract.
\details This function enables you to perform two 16-bit integer subtractions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction.
\details This function enables you to perform two unsigned 16-bit integer subtractions,
saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit operands for each subtraction.
\param [in] y second two 16-bit operands for each subtraction.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction.
\details This function enables you to perform two 16-bit signed integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtract.
\details This function enables you to perform two 16-bit unsigned integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction with halved results.
\details This function enables you to perform two signed 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction with halved results.
\details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtraction with halved results.
\details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit add and subtract with exchange.
\details This function enables you to exchange the halfwords of the one operand,
then add the high halfwords and subtract the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition and subtraction with exchange.
\details This function enables you to exchange the halfwords of the second operand and
perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction,
saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit addition and subtraction with exchange.
\details It enables you to exchange the halfwords of the second operand, add the high halfwords
and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with exchange.
\details This function enables you to exchange the two halfwords of the second operand,
add the high halfwords and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition and subtraction with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one
signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
add the high halfwords and subtract the low halfwords, halving the results.
\param [in] x first operand for the subtraction in the low halfword, and
the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword, and
the second operand for the addition in the low halfword.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit subtract and add with exchange.
\details This function enables you to exchange the halfwords of one operand,
then subtract the high halfwords and add the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction and addition with exchange.
\details This function enables you to exchange the halfwords of the second operand and perform
one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating
the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit unsigned subtract and add with exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction and addition with exchange.
\details This function enables you to exchange the two halfwords of one operand and perform one
16-bit integer subtraction and one 16-bit addition.
\param [in] x first operand for the addition in the low halfword, and the first operand
for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and the second
operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit signed subtraction and addition with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one signed
16-bit integer subtraction and one signed 16-bit addition, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction and addition with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords, halving the results.
\param [in] x first operand for the addition in the low halfword, and
the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and
the second operand for the subtraction in the low halfword.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed multiply with exchange returning difference.
\details This function enables you to perform two 16-bit signed multiplications, subtracting
one of the products from the other. The halfwords of the second operand are exchanged
before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Sum of dual 16-bit signed multiply with exchange.
\details This function enables you to perform two 16-bit signed multiplications with exchanged
halfwords of the second operand, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Saturating add.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 + SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if (x + y >= x) {
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if (x + y < x) {
result = x + y;
} else {
result = 0x80000000;
}
}
return result;
}
/**
\brief Saturating subtract.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 - SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
{
int64_t tmp;
int32_t result;
tmp = (int64_t)x - (int64_t)y;
if (tmp > 0x7fffffff) {
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
tmp = -2147483647 - 1;
}
result = tmp;
return result;
}
/**
\brief Dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications,
adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications with exchanged
halfwords of the second operand, adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication with exchanged halfwords of the second
operand added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to perform two 16-bit signed multiplications, take the
difference of the products, subtracting the high halfword product from the low
halfword product, and add the difference to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit
signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with single 64-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications, adding both results
to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition.
This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
\details This function enables you to exchange the halfwords of the second operand, and perform two
signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow
is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs.
Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief dual 16-bit signed multiply subtract with 64-bit accumulate.
\details This function It enables you to perform two 16-bit signed multiplications, take the difference
of the products, subtracting the high halfword product from the low halfword product, and add the
difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the
subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not
detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
\details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications,
adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the
multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow
is not detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief 32-bit signed multiply with 32-bit truncated accumulator.
\details This function enables you to perform a signed 32-bit multiplications, adding the most
significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
\param [in] x first operand for multiplication.
\param [in] y second operand for multiplication.
\param [in] sum accumulate value.
\return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
\remark
p = val1 * val2 \n
res[31:0] = p[63:32] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum)
{
return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum);
}
/**
\brief Sum of dual 16-bit signed multiply.
\details This function enables you to perform two 16-bit signed multiplications, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual 16-bit signed multiply returning difference.
\details This function enables you to perform two 16-bit signed multiplications, taking the difference
of the products by subtracting the high halfword product from the low halfword product.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual extracted 8-bit to 16-bit signed addition.
\details This function enables you to extract two 8-bit values from the second operand (at bit positions
[7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
\param [in] x values added to the sign-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and sign-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and sign-extended prior to the addition.
\remark
res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) |
(((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000)));
}
/**
\brief Extracted 16-bit to 32-bit unsigned addition.
\details This function enables you to extract two 8-bit values from one operand, zero-extend
them to 16 bits each, and add the results to two 16-bit values from another operand.
\param [in] x values added to the zero-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and zero-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and zero-extended prior to the addition.
\remark
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) |
((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and sign extend each to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x)
{
return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) |
((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and zero-extend to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
{
return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) |
(((x << 8) >> 8) & 0xFFFF0000)));
}
#endif /* _CSI_GCC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/csi_gcc.h | C | apache-2.0 | 115,927 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_rv32_gcc.h
* @brief CSI Header File for GCC.
* @version V1.0
* @date 01. Sep 2018
******************************************************************************/
#ifndef _CSI_RV32_GCC_H_
#define _CSI_RV32_GCC_H_
#include <stdlib.h>
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
#ifndef __ALWAYS_STATIC_INLINE
#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by setting the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("csrs mstatus, 8");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by clearing the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("csrc mstatus, 8");
}
/**
\brief Get MXSTATUS
\details Returns the content of the MXSTATUS Register.
\return MXSTATUS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MXSTATUS(void)
{
uint32_t result;
__ASM volatile("csrr %0, mxstatus" : "=r"(result));
return (result);
}
/**
\brief Set MXSTATUS
\details Writes the given value to the MXSTATUS Register.
\param [in] mxstatus MXSTATUS Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MXSTATUS(uint32_t mxstatus)
{
__ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus));
}
/**
\brief Get MSTATUS
\details Returns the content of the MSTATUS Register.
\return MSTATUS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSTATUS(void)
{
uint32_t result;
__ASM volatile("csrr %0, mstatus" : "=r"(result));
return (result);
}
/**
\brief Set MSTATUS
\details Writes the given value to the MSTATUS Register.
\param [in] mstatus MSTATUS Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSTATUS(uint32_t mstatus)
{
__ASM volatile("csrw mstatus, %0" : : "r"(mstatus));
}
/**
\brief Get MHCR
\details Returns the content of the MHCR Register.
\return MHCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MHCR(void)
{
uint32_t result;
__ASM volatile("csrr %0, mhcr" : "=r"(result));
return (result);
}
/**
\brief Set MHCR
\details Writes the given value to the MHCR Register.
\param [in] mstatus MHCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr)
{
__ASM volatile("csrw mhcr, %0" : : "r"(mhcr));
}
/**
\brief Get MISA Register
\details Returns the content of the MISA Register.
\return MISA Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MISA(void)
{
uint32_t result;
__ASM volatile("csrr %0, misa" : "=r"(result));
return (result);
}
/**
\brief Set MISA
\details Writes the given value to the MISA Register.
\param [in] misa MISA Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MISA(uint32_t misa)
{
__ASM volatile("csrw misa, %0" : : "r"(misa));
}
/**
\brief Get MIE Register
\details Returns the content of the MIE Register.
\return MIE Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIE(void)
{
uint32_t result;
__ASM volatile("csrr %0, mie" : "=r"(result));
return (result);
}
/**
\brief Set MIE
\details Writes the given value to the MIE Register.
\param [in] mie MIE Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MIE(uint32_t mie)
{
__ASM volatile("csrw mie, %0" : : "r"(mie));
}
/**
\brief Get MTVEC Register
\details Returns the content of the MTVEC Register.
\return MTVEC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MTVEC(void)
{
uint32_t result;
__ASM volatile("csrr %0, mtvec" : "=r"(result));
return (result);
}
/**
\brief Set MTVEC
\details Writes the given value to the MTVEC Register.
\param [in] mtvec MTVEC Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MTVEC(uint32_t mtvec)
{
__ASM volatile("csrw mtvec, %0" : : "r"(mtvec));
}
/**
\brief Set MTVT
\details Writes the given value to the MTVT Register.
\param [in] mtvt MTVT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MTVT(uint32_t mtvt)
{
__ASM volatile("csrw mtvt, %0" : : "r"(mtvt));
}
/**
\brief Get MTVT Register
\details Returns the content of the MTVT Register.
\return MTVT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MTVT(void)
{
uint32_t result;
__ASM volatile("csrr %0, mtvt" : "=r"(result));
return (result);
}
/**
\brief Get SP
\details Returns the content of the SP Register.
\return SP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("mv %0, sp" : "=r"(result));
return (result);
}
/**
\brief Set SP
\details Writes the given value to the SP Register.
\param [in] sp SP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp)
{
__ASM volatile("mv sp, %0" : : "r"(sp): "sp");
}
/**
\brief Get MSCRATCH Register
\details Returns the content of the MSCRATCH Register.
\return MSCRATCH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSCRATCH(void)
{
uint32_t result;
__ASM volatile("csrr %0, mscratch" : "=r"(result));
return (result);
}
/**
\brief Set MSCRATCH
\details Writes the given value to the MSCRATCH Register.
\param [in] mscratch MSCRATCH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSCRATCH(uint32_t mscratch)
{
__ASM volatile("csrw mscratch, %0" : : "r"(mscratch));
}
/**
\brief Get MEPC Register
\details Returns the content of the MEPC Register.
\return MEPC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEPC(void)
{
uint32_t result;
__ASM volatile("csrr %0, mepc" : "=r"(result));
return (result);
}
/**
\brief Set MEPC
\details Writes the given value to the MEPC Register.
\param [in] mepc MEPC Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEPC(uint32_t mepc)
{
__ASM volatile("csrw mepc, %0" : : "r"(mepc));
}
/**
\brief Get MCAUSE Register
\details Returns the content of the MCAUSE Register.
\return MCAUSE Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCAUSE(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcause" : "=r"(result));
return (result);
}
/**
\brief Get MNXTI Register
\details Returns the content of the MNXTI Register.
\return MNXTI Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MNXTI(void)
{
uint32_t result;
__ASM volatile("csrr %0, mnxti" : "=r"(result));
return (result);
}
/**
\brief Set MNXTI
\details Writes the given value to the MNXTI Register.
\param [in] mnxti MNXTI Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MNXTI(uint32_t mnxti)
{
__ASM volatile("csrw mnxti, %0" : : "r"(mnxti));
}
/**
\brief Get MINTSTATUS Register
\details Returns the content of the MINTSTATUS Register.
\return MINTSTATUS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MINTSTATUS(void)
{
uint32_t result;
__ASM volatile("csrr %0, mintstatus" : "=r"(result));
return (result);
}
/**
\brief Get MTVAL Register
\details Returns the content of the MTVAL Register.
\return MTVAL Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MTVAL(void)
{
uint32_t result;
__ASM volatile("csrr %0, mtval" : "=r"(result));
return (result);
}
/**
\brief Get MIP Register
\details Returns the content of the MIP Register.
\return MIP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIP(void)
{
uint32_t result;
__ASM volatile("csrr %0, mip" : "=r"(result));
return (result);
}
/**
\brief Set MIP
\details Writes the given value to the MIP Register.
\param [in] mip MIP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MIP(uint32_t mip)
{
__ASM volatile("csrw mip, %0" : : "r"(mip));
}
/**
\brief Get MCYCLEL Register
\details Returns the content of the MCYCLEL Register.
\return MCYCLE Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLE(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcycle" : "=r"(result));
return (result);
}
/**
\brief Get MCYCLEH Register
\details Returns the content of the MCYCLEH Register.
\return MCYCLEH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLEH(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcycleh" : "=r"(result));
return (result);
}
/**
\brief Get MINSTRET Register
\details Returns the content of the MINSTRET Register.
\return MINSTRET Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRET(void)
{
uint32_t result;
__ASM volatile("csrr %0, minstret" : "=r"(result));
return (result);
}
/**
\brief Get MINSTRETH Register
\details Returns the content of the MINSTRETH Register.
\return MINSTRETH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRETH(void)
{
uint32_t result;
__ASM volatile("csrr %0, minstreth" : "=r"(result));
return (result);
}
/**
\brief Get MVENDORID Register
\details Returns the content of the MVENDROID Register.
\return MVENDORID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MVENDORID(void)
{
uint32_t result;
__ASM volatile("csrr %0, mvendorid" : "=r"(result));
return (result);
}
/**
\brief Get MARCHID Register
\details Returns the content of the MARCHID Register.
\return MARCHID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MARCHID(void)
{
uint32_t result;
__ASM volatile("csrr %0, marchid" : "=r"(result));
return (result);
}
/**
\brief Get MIMPID Register
\details Returns the content of the MIMPID Register.
\return MIMPID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIMPID(void)
{
uint32_t result;
__ASM volatile("csrr %0, mimpid" : "=r"(result));
return (result);
}
/**
\brief Get MHARTID Register
\details Returns the content of the MHARTID Register.
\return MHARTID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MHARTID(void)
{
uint32_t result;
__ASM volatile("csrr %0, mhartid" : "=r"(result));
return (result);
}
/**
\brief Get PMPCFGx Register
\details Returns the content of the PMPCFGx Register.
\return PMPCFGx Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG0(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg0" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG1(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg1" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG2(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg2" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG3(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg3" : "=r"(result));
return (result);
}
/**
\brief Get PMPxCFG Register by index
\details Returns the content of the PMPxCFG Register.
\param [in] idx PMP region index
\return PMPxCFG Register value
*/
__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
{
uint32_t pmpcfgx = 0;
if (idx < 4) {
pmpcfgx = __get_PMPCFG0();
} else if (idx >=4 && idx < 8) {
idx -= 4;
pmpcfgx = __get_PMPCFG1();
} else if (idx >=8 && idx < 12) {
idx -= 8;
pmpcfgx = __get_PMPCFG2();
} else if (idx >=12 && idx < 16) {
idx -= 12;
pmpcfgx = __get_PMPCFG3();
} else {
return 0;
}
return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3));
}
/**
\brief Set PMPCFGx
\details Writes the given value to the PMPCFGx Register.
\param [in] pmpcfg PMPCFGx Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PMPCFG0(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg));
}
__ALWAYS_STATIC_INLINE void __set_PMPCFG1(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg));
}
__ALWAYS_STATIC_INLINE void __set_PMPCFG2(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg));
}
__ALWAYS_STATIC_INLINE void __set_PMPCFG3(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg));
}
/**
\brief Set PMPxCFG by index
\details Writes the given value to the PMPxCFG Register.
\param [in] idx PMPx region index
\param [in] pmpxcfg PMPxCFG Register value to set
*/
__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
{
uint32_t pmpcfgx = 0;
if (idx < 4) {
pmpcfgx = __get_PMPCFG0();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG0(pmpcfgx);
} else if (idx >=4 && idx < 8) {
idx -= 4;
pmpcfgx = __get_PMPCFG1();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG1(pmpcfgx);
} else if (idx >=8 && idx < 12) {
idx -= 8;
pmpcfgx = __get_PMPCFG2();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG2(pmpcfgx);
} else if (idx >=12 && idx < 16) {
idx -= 12;
pmpcfgx = __get_PMPCFG3();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG3(pmpcfgx);
} else {
return;
}
}
/**
\brief Get PMPADDRx Register
\details Returns the content of the PMPADDRx Register.
\return PMPADDRx Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR0(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr0" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR1(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr1" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR2(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr2" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR3(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr3" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR4(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr4" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR5(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr5" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR6(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr6" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR7(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr7" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR8(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr8" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR9(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr9" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR10(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr10" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR11(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr11" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR12(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr12" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR13(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr13" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR14(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr14" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR15(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr15" : "=r"(result));
return (result);
}
/**
\brief Get PMPADDRx Register by index
\details Returns the content of the PMPADDRx Register.
\param [in] idx PMP region index
\return PMPADDRx Register value
*/
__STATIC_INLINE uint32_t __get_PMPADDRx(uint32_t idx)
{
switch (idx) {
case 0: return __get_PMPADDR0();
case 1: return __get_PMPADDR1();
case 2: return __get_PMPADDR2();
case 3: return __get_PMPADDR3();
case 4: return __get_PMPADDR4();
case 5: return __get_PMPADDR5();
case 6: return __get_PMPADDR6();
case 7: return __get_PMPADDR7();
case 8: return __get_PMPADDR8();
case 9: return __get_PMPADDR9();
case 10: return __get_PMPADDR10();
case 11: return __get_PMPADDR11();
case 12: return __get_PMPADDR12();
case 13: return __get_PMPADDR13();
case 14: return __get_PMPADDR14();
case 15: return __get_PMPADDR15();
default: return 0;
}
}
/**
\brief Set PMPADDRx
\details Writes the given value to the PMPADDRx Register.
\param [in] pmpaddr PMPADDRx Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PMPADDR0(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR1(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR2(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR3(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR4(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR5(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR6(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR7(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR8(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR9(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR10(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR11(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR12(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR13(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR14(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR15(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr));
}
/**
\brief Set PMPADDRx by index
\details Writes the given value to the PMPADDRx Register.
\param [in] idx PMP region index
\param [in] pmpaddr PMPADDRx Register value to set
*/
__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, uint32_t pmpaddr)
{
switch (idx) {
case 0: __set_PMPADDR0(pmpaddr); break;
case 1: __set_PMPADDR1(pmpaddr); break;
case 2: __set_PMPADDR2(pmpaddr); break;
case 3: __set_PMPADDR3(pmpaddr); break;
case 4: __set_PMPADDR4(pmpaddr); break;
case 5: __set_PMPADDR5(pmpaddr); break;
case 6: __set_PMPADDR6(pmpaddr); break;
case 7: __set_PMPADDR7(pmpaddr); break;
case 8: __set_PMPADDR8(pmpaddr); break;
case 9: __set_PMPADDR9(pmpaddr); break;
case 10: __set_PMPADDR10(pmpaddr); break;
case 11: __set_PMPADDR11(pmpaddr); break;
case 12: __set_PMPADDR12(pmpaddr); break;
case 13: __set_PMPADDR13(pmpaddr); break;
case 14: __set_PMPADDR14(pmpaddr); break;
case 15: __set_PMPADDR15(pmpaddr); break;
default: return;
}
}
/**
\brief Enable interrupts and exceptions
\details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_excp_irq(void)
{
__enable_irq();
}
/**
\brief Disable interrupts and exceptions
\details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_excp_irq(void)
{
__disable_irq();
}
#define __CSI_GCC_OUT_REG(r) "=r" (r)
#define __CSI_GCC_USE_REG(r) "r" (r)
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__ALWAYS_STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
__ALWAYS_STATIC_INLINE void __WFI(void)
{
__ASM volatile("wfi");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __WAIT(void)
{
__ASM volatile("wfi");
}
/**
\brief Doze For Interrupt
\details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __DOZE(void)
{
__ASM volatile("wfi");
}
/**
\brief Stop For Interrupt
\details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __STOP(void)
{
__ASM volatile("wfi");
}
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__ALWAYS_STATIC_INLINE void __ISB(void)
{
__ASM volatile("fence");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("fence");
}
/**
\brief Invalid all icache
\details invalid all icache.
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
{
__ASM volatile("icache.iall");
}
/**
\brief Invalid all dcache
\details invalid all dcache.
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
{
__ASM volatile("dcache.iall");
}
/**
\brief Clear all dcache
\details clear all dcache.
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
{
__ASM volatile("dcache.call");
}
/**
\brief Clear&invalid all dcache
\details clear & invalid all dcache.
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
{
__ASM volatile("dcache.ciall");
}
/**
\brief Invalid Dcache by addr
\details Invalid Dcache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint32_t addr)
{
__ASM volatile("dcache.ipa %0" : : "r"(addr));
}
/**
\brief Clear Dcache by addr
\details Clear Dcache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint32_t addr)
{
__ASM volatile("dcache.cpa %0" : : "r"(addr));
}
/**
\brief Clear & Invalid Dcache by addr
\details Clear & Invalid Dcache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint32_t addr)
{
__ASM volatile("dcache.cipa %0" : : "r"(addr));
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__ALWAYS_STATIC_INLINE void __DMB(void)
{
__ASM volatile("fence");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value)
{
return __builtin_bswap32(value);
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) |
((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8);
return (result);
}
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value)
{
return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8));
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
*/
__ALWAYS_STATIC_INLINE void __BKPT(void)
{
__ASM volatile("ebreak");
}
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return (result);
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
/**
\details This function saturates a signed value.
\param [in] x Value to be saturated
\param [in] y Bit position to saturate to [1..32]
\return Saturated value.
*/
__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
{
int32_t posMax, negMin;
uint32_t i;
posMax = 1;
for (i = 0; i < (y - 1); i++) {
posMax = posMax * 2;
}
if (x > 0) {
posMax = (posMax - 1);
if (x > posMax) {
x = posMax;
}
// x &= (posMax * 2 + 1);
} else {
negMin = -posMax;
if (x < negMin) {
x = negMin;
}
// x &= (posMax * 2 - 1);
}
return (x);
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Unsigned Saturate for internal use
\details Saturates an unsigned value, should not call directly.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Rotate Right with Extend
\details This function moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\note carry input will always 0.
\param [in] op1 Value to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1)
{
return 0;
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] addr Pointer to location
\return value of type uint8_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr));
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] addr Pointer to location
\return value of type uint16_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr));
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] addr Pointer to location
\return value of type uint32_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr));
return (result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory");
}
/*@}*/ /* end of group CSI_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics
Access to dedicated SIMD instructions \n
Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
@{
*/
/**
\brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16]
of val2 levitated with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be left-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for left-shifting val2. Value range [0..31].
\return the combination of halfwords.
\remark
res[15:0] = val1[15:0] \n
res[31:16] = val2[31:16] << val3
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000));
}
/**
\brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0]
of val2 right-shifted with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be right-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for right-shifting val2. Value range [1..32].
\return the combination of halfwords.
\remark
res[15:0] = val2[15:0] >> val3 \n
res[31:16] = val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF));
}
/**
\brief Dual 16-bit signed saturate.
\details This function saturates a signed value.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:\n
the signed saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the signed saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF;
s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturate.
\details This function enables you to saturate two signed 16-bit values to a selected unsigned range.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the saturation of the two signed 16-bit values, as non-negative values:
the saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF;
s = __IUSAT(((x) >> 16), y) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit saturating addition.
\details This function enables you to perform four 8-bit integer additions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating addition.
\details This function enables you to perform four unsigned 8-bit integer additions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed addition.
\details This function performs four 8-bit signed integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition.
\details This function performs four unsigned 8-bit integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit saturating subtract.
\details This function enables you to perform four 8-bit integer subtractions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating subtraction.
\details This function enables you to perform four unsigned 8-bit integer subtractions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed subtraction.
\details This function enables you to perform four 8-bit signed integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtract.
\details This function enables you to perform four 8-bit unsigned integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences together, returning the result as a single unsigned integer.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n
The sum is returned as a single unsigned integer.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
*/
__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return (u + t + s + r);
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences to a 32-bit accumulate operand.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\param [in] sum accumulation value.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:
the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n
res[31:0] = sum[31:0] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
{
int32_t r, s, t, u;
#ifdef __cplusplus
r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#else
r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#endif
return (u + t + s + r + sum);
}
/**
\brief Dual 16-bit saturating addition.
\details This function enables you to perform two 16-bit integer arithmetic additions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition.
\details This function enables you to perform two unsigned 16-bit integer additions, saturating
the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition.
\details This function enables you to perform two 16-bit signed integer additions.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition
\details This function enables you to perform two 16-bit unsigned integer additions.
\param [in] x first two 16-bit summands for each addition.
\param [in] y second two 16-bit summands for each addition.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition with halved results.
\details This function enables you to perform two signed 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition with halved results.
\details This function enables you to perform two unsigned 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition with halved results.
\details This function enables you to perform four unsigned 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit saturating subtract.
\details This function enables you to perform two 16-bit integer subtractions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction.
\details This function enables you to perform two unsigned 16-bit integer subtractions,
saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit operands for each subtraction.
\param [in] y second two 16-bit operands for each subtraction.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction.
\details This function enables you to perform two 16-bit signed integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtract.
\details This function enables you to perform two 16-bit unsigned integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction with halved results.
\details This function enables you to perform two signed 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction with halved results.
\details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtraction with halved results.
\details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit add and subtract with exchange.
\details This function enables you to exchange the halfwords of the one operand,
then add the high halfwords and subtract the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition and subtraction with exchange.
\details This function enables you to exchange the halfwords of the second operand and
perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction,
saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit addition and subtraction with exchange.
\details It enables you to exchange the halfwords of the second operand, add the high halfwords
and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with exchange.
\details This function enables you to exchange the two halfwords of the second operand,
add the high halfwords and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition and subtraction with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one
signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
add the high halfwords and subtract the low halfwords, halving the results.
\param [in] x first operand for the subtraction in the low halfword, and
the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword, and
the second operand for the addition in the low halfword.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit subtract and add with exchange.
\details This function enables you to exchange the halfwords of one operand,
then subtract the high halfwords and add the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction and addition with exchange.
\details This function enables you to exchange the halfwords of the second operand and perform
one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating
the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit unsigned subtract and add with exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction and addition with exchange.
\details This function enables you to exchange the two halfwords of one operand and perform one
16-bit integer subtraction and one 16-bit addition.
\param [in] x first operand for the addition in the low halfword, and the first operand
for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and the second
operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit signed subtraction and addition with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one signed
16-bit integer subtraction and one signed 16-bit addition, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction and addition with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords, halving the results.
\param [in] x first operand for the addition in the low halfword, and
the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and
the second operand for the subtraction in the low halfword.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed multiply with exchange returning difference.
\details This function enables you to perform two 16-bit signed multiplications, subtracting
one of the products from the other. The halfwords of the second operand are exchanged
before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Sum of dual 16-bit signed multiply with exchange.
\details This function enables you to perform two 16-bit signed multiplications with exchanged
halfwords of the second operand, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Saturating add.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 + SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) {
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if ((int32_t)((uint32_t)x + (uint32_t)y) < x) {
result = x + y;
} else {
result = 0x80000000;
}
}
return result;
}
/**
\brief Saturating subtract.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 - SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
{
int64_t tmp;
int32_t result;
tmp = (int64_t)x - (int64_t)y;
if (tmp > 0x7fffffff) {
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
tmp = -2147483647 - 1;
}
result = tmp;
return result;
}
/**
\brief Dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications,
adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications with exchanged
halfwords of the second operand, adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication with exchanged halfwords of the second
operand added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to perform two 16-bit signed multiplications, take the
difference of the products, subtracting the high halfword product from the low
halfword product, and add the difference to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit
signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with single 64-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications, adding both results
to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition.
This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
\details This function enables you to exchange the halfwords of the second operand, and perform two
signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow
is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs.
Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief dual 16-bit signed multiply subtract with 64-bit accumulate.
\details This function It enables you to perform two 16-bit signed multiplications, take the difference
of the products, subtracting the high halfword product from the low halfword product, and add the
difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the
subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not
detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
\details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications,
adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the
multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow
is not detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief 32-bit signed multiply with 32-bit truncated accumulator.
\details This function enables you to perform a signed 32-bit multiplications, adding the most
significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
\param [in] x first operand for multiplication.
\param [in] y second operand for multiplication.
\param [in] sum accumulate value.
\return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
\remark
p = val1 * val2 \n
res[31:0] = p[63:32] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum)
{
return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum);
}
/**
\brief Sum of dual 16-bit signed multiply.
\details This function enables you to perform two 16-bit signed multiplications, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual 16-bit signed multiply returning difference.
\details This function enables you to perform two 16-bit signed multiplications, taking the difference
of the products by subtracting the high halfword product from the low halfword product.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual extracted 8-bit to 16-bit signed addition.
\details This function enables you to extract two 8-bit values from the second operand (at bit positions
[7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
\param [in] x values added to the sign-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and sign-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and sign-extended prior to the addition.
\remark
res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) |
(((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000)));
}
/**
\brief Extracted 16-bit to 32-bit unsigned addition.
\details This function enables you to extract two 8-bit values from one operand, zero-extend
them to 16 bits each, and add the results to two 16-bit values from another operand.
\param [in] x values added to the zero-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and zero-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and zero-extended prior to the addition.
\remark
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) |
((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and sign extend each to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x)
{
return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) |
((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and zero-extend to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
{
return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) |
(((x << 8) >> 8) & 0xFFFF0000)));
}
#endif /* _CSI_RV32_GCC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/core/csi_rv32_gcc.h | C | apache-2.0 | 105,545 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_core.h
* @brief CSI Core Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef _CORE_H_
#define _CORE_H_
#include <stdint.h>
#if defined(__CK801__) || defined(__E801__)
#include <core/core_801.h>
#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
#include <core/core_802.h>
#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
#include <core/core_804.h>
#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
#include <core/core_803.h>
#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
#include <core/core_805.h>
#elif defined(__CK610__)
#include <core/core_ck610.h>
#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
#include <core/core_810.h>
#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
#include <core/core_807.h>
#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
#include <core/core_rv32_old.h>
#elif defined(__riscv) && (__riscv_xlen == 32)
#include <core/core_rv32.h>
#elif defined(__riscv) && (__riscv_xlen == 64)
#include <core/core_rv64.h>
#endif
#if defined(__riscv) && (__riscv_xlen == 32)
#include <core/csi_rv32_gcc.h>
#elif defined(__riscv) && (__riscv_xlen == 64)
#include <core/csi_rv64_gcc.h>
#elif defined(__csky__)
#include <core/csi_gcc.h>
#endif
#ifdef __arm__
#include <csi_core_cmsis.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CORE_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/csi_core.h | C | apache-2.0 | 1,997 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file ringbuffer.h
* @brief header file for ringbuffer Driver
* @version V1.0
* @date August 15. 2019
******************************************************************************/
#ifndef _RING_BUFFER_H_
#define _RING_BUFFER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "stdint.h"
#include <stdbool.h>
typedef struct ringbuffer {
uint8_t *buffer;
uint32_t size;
uint32_t write;
uint32_t read;
uint32_t data_len;
} dev_ringbuf_t;
void dev_ringbuff_reset(dev_ringbuf_t *fifo);
uint32_t dev_ringbuf_len(dev_ringbuf_t *fifo);
uint32_t dev_ringbuf_avail(dev_ringbuf_t *fifo);
bool dev_ringbuf_is_empty(dev_ringbuf_t *fifo);
bool dev_ringbuf_is_full(dev_ringbuf_t *fifo);
/*write to ringbuffer*/
uint32_t dev_ringbuf_in(dev_ringbuf_t *fifo, const void *in, uint32_t len);
/*read to ringbuffer*/
uint32_t dev_ringbuf_out(dev_ringbuf_t *fifo, void *out, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif /* _RING_BUFFER_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/dev_ringbuf.h | C | apache-2.0 | 1,153 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_acmp.h
* @brief Header File for acmp Driver
* @version V1.0
* @date 02. June 2017
* @model acmp
******************************************************************************/
#ifndef _CSI_ACMP_H_
#define _CSI_ACMP_H_
#include <stdint.h>
#include <drv/errno.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** acmp specific error codes *****/
#define ACMP_ERROR_MODE (DRV_ERROR_SPECIFIC + 1) ///< Specified Mode not supported
/// definition for acmp handle.
typedef void *acmp_handle_t;
/*----- acmp Control Codes: Mode -----*/
typedef enum {
ACMP_MODE_FAST = 0, ///< fast mode
ACMP_MODE_SLOW, ///< slow mode
} acmp_mode_e;
/**
\brief acmp Status
*/
typedef struct {
uint32_t output_state : 1; ///< Analog comparator outputs 0 or 1
} acmp_status_t;
/**
\brief acmp Device Driver Capabilities.
*/
typedef struct {
uint32_t fast_mode : 1; ///< supports fast mode
uint32_t slow_mode : 1; ///< supports slow mode
uint32_t hysteresis_fun : 1; ///< supports Programming Hysteresis
} acmp_capabilities_t;
/**
\brief Initialize acmp Interface. 1. Initializes the resources needed for the acmp interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event event callback function \ref acmp_event_cb_t
\return return acmp handle if success
*/
acmp_handle_t drv_acmp_initialize(int32_t idx);
/**
\brief De-initialize acmp Interface. stops operation and releases the software resources used by the interface
\param[in] handle acmp handle to operate.
*/
void drv_acmp_uninitialize(acmp_handle_t handle);
/**
\brief control acmp power.
\param[in] handle acmp handle to operate.
\param[in] state power state.\ref drv_power_stat_e.
\return error code
*/
int32_t drv_acmp_power_control(acmp_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref acmp_capabilities_t
*/
acmp_capabilities_t drv_acmp_get_capabilities(int32_t idx);
/**
\brief config acmp mode.
\param[in] handle acmp handle to operate.
\param[in] mode \ref acmp_mode_e
\param[in] standard \ref acmp_standard_acmp_e
\return error code
*/
int32_t drv_acmp_config(acmp_handle_t handle, acmp_mode_e mode);
/**
\brief start comparison
\param[in] handle acmp handle to operate.
*/
void drv_acmp_comp_start(acmp_handle_t handle);
/**
\brief stop comparison.
\param[in] handle acmp handle to operate.
*/
void drv_acmp_comp_stop(acmp_handle_t handle);
/**
\brief Get acmp status.
\param[in] handle acmp handle to operate.
\return acmp status \ref acmp_status_t
*/
acmp_status_t drv_acmp_get_status(acmp_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_acmp_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/acmp.h | C | apache-2.0 | 3,159 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_adc.h
* @brief Header File for ADC Driver
* @version V1.0
* @date 15. October 2017
* @model adc
******************************************************************************/
#ifndef _CSI_ADC_H_
#define _CSI_ADC_H_
#include <stdint.h>
#include <drv/errno.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for adc handle.
typedef void *adc_handle_t;
/****** ADC conversion mode *****/
typedef enum {
ADC_SINGLE = 0, ///< Single conversion mode --- select one channel to convert at a time.
ADC_CONTINUOUS, ///< Continuous conversion mode --- select a channel to convert in a specific times.
ADC_SCAN, ///< Scan mode --- select a group channel to convert at a time.
} adc_mode_e;
/****** ADC Event *****/
typedef enum {
ADC_EVENT_CONVERSION_COMPLETE = 0, ///< All data conversion completed.
ADC_EVENT_DATA_LOST, ///< Data lost: adc buffer overflow / transmit underflow.
ADC_EVENT_DATA_OVERWRITE, ///< Converted data has not been read before the new conversion result is load to the data register.
ADC_EVENT_DATA_COMPARE_VALID, ///< Data compare right with adc comparator.
} adc_event_e;
/****** ADC Status *****/
typedef struct {
uint32_t busy : 1; ///< adc conversion on going.
uint32_t data_lost : 1; ///< adc buffer overflow.
uint32_t complete : 1; ///< adc conversion completion.
uint32_t compare_valid : 1; ///< data valid through adc comparator.
} adc_status_t;
/**
\brief ADC Driver Capabilities.
*/
typedef struct {
uint32_t single : 1;
uint32_t continuous : 1;
uint32_t scan : 1;
uint32_t calibration : 1;
uint32_t comparator : 1;
} adc_capabilities_t;
typedef struct {
uint32_t clk_prescaler; ///< select ADC clock prescaler.
adc_mode_e mode; ///< \ref adc_mode_e
uint32_t trigger; ///< 0 -- software adc start or 1 -- external event trigger to start adc.
uint32_t intrp_mode; ///< specifies whether the ADC is configured is interrupt mode (1)or in polling mode (0).
uint32_t *channel_array; ///< channel array base address, the ordinal of channel count from zero, like ADC_CHANNEL0 (0), ADC_CHANNEL1(1), etc.
uint32_t channel_nbr; ///< specifies the number of channels in channel array that will be converted.
uint32_t conv_cnt; ///< conversion count times for conversion mode.
uint32_t sampling_time; ///< sampling time value to be set for the selected channel. Unit:ADC clock cycles.
uint32_t offset; ///< reserved for future use, can be set to 0.
} adc_conf_t;
typedef struct {
uint32_t cmp_data; ///< the data is used to compare with conversion result of specified channel.
uint32_t cmp_channel; ///< compare channel selection.
uint32_t cmp_condition; ///< compare condition: 0 = Set the compare condition as that when a A/D conversion result is less than the cmp_data. 1 = Set the compare condition as that when a A/D conversion result is greater or equal to the cmp_data.
uint32_t cmp_match_cnt; ///< when the specified A/D channel analog conversion result matches the compare condition defined by cmp_condition, the internal match counter will increase 1. When the internal counter reaches the value to (cpm_match_cnt), the correspond status or flag bit will be set.
} adc_cmp_conf_t;
typedef void (*adc_event_cb_t)(int32_t idx, adc_event_e event); ///< Pointer to \ref adc_event_cb_t : adc Event call back.
/**
\brief Initialize adc Interface. 1. Initializes the resources needed for the adc interface 2.registers event callback function.
\param[in] idx adc index.
\param[in] cb_event event call back function \ref adc_event_cb_t
\return return adc handle if success
*/
adc_handle_t drv_adc_initialize(int32_t idx, adc_event_cb_t cb_event);
/**
\brief De-initialize adc Interface. stops operation and releases the software resources used by the interface
\param[in] handle adc handle to operate.
\return error code
*/
int32_t drv_adc_uninitialize(adc_handle_t handle);
/**
\brief control adc power.
\param[in] handle adc handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t drv_adc_power_control(adc_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx adc index.
\return \ref adc_capabilities_t
*/
adc_capabilities_t drv_adc_get_capabilities(int32_t idx);
int32_t drv_adc_pin2channel(int pin);
/**
\brief config adc mode.
\param[in] handle adc handle to operate.
\param[in] config adc_conf_t\ref . pointer to adc configuration structure.
\return error code
*/
int32_t drv_adc_config(adc_handle_t handle, adc_conf_t *config);
/**
\brief config adc comparator.
\param[in] handle adc handle to operate.
\param[in] config adc_conf_t\ref . pointer to adc configuration structure.
\return error code
*/
int32_t drv_adc_comparator_config(adc_handle_t handle, adc_cmp_conf_t *config);
/**
\brief start adc.
\param[in] handle adc handle to operate.
\return error code
*/
int32_t drv_adc_start(adc_handle_t handle);
/**
\brief stop adc.
\param[in] handle adc handle to operate.
\return error code
*/
int32_t drv_adc_stop(adc_handle_t handle);
/**
\brief receiving data from ADC receiver.
\param[in] handle ADC handle to operate.
\param[out] data Pointer to buffer for data to receive from ADC receiver, the data array is correspond to channel array.
\param[in] num Number of data items to receive.
\return error code
*/
int32_t drv_adc_read(adc_handle_t handle, uint32_t *data, uint32_t num);
/**
\brief Get ADC status.
\param[in] handle adc handle to operate.
\return ADC status \ref adc_status_t
*/
adc_status_t drv_adc_get_status(adc_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_ADC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/adc.h | C | apache-2.0 | 6,327 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_aes.h
* @brief Header File for AES Driver
* @version V1.0
* @date 02. June 2017
* @model aes
******************************************************************************/
#ifndef _CSI_AES_H_
#define _CSI_AES_H_
#include <stdint.h>
#include <drv/common.h>
#include <drv/errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for aes handle.
typedef void *aes_handle_t;
/****** AES specific error codes *****/
typedef enum {
AES_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
AES_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
AES_ERROR_ENDIAN ///< Specified endian not supported
} aes_error_e;
/*----- AES Control Codes: Mode -----*/
typedef enum {
AES_MODE_ECB = 0, ///< ECB Mode
AES_MODE_CBC, ///< CBC Mode
AES_MODE_CFB1, ///< CFB1 Mode
AES_MODE_CFB8, ///< CFB8 Mode
AES_MODE_CFB128, ///< CFB128 Mode
AES_MODE_OFB, ///< OFB Mode
AES_MODE_CTR ///< CTR Mode
} aes_mode_e;
/*----- AES Control Codes: Crypto Mode -----*/
typedef enum {
AES_CRYPTO_MODE_ENCRYPT = 0, ///< encrypt Mode
AES_CRYPTO_MODE_DECRYPT, ///< decrypt Mode
} aes_crypto_mode_e;
/*----- AES Control Codes: Mode Parameters: Key length -----*/
typedef enum {
AES_KEY_LEN_BITS_128 = 0, ///< 128 Data bits
AES_KEY_LEN_BITS_192, ///< 192 Data bits
AES_KEY_LEN_BITS_256 ///< 256 Data bits
} aes_key_len_bits_e;
/*----- AES Control Codes: Mode Parameters: Endian -----*/
typedef enum {
AES_ENDIAN_LITTLE = 0, ///< Little Endian
AES_ENDIAN_BIG ///< Big Endian
} aes_endian_mode_e;
/**
\brief AES Status
*/
typedef struct {
uint32_t busy : 1; ///< busy flag
} aes_status_t;
/****** AES Event *****/
typedef enum {
AES_EVENT_CRYPTO_COMPLETE = 0 ///< Encrypt completed
} aes_event_e;
typedef void (*aes_event_cb_t)(int32_t idx, aes_event_e event); ///< Pointer to \ref aes_event_cb_t : AES Event call back.
/**
\brief AES Device Driver Capabilities.
*/
typedef struct {
uint32_t ecb_mode : 1; ///< supports ECB mode
uint32_t cbc_mode : 1; ///< supports CBC mode
uint32_t cfb1_mode : 1; ///< supports CFB1 mode
uint32_t cfb8_mode : 1; ///< supports CFB8 mode
uint32_t cfb128_mode : 1; ///< supports CFB128 mode
uint32_t ofb_mode : 1; ///< supports OFB mode
uint32_t ctr_mode : 1; ///< supports CTR mode
uint32_t bits_128 : 1; ///< supports 128bits key length
uint32_t bits_192 : 1; ///< supports 192bits key length
uint32_t bits_256 : 1; ///< supports 256bits key length
} aes_capabilities_t;
// Function documentation
/**
\brief Initialize AES Interface. 1. Initializes the resources needed for the AES interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event event callback function \ref aes_event_cb_t
\return if success return aes handle else return NULL
*/
aes_handle_t csi_aes_initialize(int32_t idx, aes_event_cb_t cb_event);
/**
\brief De-initialize AES Interface. stops operation and releases the software resources used by the interface
\param[in] handle aes handle to operate.
\return error code
*/
int32_t csi_aes_uninitialize(aes_handle_t handle);
/**
\brief control aes power.
\param[in] handle aes handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_aes_power_control(aes_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref aes_capabilities_t
*/
aes_capabilities_t csi_aes_get_capabilities(int32_t idx);
/**
\brief config aes mode.
\param[in] handle aes handle to operate.
\param[in] mode \ref aes_mode_e
\param[in] keylen_bits \ref aes_key_len_bits_e
\param[in] endian \ref aes_endian_mode_e
\return error code
*/
int32_t csi_aes_config(aes_handle_t handle,
aes_mode_e mode,
aes_key_len_bits_e keylen_bits,
aes_endian_mode_e endian
);
/**
\brief set crypto key.
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] key Pointer to the key buf
\param[in] key_len Pointer to \ref aes_key_len_bits_e
\param[in] enc \ref aes_crypto_mode_e
\return error code
*/
int32_t csi_aes_set_key(aes_handle_t handle, void *context, void *key, aes_key_len_bits_e key_len, aes_crypto_mode_e enc);
/**
\brief aes ecb encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\return error code
*/
int32_t csi_aes_ecb_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len);
/**
\brief aes cbc encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\param[in] iv Pointer to initialization vector
\return error code
*/
int32_t csi_aes_cbc_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16]);
/**
\brief aes cfb1 encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\param[in] iv Pointer to initialization vector
\return error code
*/
int32_t csi_aes_cfb1_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16]);
/**
\brief aes cfb8 encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\param[in] iv Pointer to initialization vector
\return error code
*/
int32_t csi_aes_cfb8_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16]);
/**
\brief aes cfb128 encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\param[in] iv Pointer to initialization vector
\param[in] num the number of the 128-bit block we have used
\return error code
*/
int32_t csi_aes_cfb128_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16], uint32_t *num);
/**
\brief aes ofb encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\param[in] iv Pointer to initialization vector
\param[in] num the number of the 128-bit block we have used
\return error code
*/
int32_t csi_aes_ofb_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t iv[16], uint32_t *num);
/**
\brief aes ctr encrypt or decrypt
\param[in] handle aes handle to operate.
\param[in] context aes information context
\param[in] in Pointer to the Source data
\param[out] out Pointer to the Result data.
\param[in] len the Source data len.
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] num the number of the 128-bit block we have used
\return error code
*/
int32_t csi_aes_ctr_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, uint8_t nonce_counter[16], uint8_t stream_block[16], uint32_t *num);
/**
\brief Get AES status.
\param[in] handle aes handle to operate.
\return AES status \ref aes_status_t
*/
aes_status_t csi_aes_get_status(aes_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_AES_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/aes.h | C | apache-2.0 | 9,111 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_bmu.h
* @brief header file for bmu driver
* @version V1.0
* @date 02. June 2017
* @model bmu
******************************************************************************/
#ifndef _CSI_BMU_H_
#define _CSI_BMU_H_
#include <drv/common.h>
#include <drv/pmu.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for bmu handle.
typedef void *bmu_handle_t;
typedef enum {
BUCK_LS0 = 0, /*run/dor/sby onoff*/
BUCK_LS1 = 1, /*run/dor/sby onoff*/
HVIOLDO = 2, /*run/dor/sby onoff*/ /*run/dor/sby prog BW3*/
LVIOLDO = 3, /*run/dor/sby onoff*/ /*run/dor/sby prog BW3*/
ABB_LS = 4, /*run/dor/sby onoff*/
HVIO_LS = 5, /*run/dor/sby onoff*/
ACORELDO = 6, /*run/dor sby onoff*/
SIMLDO = 7, /*run/dor/sby onoff*/ /*run/dor/sby prog BW3*/
ANALDO = 8, /*run/dor/sby onoff*/ /*prog*/
LPCORELDO = 9, /* dor/sby onoff*/
MCORELDO = 10, /* dor/sby onoff*/
MAINBGP = 11, /* dor/sby onoff*/ /*prog*/
BUCKDC = 12, /* dor/sby onoff*/ /*run/dor/sby prog BW8*/
CORELDO = 13, /*run/dor/sby prog BW4*/
SDNPVD = 14, /*onoff*/ /*prog*/
SDNBOR = 15, /*prog*/
SBYLDO = 16, /*prog*/
SDNCMP = 17, /*onoff*/ /*prog*/
SDNBGP_LP = 18, /*prog*/
SDNBGP_HP = 19, /*prog*/
} bmu_regulator_e;
typedef enum {
DISABLE = 0,
ENABLE = 1,
} bmu_enable_e;
typedef enum {
HVIOLDO_1_800 = 0,
HVIOLDO_2_500 = 1,
HVIOLDO_2_700 = 2,
HVIOLDO_2_850 = 3,/*default*/
HVIOLDO_3_000 = 4,
HVIOLDO_3_300 = 5,
} bmu_hvioldo_vol_e;
typedef enum {
LVIOLDO_1_600 = 0,
LVIOLDO_1_640 = 1,
LVIOLDO_1_680 = 2,
LVIOLDO_1_720 = 3,
LVIOLDO_1_760 = 4,
LVIOLDO_1_800 = 5,/*default*/
LVIOLDO_1_840 = 6,
LVIOLDO_1_880 = 7,
} bmu_lvioldo_vol_e;
typedef enum {
SIMLDO_1_800 = 0,/*default*/
SIMLDO_2_500 = 1,
SIMLDO_2_700 = 2,
SIMLDO_2_850 = 3,
SIMLDO_3_000 = 4,
SIMLDO_3_300 = 5,
} bmu_simldo_vol_e;
typedef enum {
BUCKDC_1_500 = 0,
BUCKDC_1_620 = 4,
BUCKDC_1_740 = 8,
BUCKDC_1_800 = 10,
BUCKDC_1_830 = 11,
BUCKDC_1_860 = 12,
BUCKDC_1_950 = 15,
} bmu_buckdc_vol_e;
typedef enum {
CORELDO_0_900 = 0,
CORELDO_1_020 = 4,
CORELDO_1_110 = 7,
CORELDO_1_200 = 10,/*default*/
} bmu_coreldo_vol_e;
typedef enum {
ANALDO_2_000 = 0,
ANALDO_2_500 = 1,
ANALDO_2_700 = 2,
ANALDO_2_850 = 3,
ANALDO_3_000 = 4,
ANALDO_3_300 = 5,/*default*/
} bmu_analdo_vol_e;
typedef enum {
SBYLDO_1_640 = 0,
SBYLDO_1_680 = 1,
SBYLDO_1_720 = 2,
SBYLDO_1_760 = 3,
SBYLDO_1_800 = 4,
SBYLDO_1_840 = 5,/*default*/
SBYLDO_1_880 = 6,
SBYLDO_1_920 = 7,
} bmu_sbyldo_vol_e;
typedef enum {
SDNPVD_2_200 = 0,/*default*/
SDNPVD_2_400 = 1,
SDNPVD_2_600 = 2,
SDNPVD_2_800 = 3,
SDNPVD_3_000 = 4,
SDNPVD_3_200 = 5,
SDNPVD_3_400 = 6,
SDNPVD_3_600 = 7,
} bmu_sdnpvd_vol_e;
typedef enum {
SDNBOR_1_800 = 0,
SDNBOR_2_000 = 1,/*default*/
SDNBOR_2_200 = 2,
SDNBOR_2_500 = 3,
SDNBOR_2_800 = 4,
SDNBOR_3_000 = 5,
SDNBOR_3_100 = 6,
SDNBOR_3_200 = 7,
} bmu_sdnbor_vol_e;
typedef enum {
SDNCMP_9uA = 0,/*default*/
SDNCMP_11uA = 1,
SDNCMP_16uA = 2,
SDNCMP_30uA = 3,
} bmu_sdncmp_cur_e;
typedef enum {
MAINBGP_0_720 = 0,
MAINBGP_0_730 = 1,
MAINBGP_0_740 = 2,
MAINBGP_0_750 = 3,
MAINBGP_0_760 = 4,
MAINBGP_0_770 = 5,
MAINBGP_0_780 = 6,
MAINBGP_0_790 = 7,
MAINBGP_0_800 = 8,/*default*/
MAINBGP_0_810 = 9,
MAINBGP_0_820 = 10,
MAINBGP_0_830 = 11,
MAINBGP_0_840 = 12,
MAINBGP_0_850 = 13,
MAINBGP_0_860 = 14,
MAINBGP_0_870 = 15,
} bmu_mainbgp_vol_e;
typedef enum {
SDNBGP_LPMODE_1_137 = 0,
SDNBGP_LPMODE_1_158 = 1,
SDNBGP_LPMODE_1_175 = 2,
SDNBGP_LPMODE_1_194 = 3,
SDNBGP_LPMODE_1_214 = 4,/*default*/
SDNBGP_LPMODE_1_233 = 5,
SDNBGP_LPMODE_1_252 = 6,
SDNBGP_LPMODE_1_271 = 7,
} bmu_sdnbgp_lpmode_vol_e;
typedef enum {
SDNBGP_HPMODE_1_152 = 0,
SDNBGP_HPMODE_1_171 = 1,
SDNBGP_HPMODE_1_191 = 2,
SDNBGP_HPMODE_1_210 = 3,
SDNBGP_HPMODE_1_230 = 4,/*default*/
SDNBGP_HPMODE_1_251 = 5,
SDNBGP_HPMODE_1_270 = 6,
SDNBGP_HPMODE_1_289 = 7,
} bmu_sdnbgp_hpmode_vol_e;
typedef enum {
VBAT = 0,/*default*/
PVD_IN = 1,
} bmu_pvdsel_5V_e;
typedef enum {
LLP_SHUTDOWN = 0,/*default*/
LLP_RESTART = 1,
} bmu_llp_todo_e;
typedef enum {
PSHOLD_DOWN = 0,/*default*/
PSHOLD_UP = 1,
} bmu_pshold_status_e;
/****** BMU Event *****/
typedef enum {
BMU_EVENT_SEND_COMPLETE = 0, ///< Send completed; however BMU may still transmit data
BMU_EVENT_RECEIVE_COMPLETE = 1, ///< Receive completed
BMU_EVENT_RECEIVED = 2, ///< Receiving data
BMU_EVENT_TRANSFER_COMPLETE = 3, ///< Transfer completed
BMU_EVENT_TX_COMPLETE = 4, ///< Transmit completed (optional)
BMU_EVENT_TX_UNDERFLOW = 5, ///< Transmit data not available (Synchronous Slave)
BMU_EVENT_RX_OVERFLOW = 6, ///< Receive data overflow
BMU_EVENT_RX_TIMEOUT = 7, ///< Receive character timeout (optional)
BMU_EVENT_RX_BREAK = 8, ///< Break detected on receive
BMU_EVENT_RX_FRAMING_ERROR = 9, ///< Framing error detected on receive
BMU_EVENT_RX_PARITY_ERROR = 10, ///< Parity error detected on receive
} bmu_event_e;
typedef void (*bmu_event_cb_t)(int32_t idx, bmu_event_e event); ///< Pointer to \ref bmu_event_cb_t : BMU Event call back.
/**
\brief BMU Driver Capabilities.
*/
typedef struct {
uint32_t asynchronous : 1; ///< supports BMU (Asynchronous) mode
uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
uint32_t single_wire : 1; ///< supports BMU Single-wire mode
uint32_t event_tx_complete : 1; ///< Transmit completed event
uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event
} bmu_capabilities_t;
/**
\brief Initialize BMU Interface. 1. Initializes the resources needed for the BMU interface 2.registers event callback function
\param[in] idx bmu id
\param[in] cb_event Pointer to \ref bmu_event_cb_t
\return return bmu handle if success
*/
bmu_handle_t csi_bmu_initialize(int32_t idx, bmu_event_cb_t cb_event);
/**
\brief De-initialize BMU Interface. stops operation and releases the software resources used by the interface
\param[in] handle bmu handle to operate.
\return error code
*/
int32_t csi_bmu_uninitialize(bmu_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] handle bmu handle to operate.
\return \ref bmu_capabilities_t
*/
bmu_capabilities_t csi_bmu_get_capabilities(bmu_handle_t handle);
/**
* Pull pshold up or down.
*
* @param[in] enable Flag of up or down.
* @return none
*/
int32_t csi_bmu_set_pshold(bmu_handle_t handle, bmu_pshold_status_e enable);
/**
* Set key long long press to do.
*
* @param[in] enable Flag of shutdown or restart.
* @return none
*/
int32_t csi_bmu_set_llp_todo(bmu_handle_t handle, bmu_llp_todo_e enable);
/**
* Set mainbgp voltage.
*
* @param[in] mainbgp_vol Voltage of Regulator.
* @return none
*/
int32_t csi_bmu_mainbgp_setvol(bmu_handle_t handle, bmu_mainbgp_vol_e mainbgp_vol);
/**
* Set sdnbgp voltage in lpmode.
*
* @param[in] vol Voltage of sdnbgp in lpmode.
* @return none
*/
int32_t csi_bmu_sdnbgp_lpmode_setvol(bmu_handle_t handle, bmu_sdnbgp_lpmode_vol_e vol);
/**
* Set sdnbgp voltage in hpmode.
*
* @param[in] vol Voltage of sdnbgp in hpmode.
* @return none
*/
int32_t csi_bmu_sdnbgp_hpmode_setvol(bmu_handle_t handle, bmu_sdnbgp_hpmode_vol_e vol);
/**
* Set sdnpvd voltage.
*
* @param[in] sdnpvd_vol Voltage of sdnpvd.
* @return none
*/
int32_t csi_bmu_sdnpvd_setvol(bmu_handle_t handle, bmu_sdnpvd_vol_e sdnpvd_vol);
/**
* Set sdnpvd on or off.
*
* @param[in] enable Flag of enable or disable.
* @return none
*/
int32_t csi_bmu_sdnpvd_setonoff(bmu_handle_t handle, bmu_enable_e enable);
/**
* Select sdnpvd source.
*
* @param[in] enable Flag of sdnpvd source.
* @return none
*/
int32_t csi_bmu_sdnpvd_selsrc(bmu_handle_t handle, bmu_pvdsel_5V_e pvdsel);
/**
* Set sdnbor voltage.
*
* @param[in] sdnbor_vol Voltage of sdnbor.
* @return none
*/
int32_t csi_bmu_sdnbor_setvol(bmu_handle_t handle, bmu_sdnbor_vol_e sdnbor_vol);
/**
* Set sdncmp current.
*
* @param[in] sdncmp_cur Current of sdncmp.
* @return none
*/
int32_t csi_bmu_sdncmp_setcur(bmu_handle_t handle, bmu_sdncmp_cur_e sdncmp_cur);
/**
* Set sdncmp on or off.
*
* @param[in] enable Flag of enable or disable.
* @return none
*/
int32_t csi_bmu_sdncmp_setonoff(bmu_handle_t handle, bmu_enable_e enable);
/**
* Set hvioldo voltage in different bmu mod.
*
* @param[in] pmu_mode Pmu mode.
* @param[in] hvioldo Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_hvioldo_setvol(bmu_handle_t handle, pmu_mode_e pmu_mode, bmu_hvioldo_vol_e hvioldo_vol);
/**
* Set simldo voltage in different bmu mod.
*
* @param[in] pmu_mode Pmu mode.
* @param[in] simldo Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_simldo_setvol(bmu_handle_t handle, pmu_mode_e pmu_mode, bmu_simldo_vol_e simldo_vol);
/**
* Set buckdc voltage in different bmu mod.
*
* @param[in] pmu_mode Pmu mode.
* @param[in] buckdc Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_buckdc_setvol(bmu_handle_t handle, pmu_mode_e pmu_mode, bmu_buckdc_vol_e buckdc_vol);
/**
* Set coreldo voltage in different bmu mod.
*
* @param[in] pmu_mode Pmu mode.
* @param[in] coreldo Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_coreldo_setvol(bmu_handle_t handle, pmu_mode_e pmu_mode, bmu_coreldo_vol_e coreldo_vol);
/**
* Set lvioldo voltage in different bmu mod.
*
* @param[in] pmu_mode Pmu mode.
* @param[in] lvioldo Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_lvioldo_setvol(bmu_handle_t handle, pmu_mode_e pmu_mode, bmu_lvioldo_vol_e lvioldo_vol);
/**
* Set analdo voltage.
*
* @param[in] analdo Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_analdo_setvol(bmu_handle_t handle, bmu_analdo_vol_e analdo_vol);
/**
* Set sbyldo voltage.
*
* @param[in] sbyldo Voltage value.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_sbyldo_setvol(bmu_handle_t handle, bmu_sbyldo_vol_e sbyldo_vol);
/**
* Set regulator on or off in run mode of bmu.
*
* @param[in] regulator Identify of Regulator.
* @param[in] enable Flag of on or off.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_run_setonoff(bmu_handle_t handle, bmu_regulator_e regulator, bmu_enable_e enable);
/**
* Set regulator on or off in dormant mode of bmu.
*
* @param[in] regulator Identify of Regulator.
* @param[in] enable Flag of on or off.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_dor_setonoff(bmu_handle_t handle, bmu_regulator_e regulator, bmu_enable_e enable);
/**
* Set regulator on or off in standby mode of bmu.
*
* @param[in] regulator Identify of Regulator.
* @param[in] enable Flag of on or off.
* @return 0 is OK, others is error
*/
int32_t csi_bmu_sby_setonoff(bmu_handle_t handle, bmu_regulator_e regulator, bmu_enable_e enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_BMU_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/bmu.h | C | apache-2.0 | 12,171 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_camera.h
* @brief header file for camera driver
* @version V1.2
* @date 27. May 2019
* @model camera
******************************************************************************/
#ifndef _DRV_CAMERA_H_
#define _DRV_CAMERA_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for camera handle.
typedef void *camera_handle_t;
/**** Camera Data Types ****/
typedef enum {
CAMERA_DATA_FORMAT_YUV420_8 = 0,
CAMERA_DATA_FORMAT_YUV420_10,
CAMERA_DATA_FORMAT_YUV420_8_LEG,
CAMERA_DATA_FORMAT_YUV420_8_SHIFT,
CAMERA_DATA_FORMAT_YUV420_10_SHIFT,
CAMERA_DATA_FORMAT_YUV422_8,
CAMERA_DATA_FORMAT_YUV422_10,
CAMERA_DATA_FORMAT_RGB444,
CAMERA_DATA_FORMAT_RGB555,
CAMERA_DATA_FORMAT_RGB565,
CAMERA_DATA_FORMAT_RGB666,
CAMERA_DATA_FORMAT_RGB888,
CAMERA_DATA_FORMAT_RAW6,
CAMERA_DATA_FORMAT_RAW7,
CAMERA_DATA_FORMAT_RAW8,
CAMERA_DATA_FORMAT_RAW10,
CAMERA_DATA_FORMAT_RAW12,
CAMERA_DATA_FORMAT_RAW14,
} camera_data_format_e;
/**** Camera work mode ****/
typedef enum {
CAMERA_OUTPUT_MODE_MIPI = 0,
CAMERA_OUTPUT_MODE_DVP,
CAMERA_OUTPUT_MODE_FPD,
CAMERA_OUTPUT_MODE_GMSL,
} camera_output_mode_e;
/**
\brief Camera config structure
*/
typedef struct {
camera_data_format_e format; ///< output image format
camera_output_mode_e mode; ///< camera work mode
uint32_t width; ///< output image width
uint32_t height; ///< output image height
} camera_config_t;
/****** CAMERA Event *****/
typedef enum {
CAMERA_EVENT_READY = 0, ///< camera Ready
CAMERA_EVENT_ERROR, ///< Read/Write camera Error
} camera_event_e;
typedef void (*camera_event_cb_t)(camera_handle_t handle, camera_event_e event, void *user_data); ///< Pointer to \ref camera_event_cb_t : CAMERA Event call back.
// Function documentation
/**
\brief Initialize CAMERA Interface. 1. Initializes the resources needed for the CAMERA interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event Pointer to \ref camera_event_cb_t
\return pointer to camera handle
*/
camera_handle_t csi_camera_initialize(int32_t idx, camera_event_cb_t cb_event, void *user_data);
/**
\brief De-initialize CAMERA Interface. stops operation and releases the software resources used by the interface
\param[in] handle camera handle to operate.
\return error code
*/
int32_t csi_camera_uninitialize(camera_handle_t handle);
/**
\brief Start and config the camera.
\param[in] handle camera handle to operate.
\param[in] config the config structure of camera
\return error code
*/
int32_t csi_camera_start(camera_handle_t handle, camera_config_t *config);
/**
\brief Stop the camera.
\param[in] handle camera handle to operate.
\return error code
*/
int32_t csi_camera_stop(camera_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_CAMERA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/camera.h | C | apache-2.0 | 3,223 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_clk.h
* @brief header file for clk driver
* @version V1.0
* @date 02. June 2017
* @model clk
******************************************************************************/
#ifndef _CSI_CLK_H_
#define _CSI_CLK_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
CK_TIMER0_PCLK = 0,
CK_TIMER1_PCLK,
CK_TIMER0_WCLK,
CK_TIMER1_WCLK,
AP_WDT_PCLK,
AP_WDT_WCLK,
UART0_PCLK,
UART1_PCLK,
UART2_PCLK,
LP_UART_PCLK,
UART0_WCLK_L1,
UART0_WCLK_L2,
UART1_WCLK,
UART2_WCLK,
LP_UART_WCLK,
I2C0_PCLK,
I2C1_PCLK,
I2C0_WCLK,
I2C1_WCLK,
SSP0_PCLK,
SSP1_PCLK,
SSP2_PCLK,
SSP0_WCLK,
SSP1_WCLK,
SSP2_WCLK,
GPIO_PD_PCLK,
ADC_PCLK,
ADC_WCLK,
DAC_PCLK,
DAC_WCLK,
AD_TIMER0_PCLK,
AD_TIMER1_PCLK,
AD_TIMER0_WCLK,
AD_TIMER1_WCLK,
AP_DMA_PCLK,
LP_TIMER_PCLK,
LP_TIMER_WCLK,
I2S0_PCLK,
I2S0_WCLK,
PD_LOGIC_MATRIX_CLK,
PD_PINMUX_CLK,
ICP_CLK,
SPINOR_PCLK,
SPINOR_WCLK,
IRAM_CLK,
GPIO_PCLK,
AO_PINMUX_PCLK,
AO_PCU_PCLK,
RTC_PCLK,
EFLASH2_CLK,
EFLASH1_CTRL_CLK,
EFLASH1_CFG_CLK,
LSP_61M44_WCLK,
AON_76M8_CLK,
RTC_32K_WCLK,
IWDT_PCLK,
IWDT_WCLK,
}
clk_name;
/*
* bits domain definition for clock frequency
* base clock name same clock number reserved clock selection frequency division
* 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0
* invalid value:
* 0xff 0xf or 0x0 0x0 or ignore 0xff 0xff
*/
typedef enum {
FIXED_FREQ = 0xffffffff,
/*ck timer0&1/rm timer0&1/ceva timer0&1*/
WCLK_TIMER_32K = (CK_TIMER0_WCLK << 24) | 0x00600000,
WCLK_TIMER_19M2 = (CK_TIMER0_WCLK << 24) | 0x06000100, /* 1 div*/
WCLK_TIMER_9M6 = (CK_TIMER0_WCLK << 24) | 0x00600101, /* 2 div*/
/*ap wdt/cp wdt*/
WCLK_WDT_32K = (AP_WDT_WCLK << 24) | 0x00200000,
WCLK_WDT_19M2 = (AP_WDT_WCLK << 24) | 0x00200100,
WCLK_WDT_9M6 = (AP_WDT_WCLK << 24) | 0x00200101,
/*i2c0&1*/
WCLK_I2C_76M8 = (I2C0_WCLK << 24) | 0x00200100,
WCLK_I2C_19M2 = (I2C0_WCLK << 24) | 0x00200000,
/*uart0&1&2&lp uart*/
WCLK_UART_19M2 = (UART0_WCLK_L1 << 24) | 0x00400000,
WCLK_UART_76M8 = (UART0_WCLK_L1 << 24) | 0x00400100,
/*only for uart0& lp uart*/
WCLK_UART_32K = (UART0_WCLK_L1 << 24) | 0x00400200,
/*ssp0&1&2*/
WCLK_SSP_19M2 = (SSP0_WCLK << 24) | 0x00300000,
WCLK_SSP_76M8 = (SSP0_WCLK << 24) | 0x00300100,
WCLK_SSP_61m44 = (SSP0_WCLK << 24) | 0x00300200,
/*adc*/
WCLK_ADC_19M2 = (ADC_WCLK << 24) | 0x00100000,
WCLK_ADC_38M4 = (ADC_WCLK << 24) | 0x00100100,
WCLK_ADC_61M44 = (ADC_WCLK << 24) | 0x00100200,
WCLK_ADC_32K = (ADC_WCLK << 24) | 0x00100300,
/*dac*/
WCLK_DAC_19M2 = (DAC_WCLK << 24) | 0x001001000,
WCLK_DAC_32K = (DAC_WCLK << 24) | 0x00100200,
/*ad timer0&1*/
WCLK_AD_TIMER_32K = (AD_TIMER0_WCLK << 24) | 0x002000000,
WCLK_AD_TIMER_76M8 = (AD_TIMER0_WCLK << 24) | 0x00200100,
WCLK_AD_TIMER_19M2 = (AD_TIMER0_WCLK << 24) | 0x00200200,
/*lp timer*/
WCLK_LP_TIMER_32K = (LP_TIMER_WCLK << 24) | 0x001000000,
WCLK_LP_TIMER_76M8 = (LP_TIMER_WCLK << 24) | 0x001000100,
WCLK_LP_TIMER_19M2 = (LP_TIMER_WCLK << 24) | 0x001000200,
/*I2S0*/
WCLK_I2S_19M2 = (I2S0_WCLK << 24) | 0x00100000,
WCLK_I2S_76M8 = (I2S0_WCLK << 24) | 0x00100100,
WCLK_I2S_61M44 = (I2S0_WCLK << 24) | 0x00100200,
/*spi nor*/
WCLK_SPINOR_19M2 = (SPINOR_WCLK << 24) | 0x00100000,
WCLK_SPINOR_76M8 = (SPINOR_WCLK << 24) | 0x00100100,
WCLK_SPINOR_61M44 = (SPINOR_WCLK << 24) | 0x00100200,
/*iwdt*/
WCLK_IWDT_RC32K = (IWDT_WCLK << 24) | 0x00100000,
WCLK_IWDT_XTAL32K = (IWDT_WCLK << 24) | 0x00100100,
} clk_freq_sel;
/**
\brief set software clock gate.
\param[in] name the clock name to set.
\param[in] ctrl 0 enable; 1 disable
\return error code
*/
int csi_clk_sw_gate_ctrl(clk_name name, uint32_t ctrl);
/**
\brief set clock autogate.
\param[in] name the clock name to set.
\param[in] ctrl 0 enable; 1 disable
\return error code
*/
int csi_clk_hw_gate_ctrl(clk_name name, uint32_t ctrl);
/**
\brief config clock reset ctrl.
\param[in] name the clock name to set.
\param[in] ctrl 0 enable; 1 disable
\return error code
*/
int csi_clk_reset(clk_name name, uint32_t ctrl);
/**
\brief set clock freq.
\param[in] name the clock name to set.
\param[in] freq teh corresponding freq to set
\return error code
*/
int csi_clk_set_freq(clk_name name, clk_freq_sel freq);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_CLK_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/clk.h | C | apache-2.0 | 5,164 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_codec.h
* @brief head file for codec
* @version V1.0
* @date 12. April 2019
* @model codec
******************************************************************************/
#ifndef _DRV_CODEC_H_
#define _DRV_CODEC_H_
#include <drv/common.h>
#include "stdint.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
CODEC_SAMPLE_RATE_8000 = 8000,
CODEC_SAMPLE_RATE_11025 = 11025,
CODEC_SAMPLE_RATE_12000 = 12000,
CODEC_SAMPLE_RATE_16000 = 16000,
CODEC_SAMPLE_RATE_22050 = 22050,
CODEC_SAMPLE_RATE_24000 = 24000,
CODEC_SAMPLE_RATE_32000 = 32000,
CODEC_SAMPLE_RATE_44100 = 44100,
CODEC_SAMPLE_RATE_48000 = 48000,
CODEC_SAMPLE_RATE_96000 = 96000,
} codec_sample_rate_t;
/****** CODEC Event *****/
typedef enum {
CODEC_EVENT_PERIOD_READ_COMPLETE = 0, ///< a peroid data read complete
CODEC_EVENT_PERIOD_WRITE_COMPLETE = 1, ///< a peroid data write complete
CODEC_EVENT_WRITE_BUFFER_EMPTY = 2, ///< fifo is empty
CODEC_EVENT_READ_BUFFER_FULL = 3, ///< fifo is full
CODEC_EVENT_VAD_TRIGGER = 4, ///< vad is trigger
CODEC_EVENT_TRANSFER_ERROR = 5, ///< transfer error
} codec_event_t;
typedef enum {
CODEC_MODE_RUN = 0, ///< Running mode
CODEC_MODE_SLEEP, ///< Sleep mode
CODEC_MODE_SHUTDOWN ///< Shutdown mode
} codec_lpm_state_t;
typedef void (*codec_event_cb_t)(int idx, codec_event_t event, void *arg);
typedef void *codec_handle_t;
typedef struct {
codec_sample_rate_t sample_rate;
uint32_t channel_num; ///< record channel num
uint32_t bit_width;
} codec_input_config_t;
typedef struct {
codec_sample_rate_t sample_rate;
uint32_t bit_width;
uint32_t mono_mode_en;
} codec_output_config_t;
typedef struct {
int32_t codec_idx;
int32_t ch_idx; ///< input channle number
codec_event_cb_t cb;
void *cb_arg;
uint8_t *buf;
uint32_t buf_size; ///< Used to cache incoming data
uint32_t period; ///< when a peroid data is reached,the callback function is called
uint32_t vad_threshold;
void *priv;
} codec_input_t;
typedef struct {
int32_t codec_idx;
int32_t ch_idx;
codec_event_cb_t cb;
void *cb_arg;
uint8_t *buf; ///< Used to cache incoming data
uint32_t buf_size;
uint32_t period; ///< when a peroid data is reached,the callback function is called
void *priv;
} codec_output_t;
/**
\brief Init the CODEC according to the specified
\param[in] idx codec index
\return 0 for success, negative for error code
*/
int32_t csi_codec_init(uint32_t idx);
/**
\brief Uninit the CODEC
\param[in] idx codec index
\return none
*/
void csi_codec_uninit(uint32_t idx);
void csi_codec_lpm(uint32_t idx, codec_lpm_state_t state);
/**
\brief Control codec power
\param[in] idx codec index
\param[in] state power ctrl status
\return 0 for success, negative for error code
*/
int32_t csi_codec_power_control(int32_t idx, csi_power_stat_e state);
/**
\brief Open the codec input channel
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_open(codec_input_t *handle);
/**
\brief Config the codec input channel
\param[in] handle: codec input handle
\param[in] config: codec input config param
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_config(codec_input_t *handle, codec_input_config_t *config);
/**
\brief Close codec input channel
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_close(codec_input_t *handle);
/**
\brief Read the record data
\param[in] handle: codec input handle
\param[in] buf: used to store read data
\param[in] length: read data length
\return read data len, if the data is empty return 0;
*/
uint32_t csi_codec_input_read(codec_input_t *handle, uint8_t *buf, uint32_t length);
/**
\brief Get buffer free space
\param[in] handle: codec input handle
\return buffer free space (bytes)
*/
uint32_t csi_codec_input_buf_avail(codec_input_t *handle);
/**
\brief Reset the buf, discard all data in the cache
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_buf_reset(codec_input_t *handle);
/**
\brief Start the input channel.
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_start(codec_input_t *handle);
/**
\brief Stop the input channel and reset the input cache.
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_stop(codec_input_t *handle);
/**
\brief Pause the input channel, channel will be pause receive data.
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_pause(codec_input_t *handle);
/**
\brief Resume the input channel
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_resume(codec_input_t *handle);
/**
\brief Set input digital gain
\param[in] handle: codec input handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_set_digital_gain(codec_input_t *handle, int32_t val);
/**
\brief Set input analog gain
\param[in] handle: codec input handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_set_analog_gain(codec_input_t *handle, int32_t val);
/**
\brief Get input digital gain
\param[in] handle: codec input handle
\param[out] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_get_digital_gain(codec_input_t *handle, int32_t *val);
/**
\brief Get input analog gain
\param[in] handle: codec input handle
\param[out] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_get_analog_gain(codec_input_t *handle, int32_t *val);
/**
\brief Set input mixer gain
\param[in] handle: codec input handle
\param[in] val: gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_set_mixer_gain(codec_input_t *handle, int32_t val);
/**
\brief Get input mixer gain
\param[in] handle: codec input handle
\param[out] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_get_mixer_gain(codec_input_t *handle, int32_t *val);
/**
\brief Contol input mute
\param[in] handle: codec input handle
\param[in] en: 1 enable mute, 0 disable meute
\return 0 for success, negative for error code
*/
int32_t csi_codec_input_mute(codec_input_t *handle, int en);
/**
\brief Open the codec output channel
\param[in] handle: codec output handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_open(codec_output_t *handle);
/**
\brief Close the codec output channel
\param[in] handle: codec output handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_close(codec_output_t *handle);
/**
\brief Close the codec output channel
\param[in] handle: codec output handle
\param[in] config: channel config param
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_config(codec_output_t *handle, codec_output_config_t *config);
/**
\brief Close the codec output channel
\param[in] handle: codec output handle
\param[in] buf: write data
\param[in] lenght: write data length
\return The number of data written to the cache
*/
uint32_t csi_codec_output_write(codec_output_t *handle, uint8_t *buf, uint32_t length);
/**
\brief Get buffer free space
\param[in] handle: codec output handle
\return buffer free space (bytes)
*/
uint32_t csi_codec_output_buf_avail(codec_output_t *handle);
/**
\brief Reset the buf, discard all data in the cache
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_buf_reset(codec_output_t *handle);
/**
\brief Start the output channel.
\param[in] handle: codec output handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_start(codec_output_t *handle);
/**
\brief Stop the output channel and reset the output cache.
\param[in] handle: codec output handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_stop(codec_output_t *handle);
/**
\brief Pause the ouput channel, channel will be pause send data.
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_pause(codec_output_t *handle);
/**
\brief Resume the ouput channel.
\param[in] handle: codec input handle
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_resume(codec_output_t *handle);
/**
\brief Set output left channel digital gain
\param[in] handle: codec output handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_set_digital_left_gain(codec_output_t *handle, int32_t val);
/**
\brief Set output right channel digital gain
\param[in] handle: codec output handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_set_digital_right_gain(codec_output_t *handle, int32_t val);
/**
\brief Set output left channel analog gain
\param[in] handle: codec output handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_set_analog_left_gain(codec_output_t *handle, int32_t val);
/**
\brief Set output right channel analog gain
\param[in] handle: codec output handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_set_analog_right_gain(codec_output_t *handle, int32_t val);
/**
\brief Get output left channel digital gain
\param[in] handle: codec output handle
\param[in] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_get_digital_left_gain(codec_output_t *handle, int32_t *val);
/**
\brief Get output right channel digital gain
\param[in] handle: codec output handle
\param[in] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_get_digital_right_gain(codec_output_t *handle, int32_t *val);
/**
\brief Get output left channel analog gain
\param[in] handle: codec output handle
\param[in] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_get_analog_left_gain(codec_output_t *handle, int32_t *val);
/**
\brief Get output right channel analog gain
\param[in] handle: codec output handle
\param[in] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_get_analog_right_gain(codec_output_t *handle, int32_t *val);
/**
\brief Set output left channel mixer gain
\param[in] handle: codec output handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_set_mixer_left_gain(codec_output_t *handle, int32_t val);
/**
\brief Set output right channel mixer gain
\param[in] handle: codec output handle
\param[in] val: gain value
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_set_mixer_right_gain(codec_output_t *handle, int32_t val);
/**
\brief Get output left channel mixer gain
\param[in] handle: codec output handle
\param[in] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_get_mixer_left_gain(codec_output_t *handle, int32_t *val);
/**
\brief Get output right channel mixer gain
\param[in] handle: codec output handle
\param[in] val: pointer, that used save gain val
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_get_mixer_right_gain(codec_output_t *handle, int32_t *val);
/**
\brief Contol output channel mute
\param[in] handle: codec output handle
\param[in] en: 1 enable mute, 0 disable meute
\return 0 for success, negative for error code
*/
int32_t csi_codec_output_mute(codec_output_t *handle, int en);
/**
\brief Contol codec wakeup
\param[in] handle: codec input handle
\param[in] en: 1 enable wakeup, 0 disable wakeup
\return 0 for success, negative for error code
*/
int32_t csi_codec_vad_enable(codec_input_t *handle, int en);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_CODEC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/codec.h | C | apache-2.0 | 13,346 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_common.h
* @brief Header File for Common Driver
* @version V1.0
* @date 19. Feb 2019
* @model common
******************************************************************************/
#ifndef _DRV_COMMON_H_
#define _DRV_COMMON_H_
#include <stdint.h>
#include <drv/errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/// \details driver handle
typedef void *drv_handle_t;
#ifndef CONFIG_PARAM_NOT_CHECK
#define HANDLE_PARAM_CHK(para, err) \
do { \
if ((int32_t)para == (int32_t)NULL) { \
return (err); \
} \
} while (0)
#define HANDLE_PARAM_CHK_NORETVAL(para, err) \
do { \
if ((int32_t)para == (int32_t)NULL) { \
return; \
} \
} while (0)
#else
#define HANDLE_PARAM_CHK(para, err)
#define HANDLE_PARAM_CHK_NORETVAL(para, err)
#endif
/**
\brief General power states
*/
typedef enum {
DRV_POWER_OFF, ///< Power off: no operation possible
DRV_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
DRV_POWER_FULL, ///< Power on: full operation at maximum performance
DRV_POWER_SUSPEND, ///< Power suspend: power saving operation
} csi_power_stat_e;
#ifdef __cplusplus
}
#endif
#endif /* _DRV_COMMON_H */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/common.h | C | apache-2.0 | 2,259 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_crc.h
* @brief Header File for CRC Driver
* @version V1.0
* @date 02. June 2017
* @model crc
******************************************************************************/
#ifndef _CSI_CRC_H_
#define _CSI_CRC_H_
#include <stdint.h>
#include <drv/errno.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** CRC specific error codes *****/
#define CRC_ERROR_MODE (DRV_ERROR_SPECIFIC + 1) ///< Specified Mode not supported
/// definition for crc handle.
typedef void *crc_handle_t;
/*----- CRC Control Codes: Mode -----*/
typedef enum {
CRC_MODE_CRC8 = 0, ///< Mode CRC8
CRC_MODE_CRC16, ///< Mode CRC16
CRC_MODE_CRC32 ///< Mode CRC32
} crc_mode_e;
/*----- CRC Control Codes: Mode Parameters: Key length -----*/
typedef enum {
CRC_STANDARD_CRC_ROHC = 0, ///< Standard CRC RHOC
CRC_STANDARD_CRC_MAXIM, ///< Standard CRC MAXIAM
CRC_STANDARD_CRC_X25, ///< Standard CRC X25
CRC_STANDARD_CRC_CCITT, ///< Standard CRC CCITT
CRC_STANDARD_CRC_CCITT_FALSE, ///< Standard CRC CCITT-FALSE
CRC_STANDARD_CRC_USB, ///< Standard CRC USB
CRC_STANDARD_CRC_IBM, ///< Standard CRC IBM
CRC_STANDARD_CRC_MODBUS, ///< Standard CRC MODBUS
CRC_STANDARD_CRC_ITU, ///< Standard CRC ITU
CRC_STANDARD_CRC_PMEQ_2, ///< Standard CRC PMEQ_2
CRC_STANDARD_CRC_XMODEM, ///< Standard CRC XMODEM
CRC_STANDARD_CRC_DNP, ///< Standard CRC DNP
CRC_STANDARD_CRC_NONE, ///< Standard CRC NONE
} crc_standard_crc_e;
/**
\brief CRC Status
*/
typedef struct {
uint32_t busy : 1; ///< busy flag
} crc_status_t;
/****** CRC Event *****/
typedef enum {
CRC_EVENT_CALCULATE_COMPLETE = 0, ///< Calculate completed
} crc_event_e;
typedef void (*crc_event_cb_t)(int32_t idx, crc_event_e event); ///< Pointer to \ref crc_event_cb_t : CRC Event call back.
/**
\brief CRC Device Driver Capabilities.
*/
typedef struct {
uint32_t ROHC : 1; ///< supports ROHC mode
uint32_t MAXIM : 1; ///< supports MAXIM mode
uint32_t X25 : 1; ///< supports X25 mode
uint32_t CCITT : 1; ///< supports CCITT mode
uint32_t CCITT_FALSE : 1; ///< supports CCITT-FALSE mode
uint32_t USB : 1; ///< supports USB mode
uint32_t IBM : 1; ///< supports IBM mode
uint32_t MODBUS : 1; ///< supports MODBUS mode
uint32_t ITU : 1; ///< supports ITU mode
uint32_t PMEQ_2 : 1; ///< supports PMEQ_2 mode
uint32_t XMODEM : 1; ///< supports XMODEM mode
uint32_t DNP : 1; ///< supports DNP mode
uint32_t NONE : 1; ///< supports NONE mode
} crc_capabilities_t;
// Function documentation
/**
\brief Initialize CRC Interface. 1. Initializes the resources needed for the CRC interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event event callback function \ref crc_event_cb_t
\return return crc handle if success
*/
crc_handle_t csi_crc_initialize(int32_t idx, crc_event_cb_t cb_event);
/**
\brief De-initialize CRC Interface. stops operation and releases the software resources used by the interface
\param[in] handle crc handle to operate.
\return error code
*/
int32_t csi_crc_uninitialize(crc_handle_t handle);
/**
\brief control crc power.
\param[in] handle crc handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_crc_power_control(crc_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref crc_capabilities_t
*/
crc_capabilities_t csi_crc_get_capabilities(int32_t idx);
/**
\brief config crc mode.
\param[in] handle crc handle to operate.
\param[in] mode \ref crc_mode_e
\param[in] standard \ref crc_standard_crc_e
\return error code
*/
int32_t csi_crc_config(crc_handle_t handle,
crc_mode_e mode,
crc_standard_crc_e standard
);
/**
\brief calculate crc. this function will pad zero if input data is not word aligned
\param[in] handle crc handle to operate.
\param[in] in Pointer to the input data
\param[out] out Pointer to the result.
\param[in] len intput data len.
\return error code
*/
int32_t csi_crc_calculate(crc_handle_t handle, const void *in, void *out, uint32_t len);
/**
\brief Get CRC status.
\param[in] handle crc handle to operate.
\return CRC status \ref crc_status_t
*/
crc_status_t csi_crc_get_status(crc_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_CRC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/crc.h | C | apache-2.0 | 5,314 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_dmac.h
* @brief header file for dmac driver
* @version V1.0
* @date 02. June 2017
* @model dmac
******************************************************************************/
#ifndef _CSI_DMA_H_
#define _CSI_DMA_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief DMA Driver Capabilities.
*/
typedef struct {
uint32_t unalign_addr : 1; ///< support for unalign address transfer when memory is source
} dma_capabilities_t;
typedef enum {
DMA_STATE_FREE = 0, ///< DMA channel not yet initialized or disabled
DMA_STATE_READY, ///< DMA channel process success and ready for use, but not start yet
DMA_STATE_BUSY, ///< DMA channel process is ongoing
DMA_STATE_DONE, ///< DMA channel transfer done
DMA_STATE_ERROR, ///< DMA channel transfer error
} dma_status_e;
/****** DMA specific error codes *****/
typedef enum {
EDRV_DMA_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
} dma_error_e;
/****** DMA Event *****/
typedef enum {
DMA_EVENT_TRANSFER_DONE = 0, ///< transfer complete
DMA_EVENT_TRANSFER_HALF_DONE = 1, ///< transfer half done
DMA_EVENT_TRANSFER_MODE_DONE = 2, ///< transfer complete in a certain dma trigger mode.
DMA_EVENT_CAHNNEL_PEND = 3, ///< it happens when there is a low priority channel was preempted by a high priority channel
DMA_EVENT_TRANSFER_ERROR = 4, ///< transfer error
} dma_event_e;
typedef enum {
DMA_ADDR_INC = 0,
DMA_ADDR_DEC,
DMA_ADDR_CONSTANT
} dma_addr_inc_e;
typedef enum {
DMA_MEM2MEM = 0,
DMA_MEM2PERH,
DMA_PERH2MEM,
DMA_PERH2PERH,
} dma_trans_type_e;
typedef enum {
DMA_SINGLE_TRIGGER = 0,
DMA_GROUP_TRIGGER,
DMA_BLOCK_TRIGGER
} dma_trig_trans_mode_e;
typedef enum {
DMA_DIR_DEST = 0,
DMA_DIR_SOURCE
} dma_single_dir_e;
typedef enum {
DMA_ADDR_LITTLE = 0,
DMA_ADDR_BIG
} dma_addr_endian_e;
typedef enum {
DMA_MODE_HARDWARE = 0,
DMA_MODE_SOFTWARE
} dma_channel_req_mode_e;
typedef struct {
dma_addr_inc_e src_inc; ///< source address increment
dma_addr_inc_e dst_inc; ///< destination address increment
dma_addr_endian_e src_endian; ///< source read data little-big endian change control.
dma_addr_endian_e dst_endian; ///< destination write data little-big endian change control.
uint8_t src_tw; ///< source transfer width in byte
uint8_t dst_tw; ///< destination transfer width in byte
uint8_t hs_if; ///< a hardware handshaking interface (optional).
uint8_t preemption; ///< determine whether if a channel can be preempted by a higher priority channel, 0 -- not allow preempt, 1 -- allow preempt.
dma_trans_type_e type; ///< transfer type
dma_trig_trans_mode_e mode; ///< channel trigger mode
dma_channel_req_mode_e ch_mode; ///< software or hardware to tigger dma channel work.
dma_single_dir_e single_dir; ///< after select single mode control for source(read) or destination(write) transfer.
uint32_t group_len; ///< group transaction length (unit: bytes) when use DMA_GROUP_TRIGGER mode.
uint32_t src_reload_en; ///< 1:dma enable src addr auto reload, 0:disable
uint32_t dest_reload_en; ///< 1:dma enable dst addr auto reload, 0:disable
} dma_config_t;
typedef void (*dma_event_cb_t)(int32_t ch, dma_event_e event, void *arg); ///< Pointer to \ref dma_event_cb_t : dmac event call back.
/**
\brief get one free dma channel
\param[in] ch channel num. if -1 then allocate a free channal in this dma
else allocate a fix channal
\return dma channel num. if -1 alloc channle error
*/
int32_t csi_dma_alloc_channel_ex(int32_t ch);
/**
\brief get one free dma channel
\return dma channel num. if -1 alloc channle error
*/
int32_t csi_dma_alloc_channel(void);
/**
\brief control dma power.
\param[in] ch dma channel num
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_dma_power_control(int32_t ch, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] ch dma channel num
\return \ref dma_capabilities_t
*/
dma_capabilities_t csi_dma_get_capabilities(int32_t ch);
/**
\brief release dma channel and related resources
\param[in] ch dma channel num
\return error code
*/
void csi_dma_release_channel(int32_t ch);
/**
\brief config dma channel
\param[in] ch dma channel num
\param[in] config dma channel transfer configure
\param[in] cb_event Pointer to \ref dma_event_cb_t
\return error code
*/
int32_t csi_dma_config_channel(int32_t ch, dma_config_t *config, dma_event_cb_t cb_event, void *cb_arg);
/**
\brief start generate dma channel signal.
\param[in] ch dma channel num
\param[in] psrcaddr dma transfer source address
\param[in] pdstaddr dma transfer destination address
\param[in] length dma transfer length (unit: bytes).
*/
void csi_dma_start(int32_t ch, void *psrcaddr, void *pdstaddr, uint32_t length);
/**
\brief Stop generate dma channel signal.
\param[in] ch dma channel num
*/
void csi_dma_stop(int32_t ch);
/**
\brief start generate dma channel cyclic transfer.
\param[in] ch dma channel num
\param[in] psrcaddr dma transfer source address
\param[in] pdstaddr dma transfer destination address
\param[in] cycle_len The length of a cycle
\param[in] cycle_num the number of a cycle
\return error code
*/
int32_t csi_dma_cyclic_prep(int32_t ch, void *psrcaddr, void *pdstaddr, uint32_t cycle_len, uint32_t cycle_num);
/**
\brief start generate dma channel cyclic transfer.
\param[in] ch dma channel num
*/
void csi_dma_cyclic_start(int32_t ch);
/**
\brief Stop generate dma channel cyclic transfer.
\param[in] ch dma channel num
*/
void csi_dma_cyclic_stop(int32_t ch);
/**
\brief Get DMA channel status.
\param[in] ch dma channel num
\return DMA status \ref dma_status_e
*/
dma_status_e csi_dma_get_status(int32_t ch);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_DMA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/dmac.h | C | apache-2.0 | 6,729 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_dpu.h
* @brief header file for dpu driver
* @version V1.6
* @date 27. May 2019
* @model dpu
******************************************************************************/
#ifndef _DRV_DPU_H_
#define _DRV_DPU_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for dpu handle.
typedef void *dpu_handle_t;
typedef uint32_t dpu_rgba32_t; /* rrggbbaa */
/*----- DPU interrupt event type -----*/
typedef enum {
DPU_EVENT_VSYNC = 0, ///< VSYNC event
DPU_EVENT_HSYNC, ///< HSYNC event
} dpu_event_e;
/*----- DPU extend error type -----*/
typedef enum {
DPU_ERROR_GET_CONFIG_TYPE = (DRV_ERROR_SPECIFIC + 1),
DPU_ERROR_SET_CONFIG_TYPE,
} dpu_errno_e;
/*----- DPU color mode type -----*/
typedef enum {
DPU_COLORMODE_RGBA8888 = 0, ///< 32-bit RGBA mode
DPU_COLORMODE_ABGR8888, ///< 32-bit ABGR mode
DPU_COLORMODE_ARGB8888, ///< 32-bit ARGB mode
DPU_COLORMODE_BGRA8888, ///< 32-bit BGRA mode
DPU_COLORMODE_RGB888, ///< 24-bit RGB mode
DPU_COLORMODE_RGB565, ///< 16-bit RGB mode
DPU_COLORMODE_RGBA5551, ///< 16-bit RGBA mode
DPU_COLORMODE_RGBA4444, ///< 16-bit RGBA mode
DPU_COLORMODE_RGBA3320, ///< 8-bit RGBA mode
DPU_COLORMODE_L1, ///< 1-bit Grayscale mode from 0(black) to 1 (white)
DPU_COLORMODE_L4, ///< 4-bit Grayscale mode from 0(black) to 15 (white)
DPU_COLORMODE_L8, ///< 8-bit Grayscale mode from 0(black) to 255 (white)
DPU_COLORMODE_PALETTE8, ///< 8-bit Palatte(looked-up table) mode
DPU_COLORMODE_YUYV, ///< 32-bit/2-pixels YUV422 mode. (Y0 U0 Y1 V0)
DPU_COLORMODE_YUY2, ///< 32-bit/2-pixels YUV422 mode. (Y0 U0 Y1 V0)
DPU_COLORMODE_YUV420SP, ///< 48-bit/4-pixels YUV420 planar mode. (YYYY..UV..)
DPU_COLORMODE_YUV420P, ///< 48-bit/4-pixels YUV420 planar mode. (YYYY..U..V..)
} dpu_colormode_e;
/*----- DPU blend mode type -----*/
typedef enum {
/* Blended Color = Cs * Fs + Cd * Fd
* Cs: Color of source (previous layer)
* Cd: Color of destinaion (current layer)
* Fs: Factor of source (previous layer)
* Fd: Factor of destinaion (current layer)
*
* The factors are defined in below blend modes:
* Sa = Source alpha (pixel alpha in previous layer)
* Da = Destinaion alpha (pixel alpha in current layer)
* Ga = Global alpha (global alpha in layer configuration)
*/
DPU_BLENDMODE_SIMPLE = 0, ///< Sa * Sa + Da * (1 - Sa)
DPU_BLENDMODE_CLEAR, ///< 0
DPU_BLENDMODE_SRC, ///< Sa
DPU_BLENDMODE_SRC_OVER, ///< Sa + Da * (1 - Sa)
DPU_BLENDMODE_DST_OVER, ///< Sa * (1 - Da) + Da
DPU_BLENDMODE_SRC_IN, ///< Sa * Da
DPU_BLENDMODE_DST_IN, ///< Da * Sa
DPU_BLENDMODE_SRC_OUT, ///< Sa * (1 - Da)
DPU_BLENDMODE_DST_OUT, ///< Da * (1 - Sa)
DPU_BLENDMODE_SRC_ATOP, ///< Sa * Da + Da * (1 - Sa)
DPU_BLENDMODE_DST_ATOP, ///< Sa * (1 - Da) + Da * Sa
DPU_BLENDMODE_ADD, ///< Sa + Da
DPU_BLENDMODE_XOR, ///< Sa * (1 - Da) + Da * (1 - Sa)
DPU_BLENDMODE_MIX, ///< Sa * Ga + Da
} dpu_blendmode_e;
/*----- LCD signal active mode -----*/
typedef enum {
DPU_SIGNAL_ACTIVE_LOW = 0,
DPU_SIGNAL_ACTIVE_HIGH = 1,
} dpu_signal_polarity_e;
/**
\brief LCD display timing info
*/
typedef struct {
uint32_t resolution_x; ///< Horizontal valid data width
uint32_t resolution_y; ///< Vertical valid data width
uint32_t hsync_width; ///< HSync pulse width
uint32_t vsync_width; ///< VSync pluse width
uint32_t front_porch_x; ///< HSync front porch
uint32_t front_porch_y; ///< VSync front porch
uint32_t back_porch_x; ///< HSync back porch
uint32_t back_porch_y; ///< VSync back porch
} dpu_cfg_display_timing_t;
/**
\brief LCD signal polarity config info
*/
typedef struct {
dpu_signal_polarity_e vsync; ///< vsync signal polarity
dpu_signal_polarity_e hsync; ///< hsync signal polarity
dpu_signal_polarity_e deta_enable; ///< deta_enable signal polarity
dpu_signal_polarity_e pixel_clock; ///< pixel_clock signal polarity
} dpu_cfg_display_signal_polarity_t;
/**
\brief DPU layer config info
*/
typedef struct {
void *baseaddr; ///< picture store address
dpu_colormode_e colormode; ///< color mode of the picture
dpu_blendmode_e blendmode; ///< blend mode with other layer(s)
uint32_t resx; ///< resolution width of target display device
uint32_t resy; ///< resolution height of target display device
int32_t startx; ///< display horizontal position on target device
int32_t starty; ///< display vertical position on target device
uint32_t sizex; ///< display width on target device
uint32_t sizey; ///< display height on target device
uint8_t alpha; ///< display diaphaneity
} dpu_layer_cfg_t;
/**
\brief DPU cursor info
*/
typedef struct {
uint8_t width;
uint8_t height;
uint8_t *img_data;
} dpu_cursor_info_t;
///< Pointer to \ref dpu_event_cb_t : DPU Event call back.
typedef void (*dpu_event_cb_t)(dpu_handle_t handle, dpu_event_e event, void *user_data);
/**
\brief Initialize DPU Interface.
Initialize the resources needed for the DPU interface
\param[in] idx dpu index
\param[in] cb_event event call back function \ref dpu_event_cb_t
\return pointer to dpu instance
*/
dpu_handle_t csi_dpu_initialize(int32_t idx, dpu_event_cb_t cb_event, void *user_data);
/**
\brief De-initialize DPU Interface.
Stop operation and release the resources used by the interface
\param[in] handle dpu handle to operate.
\return error code
*/
int32_t csi_dpu_uninitialize(dpu_handle_t handle);
/**
\brief Start DPU Interface.
\param[in] handle dpu handle to operate.
\return error code
*/
int32_t csi_dpu_start(dpu_handle_t handle);
/**
\brief Stop DPU Interface.
\param[in] handle dpu handle to operate.
\return error code
*/
int32_t csi_dpu_stop(dpu_handle_t handle);
/**
\brief Configurate display parameters.
\param[in] handle dpu handle to operate.
\param[in] timing the display's timing parameters.
\param[in] polarity the display's signal parameters.
\return error code
*/
int32_t csi_dpu_config_display(dpu_handle_t handle,
dpu_cfg_display_timing_t *timing,
dpu_cfg_display_signal_polarity_t *polarity);
/**
\brief Wait for display vsync.
\param[in] handle dpu handle to operate.
\return error code
*/
int32_t csi_dpu_wait_vsync(dpu_handle_t handle);
/**
\brief Set background color.
\param[in] handle dpu handle to operate.
\param[in] color the background color.
\return error code
*/
int32_t csi_dpu_set_bgcolor(dpu_handle_t handle, dpu_rgba32_t color);
/**
\brief Set cursor image.
\param[in] handle dpu handle to operate.
\param[in] img cursor image address.
\return error code
*/
int32_t csi_dpu_cursor_set_img(dpu_handle_t handle, dpu_cursor_info_t *cursor);
/**
\brief Set cursor color palette.
\param[in] handle dpu handle to operate.
\param[in] index palette index.
\param[in] color palette color of index.
\return error code
*/
int32_t csi_dpu_cursor_set_palette(dpu_handle_t handle, uint32_t index, dpu_rgba32_t color);
/**
\brief Enable/Disable cursor
\param[in] handle dpu handle to operate.
\param[in] enable set cursor enable or not. 0:disable; 1:enable.
\return error code
*/
int32_t csi_dpu_cursor_enable(dpu_handle_t handle, int32_t enable);
/**
\brief Set cursor position.
\param[in] handle dpu handle to operate.
\param[in] x cursor's x position.
\param[in] y cursor's y position.
\return error code
*/
int32_t csi_dpu_cursor_set_position(dpu_handle_t handle, uint32_t x, uint32_t y);
/**
\brief Set layer's configuration parameters.
\param[in] handle dpu handle to operate.
\param[in] layer_id layer index number.
\param[in] config layer configuration parameters.
\return error code
*/
int32_t csi_dpu_layer_set_config(dpu_handle_t handle, uint8_t layer_id, dpu_layer_cfg_t *config);
/**
\brief Get layer's configuration parameters.
\param[in] handle dpu handle to operate.
\param[in] layer_id layer index number.
\param[out] config layer configuration parameters.
\return error code
*/
int32_t csi_dpu_layer_get_config(dpu_handle_t handle, uint8_t layer_id, dpu_layer_cfg_t *config);
/**
\brief Enable/Disable layer
\param[in] handle dpu handle to operate.
\param[in] layer_id layer index number.
\param[in] enable Set layer enable or not. 0:disable; 1:enable.
\return error code
*/
int32_t csi_dpu_layer_enable(dpu_handle_t handle, uint8_t layer_id, int32_t enable);
/**
\brief Set layer's palette lookup table color
\param[in] handle dpu handle to operate.
\param[in] layer_id layer index number.
\param[in] index the index of palette.
\param[in] color the color of the specific palette index.
\return error code
*/
int32_t csi_dpu_set_palette(dpu_handle_t handle, uint8_t layer_id,
uint32_t index, dpu_rgba32_t color);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_DPU_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/dpu.h | C | apache-2.0 | 9,892 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_eflash.h
* @brief header file for eflash driver
* @version V1.0
* @date 02. June 2017
* @model eflash
******************************************************************************/
#ifndef _CSI_EFLASH_H_
#define _CSI_EFLASH_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for eflash handle.
typedef void *eflash_handle_t;
/**
\brief Flash information
*/
typedef struct {
uint32_t start; ///< Chip Start address
uint32_t end; ///< Chip End address (start+size-1)
uint32_t sector_count; ///< Number of sectors
uint32_t sector_size; ///< Uniform sector size in bytes
uint32_t page_size; ///< Optimal programming page size in bytes
uint32_t program_unit; ///< Smallest programmable unit in bytes
uint8_t erased_value; ///< Contents of erased memory (usually 0xFF)
} eflash_info_t;
/**
\brief Flash Status
*/
typedef struct {
uint32_t busy : 1; ///< Flash busy flag
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
} eflash_status_t;
/****** EFLASH Event *****/
typedef enum {
EFLASH_EVENT_READY = 0, ///< Flash Ready
EFLASH_EVENT_ERROR, ///< Read/Program/Erase Error
} eflash_event_e;
typedef void (*eflash_event_cb_t)(int32_t idx, eflash_event_e event); ///< Pointer to \ref eflash_event_cb_t : EFLASH Event call back.
/**
\brief Flash Driver Capabilities.
*/
typedef struct {
uint32_t event_ready : 1; ///< Signal Flash Ready event
uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
uint32_t erase_chip : 1; ///< Supports EraseChip operation
} eflash_capabilities_t;
// Function documentation
/**
\brief Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event event callback function \ref eflash_event_cb_t
\return pointer to eflash handle
*/
eflash_handle_t csi_eflash_initialize(int32_t idx, eflash_event_cb_t cb_event);
/**
\brief De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface
\param[in] handle eflash handle to operate.
\return error code
*/
int32_t csi_eflash_uninitialize(eflash_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref eflash_capabilities_t
*/
eflash_capabilities_t csi_eflash_get_capabilities(int32_t idx);
/**
\brief control eflash power.
\param[in] handle eflash handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_eflash_power_control(eflash_handle_t handle, csi_power_stat_e state);
/**
\brief Read data from Flash.
\param[in] handle eflash handle to operate.
\param[in] addr Data address.
\param[out] data Pointer to a buffer storing the data read from Flash.
\param[in] cnt Number of data items to read.
\return number of data items read or error code
*/
int32_t csi_eflash_read(eflash_handle_t handle, uint32_t addr, void *data, uint32_t cnt);
/**
\brief Program data to Flash.
\param[in] handle eflash handle to operate.
\param[in] addr Data address.
\param[in] data Pointer to a buffer containing the data to be programmed to Flash.
\param[in] cnt Number of data items to program.
\return number of data items programmed or error code
*/
int32_t csi_eflash_program(eflash_handle_t handle, uint32_t addr, const void *data, uint32_t cnt);
/**
\brief Erase Flash Sector.
\param[in] handle eflash handle to operate.
\param[in] addr Sector address
\return error code
*/
int32_t csi_eflash_erase_sector(eflash_handle_t handle, uint32_t addr);
/**
\brief Erase complete Flash.
\param[in] handle eflash handle to operate.
\return error code
*/
int32_t csi_eflash_erase_chip(eflash_handle_t handle);
/**
\brief Get Flash information.
\param[in] handle eflash handle to operate.
\return Pointer to Flash information \ref eflash_info_t
*/
eflash_info_t *csi_eflash_get_info(eflash_handle_t handle);
/**
\brief Get FLASH status.
\param[in] handle eflash handle to operate.
\return EFLASH status \ref eflash_status_t
*/
eflash_status_t csi_eflash_get_status(eflash_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_EFLASH_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/eflash.h | C | apache-2.0 | 4,907 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_efusec.h
* @brief header file for efusec driver
* @version V1.0
* @date 22. Mar 2019
* @model efusec
******************************************************************************/
#ifndef _CSI_EFUSEC_H_
#define _CSI_EFUSEC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for efusec handle.
typedef void *efusec_handle_t;
/**
\brief Flash information
*/
typedef struct {
uint32_t start; ///< Chip Start address
uint32_t end; ///< Chip End address (start+size-1)
uint32_t page_size; ///< Optimal programming page size in bytes
uint32_t program_unit; ///< Smallest programmable unit in bytes
} efusec_info_t;
/**
\brief Flash Status
*/
typedef struct {
uint32_t mode : 1; ///< 0: read mode 1: program mode
uint32_t lock_shadow : 1; ///< lock shadow regs
uint32_t lock_efuse : 1; ///< lock efusec
} efusec_status_t;
typedef enum {
EFUSEC_LOCK_SHADOW = 0, ///< all shadow regs can’t be programmed
EFUSEC_LOCK_EFUSE ///< all Efuse can’t be programmed
} efusec_lock_e;
/**
\brief Flash Driver Capabilities.
*/
typedef struct {
uint32_t lock_shadow : 1; ///< Supports lock shadow operation
} efusec_capabilities_t;
// Function documentation
/**
\brief Initialize EFUSEC Interface. 1. Initializes the resources needed for the EFUSEC interface
\param[in] idx device id
\return pointer to efusec handle
*/
efusec_handle_t drv_efusec_initialize(int32_t idx);
/**
\brief De-initialize EFUSEC Interface. stops operation and releases the software resources used by the interface
\param[in] handle efusec handle to operate.
\return error code
*/
int32_t csi_efusec_uninitialize(efusec_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref efusec_capabilities_t
*/
efusec_capabilities_t drv_efusec_get_capabilities(int32_t idx);
/**
\brief control efusec power.
\param[in] handle efusec handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t drv_efusec_power_control(efusec_handle_t handle, csi_power_stat_e state);
/**
\brief Read data from Flash.
\param[in] handle efusec handle to operate.
\param[in] addr Data address.
\param[out] data Pointer to a buffer storing the data read from Flash.
\param[in] cnt Number of data items to read.
\return number of data items read or error code
*/
int32_t drv_efusec_read(efusec_handle_t handle, uint32_t addr, void *data, uint32_t cnt);
/**
\brief Program data to Flash.
\param[in] handle efusec handle to operate.
\param[in] addr Data address.
\param[in] data Pointer to a buffer containing the data to be programmed to Flash.
\param[in] cnt Number of data items to program.
\return number of data items programmed or error code
*/
int32_t drv_efusec_program(efusec_handle_t handle, uint32_t addr, const void *data, uint32_t cnt);
/**
\brief lock efusec.
\param[in] handle efusec handle to operate.
\param[in] lock efusec lock type \ref efusec_lock_e.
\return error code
*/
int32_t drv_efusec_lock(efusec_handle_t handle, efusec_lock_e lock);
/**
\brief Get Flash information.
\param[in] handle efusec handle to operate.
\return Pointer to Flash information \ref efusec_info_t
*/
efusec_info_t *drv_efusec_get_info(efusec_handle_t handle);
/**
\brief Get FLASH status.
\param[in] handle efusec handle to operate.
\return EFUSEC status \ref efusec_status_t
*/
efusec_status_t drv_efusec_get_status(efusec_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_EFUSEC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/efusec.h | C | apache-2.0 | 4,099 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_errno.h
* @brief header file for error num
* @version V1.2
* @date 22. May 2019
******************************************************************************/
#ifndef _DRV_ERRNO_H_
#define _DRV_ERRNO_H_
#include <errno.h>
#ifdef __cplusplus
extern "C" {
#endif
#define ERRNO_DRV_START 0X80
/* driver General error codes */
typedef enum {
DRV_ERROR = ERRNO_DRV_START, ///< Unspecified error
DRV_ERROR_BUSY, ///< Driver is busy
DRV_ERROR_TIMEOUT, ///< Timeout occurred
DRV_ERROR_UNSUPPORTED, ///< Operation not supported
DRV_ERROR_PARAMETER, ///< Parameter error
DRV_ERROR_SPECIFIC ///< Start of driver specific errors
} drv_err_e;
/** Get error type */
#define GET_ERROR_TYPE(errno) \
(error & 0xFF000000 >> 24)
/** Get error module */
#define GET_ERROR_MODULE(error) \
(error & 0x00FF0000 >> 16)
/** Get error API */
#define GET_ERROR_API(error) \
(error & 0x0000FF00 >> 8)
/** Get errno */
#define GET_ERROR_NUM(error) \
(error & 0x000000FF)
#ifndef CSI_DRV_ERRNO_BASE
#define CSI_DRV_ERRNO_BASE 0x81000000
#endif
/** driver module id definition*/
#define CSI_DRV_ERRNO_GPIO_BASE 0x81010000
#define CSI_DRV_ERRNO_USART_BASE 0x81020000
#define CSI_DRV_ERRNO_SPI_BASE 0x81030000
#define CSI_DRV_ERRNO_IIC_BASE 0x81040000
#define CSI_DRV_ERRNO_PWM_BASE 0x81050000
#define CSI_DRV_ERRNO_RTC_BASE 0x81060000
#define CSI_DRV_ERRNO_TIMER_BASE 0x81070000
#define CSI_DRV_ERRNO_WDT_BASE 0x81080000
#define CSI_DRV_ERRNO_AES_BASE 0x81090000
#define CSI_DRV_ERRNO_CRC_BASE 0x810A0000
#define CSI_DRV_ERRNO_RSA_BASE 0x810B0000
#define CSI_DRV_ERRNO_SHA_BASE 0x810C0000
#define CSI_DRV_ERRNO_TRNG_BASE 0x810D0000
#define CSI_DRV_ERRNO_EFLASH_BASE 0x810E0000
#define CSI_DRV_ERRNO_DMA_BASE 0x810F0000
#define CSI_DRV_ERRNO_NORFLASH_BASE 0x81100000
#define CSI_DRV_ERRNO_INTC_BASE 0x81110000
#define CSI_DRV_ERRNO_SPU_BASE 0x81120000
#define CSI_DRV_ERRNO_ADC_BASE 0x81130000
#define CSI_DRV_ERRNO_PMU_BASE 0x81140000
#define CSI_DRV_ERRNO_BMU_BASE 0x81150000
#define CSI_DRV_ERRNO_ETB_BASE 0x81160000
#define CSI_DRV_ERRNO_I2S_BASE 0x81170000
#define CSI_DRV_ERRNO_USI_BASE 0x81180000
#define CSI_DRV_ERRNO_SPIFLASH_BASE 0x81190000
#define CSI_DRV_ERRNO_ACMP_BASE 0x811A0000
#define CSI_DRV_ERRNO_MAILBOX_BASE 0x811B0000
#define CSI_DRV_ERRNO_EFUSEC_BASE 0x811C0000
#define CSI_DRV_ERRNO_CODEC_BASE 0x811D0000
#define CSI_DRV_ERRNO_DPU_BASE 0x811E0000
#define CSI_DRV_ERRNO_VPU_BASE 0x811F0000
#define CSI_DRV_ERRNO_CAMERA_BASE 0x81200000
#define CSI_DRV_ERRNO_MIPI_CSI_BASE 0x81210000
#define CSI_DRV_ERRNO_MIPI_CSI_READER_BASE 0x81220000
#define CSI_DRV_ERRNO_GMAC_BASE 0x81230000
#define CSI_DRV_ERRNO_ETHPHY_BASE 0x81240000
#define CSI_DRV_ERRNO_QW_EFUSE_BASE 0x81250000
#define CSI_DRV_ERRNO_RESET_BASE 0x81260000
#ifdef __cplusplus
}
#endif
#endif /* CSI_DRV_ERRNO_H */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/errno.h | C | apache-2.0 | 3,536 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_etb.h
* @brief header file for event trigger driver
* @version V1.0
* @date 27. octorber 2017
* @model etb
******************************************************************************/
#ifndef _CSI_ETB_H_
#define _CSI_ETB_H_
#include <stdint.h>
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ETB_SOURCE = 0,
ETB_DEST = 1
}
etb_direct_e;
typedef enum {
ETB_HARDWARE = 0, ///< etb channel inout is hardware trigger.
ETB_SOFTWWARE ///< etb channel inout is software trigger.
} etb_source_type_e;
typedef enum {
ETB_ONE_TRIGGER_ONE = 0,
ETB_ONE_TRIGGER_MORE = 1,
ETB_MORE_TRIGGER_ONE = 2
} etb_channel_func_e;
/// definition for etb handle.
typedef void *etb_handle_t;
typedef struct {
uint32_t busy : 1;
} etb_status_t;
typedef enum {
ETB_EVENT_CHANNEL_BUSY = 0, ///<
ETB_EVENT_MODE_FAULT ///<
} etb_event_e;
/**
\brief ETB Driver Capabilities.
*/
typedef struct {
uint32_t sync_trigger : 1;
uint32_t async_trigger : 1;
uint32_t etb_31_channel : 1;
uint32_t one_trigger_one : 1;
uint32_t one_trigger_more : 1;
uint32_t more_trigger_one : 1;
} etb_capabilities_t;
typedef void (*etb_event_cb_t)(int32_t idx, etb_event_e event); ///< Pointer to \ref etb_event_cb_t : etb Event call back.
/**
\brief Get driver capabilities.
\param[in] idx etb index.
\return \ref etb_capabilities_t
*/
etb_capabilities_t drv_etb_get_capabilities(int32_t idx);
/**
\brief config etb channel.
\param[in] source_lo a specific number represent a location in an source trigger location map to trigger other ip(s).
\param[in] dest_lo a specific number represent an location in an dest trigger map to wait signal(s) from source ip(s) or location(s).
\param[in] source_type \ref etb_source_type_e the input source is hardware trigger or software trigger.
\param[in] mode \ref etb_channel_func_e channel function.
\return channel nubmber or error code (negative).
*/
int32_t drv_etb_channel_config(uint32_t source_ip, uint32_t dest_ip, etb_source_type_e source_type, etb_channel_func_e mode);
/**
\brief start etb.
\param[in] channel etb channel number to operate.
\return none
*/
void drv_etb_start(int32_t channel);
/**
\brief stop etb.
\param[in] channel etb channel number to operate.
\return none
*/
void drv_etb_stop(int32_t channel);
/**
\brief Get ETB status.
\param[in] ch etb channel to operate.
\return ETB status \ref etb_status_t
*/
etb_status_t drv_etb_get_status(int32_t channel);
#endif /* _CSI_ETB_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/etb.h | C | apache-2.0 | 2,871 |
/**
* Copyright (C) 2016 CSI Project. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _CSI_NET_H_
#define _CSI_NET_H_
#ifdef __cplusplus
extern "C" {
#endif
#define CSI_ETH_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
/**
\brief Driver Version
*/
typedef struct csi_driver_version {
uint16_t api; ///< API version
uint16_t drv; ///< Driver version
} csi_drv_version_t;
/* General return codes */
#define CSI_ETH_OK 0 ///< Operation succeeded
#define CSI_ETH_ERROR CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error
#define CSI_ETH_ERROR_BUSY CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy
#define CSI_ETH_ERROR_TIMEOUT CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred
#define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported
#define CSI_ETH_ERROR_PARAMETER CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error
#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors
/**
\brief General power states
*/
typedef enum eth_power_state {
CSI_ETH_POWER_OFF, ///< Power off: no operation possible
CSI_ETH_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
CSI_ETH_POWER_FULL ///< Power on: full operation at maximum performance
} eth_power_state_t;
/**
\brief Ethernet Media Interface type
*/
#define CSI_ETH_INTERFACE_MII (0) ///< Media Independent Interface (MII)
#define CSI_ETH_INTERFACE_RMII (1) ///< Reduced Media Independent Interface (RMII)
#define CSI_ETH_INTERFACE_SMII (2) ///< Serial Media Independent Interface (SMII)
/**
\brief Ethernet link speed
*/
#define CSI_ETH_SPEED_10M (0) ///< 10 Mbps link speed
#define CSI_ETH_SPEED_100M (1) ///< 100 Mbps link speed
#define CSI_ETH_SPEED_1G (2) ///< 1 Gpbs link speed
/**
\brief Ethernet duplex mode
*/
#define CSI_ETH_DUPLEX_HALF (0) ///< Half duplex link
#define CSI_ETH_DUPLEX_FULL (1) ///< Full duplex link
/**
\brief Ethernet auto-negotiation
*/
#define CSI_ETH_AUTONEG_DISABLE (0) ///< Disable auto-negotiation
#define CSI_ETH_AUTONEG_ENABLE (1) ///< Enable auto-negotiation
/**
\brief Ethernet link state
*/
typedef enum eth_link_state {
ETH_LINK_DOWN, ///< Link is down
ETH_LINK_UP ///< Link is up
} eth_link_state_t;
/**
\brief Ethernet link information
*/
typedef volatile struct eth_link_info {
uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full
uint32_t autoneg : 1; ///< Set the interface to Auto Negotiation mode of transmission parameters
uint32_t loopback : 1; ///< Set the interface into a Loop-back test mode
uint32_t isolation : 1; ///< Set to indicate electrical isolation of PHY interface from MII/RMII interface
uint32_t reserved : 26;
} eth_link_info_t;
/**
\brief Ethernet MAC Address
*/
typedef struct eth_mac_addr {
uint8_t b[6]; ///< MAC Address (6 bytes), MSB first
} eth_mac_addr_t;
#ifdef __cplusplus
}
#endif
#endif /* CSI_NET_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/eth.h | C | apache-2.0 | 4,021 |
/**
* Copyright (C) 2016 CSI Project. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _CSI_ETH_H_
#define _CSI_ETH_H_
#include <stdbool.h>
#include "drv/eth.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void *eth_mac_handle_t;
#define MAX_FRAMELEN 1518 /* (note: maximum ethernet frame length would be 1518) */
#define CSI_ETH_MAC_API_VERSION CSI_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */
#define _CSI_Driver_ETH_MAC_(n) Driver_ETH_MAC##n
#define CSI_Driver_ETH_MAC_(n) _CSI_Driver_ETH_MAC_(n)
/****** Ethernet MAC Control Codes *****/
#define CSI_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration
#define CSI_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled
#define CSI_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled
#define CSI_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = CSI_ETH_MAC_FLUSH_...
#define CSI_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
#define CSI_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional CSI_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
#define DRV_ETH_MAC_ADJUST_LINK (0x07) ///< Adjust MAC link state according to phy state; arg: phy handle
#define DRV_ETH_MAC_CONTROL_IRQ (0x08) ///< Interrupt request; arg: 0=disable, 1=enable
/*----- Ethernet MAC Configuration -----*/
#define CSI_ETH_MAC_SPEED_Pos 0
#define CSI_ETH_MAC_SPEED_Msk (3UL << CSI_ETH_MAC_SPEED_Pos)
#define CSI_ETH_MAC_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed
#define CSI_ETH_MAC_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed
#define CSI_ETH_MAC_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed
#define CSI_ETH_MAC_DUPLEX_Pos 2
#define CSI_ETH_MAC_DUPLEX_Msk (1UL << CSI_ETH_MAC_DUPLEX_Pos)
#define CSI_ETH_MAC_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
#define CSI_ETH_MAC_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
#define CSI_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode
#define CSI_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload
#define CSI_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload
#define CSI_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address
#define CSI_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address
#define CSI_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode)
/*----- Ethernet MAC Flush Flags -----*/
#define CSI_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer
#define CSI_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer
/*----- Ethernet MAC VLAN Filter Flag -----*/
#define CSI_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
/****** Ethernet MAC Frame Transmit Flags *****/
#define CSI_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment
#define CSI_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted
#define CSI_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp
/****** Ethernet MAC Timer Control Codes *****/
#define CSI_ETH_MAC_TIMER_GET_TIME (0x01) ///< Get current time
#define CSI_ETH_MAC_TIMER_SET_TIME (0x02) ///< Set new time
#define CSI_ETH_MAC_TIMER_INC_TIME (0x03) ///< Increment current time
#define CSI_ETH_MAC_TIMER_DEC_TIME (0x04) ///< Decrement current time
#define CSI_ETH_MAC_TIMER_SET_ALCSI (0x05) ///< Set alarm time
#define CSI_ETH_MAC_TIMER_ADJUST_CLOCK (0x06) ///< Adjust clock frequency; time->ns: correction factor * 2^31
/**
\brief Ethernet MAC Time
*/
typedef struct eth_mac_time {
uint32_t ns; ///< Nano seconds
uint32_t sec; ///< Seconds
} eth_mac_time_t;
/****** Ethernet MAC Event *****/
#define CSI_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received
#define CSI_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted
#define CSI_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet)
#define CSI_ETH_MAC_EVENT_TIMER_ALCSI (1UL << 3) ///< Timer Alarm
#define CSI_ETH_MAC_EVENT_LINK_CHANGE (1UL << 4) ///< Link state
typedef void (*eth_event_cb_t)(int32_t idx, uint32_t event); ///< Pointer to \ref eth_event_cb_t : Signal Ethernet Event.
typedef enum {
FRAME_FILTER_RULE_POSITIVE_MATCHING = 0, /*!< Specifies that a filter should match a given pattern */
FRAME_FILTER_RULE_NEGATIVE_MATCHING = 1, /*!< Specifies that a filter should NOT match a given pattern */
} frame_filter_rule_t;
/**
\brief Ethernet MAC Capabilities
*/
typedef struct eth_capabilities {
uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive
uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive
uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive
uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive
uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive
uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit
uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit
uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit
uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit
uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit
uint32_t media_interface : 2; ///< Ethernet Media Interface type
uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address
uint32_t event_rx_frame : 1; ///< 1 = callback event generated
uint32_t event_tx_frame : 1; ///< 1 = callback event generated
uint32_t event_wakeup : 1; ///< 1 = wakeup event generated
uint32_t precision_timer : 1; ///< 1 = Precision Timer supported
uint32_t reserved : 15; ///< Reserved (must be zero)
} eth_capabilities_t;
/**
* Structure describing a frame filter list item
*/
typedef struct {
uint32_t id; /*!< Unique identifier for a packet filter item */
frame_filter_rule_t rule; /*!< Filter matches are either POSITIVE or NEGATIVE matching */
uint16_t offset; /*!< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */
uint16_t mask_size; /*!< Size of the mask in bytes */
uint8_t *mask; /*!< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */
uint8_t *pattern; /*!< Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */
bool enabled_status; /*!< When returned from mhd_get_packet_filters, indicates if the filter is enabled */
} eth_frame_filter_t;
struct eth_frame_filter_list {
struct eth_frame_filter_list *next;
};
typedef struct eth_frame_filter_list eth_frame_filter_list_t;
typedef struct {
eth_event_cb_t cb_event;
eth_capabilities_t capabilities;
} eth_mac_priv_t;
/**
\brief Get driver version.
\param[in] handle ethernet handle
\return ethernet version including chip version and driver version
*/
csi_drv_version_t csi_eth_mac_get_version(eth_mac_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return ethernet capabilities
*/
eth_capabilities_t csi_eth_mac_get_capabilities(int32_t idx);
/**
\brief This function is used to initialize Ethernet device and related resource, an event callback is registered. It is called when the middleware component like TCPIP starts operation.
\param[in] idx device id
\param[in] cb callback to handle ethernet event
\return return ethernet handle if success
*/
eth_mac_handle_t csi_eth_mac_initialize(int32_t idx, eth_event_cb_t cb_event);
/**
\brief This function is used to de-initialize Ethernet device. It is called when the middleware component stops operation and releases the software resources used by the interface.
\param[in] handle ethernet handle
\return error code
*/
int32_t csi_eth_mac_uninitialize(eth_mac_handle_t handle);
/**
\brief Control Ethernet MAC Device Power.
\param[in] handle ethernet handle
\param[in] state Power state
\return error code
*/
int32_t csi_eth_mac_power_control(eth_mac_handle_t handle, eth_power_state_t state);
/**
\brief Get Ethernet MAC Address.
\param[in] handle ethernet handle
\param[in] mac Pointer to address
\return error code
*/
int32_t csi_eth_mac_get_macaddr(eth_mac_handle_t handle, eth_mac_addr_t *mac);
/**
\brief Set Ethernet MAC Address.
\param[in] handle ethernet handle
\param[in] mac Pointer to address
\return error code
*/
int32_t csi_eth_mac_set_macaddr(eth_mac_handle_t handle, const eth_mac_addr_t *mac);
/**
\brief Configure Address Filter.
\param[in] handle ethernet handle
\param[in] addr Pointer to addresses
\param[in] num_addr Number of addresses to configure
\return error code
*/
int32_t csi_eth_mac_set_addrfilter(eth_mac_handle_t handle, const eth_mac_addr_t *addr, uint32_t num_addr);
/**
\brief Send Ethernet frame.
\param[in] handle ethernet handle
\param[in] frame Pointer to frame buffer with data to send
\param[in] len Frame buffer length in bytes
\param[in] flags Frame transmit flags (see CSI_ETH_MAC_TX_FRAME_...)
\return error code
*/
int32_t csi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len, uint32_t flags);
/**
\brief Read data of received Ethernet frame.
\param[in] handle ethernet handle
\param[in] frame Pointer to frame buffer for data to read into
\param[in] len Frame buffer length in bytes
\return number of data bytes read or execution status
- value >= 0: number of data bytes read
- value < 0: error occurred, value is execution status as defined with execution_status
*/
int32_t csi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t len);
/**
\brief Request data of received Ethernet frame.
drv_eth_mac_request_frame() and drv_eth_mac_release_frame()
must be called in pairs.
\param[in] handle ethernet handle
\param[in] frame Pointer to frame buffer pointer
\return number of data bytes read or execution status
- value >= 0: number of data bytes read
- value < 0: error occurred
*/
int32_t drv_eth_mac_request_frame(eth_mac_handle_t handle, uint8_t **frame);
/**
\brief Release current Ethernet frame.
drv_eth_mac_request_frame() and drv_eth_mac_release_frame()
must be called in pairs.
\param[in] handle ethernet handle
\return error code
*/
int32_t drv_eth_mac_release_frame(eth_mac_handle_t handle);
/**
\brief Get size of received Ethernet frame.
\param[in] handle ethernet handle
\return number of bytes in received frame
*/
int32_t csi_eth_mac_get_rx_framesize(eth_mac_handle_t handle);
/**
\brief Get time of received Ethernet frame.
\param[in] handle ethernet handle
\param[in] time Pointer to time structure for data to read into
\return error code
*/
int32_t csi_eth_mac_get_rx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time);
/**
\brief Get time of transmitted Ethernet frame.
\param[in] handle ethernet handle
\param[in] time Pointer to time structure for data to read into
\return error code
*/
int32_t csi_eth_mac_get_tx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time);
/**
\brief Control Ethernet Interface.
\param[in] handle ethernet handle
\param[in] control Operation
\param[in] arg Argument of operation (optional)
\return error code
*/
int32_t csi_eth_mac_control(eth_mac_handle_t handle, uint32_t control, uint32_t arg);
/**
\brief Control Precision Timer.
\param[in] handle ethernet handle
\param[in] control Operation
\param[in] time Pointer to time structure
\return error code
*/
int32_t csi_eth_mac_control_time(eth_mac_handle_t handle, uint32_t control, eth_mac_time_t *time);
/**
\brief Read Ethernet PHY Register through Management Interface.
\param[in] handle ethernet handle
\param[in] phy_addr 5-bit device address
\param[in] reg_addr 5-bit register address
\param[out] data Pointer where the result is written to
\return error code
*/
int32_t csi_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
/**
\brief Write Ethernet PHY Register through Management Interface.
\param[in] handle ethernet handle
\param[in] phy_addr 5-bit device address
\param[in] reg_addr 5-bit register address
\param[in] data 16-bit data to write
\return error code
*/
int32_t csi_eth_mac_phy_write(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
/**
\brief Callback function that signals a Ethernet Event.
\param[in] handle ethernet handle
\param[in] event event notification mask
\return none
*/
void csi_eth_mac_signal_event(eth_mac_handle_t handle, uint32_t event);
/**
\brief Add Frame Filter Setting with Filter ID.
\param[in] handle ethernet handle
\param[in] filter Pointer to filter setting
\return error code
*/
int32_t csi_eth_mac_add_framefilter(eth_mac_handle_t handle, const eth_frame_filter_t *filter);
/**
\brief Remove Frame Filter Setting.
\param[in] handle ethernet handle
\param[in] filter_id Frame Filter ID
\return error code
*/
int32_t csi_eth_mac_remove_framefilter(eth_mac_handle_t handle, uint32_t filter_id);
/**
\brief Enable/Disable Specified Frame Filter ID.
\param[in] handle ethernet handle
\param[in] filter_id Frame Filter ID
\param[in] en Enable or disable
\return error code
*/
int32_t csi_eth_mac_en_framefilter(eth_mac_handle_t handle, uint32_t filter_id, bool en);
/**
\brief Get frame filter table list.
\param[in] handle ethernet handle
\param[in] list frame filter table list
\param[in] count_out the count of filter setting added
\param[in] max_count max filter setting can be supported
\return error code
*/
int32_t csi_eth_mac_get_framefilter(eth_mac_handle_t handle, eth_frame_filter_list_t *list, uint32_t *count_out, uint32_t max_count);
#ifdef __cplusplus
}
#endif
#endif
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/eth_mac.h | C | apache-2.0 | 16,165 |
/**
* Copyright (C) 2016 CSI Project. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _CSI_ETH_PHY_H_
#define _CSI_ETH_PHY_H_
#include "drv/eth.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void *eth_phy_handle_t;
#define CSI_ETH_PHY_API_VERSION CSI_ETH_VERSION_MAJOR_MINOR(2,1) /* API version */
#define _CSI_Driver_ETH_PHY_(n) Driver_ETH_PHY##n
#define CSI_Driver_ETH_PHY_(n) _CSI_Driver_ETH_PHY_(n)
/****** Ethernet PHY Mode *****/
#define CSI_ETH_PHY_SPEED_Pos 0
#define CSI_ETH_PHY_SPEED_Msk (3UL << CSI_ETH_PHY_SPEED_Pos)
#define CSI_ETH_PHY_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed
#define CSI_ETH_PHY_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed
#define CSI_ETH_PHY_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed
#define CSI_ETH_PHY_DUPLEX_Pos 2
#define CSI_ETH_PHY_DUPLEX_Msk (1UL << CSI_ETH_PHY_DUPLEX_Pos)
#define CSI_ETH_PHY_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
#define CSI_ETH_PHY_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
#define CSI_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode
#define CSI_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode
#define CSI_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface
typedef int32_t (*csi_eth_phy_read_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Read Ethernet PHY Register.
typedef int32_t (*csi_eth_phy_write_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Write Ethernet PHY Register.
typedef struct {
csi_eth_phy_read_t phy_read;
csi_eth_phy_write_t phy_write;
eth_link_info_t link_info;
} eth_phy_priv_t;
// Function documentation
/**
\brief Get driver version.
\param[in] handle ethernet phy handle
\return driver version
*/
csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle);
/**
\brief Initialize Ethernet PHY Device.
\param[in] fn_read
\param[in] fn_write
\return ethernet phy handle
*/
eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write);
/**
\brief De-initialize Ethernet PHY Device.
\param[in] handle ethernet phy handle
\return error code
*/
int32_t csi_eth_phy_uninitialize(eth_phy_handle_t handle);
/**
\brief Control Ethernet PHY Device Power.
\param[in] handle ethernet phy handle
\param[in] state Power state
\return error code
*/
int32_t csi_eth_phy_power_control(eth_phy_handle_t handle, eth_power_state_t state);
/**
\brief Set Ethernet Media Interface.
\param[in] handle ethernet phy handle
\param[in] interface Media Interface type
\return error code
*/
int32_t csi_eth_phy_set_interface(eth_phy_handle_t handle, uint32_t interface);
/**
\brief Set Ethernet PHY Device Operation mode.
\param[in] handle ethernet phy handle
\param[in] mode Operation Mode
\return error code
*/
int32_t csi_eth_phy_set_mode(eth_phy_handle_t handle, uint32_t mode);
/**
\brief Get Ethernet PHY Device Link state.
\param[in] handle ethernet phy handle
\return current link status \ref eth_link_state_t
*/
eth_link_state_t csi_eth_phy_get_linkstate(eth_phy_handle_t handle);
/**
\brief Get Ethernet PHY Device Link information.
\param[in] handle ethernet phy handle
\return current link parameters \ref eth_link_info_t
*/
eth_link_info_t csi_eth_phy_get_linkinfo(eth_phy_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/eth_phy.h | C | apache-2.0 | 4,431 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_gpio.h
* @brief header file for gpio driver
* @version V1.0
* @date 02. June 2017
* @model gpio
******************************************************************************/
#ifndef _CSI_GPIO_H_
#define _CSI_GPIO_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for gpio pin_handle.
typedef void *gpio_pin_handle_t;
/****** GPIO specific error codes *****/
typedef enum {
GPIO_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
GPIO_ERROR_DIRECTION, ///< Specified direction not supported
GPIO_ERROR_IRQ_MODE, ///< Specified irq mode not supported
} gpio_error_e;
/*----- GPIO Control Codes: Mode -----*/
typedef enum {
GPIO_MODE_PULLNONE = 0, ///< pull none for input
GPIO_MODE_PULLUP, ///< pull up for input
GPIO_MODE_PULLDOWN, ///< pull down for input
GPIO_MODE_OPEN_DRAIN, ///< open drain mode for output
GPIO_MODE_PUSH_PULL, ///< push-pull mode for output
} gpio_mode_e;
/*----- GPIO Control Codes: Mode Parameters: Data Bits -----*/
typedef enum {
GPIO_DIRECTION_INPUT = 0, ///< gpio as input
GPIO_DIRECTION_OUTPUT, ///< gpio as output
} gpio_direction_e;
/*----- GPIO Control Codes: Mode Parameters: Parity -----*/
typedef enum {
GPIO_IRQ_MODE_RISING_EDGE = 0, ///< interrupt mode for rising edge
GPIO_IRQ_MODE_FALLING_EDGE, ///< interrupt mode for falling edge
GPIO_IRQ_MODE_DOUBLE_EDGE, ///< interrupt mode for double edge
GPIO_IRQ_MODE_LOW_LEVEL, ///< interrupt mode for low level
GPIO_IRQ_MODE_HIGH_LEVEL, ///< interrupt mode for high level
} gpio_irq_mode_e;
typedef void (*gpio_event_cb_t)(int32_t idx); ///< gpio Event call back.
/**
\brief Initialize GPIO handle.
\param[in] gpio_pin gpio pin idx.
\param[in] cb_event event callback function \ref gpio_event_cb_t
\return gpio_pin_handle
*/
gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event);
/**
\brief De-initialize GPIO pin_handle.stops operation and releases the software resources used by the handle.
\param[in] handle gpio pin_handle to operate.
\return error code
*/
int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle);
/**
\brief control gpio power.
\param[in] handle gpio handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state);
/**
\brief config pin mode
\param[in] pin gpio pin_handle to operate.
\param[in] mode \ref gpio_mode_e
\return error code
*/
int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
gpio_mode_e mode);
/**
\brief config pin direction
\param[in] pin gpio pin_handle to operate.
\param[in] dir \ref gpio_direction_e
\return error code
*/
int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
gpio_direction_e dir);
/**
\brief config pin
\param[in] pin gpio pin_handle to operate.
\param[in] mode \ref gpio_mode_e
\param[in] dir \ref gpio_direction_e
\return error code
*/
int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
gpio_mode_e mode,
gpio_direction_e dir);
/**
\brief Set one or zero to the selected GPIO pin.
\param[in] pin gpio pin_handle to operate.
\param[in] value value to be set
\return error code
*/
int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value);
/**
\brief Get the value of selected GPIO pin.
\param[in] pin gpio pin_handle to operate.
\param[out] value buffer to store the pin value
\return error code
*/
int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value);
/**
\brief set GPIO interrupt mode.
\param[in] pin gpio pin_handle to operate.
\param[in] mode irq mode to be set
\param[in] enable enable flag
\return error code
*/
int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_GPIO_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/gpio.h | C | apache-2.0 | 4,736 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_i2s.h
* @brief header file for i2s driver
* @version V1.0
* @date 02. June 2017
* @model i2s
******************************************************************************/
#ifndef _DRV_I2S_H_
#define _DRV_I2S_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for i2s handle.
typedef void *i2s_handle_t;
/****** i2s specific error codes *****/
typedef enum {
I2S_ERROR_SYNCHRONIZATION = (DRV_ERROR_SPECIFIC + 1), ///< Specified Synchronization not supported
I2S_ERROR_PROTOCOL, ///< Specified Protocol not supported
I2S_ERROR_DATA_SIZE, ///< Specified Data size not supported
I2S_ERROR_BIT_ORDER, ///< Specified Bit order not supported
I2S_ERROR_MONO_MODE, ///< Specified Mono mode not supported
I2S_ERROR_COMPANDING, ///< Specified Companding not supported
I2S_ERROR_CLOCK_POLARITY, ///< Specified Clock polarity not supported
I2S_ERROR_AUDIO_FREQ, ///< Specified Audio frequency not supported
I2S_ERROR_MCLK_PIN, ///< Specified MCLK Pin setting not supported
I2S_ERROR_MCLK_PRESCALER, ///< Specified MCLK Prescaler not supported
I2S_ERROR_FRAME_LENGHT, ///< Specified Frame length not supported
I2S_ERROR_FRAME_SYNC_WIDTH, ///< Specified Frame Sync width not supported
I2S_ERROR_FRAME_SYNC_POLARITY, ///< Specified Frame Sync polarity not supported
I2S_ERROR_FRAME_SYNC_EARLY, ///< Specified Frame Sync early not supported
I2S_ERROR_SLOT_COUNT, ///< Specified Slot count not supported
I2S_ERROR_SLOT_SIZE, ///< Specified Slot size not supported
I2S_ERROR_SLOT_OFFESET ///< Specified Slot offset not supported
} i2s_error_e;
typedef enum {
I2S_MODE_TX_MASTER, ///< i2s transmitter master mode
I2S_MODE_TX_SLAVE, ///< i2s transmitter slave mode
I2S_MODE_RX_MASTER, ///< i2s receiver master mode
I2S_MODE_RX_SLAVE, ///< i2s receiver slave mode
///< full duplex mode only for idx0, if used full duplex mode, rx and tx must used same rate, mclk_freq, sclk_freq.
I2S_MODE_FULL_DUPLEX_MASTER, ///< i2s full duplex master mode
I2S_MODE_FULL_DUPLEX_SLAVE, ///< i2s full duplex slave mode
} i2s_mode_e;
typedef enum {
I2S_PROTOCOL_I2S, ///< i2s bus
I2S_PROTOCOL_MSB_JUSTIFIED, ///< MSB (left) justified
I2S_PROTOCOL_LSB_JUSTIFIED, ///< LSB (right) justified
I2S_PROTOCOL_PCM,
} i2s_protocol_e;
typedef enum {
I2S_SAMPLE_16BIT,
I2S_SAMPLE_24BIT,
I2S_SAMPLE_32BIT,
} i2s_sample_width_e;
typedef enum {
I2S_LEFT_POLARITY_LOW,
I2S_LEFT_POLARITY_HITH,
} i2s_left_channel_polarity_e;
typedef enum {
I2S_SCLK_32FS, ///< SCLK Freq = 32 * sample_rate, freq must >= sample_rate * sample_witch
I2S_SCLK_48FS,
I2S_SCLK_64FS,
I2S_SCLK_16FS,
} i2s_sclk_freq_e;
typedef enum {
I2S_MCLK_256FS = 256,
I2S_MCLK_384FS = 384,
} i2s_mclk_freq_e;
/**
\brief I2S Status
*/
typedef struct {
uint32_t tx_runing : 1; ///< Transmitter runing flag
uint32_t rx_runing : 1; ///< Receiver runing flag
uint32_t tx_fifo_empty : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
uint32_t rx_fifo_full : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation)
} i2s_status_t;
/****** I2S Event *****/
typedef enum {
I2S_EVENT_SEND_COMPLETE = (0x01 << 0), ///< Send completed
I2S_EVENT_RECEIVE_COMPLETE = (0x01 << 1), ///< Receive completed
I2S_EVENT_TX_BUFFER_EMPYT = (0x01 << 2), ///< Transmit buffer empty
I2S_EVENT_TX_UNDERFLOW = (0x01 << 3), ///< Transmit data not available
I2S_EVENT_RX_BUFFER_FULL = (0x01 << 4),
I2S_EVENT_RX_OVERFLOW = (0x01 << 5), ///< Receive data overflow
I2S_EVENT_FRAME_ERROR = (0x01 << 6), ///< Sync Frame error in Slave mode (optional)
} i2s_event_e;
/**
\brief i2s ctrl cmd.
*/
typedef enum {
I2S_STREAM_PAUSE,
I2S_STREAM_RESUME,
I2S_STREAM_STOP,
I2S_STREAM_START,
} i2s_ctrl_e;
/**
\brief i2s Driver Capabilities.
*/
typedef struct {
uint32_t protocol_user : 1; ///< supports user defined Protocol
uint32_t protocol_i2s : 1; ///< supports I2S Protocol
uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol
uint32_t protocol_pcm : 1;
uint32_t mono_mode : 1; ///< supports Mono mode
uint32_t full_duplex : 1;
uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin
uint32_t event_frame_error : 1; ///< supports Frame error event: ARM_SAI_EVENT_FRAME_ERROR
} i2s_capabilities_t;
typedef enum {
I2S_RX_RIGHT_CHANNEL,
I2S_RX_LEFT_CHANNEL,
} i2s_rx_mono_channel;
typedef struct {
i2s_mode_e mode;
i2s_protocol_e protocol;
i2s_sample_width_e width;
i2s_left_channel_polarity_e left_polarity; ///< set ws signel left channle polarity
i2s_sclk_freq_e sclk_freq; ///< I2S sclk freq select. example:32fs = 32 * sample_rate
i2s_mclk_freq_e mclk_freq; ///< I2S mclk freq select. example:256fs = 256 * sample_rate
int32_t tx_mono_enable; ///< used for tx or full duplex mode, tx mono mode enable. 1 eanble, 0 disable
int32_t rx_mono_enable; ///< used for rx or full duplex mode,rx mono mode enable. 1 eanble, 0 disable
i2s_rx_mono_channel rx_mono_select_ch; ///< used for rx or full duplex mode,
} i2s_config_type_t;
typedef struct {
i2s_config_type_t cfg;
uint32_t rate;
uint32_t tx_period; ///< i2s send bytes tigger cb
uint32_t rx_period; ///< i2s receive bytes tigger cb
uint8_t *tx_buf; ///< i2s send buf
uint32_t tx_buf_length; ///< i2s send buf length
uint8_t *rx_buf; ///< i2s recv buf
uint32_t rx_buf_length; ///< i2s recv buf length
} i2s_config_t;
typedef void (*i2s_event_cb_t)(int32_t idx, i2s_event_e event, void *arg); ///< Pointer to \ref i2s_event_cb_t : i2s Event call back.
/**
\brief Initialize I2S Interface. 1. Initializes the resources needed for the I2S index 2.registers event callback function
\param[in] idx i2s index
\param[in] cb_event Pointer to \ref i2s_event_cb_t
\param[in] cb_arg event callback arg
\return pointer to i2s instances
*/
i2s_handle_t csi_i2s_initialize(int32_t idx, i2s_event_cb_t cb_event, void *cb_arg);
/**
\brief De-initialize I2S Interface. stops operation and releases the software resources used by the interface
\param[in] handle i2s handle to operate.
\return 0 for success, negative for error code
*/
int32_t csi_i2s_uninitialize(i2s_handle_t handle);
/**
\brief enable the i2s module
\param[in] handle i2s handle to operate.
\param[in] en: 1 enable, 0 disable
\return none
*/
void csi_i2s_enable(i2s_handle_t handle, int en);
/**
\brief Get driver capabilities.
\param[in] idx i2s index.
\return \ref i2s_capabilities_t
*/
i2s_capabilities_t csi_i2s_get_capabilities(int32_t idx);
/**
\brief config i2s attributes.
\param[in] handle i2s handle to operate.
\param[in] config i2s config.
\return 0 for success, negative for error code
*/
int32_t csi_i2s_config(i2s_handle_t handle, i2s_config_t *config);
/**
\brief sending data to i2s transmitter.
\param[in] handle i2s handle to operate.
\param[in] data Pointer to buffer for data to send
\param[in] data_size size of tranmitter data
\return send data size.(bytes)
*/
uint32_t csi_i2s_send(i2s_handle_t handle, const uint8_t *data, uint32_t length);
/**
\brief receiving data from i2s receiver.
\param[in] handle i2s handle to operate.
\param[in] data Pointer to buffer for data to receive from i2s receiver
\param[in] data_size size of receiver data
\return receive data size.(bytes)
*/
uint32_t csi_i2s_receive(i2s_handle_t handle, uint8_t *buf, uint32_t length);
/**
\brief control the i2s transfer.
\param[in] handle i2s handle to operate.
\param[in] cmd i2s ctrl command
\return 0 for success, negative for error code
*/
int32_t csi_i2s_send_ctrl(i2s_handle_t handle, i2s_ctrl_e cmd);
/**
\brief control the i2s receive.
\param[in] handle i2s handle to operate.
\param[in] cmd i2s ctrl command
\return 0 for success, negative for error code
*/
int32_t csi_i2s_receive_ctrl(i2s_handle_t handle, i2s_ctrl_e cmd);
/**
\brief Get i2s status.
\param[in] handle i2s handle to operate.
\return i2s status \ref i2s_status_e
*/
i2s_status_t csi_i2s_get_status(i2s_handle_t handle);
/**
\brief control I2S power.
\param[in] handle i2s handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_i2s_power_control(i2s_handle_t handle, csi_power_stat_e state);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_I2S_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/i2s.h | C | apache-2.0 | 10,064 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_iic.h
* @brief header file for iic driver
* @version V1.0
* @date 02. June 2017
* @model iic
******************************************************************************/
#ifndef _CSI_IIC_H_
#define _CSI_IIC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for iic handle.
typedef void *iic_handle_t;
/*----- IIC Control Codes: Mode -----*/
typedef enum {
IIC_MODE_MASTER, ///< IIC Master
IIC_MODE_SLAVE ///< IIC Slave
} iic_mode_e;
/*----- IIC Control Codes: IIC Bus Speed -----*/
typedef enum {
IIC_BUS_SPEED_STANDARD = 0, ///< Standard Speed (100kHz)
IIC_BUS_SPEED_FAST = 1, ///< Fast Speed (400kHz)
IIC_BUS_SPEED_FAST_PLUS = 2, ///< Fast+ Speed ( 1MHz)
IIC_BUS_SPEED_HIGH = 3 ///< High Speed (3.4MHz)
} iic_speed_e;
/*----- IIC Control Codes: IIC Address Mode -----*/
typedef enum {
IIC_ADDRESS_7BIT = 0, ///< 7-bit address mode
IIC_ADDRESS_10BIT = 1 ///< 10-bit address mode
} iic_address_mode_e;
/**
\brief IIC Status
*/
typedef struct {
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master
uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver
uint32_t general_call : 1; ///< General Call(address 0) indication (cleared on start of next Slave operation)
uint32_t arbitration_lost : 1; ///< Master lost arbitration(in case of multi-masters) (cleared on start of next Master operation)
uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation)
} iic_status_t;
/****** IIC Event *****/
typedef enum {
IIC_EVENT_TRANSFER_DONE = 0, ///< Master/Slave Transmit/Receive finished
IIC_EVENT_TRANSFER_INCOMPLETE = 1, ///< Master/Slave Transmit/Receive incomplete transfer
IIC_EVENT_SLAVE_TRANSMIT = 2, ///< Slave Transmit operation requested
IIC_EVENT_SLAVE_RECEIVE = 3, ///< Slave Receive operation requested
IIC_EVENT_ADDRESS_NACK = 4, ///< Address not acknowledged from Slave
IIC_EVENT_GENERAL_CALL = 5, ///< General Call indication
IIC_EVENT_ARBITRATION_LOST = 6, ///< Master lost arbitration
IIC_EVENT_BUS_ERROR = 7, ///< Bus error detected (START/STOP at illegal position)
IIC_EVENT_BUS_CLEAR = 8 ///< Bus clear finished
} iic_event_e;
typedef void (*iic_event_cb_t)(int32_t idx, iic_event_e event); ///< Pointer to \ref iic_event_cb_t : IIC Event call back.
/**
\brief IIC Driver Capabilities.
*/
typedef struct {
uint32_t address_10_bit : 1; ///< supports 10-bit addressing
} iic_capabilities_t;
/**
\brief Initialize IIC Interface specified by pins. \n
1. Initializes the resources needed for the IIC interface 2.registers event callback function
\param[in] idx iic index
\param[in] cb_event event callback function \ref iic_event_cb_t
\return 0 for success, negative for error code
*/
iic_handle_t csi_iic_initialize(int32_t idx, iic_event_cb_t cb_event);
/**
\brief De-initialize IIC Interface. stops operation and releases the software resources used by the interface
\param[in] handle iic handle to operate.
\return 0 for success, negative for error code
*/
int32_t csi_iic_uninitialize(iic_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx iic index
\return \ref iic_capabilities_t
*/
iic_capabilities_t csi_iic_get_capabilities(int32_t idx);
/**
\brief config iic attributes.
\param[in] handle iic handle to operate.
\param[in] mode iic mode \ref iic_mode_e. if negative, then this attribute not changed.
\param[in] speed iic speed \ref iic_speed_e. if negative, then this attribute not changed.
\param[in] addr_mode iic address mode \ref iic_address_mode_e. if negative, then this attribute not changed.
\param[in] slave_addr iic address of slave. if negative, then this attribute not changed.
\return 0 for success, negative for error code
*/
int32_t csi_iic_config(iic_handle_t handle,
iic_mode_e mode,
iic_speed_e speed,
iic_address_mode_e addr_mode,
int32_t slave_addr);
/**
\brief Start transmitting data as IIC Master.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref csi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] devaddr iic addrress of slave device. |_BIT[7:1]devaddr_|_BIT[0]R/W_|
eg: BIT[7:0] = 0xA0, devaddr = 0x50.
\param[in] data data to send to IIC Slave
\param[in] num Number of data items to send
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
Master generates STOP condition (if xfer_pending is "false")
\return 0 for success, negative for error code
*/
int32_t csi_iic_master_send(iic_handle_t handle, uint32_t devaddr, const void *data, uint32_t num, bool xfer_pending);
/**
\brief Start receiving data as IIC Master.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref csi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] devaddr iic addrress of slave device.
\param[out] data Pointer to buffer for data to receive from IIC receiver
\param[in] num Number of data items to receive
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
\return 0 for success, negative for error code
*/
int32_t csi_iic_master_receive(iic_handle_t handle, uint32_t devaddr, void *data, uint32_t num, bool xfer_pending);
/**
\brief Start transmitting data as IIC Slave.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref csi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] data Pointer to buffer with data to transmit to IIC Master
\param[in] num Number of data items to send
\return 0 for success, negative for error code
*/
int32_t csi_iic_slave_send(iic_handle_t handle, const void *data, uint32_t num);
/**
\brief Start receiving data as IIC Slave.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref csi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[out] data Pointer to buffer for data to receive from IIC Master
\param[in] num Number of data items to receive
\return 0 for success, negative for error code
*/
int32_t csi_iic_slave_receive(iic_handle_t handle, void *data, uint32_t num);
/**
\brief abort transfer.
\param[in] handle iic handle to operate.
\return 0 for success, negative for error code
*/
int32_t csi_iic_abort_transfer(iic_handle_t handle);
/**
\brief Get IIC status.
\param[in] handle iic handle to operate.
\return IIC status \ref iic_status_t
*/
iic_status_t csi_iic_get_status(iic_handle_t handle);
/**
\brief control IIC power.
\param[in] handle iic handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_iic_power_control(iic_handle_t handle, csi_power_stat_e state);
/**
\brief config iic mode.
\param[in] handle iic handle to operate.
\param[in] mode \ref iic_mode_e
\return error code
*/
int32_t csi_iic_config_mode(iic_handle_t handle, iic_mode_e mode);
/**
\brief config iic speed.
\param[in] handle iic handle to operate.
\param[in] speed \ref iic_speed_e
\return error code
*/
int32_t csi_iic_config_speed(iic_handle_t handle, iic_speed_e speed);
/**
\brief config iic address mode.
\param[in] handle iic handle to operate.
\param[in] addr_mode \ref iic_address_mode_e
\return error code
*/
int32_t csi_iic_config_addr_mode(iic_handle_t handle, iic_address_mode_e addr_mode);
/**
\brief config iic slave address.
\param[in] handle iic handle to operate.
\param[in] slave_addr slave address
\return error code
*/
int32_t csi_iic_config_slave_addr(iic_handle_t handle, int32_t slave_addr);
/**
\brief Get IIC transferred data count.
\param[in] handle iic handle to operate.
\return the number of the currently transferred data items
*/
uint32_t csi_iic_get_data_count(iic_handle_t handle);
/**
\brief Send START command.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t csi_iic_send_start(iic_handle_t handle);
/**
\brief Send STOP command.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t csi_iic_send_stop(iic_handle_t handle);
/**
\brief Reset IIC peripheral.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t csi_iic_reset(iic_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_IIC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/iic.h | C | apache-2.0 | 9,760 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_intc.h
* @brief header file for intc driver
* @version V1.0
* @date 02. June 2017
* @model intc
******************************************************************************/
#ifndef _CSI_INTC_H_
#define _CSI_INTC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum int_trigger_mode_t {
INT_MODE_LOW_LEVEL,
INT_MODE_HIGH_LEVEL,
INT_MODE_RISING_EDGE,
INT_MODE_FALLING_EDGE,
INT_MODE_DOUBLE_EDGE,
}
int_trigger_mode_t;
/**
\brief initialize the INTC interrupt controller
\param [in] prio_bits the priority bits of INTC interrupt controller.
*/
void csi_intc_init(void);
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the INTC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_enable_irq(int32_t IRQn);
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the INTC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_disable_irq(int32_t IRQn);
/**
\brief Get Pending Interrupt
\details Reads the pending register in the INTC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
uint32_t csi_intc_get_pending_irq(int32_t IRQn);
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
void csi_intc_set_pending_irq(int32_t IRQn);
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_clear_pending_irq(int32_t IRQn);
/**
\brief Get Wake up Interrupt
\details Reads the wake up register in the INTC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
uint32_t csi_intc_get_wakeup_irq(int32_t IRQn);
/**
\brief Set Wake up Interrupt
\details Sets the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
void csi_intc_set_wakeup_irq(int32_t IRQn);
/**
\brief Clear Wake up Interrupt
\details Clears the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_clear_wakeup_irq(int32_t IRQn);
/**
\brief Get Active Interrupt
\details Reads the active register in the INTC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
uint32_t csi_intc_get_active(int32_t IRQn);
/**
\brief Set Threshold register
\details set the threshold register in the INTC.
\param [in] VectThreshold specific vecter threshold.
\param [in] PrioThreshold specific priority threshold.
*/
void csi_intc_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold);
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
void csi_intc_set_prio(int32_t IRQn, uint32_t priority);
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
uint32_t csi_intc_get_prio(int32_t IRQn);
/**
\brief funciton is acknowledge the IRQ. this interface is internally used by irq system
\param[in] irq irq number to operate
\return 0 on success; -1 on failure
*/
int csi_intc_ack_irq(int32_t IRQn);
/**
\briefThis function is set the attributes of an IRQ.
\param[in] irq irq number to operate
\param[in] priority interrupt priority
\param[in] trigger_mode interrupt trigger_mode
\return 0 on success; -1 on failure
*/
int csi_intc_set_attribute(int32_t IRQn, uint32_t priority, int_trigger_mode_t trigger_mode);
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in g_irqvector[].
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
void csi_intc_set_vector(int32_t IRQn, uint32_t handler);
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
uint32_t csi_intc_get_vector(int32_t IRQn);
#endif /* _CSI_INTC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/intc.h | C | apache-2.0 | 5,541 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_irq.h
* @brief header File for IRQ Driver
* @version V1.0
* @date 21. Dec 2018
* @model irq
******************************************************************************/
#include <stdint.h>
/**
\brief enable irq.
\param[in] irq_num Number of IRQ.
\return None.
*/
void drv_irq_enable(uint32_t irq_num);
/**
\brief disable irq.
\param[in] irq_num Number of IRQ.
\return None.
*/
void drv_irq_disable(uint32_t irq_num);
/**
\brief register irq handler.
\param[in] irq_num Number of IRQ.
\param[in] irq_handler IRQ Handler.
\return None.
*/
void drv_irq_register(uint32_t irq_num, void *irq_handler);
/**
\brief unregister irq handler.
\param[in] irq_num Number of IRQ.
\param[in] irq_handler IRQ Handler.
\return None.
*/
void drv_irq_unregister(uint32_t irq_num);
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/irq.h | C | apache-2.0 | 1,072 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_mailbox.h
* @brief header file for mailbox driver
* @version V1.0
* @date 28. Jan 2019
* @model mailbox
******************************************************************************/
#ifndef _CSI_MAILBOX_H_
#define _CSI_MAILBOX_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
int count;
struct {
uint32_t mailbox_id;
uint32_t tx_chnl;
uint32_t rx_chnl;
} config[];
} mailbox_chnl_config_t;
/// definition for mailbox handle.
typedef void *mailbox_handle_t;
/****** MAILBOX Event *****/
typedef enum {
MAILBOX_EVENT_SEND_COMPLETE = 0, ///< Send completed; however mailbox may still transmit data
MAILBOX_EVENT_RECEIVED = 1, ///< Data Received, only in mailbox buf, call memcpy() get the data
} mailbox_event_e;
typedef void (*mailbox_event_cb_t)(mailbox_handle_t handle, int32_t mailbox_id, uint32_t received_len, mailbox_event_e event); ///< Pointer to \ref mailbox_event_cb_t : MAILBOX Event call back.
/**
\brief Initialize MAILBOX Interface. 1. Initializes the resources needed for the MAILBOX interface 2.registers event callback function
\param[in] cb_event event call back function \ref mailbox_event_cb_t
\return return mailbox handle if success
*/
mailbox_handle_t csi_mailbox_initialize(mailbox_event_cb_t cb_event);
/**
\brief De-initialize MAILBOX Interface. stops operation and releases the software resources used by the interface
\param[in] handle mailbox handle to operate.
\return error code
*/
int32_t csi_mailbox_uninitialize(mailbox_handle_t handle);
/**
\brief Start sending data to MAILBOX transmitter,(received data is ignored).
This function is non-blocking,\ref mailbox_event_e is signaled when operation completes or error happens.
\ref csi_mailbox_get_status can get operation status.
\param[in] handle mailbox handle to operate.
\param[in] mailbox_id index of dest mailbox
\param[in] data Pointer to buffer with data to send to MAILBOX transmitter.
\param[in] num Number of data items to send
\return sent number of data
*/
int32_t csi_mailbox_send(mailbox_handle_t handle, int32_t mailbox_id, const void *data, uint32_t num);
/**
\brief Start Receiving data from Mailbox receiver.
\param[in] handle mailbox handle to operate.
\param[in] mailbox_id index of dest mailbox
\param[out] data Pointer to buffer with data to receive from mailbox.
\param[in] num Number of data items to receive
\return received number or error code
*/
int32_t csi_mailbox_receive(mailbox_handle_t handle, int32_t mailbox_id, void *data, uint32_t num);
/**
\brief enable mailbox ch irq
\param[in] cb_event event call back function \ref mailbox_event_cb_t
\return return mailbox handle if success
*/
int32_t csi_mailbox_chnl_enable(mailbox_handle_t handle, int32_t mailbox_id);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_MAILBOX_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/mailbox.h | C | apache-2.0 | 3,231 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_mipi_csi.h
* @brief header file for mipi_csi driver
* @version V1.2
* @date 27. May 2019
******************************************************************************/
#ifndef _DRV_MIPI_CSI_H_
#define _DRV_MIPI_CSI_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for mipi csi handle.
typedef void *mipi_csi_handle_t;
/**** IPI Data Types ****/
typedef enum {
MIPI_YUV420_8 = 0x18,
MIPI_YUV420_10 = 0x19,
MIPI_YUV420_8_LEG = 0x1A,
MIPI_YUV420_8_SHIFT = 0x1C,
MIPI_YUV420_10_SHIFT = 0x1D,
MIPI_YUV422_8 = 0x1E,
MIPI_YUV422_10 = 0x1F,
MIPI_RGB444 = 0x20,
MIPI_RGB555 = 0x21,
MIPI_RGB565 = 0x22,
MIPI_RGB666 = 0x23,
MIPI_RGB888 = 0x24,
MIPI_RAW6 = 0x28,
MIPI_RAW7 = 0x29,
MIPI_RAW8 = 0x2A,
MIPI_RAW10 = 0x2B,
MIPI_RAW12 = 0x2C,
MIPI_RAW14 = 0x2D,
} mipi_csi_data_format_e;
/**
\brief mipi config structure
*/
typedef struct {
mipi_csi_data_format_e data_format; ///< Output format
uint16_t lane_count; ///< the count of lane
} mipi_csi_config_t;
/****** MIPI Event *****/
typedef enum {
MIPI_CSI_EVENT_RECEIVED_ERROR = 0, ///< Receive data error.
} mipi_csi_event_e;
typedef void (*mipi_csi_event_cb_t)(mipi_csi_handle_t handle, mipi_csi_event_e event, void *user_data); //< Pointer to \ref mipi_event_cb_t : MIPI Event call back.
/**
\brief Initialize MIPI CSI Interface. 1. Initializes the resources needed for the MIPI interface 2.registers event callback function
\param[in] idx mipi index
\param[in] cb_event event call back function \ref mipi_event_cb_t
\return return mipi handle if success
*/
mipi_csi_handle_t csi_mipi_csi_initialize(int32_t idx, mipi_csi_event_cb_t cb_event, void *user_data);
/**
\brief De-initialize MIPI CSI Interface. stops operation and releases the software resources used by the interface
\param[in] handle mipi handle to operate.
\return error code
*/
int32_t csi_mipi_csi_uninitialize(mipi_csi_handle_t handle);
/**
\brief Start the mipi csi.
\param[in] handle mipi csi handle to operate.
\param[in] config Pointer of mipi_config_t with data to set to MIPI conteroller.
\return error code
*/
int32_t csi_mipi_csi_start(mipi_csi_handle_t handle, mipi_csi_config_t *config);
/**
\brief Stop the mipi.
\param[in] handle mipi handle to operate.
\return error code
*/
int32_t csi_mipi_csi_stop(mipi_csi_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_MIPI_CSI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/mipi_csi.h | C | apache-2.0 | 2,956 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_mipi_csi_reader.h
* @brief header file for mipi csi reader
* @version V1.4
* @date 27. May 2019
******************************************************************************/
#ifndef _DRV_MIPI_CSI_READER_H_
#define _DRV_MIPI_CSI_READER_H_
#include <drv/common.h>
#include <drv/mipi_csi.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for mipi_csi_reader handle.
typedef void *mipi_csi_reader_handle_t;
/****** MIPI CSI READER Event *****/
typedef enum {
MIPI_CSI_READER_EVENT_RECEIVE_ERROR = 0, ///< Receive data error
MIPI_CSI_READER_EVENT_FRAME_READY = 1, ///< Receive data ready
} mipi_csi_reader_event_e;
typedef enum {
MIPI_CSI_READER_NO_ERROR = 0, ///< No error
MIPI_CSI_READER_ERROR_CRC = 1, ///< occur CRC error
MIPI_CSI_READER_ERROR_PIXEL_NUM = 2, ///< occur pixel number
} mipi_csi_reader_error_e;
typedef struct {
mipi_csi_data_format_e format; ///< frame format
uint32_t height; ///< frame height
uint32_t width; ///< frame width
uint8_t **frame_list; ///< output frame address list
uint8_t frame_count; ///< frame count
uint8_t mipi_id; ///< the mipi id to connect
} mipi_csi_reader_config_t;
typedef struct {
uint32_t index; ///< frame index
uint8_t *addr; ///< frame address
mipi_csi_data_format_e format; ///< frame format
uint32_t height; ///< frame height
uint32_t width; ///< frame width
uint32_t size; ///< frame size
} mipi_csi_reader_frame_t;
typedef void (*mipi_csi_reader_event_cb_t)(mipi_csi_reader_handle_t handle, mipi_csi_reader_event_e event, void *user_data); ///< Pointer to \ref mipi_csi_reader_event_cb_t : MIPI_CSI_READER Event call back.
/**
\brief Initialize mipi csi reader Interface. 1. Initializes the resources needed for the mipi csi reader interface 2.registers event callback function
\param[in] idx mipi_csi_reader index
\param[in] cb_event event call back function \ref mipi_csi_reader_event_cb_t
\return return mipi csi reader handle if success
*/
mipi_csi_reader_handle_t csi_mipi_csi_reader_initialize(int32_t idx, mipi_csi_reader_event_cb_t cb_event, void *user_data);
/**
\brief De-initialize mipi csi reader Interface. stops operation and releases the software resources used by the interface
\param[in] handle mipi csi reader handle to operate.
\return error code
*/
int32_t csi_mipi_csi_reader_uninitialize(mipi_csi_reader_handle_t handle);
/**
\brief Config the mipi csi reader and start to work
\param[in] handle mipi csi reader handle to operate.
\param[in] input the config of mipi csi reader.
\return error code
*/
int32_t csi_mipi_csi_reader_start(mipi_csi_reader_handle_t handle, mipi_csi_reader_config_t *input);
/**
\brief Stop the mipi csi reader
\param[in] handle mipi csi reader handle to operate.
\return error code
*/
int32_t csi_mipi_csi_reader_stop(mipi_csi_reader_handle_t handle);
/**
\brief Hold the specific frame.
\param[in] handle mipi csi reader handle to operate.
\param[in] frame the frame to hold.
\return error code.
*/
int32_t csi_mipi_csi_reader_hold_frame(mipi_csi_reader_handle_t handle, uint8_t *frame);
/**
\brief Release the specific frame.
\param[in] handle mipi csi reader handle to operate.
\param[in] frame the frame to release.
\return error code.
*/
int32_t csi_mipi_csi_reader_release_frame(mipi_csi_reader_handle_t handle, uint8_t *frame);
/**
\brief Get the frame idx when frame ready.
\param[in] handle mipi csi reader handle to operate.
\param[out] frame the ready frame.
\return error code.
*/
int32_t csi_mipi_csi_reader_get_frame(mipi_csi_reader_handle_t handle, mipi_csi_reader_frame_t *frame);
/**
\brief When get frame error, output the error type.
\param[in] handle mipi csi reader handle to operate.
\param[out] error output the error type.
\param[out] frame output the error frame address, when *fram is NULL, it represent unkonw frame.
\return error code.
*/
int32_t csi_mipi_csi_reader_get_error_info(mipi_csi_reader_handle_t handle, mipi_csi_reader_error_e *error, uint8_t **frame);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_MIPI_CSI_READER_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/mipi_csi_reader.h | C | apache-2.0 | 4,658 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_norflash.h
* @brief header file for norflash driver
* @version V1.0
* @date 02. June 2017
* @model norflash
******************************************************************************/
#ifndef _CSI_NORFLASH_H_
#define _CSI_NORFLASH_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for norflash handle.
typedef void *norflash_handle_t;
/**
\brief Flash information
*/
typedef struct {
uint32_t start; ///< Chip Start address
uint32_t end; ///< Chip End address (start+size-1)
uint32_t sector_count; ///< Number of sectors
uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used)
uint32_t page_size; ///< Optimal programming page size in bytes
uint32_t program_unit; ///< Smallest programmable unit in bytes
uint8_t erased_value; ///< Contents of erased memory (usually 0xFF)
} norflash_info;
/**
\brief Flash Status
*/
typedef struct {
uint32_t busy : 1; ///< Flash busy flag
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
} norflash_status_t;
/****** NORFLASH Event *****/
typedef enum {
NORFLASH_EVENT_READY = 0, ///< Flash Ready
NORFLASH_EVENT_ERROR, ///< Read/Program/Erase Error
} norflash_event_e;
typedef void (*norflash_event_cb_t)(int32_t idx, norflash_event_e event); ///< Pointer to \ref norflash_event_cb_t : NORFLASH Event call back.
/**
\brief Flash Driver Capabilities.
*/
typedef struct {
uint32_t event_ready : 1; ///< Signal Flash Ready event
uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
uint32_t erase_chip : 1; ///< Supports EraseChip operation
} norflash_capabilities_t;
// Function documentation
/**
\brief Get driver capabilities.
\param[in] handle norflash handle to operate.
\return \ref norflash_capabilities_t
*/
norflash_capabilities_t csi_norflash_get_capabilities(int32_t idx);
/**
\brief Initialize NORFLASH Interface. 1. Initializes the resources needed for the NORFLASH interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event Pointer to \ref norflash_event_cb_t
\return pointer to norflash handle
*/
norflash_handle_t csi_norflash_initialize(int32_t idx, norflash_event_cb_t cb_event);
/**
\brief control norflash power.
\param[in] handle norflash handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_norflash_power_control(norflash_handle_t handle, csi_power_stat_e state);
/**
\brief De-initialize NORFLASH Interface. stops operation and releases the software resources used by the interface
\param[in] handle norflash handle to operate.
\return error code
*/
int32_t csi_norflash_uninitialize(norflash_handle_t handle);
/**
\brief Read data from Flash.
\param[in] handle norflash handle to operate.
\param[in] addroffset read address offset.
\param[out] dstbuf Pointer to a buffer storing the data read from Flash.
\param[in] len Number of data items to read.
\return number of data items read or error code
*/
int32_t csi_norflash_read(norflash_handle_t handle, uint32_t addroffset, void *dstbuf, uint32_t len);
/**
\brief Read id num from Flash.
\param[in] handle norflash handle to operate.
\param[in] id Pointer to a buffer storing the id num.
\return error code
*/
int32_t csi_norflash_readid(norflash_handle_t handle, void *id);
/**
\brief Program data to Flash.
\param[in] handle norflash handle to operate.
\param[in] addroffset program address offset.
\param[in] srcbuf Pointer to a buffer containing the data to be programmed to Flash..
\param[in] len Number of data items to program.
\return number of data items programmed or error code
*/
int32_t csi_norflash_write(norflash_handle_t handle, uint32_t addroffset, const void *srcbuf, uint32_t len);
/**
\brief Erase Flash Sector.
\param[in] handle norflash handle to operate.
\param[in] addroffset erase address offset
\param[in] num erase sector num
\return error code
*/
int32_t csi_norflash_erase_sector(norflash_handle_t handle, uint32_t addroffset, uint32_t num);
/**
\brief Erase complete Flash.
\param[in] handle norflash handle to operate.
\return error code
*/
int32_t csi_norflash_erase_chip(norflash_handle_t handle);
/**
\brief Get Flash information.
\param[in] handle norflash handle to operate.
\return Pointer to Flash information \ref norflash_info
*/
norflash_info *csi_norflash_get_info(norflash_handle_t handle);
/**
\brief Get NORFLASH status.
\param[in] handle norflash handle to operate.
\return NORFLASH status \ref norflash_status_t
*/
norflash_status_t csi_norflash_get_status(norflash_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_NORFLASH_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/norflash.h | C | apache-2.0 | 5,422 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_pmu.h
* @brief header file for pmu driver
* @version V1.0
* @date 02. June 2017
* @model pmu
******************************************************************************/
#ifndef _CSI_PMU_H_
#define _CSI_PMU_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for pmu handle.
typedef void *pmu_handle_t;
/****** PMU specific error codes *****/
typedef enum {
EDRV_PMU_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
} pmu_error_e;
/*----- PMU Control Codes: Mode -----*/
typedef enum {
PMU_MODE_RUN = 0, ///< Running mode
PMU_MODE_SLEEP, ///< Sleep mode
PMU_MODE_DOZE, ///< Doze mode
PMU_MODE_DORMANT, ///< Dormant mode
PMU_MODE_STANDBY, ///< Standby mode
PMU_MODE_SHUTDOWN ///< Shutdown mode
} pmu_mode_e;
/*----- PMU Control Codes: Wakeup type -----*/
typedef enum {
PMU_WAKEUP_TYPE_PULSE = 0, ///< Pulse interrupt
PMU_WAKEUP_TYPE_LEVEL ///< Level interrupt
} pmu_wakeup_type_e;
/*----- PMU Control Codes: Wakeup polarity -----*/
typedef enum {
PMU_WAKEUP_POL_LOW = 0, ///< Low or negedge
PMU_WAKEUP_POL_HIGH ///< High or posedge
} pmu_wakeup_pol_e;
/****** PMU Event *****/
typedef enum {
PMU_EVENT_SLEEP_DONE = 0, ///< Send completed; however PMU may still transmit data
PMU_EVENT_PREPARE_SLEEP = 1
} pmu_event_e;
typedef void (*pmu_event_cb_t)(int32_t idx, pmu_event_e event, pmu_mode_e mode); ///< Pointer to \ref pmu_event_cb_t : PMU Event call back.
/**
\brief Initialize PMU Interface. 1. Initializes the resources needed for the PMU interface 2.registers event callback function
\param[in] idx the id of the pmu
\param[in] cb_event Pointer to \ref pmu_event_cb_t
\return return pmu handle if success
*/
pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event);
/**
\brief De-initialize PMU Interface. stops operation and releases the software resources used by the interface
\param[in] handle pmu handle to operate.
\return error code
*/
int32_t csi_pmu_uninitialize(pmu_handle_t handle);
/**
\brief choose the pmu mode to enter
\param[in] handle pmu handle to operate.
\param[in] mode \ref pmu_mode_e
\return error code
*/
int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode);
/**
\brief control pmu power.
\param[in] handle pmu handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_pmu_power_control(pmu_handle_t handle, csi_power_stat_e state);
/**
\brief Config the wakeup source.
\param[in] handle pmu handle to operate
\param[in] wakeup_num wakeup source num
\param[in] type \ref pmu_wakeup_type
\param[in] pol \ref pmu_wakeup_pol
\param[in] enable flag control the wakeup source is enable or not
\return error code
*/
int32_t csi_pmu_config_wakeup_source(pmu_handle_t handle, uint32_t wakeup_num, pmu_wakeup_type_e type, pmu_wakeup_pol_e pol, uint8_t enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_PMU_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/pmu.h | C | apache-2.0 | 3,464 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_pwm.h
* @brief header file for pwm driver
* @version V1.0
* @date 19. Feb 2019
* @model pwm
******************************************************************************/
#ifndef _CSI_PWM_H_
#define _CSI_PWM_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for pwm handle.
typedef void *pwm_handle_t;
/****** PWM specific error codes *****/
typedef enum {
EDRV_PWM_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
} csi_pwm_error_e;
/*----- PWM Input Capture Mode -----*/
typedef enum {
PWM_INPUT_MODE_EDGE_TIME = 0, ///< Input Edge Time Mode
PWM_INPUT_MODE_EDGE_COUNT = 1 ///< Input Edge Count Mode
} pwm_input_mode_e;
typedef enum {
PWM_INPUT_EVENT_MODE_POSEDGE = 0, ///< Posedge Edge
PWM_INPUT_EVENT_MODE_NEGEDGE = 1, ///< Negedge Edge
PWM_INPUT_EVENT_MODE_BOTHEDGE = 2 ///< Both Edge
} pwm_input_event_mode_e;
typedef struct {
pwm_input_mode_e input_mode; ///< Input Mode
pwm_input_event_mode_e event_mode; ///< Input Event Mode
uint32_t count; ///< Capture Mode Count
} pwm_input_config_t;
typedef enum {
PWM_CAPTURE_EVENT_COUNT = 0, ///< Capture Count Event
PWM_CAPTURE_EVENT_TIME = 1, ///< Capture Time Event
PWM_TIMER_EVENT_TIMEOUT = 2 ///< Timer Timeout Event
} pwm_event_e;
typedef void (*pwm_event_cb_t)(int32_t ch, pwm_event_e event, uint32_t val);
/**
\brief Initialize PWM Interface. 1. Initializes the resources needed for the PWM interface 2.registers event callback function
\param[in] idx pwm idx
\return handle pwm handle to operate.
*/
pwm_handle_t csi_pwm_initialize(uint32_t idx);
/**
\brief De-initialize PWM Interface. stops operation and releases the software resources used by the interface
\param[in] handle pwm handle to operate.
*/
void csi_pwm_uninitialize(pwm_handle_t handle);
/**
\brief control pwm power.
\param[in] handle pwm handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_pwm_power_control(pwm_handle_t handle, csi_power_stat_e state);
/**
\brief config pwm mode.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[in] period_us the PWM period in us
\param[in] pulse_width_us the PMW pulse width in us
\return error code
*/
int32_t csi_pwm_config(pwm_handle_t handle,
uint8_t channel,
uint32_t period_us,
uint32_t pulse_width_us);
/**
\brief start generate pwm signal.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
*/
void csi_pwm_start(pwm_handle_t handle, uint8_t channel);
/**
\brief stop generate pwm signal.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
*/
void csi_pwm_stop(pwm_handle_t handle, uint8_t channel);
/**
\brief config pwm clock division.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[in] div clock div.
*/
void drv_pwm_config_clockdiv(pwm_handle_t handle, uint8_t channel, uint32_t div);
/**
\brief get pwm clock division.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\return clock div.
*/
uint32_t drv_pwm_get_clockdiv(pwm_handle_t handle, uint8_t channel);
/**
\brief config pwm clock division.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[in] cb_event event callback.
*/
void drv_pwm_config_cb(pwm_handle_t handle, uint8_t channel, pwm_event_cb_t cb_event);
/**
\brief set pwm timeout.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[in] timeout the timeout value in microseconds(us).
*/
void drv_pwm_timer_set_timeout(pwm_handle_t handle, uint8_t channel, uint32_t timeout);
/**
\brief start pwm timer.
\param[in] handle pwm handle to operate.
\param[in] channel chnnel num.
*/
void drv_pwm_timer_start(pwm_handle_t handle, uint8_t channel);
/**
\brief stop pWM timer.
\param[in] handle pwm handle to operate.
\param[in] channel chnnel num.
*/
void drv_pwm_timer_stop(pwm_handle_t handle, uint8_t channel);
/**
\brief get pwm timer current value
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[out] value timer current value
*/
void drv_pwm_timer_get_current_value(pwm_handle_t handle, uint8_t channel, uint32_t *value);
/**
\brief get pwm timer reload value
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[out] value timer reload value
*/
void drv_pwm_timer_get_load_value(pwm_handle_t handle, uint8_t channel, uint32_t *value);
/**
\brief config pwm capture mode.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
\param[in] config capture config.
*/
void drv_pwm_capture_config(pwm_handle_t handle, uint8_t channel, pwm_input_config_t *config);
/**
\brief start pwm capture.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
*/
void drv_pwm_capture_start(pwm_handle_t handle, uint8_t channel);
/**
\brief stop pwm capture.
\param[in] handle pwm handle to operate.
\param[in] channel channel num.
*/
void drv_pwm_capture_stop(pwm_handle_t handle, uint8_t channel);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_PWM_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/pwm.h | C | apache-2.0 | 5,986 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_rsa.h
* @brief header file for rsa driver
* @version V1.0
* @date 02. June 2017
* @model rsa
******************************************************************************/
#ifndef _CSI_RSA_H_
#define _CSI_RSA_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for rsa handle.
typedef void *rsa_handle_t;
/****** RSA specific error codes *****/
typedef enum {
RSA_ERROR_DATA_BITS = (DRV_ERROR_SPECIFIC + 1), ///< Specified number of Data bits not supported
RSA_ERROR_ENDIAN ///< Specified endian not supported
} rsa_error_e;
/*----- RSA Control Codes: Mode Parameters: Data Bits -----*/
typedef enum {
RSA_DATA_BITS_192 = 0, ///< 192 Data bits
RSA_DATA_BITS_256, ///< 256 Data bits
RSA_DATA_BITS_512, ///< 512 Data bits
RSA_DATA_BITS_1024, ///< 1024 Data bits
RSA_DATA_BITS_2048, ///< 2048 Data bits
RSA_DATA_BITS_3072 ///< 3072 Data bits
} rsa_data_bits_e;
/*----- RSA Control Codes: Mode Parameters: Endian -----*/
typedef enum {
RSA_ENDIAN_MODE_LITTLE = 0, ///< RSA Little Endian Mode
RSA_ENDIAN_MODE_BIG ///< RSA Big Endian Mode
} rsa_endian_mode_e;
typedef enum {
RSA_PADDING_MODE_PKCS1 = 1, ///< RSA PKCS1 Padding Mode
RSA_PADDING_MODE_NO, ///< RSA NO Padding Mode
RSA_PADDING_MODE_SSLV23, ///< RSA SSLV23 Padding Mode
RSA_PADDING_MODE_PKCS1_OAEP, ///< RSA PKCS1 OAEP Padding Mode
RSA_PADDING_MODE_X931, ///< RSA X931 Padding Mode
RSA_PADDING_MODE_PSS ///< RSA PSS Padding Mode
} rsa_padding_type_e;
typedef enum {
RSA_HASH_TYPE_MD5 = 0,
RSA_HASH_TYPE_SHA1,
RSA_HASH_TYPE_SHA224,
RSA_HASH_TYPE_SHA256,
RSA_HASH_TYPE_SHA384,
RSA_HASH_TYPE_SHA512
} rsa_hash_type_e;
/*----- RSA Control Codes: Mode Parameters: Padding mode -----*/
typedef struct {
rsa_padding_type_e padding_type;
rsa_hash_type_e hash_type;
} rsa_padding_t;
/**
\brief RSA Status
*/
typedef struct {
uint32_t busy : 1; ///< Calculate busy flag
} rsa_status_t;
/****** RSA Event *****/
typedef enum {
RSA_EVENT_ENCRYPT_COMPLETE = 0, ///< Encrypt completed
RSA_EVENT_DECRYPT_COMPLETE, ///< Decrypt completed
RSA_EVENT_SIGN_COMPLETE, ///< Sign completed
RSA_EVENT_VERIFY_COMPLETE, ///< Verify completed
} rsa_event_e;
typedef void (*rsa_event_cb_t)(int32_t idx, rsa_event_e event); ///< Pointer to \ref rsa_event_cb_t : RSA Event call back.
/**
\brief RSA Device Driver Capabilities.
*/
typedef struct {
uint32_t bits_192 : 1; ///< supports 192bits modular length
uint32_t bits_256 : 1; ///< supports 256bits modular length
uint32_t bits_512 : 1; ///< supports 512bits modular length
uint32_t bits_1024 : 1; ///< supports 1024bits modular length
uint32_t bits_2048 : 1; ///< supports 2048bits modular length
uint32_t bits_3072 : 1; ///< supports 30728bits modular length
} rsa_capabilities_t;
// Function documentation
/**
\brief Initialize RSA Interface. 1. Initializes the resources needed for the RSA interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event event callback function \ref rsa_event_cb_t
\return pointer to rsa handle
*/
rsa_handle_t csi_rsa_initialize(int32_t idx, rsa_event_cb_t cb_event);
/**
\brief De-initialize RSA Interface. stops operation and releases the software resources used by the interface
\param[in] handle rsa handle to operate.
\return error code
*/
int32_t csi_rsa_uninitialize(rsa_handle_t handle);
/**
\brief control rsa power.
\param[in] handle rsa handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_rsa_power_control(rsa_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref rsa_capabilities_t
*/
rsa_capabilities_t csi_rsa_get_capabilities(int32_t idx);
/**
\brief config rsa mode.
\param[in] handle rsa handle to operate.
\param[in] data_bits \ref rsa_data_bits_e
\param[in] endian \ref rsa_endian_mode_e
\param[in] arg the addr of modulus value
\return error code
*/
int32_t csi_rsa_config(rsa_handle_t handle,
rsa_data_bits_e data_bits,
rsa_endian_mode_e endian,
void *arg
);
/**
\brief encrypt
\param[in] handle rsa handle to operate.
\param[in] n Pointer to the public modulus
\param[in] e Pointer to the public exponent
\param[in] src Pointer to the source data.
\param[in] src_size the source data len
\param[out] out Pointer to the result buffer
\param[out] out_size the result size
\param[in] padding \ref rsa_padding_t
\return error code
*/
int32_t csi_rsa_encrypt(rsa_handle_t handle, void *n, void *e, void *src, uint32_t src_size, void *out, uint32_t *out_size, rsa_padding_t padding);
/**
\brief decrypt
\param[in] handle rsa handle to operate.
\param[in] n Pointer to the public modulus
\param[in] d Pointer to the privte exponent
\param[in] src Pointer to the source data.
\param[in] src_size the source data len
\param[out] out Pointer to the result buffer
\param[out] out_size the result size
\param[in] padding \ref rsa_padding_t
\return error code
*/
int32_t csi_rsa_decrypt(rsa_handle_t handle, void *n, void *d, void *src, uint32_t src_size, void *out, uint32_t *out_size, rsa_padding_t padding);
/**
\brief rsa sign
\param[in] handle rsa handle to operate.
\param[in] n Pointer to the public modulus
\param[in] d Pointer to the privte exponent
\param[in] src Pointer to the source data.
\param[in] src_size the source data len
\param[out] signature Pointer to the signature
\param[out] sig_size the signature size
\param[in] padding \ref rsa_padding_t
\return error code
*/
int32_t csi_rsa_sign(rsa_handle_t handle, void *n, void *d, void *src, uint32_t src_size, void *signature, uint32_t *sig_size, rsa_padding_t padding);
/**
\brief rsa verify
\param[in] handle rsa handle to operate.
\param[in] n Pointer to the public modulus
\param[in] e Pointer to the public exponent
\param[in] src Pointer to the source data.
\param[in] src_size the source data len
\param[in] signature Pointer to the signature
\param[in] sig_size the signature size
\param[out] result Pointer to the result
\param[in] padding \ref rsa_padding_t
\return error code
*/
int32_t csi_rsa_verify(rsa_handle_t handle, void *n, void *e, void *src, uint32_t src_size, void *signature, uint32_t sig_size, void *result, rsa_padding_t padding);
/**
\brief Get RSA status.
\param[in] handle rsa handle to operate.
\return RSA status \ref rsa_status_t
*/
rsa_status_t csi_rsa_get_status(rsa_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_RSA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/rsa.h | C | apache-2.0 | 7,676 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_rtc.h
* @brief header file for rtc driver
* @version V1.0
* @date 02. June 2017
* @model rtc
******************************************************************************/
#ifndef _CSI_RTC_H_
#define _CSI_RTC_H_
#include <stdint.h>
#include <drv/common.h>
#include <time.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for rtc handle.
typedef void *rtc_handle_t;
/****** rtc specific error codes *****/
typedef enum {
RTC_ERROR_TIME = (DRV_ERROR_SPECIFIC + 1), ///<invalid data time
} rtc_error_e;
/**
\brief RTC Status
*/
typedef struct {
uint32_t active : 1; ///< rtc is running or not
} rtc_status_t;
/****** RTC Event *****/
typedef enum {
RTC_EVENT_TIMER_INTRERRUPT = 0 ///< generate interrupt
} rtc_event_e;
typedef void (*rtc_event_cb_t)(int32_t idx, rtc_event_e event); ///< Pointer to \ref rtc_event_cb_t : RTC Event call back.
/**
\brief RTC Device Driver Capabilities.
*/
typedef struct {
uint32_t interrupt_mode : 1; ///< supports Interrupt mode
uint32_t wrap_mode : 1; ///< supports wrap mode
} rtc_capabilities_t;
/**
\brief Initialize RTC Interface. 1. Initializes the resources needed for the RTC interface 2.registers event callback function
\param[in] idx rtc index
\param[in] cb_event event callback function \ref rtc_event_cb_t
\return pointer to rtc instance
*/
rtc_handle_t csi_rtc_initialize(int32_t idx, rtc_event_cb_t cb_event);
/**
\brief De-initialize RTC Interface. stops operation and releases the software resources used by the interface
\param[in] handle rtc handle to operate.
\return error code
*/
int32_t csi_rtc_uninitialize(rtc_handle_t handle);
/**
\brief control rtc power.
\param[in] handle rtc handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_rtc_power_control(rtc_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx rtc index
\return \ref rtc_capabilities_t
*/
rtc_capabilities_t csi_rtc_get_capabilities(int32_t idx);
/**
\brief Set system date.
\param[in] handle rtc handle to operate.
\param[in] rtctime pointer to rtc time
\return error code
*/
int32_t csi_rtc_set_time(rtc_handle_t handle, const struct tm *rtctime);
/**
\brief Get system date.
\param[in] handle rtc handle to operate.
\param[out] rtctime pointer to rtc time
\return error code
*/
int32_t csi_rtc_get_time(rtc_handle_t handle, struct tm *rtctime);
/**
\brief Start RTC timer.
\param[in] handle rtc handle to operate.
\return error code
*/
int32_t csi_rtc_start(rtc_handle_t handle);
/**
\brief Stop RTC timer.
\param[in] handle rtc handle to operate.
\return error code
*/
int32_t csi_rtc_stop(rtc_handle_t handle);
/**
\brief Get RTC status.
\param[in] handle rtc handle to operate.
\return RTC status \ref rtc_status_t
*/
rtc_status_t csi_rtc_get_status(rtc_handle_t handle);
/**
\brief config RTC timer.
\param[in] handle rtc handle to operate.
\param[in] rtctime time to wake up
\return error code
*/
int32_t csi_rtc_set_alarm(rtc_handle_t handle, const struct tm *rtctime);
/**
\brief disable or enable RTC timer.
\param[in] handle rtc handle to operate.
\param[in] flag 1 - enable rtc alarm 0 - disable rtc alarm
\return error code
*/
int32_t csi_rtc_enable_alarm(rtc_handle_t handle, uint8_t flag);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_RTC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/rtc.h | C | apache-2.0 | 3,843 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_sasc.h
* @brief header file for sasc driver
* @version V1.0
* @date 02. June 2017
* @model sasc
******************************************************************************/
#ifndef _CSI_SASC_H_
#define _CSI_SASC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SASC_AP_RW = 0,
SASC_AP_RO = 1,
SASC_AP_WO = 2,
SASC_AP_DN = 3
}
sasc_ap_e;
typedef enum {
SASC_CD_DI = 0,
SASC_CD_DA = 1,
SASC_CD_IN = 2,
SASC_CD_DN = 3
} sasc_cd_e;
typedef enum {
SASC_SRAM_4B = 5,
SASC_SRAM_8B = 6,
SASC_SRAM_16B = 7,
SASC_SRAM_32B = 8,
SASC_SRAM_64B = 9,
SASC_SRAM_128B = 10,
SASC_SRAM_256B = 11,
SASC_SRAM_512B = 12,
SASC_SRAM_1KB = 13,
SASC_SRAM_2KB = 14,
SASC_SRAM_4KB = 15,
SASC_SRAM_8KB = 16,
SASC_SRAM_16KB = 17,
SASC_SRAM_32KB = 18,
SASC_SRAM_64KB = 19,
SASC_SRAM_128KB = 20,
SASC_FLASH_1S = 21,
SASC_FLASH_2S = 22,
SASC_FLASH_4S = 23,
SASC_FLASH_8S = 24,
SASC_FLASH_16S = 25,
SASC_FLASH_32S = 26,
SASC_FLASH_64S = 27,
SASC_FLASH_128S = 28,
SASC_FLASH_256S = 29,
SASC_FLASH_512S = 30,
SASC_FLASH_1024S = 31,
SASC_FLASH_2048S = 32
} sasc_size_e;
/**
\brief Config the sasc region attribute.
\param[in] handle sasc handle to operate.
\param[in] addr config region base address.
\param[in] size config region addr.
\param[in] sap super mode ap.
\param[in] uap user mode ap.
\param[in] scd super mode cd.
\param[in] ucd user mode cd.
\param[in] is_security config the region is security or not.
\return error code
*/
int32_t drv_sasc_config_region(uint32_t addr, sasc_size_e size, sasc_ap_e sap, sasc_ap_e uap, sasc_cd_e ucd, uint8_t is_security);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_SASC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/sasc.h | C | apache-2.0 | 2,070 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_sdif.h
* @brief head file for sd/mmc sdio
* @version V1.0
* @date 28. June 2018
* @model sdif
******************************************************************************/
#ifndef _CSI_SDIF_H_
#define _CSI_SDIF_H_
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef void *sdif_handle_t;
typedef enum {
SDIF_ERROR_CMD_CRC_FAIL = (DRV_ERROR_SPECIFIC + 1), ///< Command response received (but CRC check failed)
SDIF_ERROR_DATA_CRC_FAIL, ///< Data block sent/received (CRC check failed)
SDIF_ERROR_CMD_RSP_TIMEOUT, ///< Command response timeout
SDIF_ERROR_DATA_TIMEOUT, ///< Data timeout
SDIF_ERROR_TX_UNDERRUN, ///< Transmit FIFO underrun
SDIF_ERROR_RX_OVERRUN, ///< Receive FIFO overrun
SDIF_ERROR_ADDR_MISALIGNED, ///< Misaligned address
SDIF_ERROR_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
SDIF_ERROR_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs
SDIF_ERROR_BAD_ERASE_PARAM, ///< An invalid selection for erase groups
SDIF_ERROR_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block
SDIF_ERROR_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
SDIF_ERROR_COM_CRC_FAILED, ///< CRC check of the previous command failed
SDIF_ERROR_ILLEGAL_CMD, ///< Command is not legal for the card state
SDIF_ERROR_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data
SDIF_ERROR_CC_ERR, ///< Internal card controller error
SDIF_ERROR_GENERAL_UNKNOWN_ERR, ///< General or unknown error
SDIF_ERROR_STREAM_READ_UNDERRUN, ///< The card could not sustain data reading in stream rmode
SDIF_ERROR_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode
SDIF_ERROR_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error
SDIF_ERROR_WP_ERASE_SKIP, ///< Only partial address space was erased
SDIF_ERROR_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC
SDIF_ERROR_ERASE_RESET, ///< Erase sequence was cleared before executing because an out
SDIF_ERROR_AKE_SEQ_ERR, ///< Error in sequence of authentication
SDIF_ERROR_INVALID_VOLTRANGE, ///< Error in case of invalid voltage range
SDIF_ERROR_ADDR_OUT_OF_RANGE, ///< Error when addressed block is out of range
SDIF_ERROR_REQUEST_NOT_APPLICABLE, ///< Error when command request is not applicable
SDIF_ERROR_UNSUPPORTED_FEATURE, ///< Error when feature is not insupported
} sdif_error_e;
/* Host controller capabilities flag mask */
typedef enum {
SDIF_SUPPORT_HIGH_SPEED = 0x1U, ///< Support high-speed
SDIF_SUPPORT_DMA_SPEED = 0x2U, ///< Support DMA
SDIF_SUPPORT_USPEND_RESUME = 0x4U, ///< Support suspend/resume
SDIF_SUPPORT_V330 = 0x8U, ///< Support voltage 3.3V
SDIF_SUPPORT_4BIT = 0x10U, ///< Support 4 bit mode
SDIF_SUPPORT_8BIT = 0x20U, ///< Support 8 bit mode
} sdif_capability_flag_e;
/* \brief define the internal DMA mode */
typedef enum {
SDIF_CHAIN_DMA_MODE = 0x01U, ///< one descriptor with one buffer,but one descriptor point to another
SDIF_DUAL_DMA_MODE = 0x02U, ///< dual mode is one descriptor with two buffer
} sdif_dma_mode_e;
/* The command type */
typedef enum {
SDIF_CARD_COMMAND_NORMAL = 0U, ///< Normal command
SDIF_CARD_COMMAND_SUSPEND = 1U, ///< Suspend command
SDIF_CARD_COMMAND_RESUME = 2U, ///< Resume command
SDIF_CARD_COMMAND_ABORT = 3U, ///< Abort command
} sdif_card_command_type_e;
/* The command response type */
typedef enum {
SDIF_CARD_RESPONSE_NONE = 0U, ///< Response type: none
SDIF_CARD_RESPONSE_R1 = 1U, ///< Response type: R1
SDIF_CARD_RESPONSE_R1b = 2U, ///< Response type: R1b
SDIF_CARD_RESPONSE_R2 = 3U, ///< Response type: R2
SDIF_CARD_RESPONSE_R3 = 4U, ///< Response type: R3
SDIF_CARD_RESPONSE_R4 = 5U, ///< Response type: R4
SDIF_CARD_RESPONSE_R5 = 6U, ///< Response type: R5
SDIF_CARD_RESPONSE_R5b = 7U, ///< Response type: R5b
SDIF_CARD_RESPONSE_R6 = 8U, ///< Response type: R6
SDIF_CARD_RESPONSE_R7 = 9U, ///< Response type: R7
} sdif_card_response_type_e;
/* \brief define the card bus width type */
typedef enum {
SDIF_BUS_1BIT_WIDTH = 0U, ///< 1bit bus width, 1bit mode and 4bit mode share one register bit
SDIF_BUS_4BIT_WIDTH = 1U, ///< 4bit mode mask
SDIF_BUS_8BIT_WIDTH = 2U, ///< support 8 bit mode
} sdif_bus_width_e;
/* \brief Defines the internal DMA configure structure. */
typedef struct {
bool enable_fix_burst_len; ///< fix burst len enable/disable flag,When set, the AHB will
/// use only SINGLE, INCR4, INCR8 or INCR16 during start of
/// normal burst transfers. When reset, the AHB will use SINGLE
/// and INCR burst transfer operations
sdif_dma_mode_e mode; ///< define the DMA mode */
uint32_t *dma_des_buffer_start_addr; ///< internal DMA descriptor start address
uint32_t dma_des_buffer_len; /// internal DMA buffer descriptor buffer len ,user need to pay attention to the
/// dma descriptor buffer length if it is bigger enough for your transfer
uint8_t dma_dws_skip_len; ///< define the descriptor skip length ,the length between two descriptor
/// this field is special for dual DMA mode
} sdif_dma_config_t;
/* \brief sdif callback functions. */
typedef struct {
void (*card_inserted)(uint32_t idx, void *user_data); ///< card insert call back
void (*card_removed)(uint32_t idx, void *user_data); ///< card remove call back
void (*sdif_interrupt)(uint32_t idx, void *user_data); ///< SDIF card interrupt occurs
void (*dma_des_unavailable)(uint32_t idx, void *user_data);///< DMA descriptor unavailable
void (*command_reload)(uint32_t idx, void *user_data); ///< command buffer full,need re-load
void (*transfer_complete)(uint32_t idx,
void *state,
int32_t status,
void *user_data); ///<Transfer complete callback
} sdif_callback_t;
/* Card data descriptor */
typedef struct {
bool stream_transfer; ///< indicate this is a stream data transfer command
bool enable_auto_command12; ///< indicate if auto stop will send when data transfer over
bool enable_ignore_error; ///< indicate if enable ignore error when transfer data
uint32_t block_size; ///< Block size, take care when configure this parameter
uint32_t block_count; ///< Block count
uint32_t *rx_date_buffer; ///< data buffer to receive
const uint32_t *tx_data_buffer; ///< data buffer to transfer
} sdif_data_t;
/* Card command descriptor */
typedef struct {
uint32_t index; ///< Command index
uint32_t argument; ///< Command argument
uint32_t response[4U]; ///< Response for this command
uint32_t type; ///< define the command type
uint32_t response_type; ///< Command response type
uint32_t flags; ///< Cmd flags
uint32_t resopnse_error_flags; ///< response error flags, need to check the flags when receive the cmd response
} sdif_command_t;
/* Transfer state */
typedef struct {
sdif_data_t *data; ///< Data to transfer
sdif_command_t *command; ///< Command to send
} sdif_transfer_t;
/* Data structure to initialize the sdif */
typedef struct {
uint8_t response_timeout; ///< command response timeout value
uint32_t card_det_debounce_clock; ///< define the debounce clock count which will used in
/// card detect logic,typical value is 5-25ms
uint32_t endian_mode; ///< define endian mode ,this field is not used in this
/// module actually, keep for compatible with middleware
uint32_t data_timeout; ///< data timeout value
} sdif_config_t;
/*
* \brief SDIF capability information.
* Defines a structure to get the capability information of SDIF.
*/
typedef struct {
uint32_t sd_version; ///< support SD card/SDIF version
uint32_t mmc_version; ///< support emmc card version
uint32_t max_block_length; ///< Maximum block length united as byte
uint32_t max_block_count; ///< Maximum byte count can be transfered
uint32_t flags; ///< Capability flags to indicate the support information
} sdif_capability_t;
/**
\brief Initializes the SDIF according to the specified
\param[in] idx sdif index
\param[in] callback callback Structure pointer to contain all callback functions.
\param[in] user_data user_data Callback function parameter.
\return sdif handle if success
*/
sdif_handle_t drv_sdif_initialize(uint32_t idx, sdif_callback_t *callback, void *user_data);
/**
\brief De-initialize SD Interface. stops operation and releases the software resources used by the interface
\param[in] handle SDIF handle to operate.
*/
void drv_sdif_uninitialize(sdif_handle_t handle);
/**
\brief Initializes the SDIF config
\param[in] idx sdif index
\param[in] config sdif config descriptor \ref sdif_config_t
*/
void drv_sdif_config(sdif_handle_t handle, sdif_config_t *config);
/**
\brief Get driver capabilities.
\param[in] handle SDIF handle to operate.
\param[out] capability SDIF capability information \ref sdif_capabilities_t
*/
void drv_sdif_get_capabilities(sdif_handle_t handle, sdif_capability_t *capability);
/**
\brief control sdif power.
\param[in] handle SDIF handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t drv_sdif_power_control(sdif_handle_t handle, csi_power_stat_e state);
/**
\brief send command to the card
\param[in] handle SDIF handle to operate.
\param[in] cmd command configuration collection
\param[in] retries total number of tries
\return error code
*/
int32_t drv_sdif_send_command(sdif_handle_t handle, sdif_command_t *cmd, uint32_t retries);
/**
\brief SDIF transfer function data/cmd in a non-blocking way
this API should be use in interrupt mode, when use this API user
must call drv_sdif_create_state first, all status check through
interrupt
\param[in] handle SDIF handle to operate.
\param[in] dma_config DMA config structure \ref sdif_dma_config_t
This parameter can be config as:
1. NULL
In this condition, polling transfer mode is selected
2. avaliable DMA config
In this condition, DMA transfer mode is selected
\param[in] transfer sdif transfer configuration collection. \ref sdif_transfer_t
\return error code
*/
int32_t drv_sdif_transfer(sdif_handle_t handle, sdif_dma_config_t *dma_config, sdif_transfer_t *transfer);
/**
\brief Poll-wait for the response to the last command to be ready. This
function should be called even after sending commands that have no
response (such as CMD0) to make sure that the hardware is ready to
receive the next command.
\param[in] handle SDIF handle to operate.
\param[in] cmd : The command that was sent. See 32-bit command definitions above.
*/
void drv_sdif_transfer_abort(sdif_handle_t handle);
/**
\brief Called after change in Bus width has been selected (via ACMD6). Most
controllers will need to perform some special operations to work
correctly in the new bus mode.
\param[in] handle SDIF handle to operate.
\param[in] bus_width wide bus mode \ref sdif_bus_width_e.
*/
void drv_sdif_bus_width(sdif_handle_t handle, sdif_bus_width_e bus_width);
/**
\brief Set SDIF clocking
\param[in] handle SDIF handle to operate.
\param[in] target_hz card bus clock frequency united in Hz.
\return code error
*/
uint32_t drv_sdif_set_clock(sdif_handle_t handle, uint32_t target_hz);
/**
\brief Get sdif handle
\param[in] idx sdif index
\return sdif handle
*/
sdif_handle_t drv_sdif_get_handle(uint32_t idx);
/**
\brief Get sdif index
\param[out] handle SDIF handle to operate.
\return sdif index
*/
uint32_t drv_sdif_get_idx(sdif_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_SDIF_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/sdif.h | C | apache-2.0 | 13,665 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_sha.h
* @brief header file for sha driver
* @version V1.0
* @date 02. June 2017
* @model sha
******************************************************************************/
#ifndef _CSI_SHA_H_
#define _CSI_SHA_H_
#include <stdint.h>
#include <drv/common.h>
#include <drv/errno.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for sha handle.
typedef void *sha_handle_t;
/****** SHA specific error codes *****/
typedef enum {
SHA_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
SHA_ERROR_ENDIAN ///< Specified endian not supported
} sha_error_e;
/*----- SHA Control Codes: Mode -----*/
typedef enum {
SHA_MODE_1 = 1, ///< SHA_1 mode
SHA_MODE_256, ///< SHA_256 mode
SHA_MODE_224, ///< SHA_224 mode
SHA_MODE_512, ///< SHA_512 mode
SHA_MODE_384, ///< SHA_384 mode
SHA_MODE_512_256, ///< SHA_512_256 mode
SHA_MODE_512_224 ///< SHA_512_224 mode
} sha_mode_e;
/*----- SHA Control Codes: Mode Parameters: Endian -----*/
typedef enum {
SHA_ENDIAN_MODE_BIG = 0, ///< Big Endian Mode
SHA_ENDIAN_MODE_LITTLE, ///< Little Endian Mode
} sha_endian_mode_e;
/**
\brief SHA Status
*/
typedef struct {
uint32_t busy : 1; ///< calculate busy flag
} sha_status_t;
/****** SHA Event *****/
typedef enum {
SHA_EVENT_COMPLETE = 0 ///< calculate completed
} sha_event_e;
typedef void (*sha_event_cb_t)(int32_t idx, sha_event_e event); ///< Pointer to \ref sha_event_cb_t : SHA Event call back.
/**
\brief SHA Device Driver Capabilities.
*/
typedef struct {
uint32_t sha1 : 1; ///< supports sha1 mode
uint32_t sha224 : 1; ///< supports sha224 mode
uint32_t sha256 : 1; ///< supports sha256 mode
uint32_t sha384 : 1; ///< supports sha384 mode
uint32_t sha512 : 1; ///< supports sha512 mode
uint32_t sha512_224 : 1; ///< supports sha512_224 mode
uint32_t sha512_256 : 1; ///< supports sha512_256 mode
uint32_t endianmode : 1; ///< supports endian mode control
uint32_t interruptmode : 1; ///< supports interrupt mode
} sha_capabilities_t;
// Function documentation
/**
\brief Initialize SHA Interface. 1. Initializes the resources needed for the SHA interface 2.registers event callback function
\param[in] idx index of sha
\param[in] context Pointer to the buffer storing the sha context
\param[in] cb_event event callback function \ref sha_event_cb_t
\return return sha handle if success
*/
sha_handle_t csi_sha_initialize(int32_t idx, void *context, sha_event_cb_t cb_event);
/**
\brief De-initialize SHA Interface. stops operation and releases the software resources used by the interface
\param[in] handle sha handle to operate.
\return error code
*/
int32_t csi_sha_uninitialize(sha_handle_t handle);
/**
\brief control sha power.
\param[in] handle sha handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_sha_power_control(sha_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx device id
\return \ref sha_capabilities_t
*/
sha_capabilities_t csi_sha_get_capabilities(int32_t idx);
/**
\brief config sha mode.
\param[in] handle sha handle to operate.
\param[in] mode \ref sha_mode_e
\param[in] endian \ref sha_endian_mode_e
\return error code
*/
int32_t csi_sha_config(sha_handle_t handle,
sha_mode_e mode,
sha_endian_mode_e endian
);
/**
\brief start the engine
\param[in] handle sha handle to operate.
\param[in] context Pointer to the buffer storing the sha context
\return error code
*/
int32_t csi_sha_start(sha_handle_t handle, void *context);
/**
\brief update the engine
\param[in] handle sha handle to operate.
\param[in] context Pointer to the buffer storing the sha context
\param[in] input Pointer to the Source data
\param[in] len the data len
\return error code
*/
int32_t csi_sha_update(sha_handle_t handle, void *context, const void *input, uint32_t len);
/**
\brief finish the engine
\param[in] handle sha handle to operate.
\param[in] context Pointer to the buffer storing the sha context
\param[out] output Pointer to the result data
\return error code
*/
int32_t csi_sha_finish(sha_handle_t handle, void *context, void *output);
/**
\brief Get SHA status.
\param[in] handle sha handle to operate.
\return SHA status \ref sha_status_t
*/
sha_status_t csi_sha_get_status(sha_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_SHA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/sha.h | C | apache-2.0 | 5,294 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_spi.h
* @brief header file for spi driver
* @version V1.0
* @date 02. June 2017
* @model spi
******************************************************************************/
#ifndef _CSI_SPI_H_
#define _CSI_SPI_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for spi handle.
typedef void *spi_handle_t;
/****** SPI specific error codes *****/
typedef enum {
SPI_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
SPI_ERROR_FRAME_FORMAT, ///< Specified Frame Format not supported
SPI_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
SPI_ERROR_BIT_ORDER, ///< Specified Bit order not supported
SPI_ERROR_SS_MODE ///< Specified Slave Select Mode not supported
} spi_error_e;
/*----- SPI Control Codes: Mode -----*/
typedef enum {
SPI_MODE_INACTIVE = 0, ///< SPI Inactive
SPI_MODE_MASTER, ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
SPI_MODE_SLAVE, ///< SPI Slave (Output on MISO, Input on MOSI)
SPI_MODE_MASTER_SIMPLEX, ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
SPI_MODE_SLAVE_SIMPLEX ///< SPI Slave (Output/Input on MISO)
} spi_mode_e;
/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
typedef enum {
SPI_FORMAT_CPOL0_CPHA0 = 0, ///< Clock Polarity 0, Clock Phase 0
SPI_FORMAT_CPOL0_CPHA1, ///< Clock Polarity 0, Clock Phase 1
SPI_FORMAT_CPOL1_CPHA0, ///< Clock Polarity 1, Clock Phase 0
SPI_FORMAT_CPOL1_CPHA1, ///< Clock Polarity 1, Clock Phase 1
} spi_format_e;
/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
typedef enum {
SPI_ORDER_MSB2LSB = 0, ///< SPI Bit order from MSB to LSB
SPI_ORDER_LSB2MSB ///< SPI Bit order from LSB to MSB
} spi_bit_order_e;
/*----- SPI Control Codes: Mode Parameters: Data Width in bits -----*/
#define SPI_DATAWIDTH_MAX 32 /* 1 ~ 32 bit*/
/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
typedef enum {
/*options for SPI_MODE_MASTER/SPI_MODE_MASTER_SIMPLEX */
SPI_SS_MASTER_UNUSED = 0, ///< SPI Slave Select when Master: Not used.SS line is not controlled by master, For example,SS line connected to a fixed low level
SPI_SS_MASTER_SW, ///< SPI Slave Select when Master: Software controlled. SS line is configured by software
SPI_SS_MASTER_HW_OUTPUT, ///< SPI Slave Select when Master: Hardware controlled Output.SS line is activated or deactivated automatically by hardware
SPI_SS_MASTER_HW_INPUT, ///< SPI Slave Select when Master: Hardware monitored Input.Used in multi-master configuration where a master does not drive the Slave Select when driving the bus, but rather monitors it
/*options for SPI_MODE_SLAVE/SPI_MODE_SLAVE_SIMPLEX */
SPI_SS_SLAVE_HW, ///< SPI Slave Select when Slave: Hardware monitored.Hardware monitors the Slave Select line and accepts transfers only when the line is active
SPI_SS_SLAVE_SW ///< SPI Slave Select when Slave: Software controlled.Used only when the Slave Select line is not used. Software controls if the slave is responding or not(enables or disables transfers)
} spi_ss_mode_e;
/****** SPI Slave Select Signal definitions *****/
typedef enum {
SPI_SS_INACTIVE = 0, ///< SPI Slave Select Signal/line Inactive
SPI_SS_ACTIVE ///< SPI Slave Select Signal/line Active
} spi_ss_stat_e;
/**
\brief SPI Status
*/
typedef struct {
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation)
} spi_status_t;
/****** SPI Event *****/
typedef enum {
SPI_EVENT_TRANSFER_COMPLETE = 0, ///< Data Transfer completed. Occurs after call to csi_spi_send, csi_spi_receive, or csi_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_TX_COMPLETE, ///< Data Transfer completed. Occurs after call to csi_spi_send, csi_spi_receive, or csi_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_RX_COMPLETE, ///< Data Transfer completed. Occurs after call to csi_spi_send, csi_spi_receive, or csi_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_DATA_LOST, ///< Data lost: Receive overflow / Transmit underflow. Occurs in slave mode when data is requested/sent by master but send/receive/transfer operation has not been started and indicates that data is lost. Occurs also in master mode when driver cannot transfer data fast enough.
SPI_EVENT_MODE_FAULT ///< Master Mode Fault (SS deactivated when Master).Occurs in master mode when Slave Select is deactivated and indicates Master Mode Fault. The driver is ready for the next transfer operation.
} spi_event_e;
typedef void (*spi_event_cb_t)(int32_t idx, spi_event_e event); ///< Pointer to \ref spi_event_cb_t : SPI Event call back.
/**
\brief SPI Driver Capabilities.
*/
typedef struct {
uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave)
uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface
uint32_t microwire : 1; ///< supports Microwire Interface
uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref spi_event_e
} spi_capabilities_t;
/**
\brief Initialize SPI Interface. 1. Initializes the resources needed for the SPI interface 2.registers event callback function
\param[in] idx spi index
\param[in] cb_event event callback function \ref spi_event_cb_t
\param[in] cb_arg argument for call back function
\return return spi handle if success
*/
spi_handle_t csi_spi_initialize(int32_t idx, spi_event_cb_t cb_event);
/**
\brief De-initialize SPI Interface. stops operation and releases the software resources used by the interface
\param[in] handle spi handle to operate.
\return error code
*/
int32_t csi_spi_uninitialize(spi_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx spi index
\return \ref spi_capabilities_t
*/
spi_capabilities_t csi_spi_get_capabilities(int32_t idx);
/**
\brief config spi mode.
\param[in] handle spi handle to operate.
\param[in] baud spi baud rate. if negative, then this attribute not changed
\param[in] mode \ref spi_mode_e . if negative, then this attribute not changed
\param[in] format \ref spi_format_e . if negative, then this attribute not changed
\param[in] order \ref spi_bit_order_e . if negative, then this attribute not changed
\param[in] ss_mode \ref spi_ss_mode_e . if negative, then this attribute not changed
\param[in] bit_width spi data bitwidth: (1 ~ SPI_DATAWIDTH_MAX) . if negative, then this attribute not changed
\return error code
*/
int32_t csi_spi_config(spi_handle_t handle,
int32_t baud,
spi_mode_e mode,
spi_format_e format,
spi_bit_order_e order,
spi_ss_mode_e ss_mode,
int32_t bit_width);
/**
\brief sending data to SPI transmitter,(received data is ignored).
if non-blocking mode, this function only starts the sending,
\ref spi_event_e is signaled when operation completes or error happens.
\ref csi_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[in] data Pointer to buffer with data to send to SPI transmitter. data_type is : uint8_t for 1..8 data bits, uint16_t for 9..16 data bits,uint32_t for 17..32 data bits,
\param[in] num Number of data items to send.
\return error code
*/
int32_t csi_spi_send(spi_handle_t handle, const void *data, uint32_t num);
/**
\brief receiving data from SPI receiver. if non-blocking mode, this function only starts the receiving,
\ref spi_event_e is signaled when operation completes or error happens.
\ref csi_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] num Number of data items to receive
\return error code
*/
int32_t csi_spi_receive(spi_handle_t handle, void *data, uint32_t num);
/**
\brief sending/receiving data to/from SPI transmitter/receiver.
if non-blocking mode, this function only starts the transfer,
\ref spi_event_e is signaled when operation completes or error happens.
\ref csi_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] num_out Number of data items to send
\param[in] num_in Number of data items to receive
\return error code
*/
int32_t csi_spi_transfer(spi_handle_t handle, const void *data_out, void *data_in, uint32_t num_out, uint32_t num_in);
/**
\brief abort spi transfer.
\param[in] handle spi handle to operate.
\return error code
*/
int32_t csi_spi_abort_transfer(spi_handle_t handle);
/**
\brief Get SPI status.
\param[in] handle spi handle to operate.
\return SPI status \ref spi_status_t
*/
spi_status_t csi_spi_get_status(spi_handle_t handle);
/**
\brief config the SPI mode.
\param[in] handle spi handle
\param[in] mode spi mode. \ref spi_mode_e
\return error code
*/
int32_t csi_spi_config_mode(spi_handle_t handle, spi_mode_e mode);
/**
\brief config the SPI block mode.
\param[in] handle spi handle
\param[in] flag 1 - enbale the block mode. 0 - disable the block mode
\return error code
*/
int32_t csi_spi_config_block_mode(spi_handle_t handle, int32_t flag);
/**
\brief Set the SPI baudrate.
\param[in] handle spi handle
\param[in] baud spi baud rate
\return error code
*/
int32_t csi_spi_config_baudrate(spi_handle_t handle, uint32_t baud);
/**
\brief config the SPI bit order.
\param[in] handle spi handle
\param[in] order spi bit order.\ref spi_bit_order_e
\return error code
*/
int32_t csi_spi_config_bit_order(spi_handle_t handle, spi_bit_order_e order);
/**
\brief Set the SPI datawidth.
\param[in] handle spi handle
\param[in] datawidth date frame size in bits
\return error code
*/
int32_t csi_spi_config_datawidth(spi_handle_t handle, uint32_t datawidth);
/**
\brief config the SPI format.
\param[in] handle spi handle
\param[in] format spi format. \ref spi_format_e
\return error code
*/
int32_t csi_spi_config_format(spi_handle_t handle, spi_format_e format);
/**
\brief config the SPI slave select mode.
\param[in] handle spi handle
\param[in] ss_mode spi slave select mode. \ref spi_ss_mode_e
\return error code
*/
int32_t csi_spi_config_ss_mode(spi_handle_t handle, spi_ss_mode_e ss_mode);
/**
\brief Get the number of the currently transferred.
\param[in] handle spi handle to operate.
\return the number of the currently transferred data items
*/
uint32_t csi_spi_get_data_count(spi_handle_t handle);
/**
\brief control spi power.
\param[in] handle spi handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_spi_power_control(spi_handle_t handle, csi_power_stat_e state);
/**
\brief Control the Slave Select signal (SS).
\param[in] handle spi handle to operate.
\param[in] stat SS state. \ref spi_ss_stat_e.
\return error code
*/
int32_t csi_spi_ss_control(spi_handle_t handle, spi_ss_stat_e stat);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_SPI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/spi.h | C | apache-2.0 | 13,080 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_spiflash.h
* @brief header file for spiflash driver
* @version V1.0
* @date 02. June 2017
* @model spiflash
******************************************************************************/
#ifndef _CSI_SPIFLASH_H_
#define _CSI_SPIFLASH_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for spiflash handle.
typedef void *spiflash_handle_t;
/**
\brief Flash information
*/
typedef struct {
uint32_t start; ///< Chip Start address
uint32_t end; ///< Chip End address (start+size-1)
uint32_t sector_count; ///< Number of sectors
uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used)
uint32_t page_size; ///< Optimal programming page size in bytes
uint32_t program_unit; ///< Smallest programmable unit in bytes
uint8_t erased_value; ///< Contents of erased memory (usually 0xFF)
} spiflash_info_t;
/**
\brief Flash Status
*/
typedef struct {
uint32_t busy : 1; ///< Flash busy flag
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
} spiflash_status_t;
/****** SPIFLASH Event *****/
typedef enum {
SPIFLASH_EVENT_READY = 0, ///< Flash Ready
SPIFLASH_EVENT_ERROR, ///< Read/Program/Erase Error
} spiflash_event_e;
typedef enum {
SPIFLASH_DATA_1_LINE = 1,
SPIFLASH_DATA_2_LINES = 2,
SPIFLASH_DATA_4_LINES = 4
} spiflash_data_line_e;
typedef void (*spiflash_event_cb_t)(int32_t idx, spiflash_event_e event); ///< Pointer to \ref spiflash_event_cb_t : SPIFLASH Event call back.
/**
\brief Flash Driver Capabilities.
*/
typedef struct {
uint32_t event_ready : 1; ///< Signal Flash Ready event
uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
uint32_t erase_chip : 1; ///< Supports EraseChip operation
} spiflash_capabilities_t;
// Function documentation
/**
\brief Initialize SPIFLASH Interface. 1. Initializes the resources needed for the SPIFLASH interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event Pointer to \ref spiflash_event_cb_t
\return pointer to spiflash handle
*/
spiflash_handle_t csi_spiflash_initialize(int32_t idx, spiflash_event_cb_t cb_event);
/**
\brief De-initialize SPIFLASH Interface. stops operation and releases the software resources used by the interface
\param[in] handle spiflash handle to operate.
\return error code
*/
int32_t csi_spiflash_uninitialize(spiflash_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] handle spiflash handle to operate.
\return \ref spiflash_capabilities_t
*/
spiflash_capabilities_t csi_spiflash_get_capabilities(int32_t idx);
/**
\brief Set QSPI data line
\param[in] handle spiflash handle to operate
\param[in] line spiflash data line mode
\return error code
*/
int32_t csi_spiflash_config_data_line(spiflash_handle_t handle, spiflash_data_line_e line);
/**
\brief Read data from Flash.
\param[in] handle spiflash handle to operate.
\param[in] addr Data address.
\param[out] data Pointer to a buffer storing the data read from Flash.
\param[in] cnt Number of data items to read.
\return number of data items read or error code
*/
int32_t csi_spiflash_read(spiflash_handle_t handle, uint32_t addr, void *data, uint32_t cnt);
/**
\brief Program data to Flash.
\param[in] handle spiflash handle to operate.
\param[in] addr Data address.
\param[in] data Pointer to a buffer containing the data to be programmed to Flash..
\param[in] cnt Number of data items to program.
\return number of data items programmed or error code
*/
int32_t csi_spiflash_program(spiflash_handle_t handle, uint32_t addr, const void *data, uint32_t cnt);
/**
\brief Erase Flash Sector.
\param[in] handle spiflash handle to operate.
\param[in] addr Sector address
\return error code
*/
int32_t csi_spiflash_erase_sector(spiflash_handle_t handle, uint32_t addr);
/**
\brief Erase complete Flash.
\param[in] handle spiflash handle to operate.
\return error code
*/
int32_t csi_spiflash_erase_chip(spiflash_handle_t handle);
/**
\brief Flash power down.
\param[in] handle spiflash handle to operate.
\return error code
*/
int32_t csi_spiflash_power_down(spiflash_handle_t handle);
/**
\brief Flash release power down.
\param[in] handle spiflash handle to operate.
\return error code
*/
int32_t csi_spiflash_release_power_down(spiflash_handle_t handle);
/**
\brief Get Flash information.
\param[in] handle spiflash handle to operate.
\return Pointer to Flash information \ref spiflash_info_t
*/
spiflash_info_t *csi_spiflash_get_info(spiflash_handle_t handle);
/**
\brief Get SPIFLASH status.
\param[in] handle spiflash handle to operate.
\return SPIFLASH status \ref spiflash_status_t
*/
spiflash_status_t csi_spiflash_get_status(spiflash_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_SPIFLASH_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/spiflash.h | C | apache-2.0 | 5,548 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_spu.h
* @brief header file for spu driver
* @version V1.0
* @date 02. June 2017
* @model spu
******************************************************************************/
#ifndef _CSI_spu_H_
#define _CSI_spu_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for spu handle.
typedef void *spu_handle_t;
/****** spu specific error codes *****/
typedef enum {
EDRV_SPU_INST_OVERFLOW = (DRV_ERROR_SPECIFIC + 1), ///< INST_RAM size not enough
EDRV_SPU_PROG_OVERFLOW, ///<PROG_RAM size not enough
} drv_spu_error_e;
/**
\brief spu Driver Capabilities.
*/
typedef struct {
uint32_t spu_usart : 1; ///< supports usart device
uint32_t spu_spi : 1; ///< spuports spi device
uint32_t spu_iic : 1; ///< supports iic device
uint32_t spu_can : 1; ///< supports can device
uint32_t spu_i2s : 1; ///< supports i2s device
} spu_capabilities_t;
/**
\brief Get driver capabilities.
\param[in] handle spu handle to operate.
\return \ref spu_capabilities_t
*/
spu_capabilities_t drv_spu_get_capabilities(spu_handle_t handle);
/**
\brief Initialize spu Interface. Initializes the resources needed for the spu interface
\param[in] idx spu index
\param[in] num spu pin number, a maximum of 32
\return return spu handle if success
*/
spu_handle_t drv_spu_initialize(int32_t idx);
/**
\brief De-initialize spu Interface. stops operation and releases the software resources used by the interface
\param[in] handle spu handle to operate.
\return error code
*/
int32_t drv_spu_uninitialize(spu_handle_t handle);
/**
\brief config spu mode.
\param[in] handle spu handle to operate.
\param[in] capabilities type of device that SPU supports(uart/spi/i2c/can)
\return error code
*/
int32_t drv_spu_config(spu_handle_t handle, spu_capabilities_t capabilities);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_spu_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/spu.h | C | apache-2.0 | 2,203 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_spu_iic.h
* @brief header file for iic driver
* @version V1.0
* @date 02. June 2017
* @model spu_iic
******************************************************************************/
#ifndef _DRV_SPU_IIC_H_
#define _DRV_SPU_IIC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for iic handle.
typedef void *iic_handle_t;
/*----- IIC Control Codes: Mode -----*/
typedef enum {
IIC_MODE_MASTER, ///< IIC Master
IIC_MODE_SLAVE ///< IIC Slave
} iic_mode_e;
/*----- IIC Control Codes: IIC Bus Speed -----*/
typedef enum {
IIC_BUS_SPEED_STANDARD = 0, ///< Standard Speed (100kHz)
IIC_BUS_SPEED_FAST = 1, ///< Fast Speed (400kHz)
IIC_BUS_SPEED_FAST_PLUS = 2, ///< Fast+ Speed ( 1MHz)
IIC_BUS_SPEED_HIGH = 3 ///< High Speed (3.4MHz)
} iic_speed_e;
/*----- IIC Control Codes: IIC Address Mode -----*/
typedef enum {
IIC_ADDRESS_7BIT = 0, ///< 7-bit address mode
IIC_ADDRESS_10BIT = 1 ///< 10-bit address mode
} iic_address_mode_e;
/**
\brief IIC Status
*/
typedef struct {
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master
uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver
uint32_t general_call : 1; ///< General Call(address 0) indication (cleared on start of next Slave operation)
uint32_t arbitration_lost : 1; ///< Master lost arbitration(in case of multi-masters) (cleared on start of next Master operation)
uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation)
} iic_status_t;
/****** IIC Event *****/
typedef enum {
IIC_EVENT_TRANSFER_DONE = 0, ///< Master/Slave Transmit/Receive finished
IIC_EVENT_TRANSFER_INCOMPLETE = 1, ///< Master/Slave Transmit/Receive incomplete transfer
IIC_EVENT_SLAVE_TRANSMIT = 2, ///< Slave Transmit operation requested
IIC_EVENT_SLAVE_RECEIVE = 3, ///< Slave Receive operation requested
IIC_EVENT_ADDRESS_NACK = 4, ///< Address not acknowledged from Slave
IIC_EVENT_GENERAL_CALL = 5, ///< General Call indication
IIC_EVENT_ARBITRATION_LOST = 6, ///< Master lost arbitration
IIC_EVENT_BUS_ERROR = 7, ///< Bus error detected (START/STOP at illegal position)
IIC_EVENT_BUS_CLEAR = 8 ///< Bus clear finished
} iic_event_e;
typedef void (*iic_event_cb_t)(int32_t idx, iic_event_e event); ///< Pointer to \ref iic_event_cb_t : IIC Event call back.
/**
\brief IIC Driver Capabilities.
*/
typedef struct {
uint32_t address_10_bit : 1; ///< supports 10-bit addressing
} iic_capabilities_t;
/**
\brief Initialize IIC Interface specified by pins. \n
1. Initializes the resources needed for the IIC interface 2.registers event callback function
\param[in] idx iic index
\param[in] cb_event event callback function \ref iic_event_cb_t
\return 0 for success, negative for error code
*/
iic_handle_t drv_spu_iic_initialize(int32_t idx, iic_event_cb_t cb_event);
/**
\brief De-initialize IIC Interface. stops operation and releases the software resources used by the interface
\param[in] handle iic handle to operate.
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_uninitialize(iic_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx iic index
\return \ref iic_capabilities_t
*/
iic_capabilities_t drv_spu_iic_get_capabilities(int32_t idx);
/**
\brief config iic attributes.
\param[in] handle iic handle to operate.
\param[in] mode iic mode \ref iic_mode_e. if negative, then this attribute not changed.
\param[in] speed iic speed \ref iic_speed_e. if negative, then this attribute not changed.
\param[in] addr_mode iic address mode \ref iic_address_mode_e. if negative, then this attribute not changed.
\param[in] slave_addr iic address of slave. if negative, then this attribute not changed.
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_config(iic_handle_t handle,
iic_mode_e mode,
iic_speed_e speed,
iic_address_mode_e addr_mode,
int32_t slave_addr);
/**
\brief Start transmitting data as I2C Master.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_spu_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] devaddr iic addrress of slave device.
\param[in] data data to send to I2C Slave
\param[in] num Number of data items to send
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
Master generates STOP condition (if xfer_pending is "false")
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_master_send(iic_handle_t handle, uint32_t devaddr, const void *data, uint32_t num, bool xfer_pending);
/**
\brief Start receiving data as I2C Master.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_spu_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] devaddr iic addrress of slave device.
\param[out] data Pointer to buffer for data to receive from IIC receiver
\param[in] num Number of data items to receive
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_master_receive(iic_handle_t handle, uint32_t devaddr, void *data, uint32_t num, bool xfer_pending);
/**
\brief Start transmitting data as I2C Slave.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_spu_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] data Pointer to buffer with data to transmit to I2C Master
\param[in] num Number of data items to send
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_slave_send(iic_handle_t handle, const void *data, uint32_t num);
/**
\brief Start receiving data as I2C Slave.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_spu_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[out] data Pointer to buffer for data to receive from I2C Master
\param[in] num Number of data items to receive
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_slave_receive(iic_handle_t handle, void *data, uint32_t num);
/**
\brief abort transfer.
\param[in] handle iic handle to operate.
\return 0 for success, negative for error code
*/
int32_t drv_spu_iic_abort_transfer(iic_handle_t handle);
/**
\brief Get IIC status.
\param[in] handle iic handle to operate.
\return IIC status \ref iic_status_t
*/
iic_status_t drv_spu_iic_get_status(iic_handle_t handle);
/**
\brief control IIC power.
\param[in] handle iic handle to operate.
\param[in] state power state.\ref drv_spu_power_stat_e.
\return error code
*/
int32_t drv_spu_iic_power_control(iic_handle_t handle, csi_power_stat_e state);
/**
\brief config iic mode.
\param[in] handle iic handle to operate.
\param[in] mode \ref iic_mode_e
\return error code
*/
int32_t drv_spu_iic_config_mode(iic_handle_t handle, iic_mode_e mode);
/**
\brief config iic speed.
\param[in] handle iic handle to operate.
\param[in] speed \ref iic_speed_e
\return error code
*/
int32_t drv_spu_iic_config_speed(iic_handle_t handle, iic_speed_e speed);
/**
\brief config iic address mode.
\param[in] handle iic handle to operate.
\param[in] addr_mode \ref iic_address_mode_e
\return error code
*/
int32_t drv_spu_iic_config_addr_mode(iic_handle_t handle, iic_address_mode_e addr_mode);
/**
\brief config iic slave address.
\param[in] handle iic handle to operate.
\param[in] slave_addr slave address
\return error code
*/
int32_t drv_spu_iic_config_slave_addr(iic_handle_t handle, int32_t slave_addr);
/**
\brief Get IIC transferred data count.
\param[in] handle iic handle to operate.
\return the number of the currently transferred data items
*/
uint32_t drv_spu_iic_get_data_count(iic_handle_t handle);
/**
\brief Send START command.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t drv_spu_iic_send_start(iic_handle_t handle);
/**
\brief Send STOP command.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t drv_spu_iic_send_stop(iic_handle_t handle);
/**
\brief Reset I2C peripheral.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t drv_spu_iic_reset(iic_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SPU_IIC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/spu_iic.h | C | apache-2.0 | 9,793 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_spu_spi.h
* @brief header file for spi driver
* @version V1.0
* @date 02. June 2017
* @model spu_spi
******************************************************************************/
#ifndef _DRV_SPU_SPI_H_
#define _DRV_SPU_SPI_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef CONFIG_SPI_DMA
#include <drv/dmac.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/// definition for spi handle.
typedef void *spi_handle_t;
/****** SPI specific error codes *****/
typedef enum {
SPI_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
SPI_ERROR_FRAME_FORMAT, ///< Specified Frame Format not supported
SPI_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
SPI_ERROR_BIT_ORDER, ///< Specified Bit order not supported
SPI_ERROR_SS_MODE ///< Specified Slave Select Mode not supported
} spi_error_e;
/*----- SPI Control Codes: Mode -----*/
typedef enum {
SPI_MODE_INACTIVE = 0, ///< SPI Inactive
SPI_MODE_MASTER, ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
SPI_MODE_SLAVE, ///< SPI Slave (Output on MISO, Input on MOSI)
SPI_MODE_MASTER_SIMPLEX, ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
SPI_MODE_SLAVE_SIMPLEX ///< SPI Slave (Output/Input on MISO)
} spi_mode_e;
/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
typedef enum {
SPI_FORMAT_CPOL0_CPHA0 = 0, ///< Clock Polarity 0, Clock Phase 0
SPI_FORMAT_CPOL0_CPHA1, ///< Clock Polarity 0, Clock Phase 1
SPI_FORMAT_CPOL1_CPHA0, ///< Clock Polarity 1, Clock Phase 0
SPI_FORMAT_CPOL1_CPHA1, ///< Clock Polarity 1, Clock Phase 1
} spi_format_e;
/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
typedef enum {
SPI_ORDER_MSB2LSB = 0, ///< SPI Bit order from MSB to LSB
SPI_ORDER_LSB2MSB ///< SPI Bit order from LSB to MSB
} spi_bit_order_e;
/*----- SPI Control Codes: Mode Parameters: Data Width in bits -----*/
#define SPI_DATAWIDTH_MAX 32 /* 1 ~ 32 bit*/
/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
typedef enum {
/*options for SPI_MODE_MASTER/SPI_MODE_MASTER_SIMPLEX */
SPI_SS_MASTER_UNUSED = 0, ///< SPI Slave Select when Master: Not used.SS line is not controlled by master, For example,SS line connected to a fixed low level
SPI_SS_MASTER_SW, ///< SPI Slave Select when Master: Software controlled. SS line is configured by software
SPI_SS_MASTER_HW_OUTPUT, ///< SPI Slave Select when Master: Hardware controlled Output.SS line is activated or deactivated automatically by hardware
SPI_SS_MASTER_HW_INPUT, ///< SPI Slave Select when Master: Hardware monitored Input.Used in multi-master configuration where a master does not drive the Slave Select when driving the bus, but rather monitors it
/*options for SPI_MODE_SLAVE/SPI_MODE_SLAVE_SIMPLEX */
SPI_SS_SLAVE_HW, ///< SPI Slave Select when Slave: Hardware monitored.Hardware monitors the Slave Select line and accepts transfers only when the line is active
SPI_SS_SLAVE_SW ///< SPI Slave Select when Slave: Software controlled.Used only when the Slave Select line is not used. Software controls if the slave is responding or not(enables or disables transfers)
} spi_ss_mode_e;
/****** SPI Slave Select Signal definitions *****/
typedef enum {
SPI_SS_INACTIVE = 0, ///< SPI Slave Select Signal/line Inactive
SPI_SS_ACTIVE ///< SPI Slave Select Signal/line Active
} spi_ss_stat_e;
/**
\brief SPI Status
*/
typedef struct {
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation)
} spi_status_t;
/****** SPI Event *****/
typedef enum {
SPI_EVENT_TRANSFER_COMPLETE = 0, ///< Data Transfer completed. Occurs after call to drv_spu_spi_send, drv_spu_spi_receive, or drv_spu_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_TX_COMPLETE, ///< Data Transfer completed. Occurs after call to drv_spu_spi_send, drv_spu_spi_receive, or drv_spu_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_RX_COMPLETE, ///< Data Transfer completed. Occurs after call to drv_spu_spi_send, drv_spu_spi_receive, or drv_spu_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_DATA_LOST, ///< Data lost: Receive overflow / Transmit underflow. Occurs in slave mode when data is requested/sent by master but send/receive/transfer operation has not been started and indicates that data is lost. Occurs also in master mode when driver cannot transfer data fast enough.
SPI_EVENT_MODE_FAULT ///< Master Mode Fault (SS deactivated when Master).Occurs in master mode when Slave Select is deactivated and indicates Master Mode Fault. The driver is ready for the next transfer operation.
} spi_event_e;
typedef void (*spi_event_cb_t)(int32_t idx, spi_event_e event); ///< Pointer to \ref spi_event_cb_t : SPI Event call back.
/**
\brief SPI Driver Capabilities.
*/
typedef struct {
uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave)
uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface
uint32_t microwire : 1; ///< supports Microwire Interface
uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref spi_event_e
} spi_capabilities_t;
/**
\brief Initialize SPI Interface. 1. Initializes the resources needed for the SPI interface 2.registers event callback function
\param[in] idx spi index
\param[in] cb_event event callback function \ref spi_event_cb_t
\param[in] cb_arg argument for call back function
\return return spi handle if success
*/
spi_handle_t drv_spu_spi_initialize(int32_t idx, spi_event_cb_t cb_event);
/**
\brief De-initialize SPI Interface. stops operation and releases the software resources used by the interface
\param[in] handle spi handle to operate.
\return error code
*/
int32_t drv_spu_spi_uninitialize(spi_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx spi index
\return \ref spi_capabilities_t
*/
spi_capabilities_t drv_spu_spi_get_capabilities(int32_t idx);
/**
\brief config spi mode.
\param[in] handle spi handle to operate.
\param[in] baud spi baud rate. if negative, then this attribute not changed
\param[in] mode \ref spi_mode_e . if negative, then this attribute not changed
\param[in] format \ref spi_format_e . if negative, then this attribute not changed
\param[in] order \ref spi_bit_order_e . if negative, then this attribute not changed
\param[in] ss_mode \ref spi_ss_mode_e . if negative, then this attribute not changed
\param[in] bit_width spi data bitwidth: (1 ~ SPI_DATAWIDTH_MAX) . if negative, then this attribute not changed
\return error code
*/
int32_t drv_spu_spi_config(spi_handle_t handle,
int32_t baud,
spi_mode_e mode,
spi_format_e format,
spi_bit_order_e order,
spi_ss_mode_e ss_mode,
int32_t bit_width);
/**
\brief sending data to SPI transmitter,(received data is ignored).
if non-blocking mode, this function only starts the sending,
\ref spi_event_e is signaled when operation completes or error happens.
\ref drv_spu_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[in] data Pointer to buffer with data to send to SPI transmitter. data_type is : uint8_t for 1..8 data bits, uint16_t for 9..16 data bits,uint32_t for 17..32 data bits,
\param[in] num Number of data items to send.
\return error code
*/
int32_t drv_spu_spi_send(spi_handle_t handle, const void *data, uint32_t num);
/**
\brief receiving data from SPI receiver. if non-blocking mode, this function only starts the receiving,
\ref spi_event_e is signaled when operation completes or error happens.
\ref drv_spu_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] num Number of data items to receive
\return error code
*/
int32_t drv_spu_spi_receive(spi_handle_t handle, void *data, uint32_t num);
/**
\brief sending/receiving data to/from SPI transmitter/receiver.
if non-blocking mode, this function only starts the transfer,
\ref spi_event_e is signaled when operation completes or error happens.
\ref drv_spu_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] num_out Number of data items to send
\param[in] num_in Number of data items to receive
\return error code
*/
int32_t drv_spu_spi_transfer(spi_handle_t handle, const void *data_out, void *data_in, uint32_t num_out, uint32_t num_in);
/**
\brief abort spi transfer.
\param[in] handle spi handle to operate.
\return error code
*/
int32_t drv_spu_spi_abort_transfer(spi_handle_t handle);
/**
\brief Get SPI status.
\param[in] handle spi handle to operate.
\return SPI status \ref spi_status_t
*/
spi_status_t drv_spu_spi_get_status(spi_handle_t handle);
/**
\brief config the SPI mode.
\param[in] handle spi handle
\param[in] mode spi mode. \ref spi_mode_e
\return error code
*/
int32_t drv_spu_spi_config_mode(spi_handle_t handle, spi_mode_e mode);
/**
\brief config the SPI block mode.
\param[in] handle spi handle
\param[in] flag 1 - enbale the block mode. 0 - disable the block mode
\return error code
*/
int32_t drv_spu_spi_config_block_mode(spi_handle_t handle, int32_t flag);
/**
\brief Set the SPI baudrate.
\param[in] handle spi handle
\param[in] baud spi baud rate
\return error code
*/
int32_t drv_spu_spi_config_baudrate(spi_handle_t handle, uint32_t baud);
/**
\brief config the SPI bit order.
\param[in] handle spi handle
\param[in] order spi bit order.\ref spi_bit_order_e
\return error code
*/
int32_t drv_spu_spi_config_bit_order(spi_handle_t handle, spi_bit_order_e order);
/**
\brief Set the SPI datawidth.
\param[in] handle spi handle
\param[in] datawidth date frame size in bits
\return error code
*/
int32_t drv_spu_spi_config_datawidth(spi_handle_t handle, uint32_t datawidth);
/**
\brief config the SPI format.
\param[in] handle spi handle
\param[in] format spi format. \ref spi_format_e
\return error code
*/
int32_t drv_spu_spi_config_format(spi_handle_t handle, spi_format_e format);
/**
\brief config the SPI slave select mode.
\param[in] handle spi handle
\param[in] ss_mode spi slave select mode. \ref spi_ss_mode_e
\return error code
*/
int32_t drv_spu_spi_config_ss_mode(spi_handle_t handle, spi_ss_mode_e ss_mode);
/**
\brief Get the number of the currently transferred.
\param[in] handle spi handle to operate.
\return the number of the currently transferred data items
*/
uint32_t drv_spu_spi_get_data_count(spi_handle_t handle);
/**
\brief control spi power.
\param[in] handle spi handle to operate.
\param[in] state power state.\ref drv_spu_power_stat_e.
\return error code
*/
int32_t drv_spu_spi_power_control(spi_handle_t handle, csi_power_stat_e state);
/**
\brief Control the Slave Select signal (SS).
\param[in] handle spi handle to operate.
\param[in] stat SS state. \ref spi_ss_stat_e.
\return error code
*/
int32_t drv_spu_spi_ss_control(spi_handle_t handle, spi_ss_stat_e stat);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SPU_SPI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/spu_spi.h | C | apache-2.0 | 13,301 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_spu_usart.h
* @brief header file for usart driver
* @version V1.0
* @date 02. June 2017
* @model spu_uart
******************************************************************************/
#ifndef _CSI_USART_H_
#define _CSI_USART_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for usart handle.
typedef void *usart_handle_t;
/****** USART specific error codes *****/
typedef enum {
USART_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
USART_ERROR_BAUDRATE, ///< Specified baudrate not supported
USART_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
USART_ERROR_PARITY, ///< Specified Parity not supported
USART_ERROR_STOP_BITS, ///< Specified number of Stop bits not supported
USART_ERROR_FLOW_CONTROL, ///< Specified Flow Control not supported
USART_ERROR_CPOL, ///< Specified Clock Polarity not supported
USART_ERROR_CPHA ///< Specified Clock Phase not supported
} usart_error_e;
/*----- USART Control Codes: Mode -----*/
typedef enum {
USART_MODE_ASYNCHRONOUS = 0, ///< USART (Asynchronous)
USART_MODE_SYNCHRONOUS_MASTER, ///< Synchronous Master
USART_MODE_SYNCHRONOUS_SLAVE, ///< Synchronous Slave (external clock signal)
USART_MODE_SINGLE_WIRE, ///< USART Single-wire (half-duplex)
USART_MODE_SINGLE_IRDA, ///< UART IrDA
USART_MODE_SINGLE_SMART_CARD, ///< UART Smart Card
} usart_mode_e;
/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
typedef enum {
USART_DATA_BITS_5 = 0, ///< 5 Data bits
USART_DATA_BITS_6, ///< 6 Data bit
USART_DATA_BITS_7, ///< 7 Data bits
USART_DATA_BITS_8, ///< 8 Data bits (default)
USART_DATA_BITS_9 ///< 9 Data bits
} usart_data_bits_e;
/*----- USART Control Codes: Mode Parameters: Parity -----*/
typedef enum {
USART_PARITY_NONE = 0, ///< No Parity (default)
USART_PARITY_EVEN, ///< Even Parity
USART_PARITY_ODD, ///< Odd Parity
USART_PARITY_1, ///< Parity forced to 1
USART_PARITY_0 ///< Parity forced to 0
} usart_parity_e;
/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
typedef enum {
USART_STOP_BITS_1 = 0, ///< 1 Stop bit (default)
USART_STOP_BITS_2, ///< 2 Stop bits
USART_STOP_BITS_1_5, ///< 1.5 Stop bits
USART_STOP_BITS_0_5 ///< 0.5 Stop bits
} usart_stop_bits_e;
/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
typedef enum {
USART_CPOL0 = 0, ///< CPOL = 0 (default). data are captured on rising edge (low->high transition)
USART_CPOL1 ///< CPOL = 1. data are captured on falling edge (high->lowh transition)
} usart_cpol_e;
/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
typedef enum {
USART_CPHA0 = 0, ///< CPHA = 0 (default). sample on first (leading) edge
USART_CPHA1 ///< CPHA = 1. sample on second (trailing) edge
} usart_cpha_e;
/*----- USART Control Codes: flush data type-----*/
typedef enum {
USART_FLUSH_WRITE,
USART_FLUSH_READ
} usart_flush_type_e;
/*----- USART Control Codes: flow control type-----*/
typedef enum {
USART_FLOWCTRL_NONE,
USART_FLOWCTRL_CTS,
USART_FLOWCTRL_RTS,
USART_FLOWCTRL_CTS_RTS
} usart_flowctrl_type_e;
/*----- USART Modem Control -----*/
typedef enum {
USART_RTS_CLEAR, ///< Deactivate RTS
USART_RTS_SET, ///< Activate RTS
USART_DTR_CLEAR, ///< Deactivate DTR
USART_DTR_SET ///< Activate DTR
} usart_modem_ctrl_e;
/*----- USART Modem Status -----*/
typedef struct {
uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
} usart_modem_stat_t;
/*----- USART Control Codes: on-off intrrupte type-----*/
typedef enum {
USART_INTR_WRITE,
USART_INTR_READ
} usart_intr_type_e;
/**
\brief USART Status
*/
typedef struct {
uint32_t tx_busy : 1; ///< Transmitter busy flag
uint32_t rx_busy : 1; ///< Receiver busy flag
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)(Synchronous Slave)
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
uint32_t tx_enable : 1; ///< Transmitter enable flag
uint32_t rx_enable : 1; ///< Receiver enbale flag
} usart_status_t;
/****** USART Event *****/
typedef enum {
USART_EVENT_SEND_COMPLETE = 0, ///< Send completed; however USART may still transmit data
USART_EVENT_RECEIVE_COMPLETE = 1, ///< Receive completed
USART_EVENT_TRANSFER_COMPLETE = 2, ///< Transfer completed
USART_EVENT_TX_COMPLETE = 3, ///< Transmit completed (optional)
USART_EVENT_TX_UNDERFLOW = 4, ///< Transmit data not available (Synchronous Slave)
USART_EVENT_RX_OVERFLOW = 5, ///< Receive data overflow
USART_EVENT_RX_TIMEOUT = 6, ///< Receive character timeout (optional)
USART_EVENT_RX_BREAK = 7, ///< Break detected on receive
USART_EVENT_RX_FRAMING_ERROR = 8, ///< Framing error detected on receive
USART_EVENT_RX_PARITY_ERROR = 9, ///< Parity error detected on receive
USART_EVENT_CTS = 10, ///< CTS state changed (optional)
USART_EVENT_DSR = 11, ///< DSR state changed (optional)
USART_EVENT_DCD = 12, ///< DCD state changed (optional)
USART_EVENT_RI = 13, ///< RI state changed (optional)
USART_EVENT_RECEIVED = 14, ///< Data Received, only in usart fifo, call receive()/transfer() get the data
} usart_event_e;
typedef void (*usart_event_cb_t)(int32_t idx, usart_event_e event); ///< Pointer to \ref usart_event_cb_t : USART Event call back.
/**
\brief USART Driver Capabilities.
*/
typedef struct {
uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
uint32_t single_wire : 1; ///< supports UART Single-wire mode
uint32_t irda : 1; ///< supports UART IrDA mode
uint32_t smart_card : 1; ///< supports UART Smart Card mode
uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
uint32_t flow_control_rts : 1; ///< RTS Flow Control available
uint32_t flow_control_cts : 1; ///< CTS Flow Control available
uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref USART_EVENT_TX_COMPLETE
uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref USART_EVENT_RX_TIMEOUT
uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
uint32_t event_cts : 1; ///< Signal CTS change event: \ref USART_EVENT_CTS
uint32_t event_dsr : 1; ///< Signal DSR change event: \ref USART_EVENT_DSR
uint32_t event_dcd : 1; ///< Signal DCD change event: \ref USART_EVENT_DCD
uint32_t event_ri : 1; ///< Signal RI change event: \ref USART_EVENT_RI
} usart_capabilities_t;
/**
\brief Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
\param[in] idx usart index
\param[in] cb_event event call back function \ref usart_event_cb_t
\return return usart handle if success
*/
usart_handle_t drv_spu_usart_initialize(int32_t idx, usart_event_cb_t cb_event);
/**
\brief De-initialize USART Interface. stops operation and releases the software resources used by the interface
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_spu_usart_uninitialize(usart_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx usart index
\return \ref usart_capabilities_t
*/
usart_capabilities_t drv_spu_usart_get_capabilities(int32_t idx);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.
\param[in] baud baud rate.
\param[in] mode \ref usart_mode_e .
\param[in] parity \ref usart_parity_e .
\param[in] stopbits \ref usart_stop_bits_e .
\param[in] bits \ref usart_data_bits_e .
\return error code
*/
int32_t drv_spu_usart_config(usart_handle_t handle,
uint32_t baud,
usart_mode_e mode,
usart_parity_e parity,
usart_stop_bits_e stopbits,
usart_data_bits_e bits);
/**
\brief Start sending data to USART transmitter,(received data is ignored).
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref drv_spu_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[in] data Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to send
\return error code
*/
int32_t drv_spu_usart_send(usart_handle_t handle, const void *data, uint32_t num);
/**
\brief Abort Send data to USART transmitter
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_spu_usart_abort_send(usart_handle_t handle);
/**
\brief Start receiving data from USART receiver. \n
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref drv_spu_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[out] data Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to receive
\return error code
*/
int32_t drv_spu_usart_receive(usart_handle_t handle, void *data, uint32_t num);
/**
\brief query data from UART receiver FIFO.
\param[in] handle usart handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver
\param[in] num Number of data items to receive
\return fifo data num to receive
*/
int32_t drv_spu_usart_receive_query(usart_handle_t handle, void *data, uint32_t num);
/**
\brief Abort Receive data from USART receiver
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_spu_usart_abort_receive(usart_handle_t handle);
/**
\brief Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref drv_spu_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[in] data_out Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[out] data_in Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to transfer
\return error code
*/
int32_t drv_spu_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num);
/**
\brief abort sending/receiving data to/from USART transmitter/receiver.
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_spu_usart_abort_transfer(usart_handle_t handle);
/**
\brief Get USART status.
\param[in] handle usart handle to operate.
\return USART status \ref usart_status_t
*/
usart_status_t drv_spu_usart_get_status(usart_handle_t handle);
/**
\brief flush receive/send data.
\param[in] handle usart handle to operate.
\param[in] type \ref usart_flush_type_e .
\return error code
*/
int32_t drv_spu_usart_flush(usart_handle_t handle, usart_flush_type_e type);
/**
\brief set interrupt mode.
\param[in] handle usart handle to operate.
\param[in] type \ref usart_intr_type_e.
\param[in] flag 0-OFF, 1-ON.
\return error code
*/
int32_t drv_spu_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag);
/**
\brief set the baud rate of usart.
\param[in] baud usart base to operate.
\param[in] baudrate baud rate
\return error code
*/
int32_t drv_spu_usart_config_baudrate(usart_handle_t handle, uint32_t baud);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.
\param[in] mode \ref usart_mode_e
\return error code
*/
int32_t drv_spu_usart_config_mode(usart_handle_t handle, usart_mode_e mode);
/**
\brief config usart parity.
\param[in] handle usart handle to operate.
\param[in] parity \ref usart_parity_e
\return error code
*/
int32_t drv_spu_usart_config_parity(usart_handle_t handle, usart_parity_e parity);
/**
\brief config usart stop bit number.
\param[in] handle usart handle to operate.
\param[in] stopbits \ref usart_stop_bits_e
\return error code
*/
int32_t drv_spu_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit);
/**
\brief config usart data length.
\param[in] handle usart handle to operate.
\param[in] databits \ref usart_data_bits_e
\return error code
*/
int32_t drv_spu_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits);
/**
\brief get character in query mode.
\param[in] handle usart handle to operate.
\param[out] ch the pointer to the received character.
\return error code
*/
int32_t drv_spu_usart_getchar(usart_handle_t handle, uint8_t *ch);
/**
\brief transmit character in query mode.
\param[in] handle usart handle to operate.
\param[in] ch the input character
\return error code
*/
int32_t drv_spu_usart_putchar(usart_handle_t handle, uint8_t ch);
/**
\brief Get usart send data count.
\param[in] handle usart handle to operate.
\return number of currently transmitted data bytes
*/
uint32_t drv_spu_usart_get_tx_count(usart_handle_t handle);
/**
\brief Get usart received data count.
\param[in] handle usart handle to operate.
\return number of currently received data bytes
*/
uint32_t drv_spu_usart_get_rx_count(usart_handle_t handle);
/**
\brief control usart power.
\param[in] handle usart handle to operate.
\param[in] state power state.\ref drv_spu_power_stat_e.
\return error code
*/
int32_t drv_spu_usart_power_control(usart_handle_t handle, csi_power_stat_e state);
/**
\brief config usart flow control type.
\param[in] handle usart handle to operate.
\param[in] flowctrl_type flow control type.\ref usart_flowctrl_type_e.
\return error code
*/
int32_t drv_spu_usart_config_flowctrl(usart_handle_t handle,
usart_flowctrl_type_e flowctrl_type);
/**
\brief config usart clock Polarity and Phase.
\param[in] handle usart handle to operate.
\param[in] cpol Clock Polarity.\ref usart_cpol_e.
\param[in] cpha Clock Phase.\ref usart_cpha_e.
\return error code
*/
int32_t drv_spu_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha);
/**
\brief control the transmitter.
\param[in] handle usart handle to operate.
\param[in] enable 1 - enable the transmitter. 0 - disable the transmitter
\return error code
*/
int32_t drv_spu_usart_control_tx(usart_handle_t handle, uint32_t enable);
/**
\brief control the receiver.
\param[in] handle usart handle to operate.
\param[in] enable 1 - enable the receiver. 0 - disable the receiver
\return error code
*/
int32_t drv_spu_usart_control_rx(usart_handle_t handle, uint32_t enable);
/**
\brief control the break.
\param[in] handle usart handle to operate.
\param[in] enable 1- Enable continuous Break transmission,0 - disable continuous Break transmission
\return error code
*/
int32_t drv_spu_usart_control_break(usart_handle_t handle, uint32_t enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_USART_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/spu_usart.h | C | apache-2.0 | 18,463 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_tee.h
* @brief Header File for TEE
* @version V1.0
* @date 12 Sep 2017
* @model tee
******************************************************************************/
#ifndef _CSI_AES_H_
#define _CSI_AES_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** TEE AES mode *****/
typedef enum {
TEE_AES_MODE_ECB = 0, ///< TEE AES ECB mode
TEE_AES_MODE_CBC = 1, ///< TEE AES CBC mode
TEE_AES_MODE_MAX, ///< invaild mode
}
tee_aes_mode_e;
/**
\brief TEE AES encrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to ciphertext buffer
\param[in] mode \ref tee_aes_mode_e
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_aes_encrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t iv[16],
uint8_t *out,
tee_aes_mode_e mode);
/**
\brief TEE AES decrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\param[in] mode \ref tee_aes_mode_e
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_aes_decrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t iv[16],
uint8_t *out,
uint32_t mode);
/**
\brief TEE AES ECB encrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to ciphertext buffer
\return return 0 if successful,otherwise error code
*/
#define csi_tee_aes_encrypt_ecb(in, in_len, key, key_len, out) \
csi_tee_aes_encrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB)
/**
\brief TEE AES ECB decrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\return return 0 if successful,otherwise error code
*/
#define csi_tee_aes_decrypt_ecb(in, in_len, key, key_len, out) \
csi_tee_aes_decrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB)
/**
\brief TEE AES CBC encrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\return return 0 if successful,otherwise error code
*/
#define csi_tee_aes_encrypt_cbc(in, in_len, key, key_len, iv, out) \
csi_tee_aes_encrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC)
/**
\brief TEE AES CBC decrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\return return 0 if successful,otherwise error code
*/
#define csi_tee_aes_decrypt_cbc(in, in_len, key, key_len, iv, out) \
csi_tee_aes_decrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC)
/**
\brief TEE BASE64 encode/decode
\param[in] in Pointer to input data buffer
\param[in] in_len input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len output data buffer length
\param[in] is_encode 1 encode 0 decode
\param[in] wsafe base64 websafe feature,set 1, replace "+/" with "-_"
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_base64(const uint8_t *in, uint32_t in_len,
uint8_t *out, uint32_t *out_len,
uint32_t is_encode,
uint32_t wsafe);
/**
\brief TEE BASE64 encode
\param[in] in Pointer to input data buffer
\param[in] in_len input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len output data buffer length
\return return 0 if successful,otherwise error code
*/
#define csi_tee_base64_encode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,1,0)
/**
\brief TEE BASE64 decode
\param[in] in Pointer to input data buffer
\param[in] in_len input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len output data buffer length
\return return 0 if successful,otherwise error code
*/
#define csi_tee_base64_decode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,0,0)
/**
\brief TEE BASE64 web safe encode
\param[in] in Pointer to input data buffer
\param[in] in_len input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len output data buffer length
\return return 0 if successful,otherwise error code
*/
#define csi_tee_base64_websafe_encode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,1,1)
/**
\brief TEE BASE64 web safe decode
\param[in] in Pointer to input data buffer
\param[in] in_len input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len output data buffer length
\return return 0 if successful,otherwise error code
*/
#define csi_tee_base64_websafe_decode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,0,1)
/**
\brief TEE obtain CID from Key Provisioning
\param[out] out Pointer to cid buffer
\param[out] out_len cid buffer length,if cid obtain successfully,
out_len is updated to actual cid sizes
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_get_cid(uint8_t *out, uint32_t *out_len);
/****** lpm mode *****/
typedef enum {
TEE_LPM_MODE_WAIT = 0, ///< lpm wait
TEE_LPM_MODE_DOZE = 1, ///< lpm doze
TEE_LPM_MODE_STOP = 2, ///< lpm stop
TEE_LPM_MODE_STANDBY = 3, ///< lpm standby
TEE_LPM_MODE_CLOCK = 4, ///< lpm clock gate
TEE_LPM_MODE_MAX,
} tee_lpm_mode_e;
/**
\brief TEE set low power mode
\param[in] gate not use for now
\param[in] irqid not use for now
\param[in] mode \ref tee_lpm_mode_e
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_enter_lpm(uint32_t gate, uint32_t irqid, tee_lpm_mode_e mode);
/**
\brief TEE obtain manifest info from manifest table
\note call csi_tee_get_sys_img_info, csi_tee_get_sys_os_version or csi_tee_get_sys_partition is better
\param[out] out Pointer to info buffer
\param[out] out_len Info buffer length,if info obtain successfully,
out_len is updated to actual sizes
\param[in] name info name
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_get_manifest_info(uint8_t *out, uint32_t *out_len, char *name);
/**
\brief TEE obtain image buffer from manifest table
\param[out] out Pointer to image buffer
\param[out] out_len Image buffer length,if info obtain successfully,
out_len is updated to actual image buffer sizes
\param[in] img_name image name
\return return 0 if successful,otherwise error code
*/
#define csi_tee_get_sys_img_info(out,out_len,img_name) \
csi_tee_get_manifest_info(out,out_len,img_name)
/**
\brief TEE obtain os version from manifest table
\param[out] out Pointer to os version buffer
\param[out] out_len OS version buffer length,if info obtain successfully,
out_len is updated to actual os version buffer sizes
\return return 0 if successful,otherwise error code
*/
#define csi_tee_get_sys_os_version(out,out_len) \
csi_tee_get_manifest_info(out,out_len,"os_v")
/**
\brief TEE obtain partition buffer from manifest table
\param[out] out Pointer to partition buffer
\param[out] out_len Partition buffer length,if info obtain successfully,
out_len is updated to actual partition buffer sizes
\return return 0 if successful,otherwise error code
*/
#define csi_tee_get_sys_partition(out,out_len) \
csi_tee_get_manifest_info(out,out_len,"sys_p")
/**
\brief TEE set random seed
\param[in] Seed random sedd
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_rand_seed(uint32_t seed);
/**
\brief TEE ramdom date generation
\param[out] out Pointer to random data buffer
\param[in] out_len Data buffer length
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_rand_generate(uint8_t *out, uint32_t out_len);
/****** TEE RSA sign type *****/
typedef enum {
TEE_RSA_MD5 = 0, ///< MD5
TEE_RSA_SHA1 = 1, ///< SHA1
TEE_RSA_SHA256 = 3, ///< SHA256
TEE_RSA_SIGN_TYPE_MAX, ///< invailed type
} tee_rsa_sign_type_e;
/**
\brief TEE RSA sign with private key
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] key Pointer to private key,key contains n, e, d
\param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048
\param[out] sign Pointer to sign buffer
\param[out] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_rsa_sign(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *sign, uint32_t *sign_len,
tee_rsa_sign_type_e type);
/**
\brief TEE RSA verify with public key
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] key Pointer to public key,key contains n, e
\param[in] key_len Public key size,must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048
\param[in] sign Pointer to sign buffer
\param[in] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return return 0 if verify successful,otherwise error code
*/
int32_t csi_tee_rsa_verify(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *sign, uint32_t sign_len,
tee_rsa_sign_type_e type);
/****** TEE RSA padding mode *****/
typedef enum {
TEE_RSA_PKCS1_PADDING = 0x01, ///< RSA PKCS padding mode
TEE_RSA_NO_PADDING = 0x02, ///< RSA no padding mode
} tee_rsa_padding_mode_e;
/**
\brief TEE RSA encrypt with public key
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] key Pointer to public key,key contains n, e
\param[in] key_len Public key size, must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048
\param[in] out Pointer to ciphertext buffer
\param[in] out_len Ciphertext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_rsa_encrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *out, uint32_t *out_len,
tee_rsa_padding_mode_e padding);
/**
\brief TEE RSA decrypt with private key
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to private key,key contains n, e, d
\param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048
\param[in] out Pointer to plaintext buffer
\param[in] out_len Plaintext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_rsa_decrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *out, uint32_t *out_len,
tee_rsa_padding_mode_e padding);
/**
\brief TEE RSA sign with internal private key
\note Only use if key provisioning exist
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[out] sign Pointer to sign buffer
\param[out] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return return 0 if successful,otherwise error code
*/
#define csi_tee_cid_rsa_sign(in,in_len,sign,sign_len,type) \
csi_tee_rsa_sign(in,in_len,NULL,0,sign,sign_len,type)
/**
\brief TEE RSA verify with internal public key
\note Only use if key provisioning exist
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] sign Pointer to sign buffer
\param[in] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return return 0 if verify successful,otherwise error code
*/
#define csi_tee_cid_rsa_verify(in,in_len,sign,sign_len,type) \
csi_tee_rsa_verify(in,in_len,NULL,0,sign,sign_len,type)
/**
\brief TEE RSA encrypt with internal public key
\note Only use if key provisioning exist
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] out Pointer to ciphertext buffer
\param[in] out_len Ciphertext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return return 0 if successful,otherwise error code
*/
#define csi_tee_cid_rsa_encrypt(in,in_len,out,out_len,padding) \
csi_tee_rsa_encrypt(in,in_len,NULL,0,out,out_len,padding)
/**
\brief TEE RSA decrypt with internal private key
\note Only use if key provisioning exist
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to private key,key contains n, e, d
\param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048
\param[in] out Pointer to plaintext buffer
\param[in] out_len Plaintext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return return 0 if successful,otherwise error code
*/
#define csi_tee_cid_rsa_decrypt(in,in_len,out,out_len,padding) \
csi_tee_rsa_decrypt(in,in_len,NULL,0,out,out_len,padding)
/**
\brief verify boot image with boot public key
\note Only use if key provisioning exist
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] sign Pointer to sign buffer
\param[in] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return return 0 if verify successful,otherwise error code
*/
int32_t csi_tee_img_rsa_verify(const uint8_t *in, uint32_t in_len,
uint8_t *sign, uint32_t sign_len,
tee_rsa_sign_type_e type);
/****** TEE HASH operation mode *****/
typedef enum {
TEE_HASH_OP_NONE = 0, ///< No operation
TEE_HASH_OP_START = 1, ///< HASH init
TEE_HASH_OP_UPDATA = 2, ///< HASH update
TEE_HASH_OP_FINISH = 3, ///< HASH finish
TEE_HASH_OP_MAX, ///< invailed operation
} tee_hash_op_e;
/****** TEE HMAC type *****/
typedef enum {
TEE_HMAC_SHA1 = 1, ///< HMAC with SHA1
} tee_hmac_type_e;
/**
\brief TEE HAMC
\note Call csi_tee_hmac_digest is better
out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[in] key Pointer to key buffer
\param[in] key_len Key buffer size
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_hmac_type_e
\param[in] hash_op \ref tee_hash_op_e
\param[in] ctx Pointer to context of hmac
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_hmac(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *out,
tee_hmac_type_e type,
tee_hash_op_e hash_op,
uint32_t *ctx);
/**
\brief TEE HAMC digest
\note out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[in] key Pointer to key buffer
\param[in] key_len Key buffer size
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_hmac_type_e
\return return 0 if successful,otherwise error code
*/
#define csi_tee_hmac_digest(in,in_len,key,key_len,out,type) \
csi_tee_hmac(in,in_len,key,key_len,out,type,TEE_HASH_OP_NONE,NULL)
/****** TEE SHA type *****/
typedef enum {
TEE_SHA1 = 0, ///< SHA1
TEE_SHA256 = 1, ///< SHA256
TEE_SHA224 = 2, ///< SHA224
TEE_SHA384 = 3, ///< SHA384
TEE_SHA512 = 4, ///< SHA512
TEE_SHA_MAX, ///< invaild sha type
} tee_sha_type_t;
/**
\brief TEE SHA
\note Call csi_tee_sha_digest, csi_tee_sha_start, csi_tee_sha_update or csi_tee_sha_finish is better
out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_sha_type_t
\param[in] hash_op \ref tee_hash_op_e
\param[in] ctx Pointer to context of sha
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_sha(const uint8_t *in, uint32_t in_len,
uint8_t *out,
tee_sha_type_t type,
tee_hash_op_e hash_op,
void *ctx);
/**
\brief TEE SHA digest
\note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_sha_type_t
\return return 0 if successful,otherwise error code
*/
#define csi_tee_sha_digest(in,in_len,out,type) \
csi_tee_sha(in,in_len,out,type,TEE_HASH_OP_NONE,NULL);
/**
\brief TEE SHA start, initial sha
\param[in] type \ref tee_sha_type_t
\param[in] ctx Pointer to context of sha
\return return 0 if successful,otherwise error code
*/
#define csi_tee_sha_start(type,ctx) \
csi_tee_sha(NULL,0,NULL,type,TEE_HASH_OP_START,ctx);
/**
\brief TEE SHA update, update data
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[in] ctx Pointer to context of sha
\return return 0 if successful,otherwise error code
*/
#define csi_tee_sha_update(in,in_len,ctx) \
csi_tee_sha(in,in_len,NULL,0,TEE_HASH_OP_UPDATA,ctx);
/**
\brief TEE SHA digest, get sha digest
\note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256
\param[out] out Pointer to output date buffer
\param[in] ctx Pointer to context of sha
\return return 0 if successful,otherwise error code
*/
#define csi_tee_sha_finish(out,ctx) \
csi_tee_sha(NULL,0,out,0,TEE_HASH_OP_FINISH,ctx);
/**
\brief TEE get device name and product key
\param[in] name_encrypted Pointer to device name ciphertext
\param[in] name_encrypted_len device name ciphertext length
\param[in] product_key_encrypted Pointer to device product key ciphertext
\param[in] product_key_encrypted_len Device product key ciphertext length
\param[out] name Pointer to device name
\param[out] name_len Device name length
\param[out] product_key Pointer to device product key
\param[out] product_key_len Device product key length
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_dev_info_get(const uint8_t *name_encrypted, uint32_t name_encrypted_len,
const uint8_t *product_key_encrypted, uint32_t product_key_encrypted_len,
const uint8_t *name, uint32_t *name_len,
const uint8_t *product_key, uint32_t *product_key_len);
/**
\brief TEE device info sign
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] device_secret Pointer to device secret ciphertext
\param[in] device_secret_len Device secret ciphertext length
\param[out] sign Pointer to signed buffer
\param[out] sign_len Signed buffer length
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_dev_info_sign(const uint8_t *in, uint32_t in_len,
const uint8_t *device_secret, uint32_t device_secret_len,
const uint8_t *sign, uint32_t *sign_len);
/**
\brief TEE device info encrypt/decrypt
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] out Pointer to output date buffer
\param[in] out_len Onput data buffer length
\param[in] is_enc 1 incrypt 0 decrypt
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_dev_info_crypt(const uint8_t *in, uint32_t in_len,
uint8_t *out, uint32_t *out_len,
uint8_t is_enc);
/**
\brief TEE device info encrypt
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] out Pointer to output date buffer
\param[in] out_len Onput data buffer length
\return return 0 if successful,otherwise error code
*/
#define csi_tee_dev_info_encrypt(in, in_len, out, out_len) \
csi_tee_dev_info_crypt(in, in_len, out, out_len, 1)
/**
\brief TEE device info decrypt
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] out Pointer to output date buffer
\param[in] out_len Onput data buffer length
\return return 0 if successful,otherwise error code
*/
#define csi_tee_dev_info_decrypt(in, in_len, out, out_len) \
csi_tee_dev_info_crypt(in, in_len, out, out_len, 0)
/**
\brief Set system frequence
\param[in] clk_src indicate clock source type
\param[in] clk_val system freqence to be set
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_set_sys_freq(uint32_t clk_src, uint32_t clk_val);
/**
\brief Get system frequence
\param[in] clk_val value address to store system freqence
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_get_sys_freq(uint32_t *clk_val);
/**
\brief read system register
\param[in] addr indicate register address
\param[out] val value to read from the address
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_read_reg(uint32_t addr, uint32_t *val);
/**
\brief wrte system register
\param[in] addr indicate register address
\param[in] val value to be written into the address
\return return 0 if successful,otherwise error code
*/
int32_t csi_tee_write_reg(uint32_t addr, uint32_t val);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_AES_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/tee.h | C | apache-2.0 | 26,317 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_timer.h
* @brief header file for timer driver
* @version V1.0
* @date 02. June 2017
* @model timer
******************************************************************************/
#ifndef _CSI_TIMER_H_
#define _CSI_TIMER_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for timer handle.
typedef void *timer_handle_t;
/*----- TIMER Control Codes: Mode -----*/
typedef enum {
TIMER_MODE_FREE_RUNNING = 0, ///< free running mode
TIMER_MODE_RELOAD ///< reload mode
} timer_mode_e;
/**
\brief TIMER Status
*/
typedef struct {
uint32_t active : 1; ///< timer active flag
uint32_t timeout : 1; ///< timeout flag
} timer_status_t;
/**
\brief TIMER Event
*/
typedef enum {
TIMER_EVENT_TIMEOUT = 0 ///< time out event
} timer_event_e;
typedef void (*timer_event_cb_t)(int32_t idx, timer_event_e event); ///< Pointer to \ref timer_event_cb_t : TIMER Event call back.
/**
\brief Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
\param[in] idx timer index
\param[in] cb_event event call back function \ref timer_event_cb_t
\param[in] cb_arg arguments of cb_event
\return pointer to timer instance
*/
timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event);
/**
\brief De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
\param[in] handle timer handle to operate.
\return error code
*/
int32_t csi_timer_uninitialize(timer_handle_t handle);
/**
\brief control timer power.
\param[in] handle timer handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state);
/**
\brief config timer mode.
\param[in] handle timer handle to operate.
\param[in] mode \ref timer_mode_e
\return error code
*/
int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode);
/**
\brief Set timeout just for the reload mode.
\param[in] handle timer handle to operate.
\param[in] timeout the timeout value in microseconds(us).
\return error code
*/
int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout);
/**
\brief Start timer.
\param[in] handle timer handle to operate.
\return error code
*/
int32_t csi_timer_start(timer_handle_t handle);
/**
\brief Stop timer.
\param[in] handle timer handle to operate.
\return error code
*/
int32_t csi_timer_stop(timer_handle_t handle);
/**
\brief suspend timer.
\param[in] handle timer handle to operate.
\return error code
*/
int32_t csi_timer_suspend(timer_handle_t handle);
/**
\brief resume timer.
\param[in] handle timer handle to operate.
\return error code
*/
int32_t csi_timer_resume(timer_handle_t handle);
/**
\brief get timer current value
\param[in] handle timer handle to operate.
\param[out] value timer current value
\return error code
*/
int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value);
/**
\brief Get TIMER status.
\param[in] handle timer handle to operate.
\return TIMER status \ref timer_status_t
*/
timer_status_t csi_timer_get_status(timer_handle_t handle);
/**
\brief get timer reload value
\param[in] handle timer handle to operate.
\param[out] value timer reload value
\return error code
*/
int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_TIMER_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/timer.h | C | apache-2.0 | 4,042 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_tipc.h
* @brief header file for tipc driver
* @version V1.0
* @date 08. Mar 2019
* @model tipc
******************************************************************************/
#ifndef _DRV_TIPC_H_
#define _DRV_TIPC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
TIPC_PROPERITY_UNTRUST = 0, ///< untrust property in AHB/APB island
TIPC_PROPERITY_TRUST ///< trust property in AHB/APB island
} enum_tipc_properity_e;
/**
\brief Config the tipc module properity
\param[in] idx tipc module idx \ref ckenum_tipc_module_e
\param[in] properity module properity for trust \ref enum_tipc_properity_e
*/
void drv_tipc_set_module_properity(uint32_t idx, enum_tipc_properity_e properity);
/**
\brief set data to a module readable address
\param[in] idx tipc module idx \ref ckenum_tipc_module_e
\param[in] data set data
*/
void drv_tipc_set_module_rw_addr(uint32_t idx, uint32_t data);
/**
\brief get data from a module readable address
\param[in] idx tipc module idx \ref ckenum_tipc_module_e
\return get data
*/
uint32_t drv_tipc_get_module_rw_addr(uint32_t idx);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TIPC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/tipc.h | C | apache-2.0 | 1,478 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_trng.h
* @brief header file for trng driver
* @version V1.0
* @date 02. June 2017
* @model trng
******************************************************************************/
#ifndef _CSI_TRNG_H_
#define _CSI_TRNG_H_
#include "drv/common.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for trng handle.
typedef void *trng_handle_t;
/****** TRNG specific error codes *****/
typedef enum {
TRNG_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1) ///< Specified Mode not supported
} trng_error_e;
/**
\brief TRNG Status
*/
typedef struct {
uint32_t busy : 1;
uint32_t data_valid : 1; ///< Data is valid flag
} trng_status_t;
/****** TRNG Event *****/
typedef enum {
TRNG_EVENT_DATA_GENERATE_COMPLETE = 0 ///< True random number generates completely
} trng_event_e;
typedef void (*trng_event_cb_t)(int32_t idx, trng_event_e event); ///< Pointer to \ref trng_event_cb_t : TRNG Event call back.
/**
\brief TRNG Device Driver Capabilities.
*/
typedef struct {
uint32_t lowper_mode : 1; ///< supports low power mode
} trng_capabilities_t;
// Function documentation
/**
\brief Initialize TRNG Interface. 1. Initializes the resources needed for the TRNG interface 2.registers event callback function
\param[in] idx device id
\param[in] cb_event event call back function \ref trng_event_cb_t
\return pointer to trng handle
*/
trng_handle_t csi_trng_initialize(int32_t idx, trng_event_cb_t cb_event);
/**
\brief De-initialize TRNG Interface. stops operation and releases the software resources used by the interface
\param[in] handle trng handle to operate.
\return error code
*/
int32_t csi_trng_uninitialize(trng_handle_t handle);
/**
\brief control trng power.
\param[in] handle trng handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_trng_power_control(trng_handle_t handle, csi_power_stat_e state);
/**
\brief Get driver capabilities.
\param[in] idx device id.
\return \ref trng_capabilities_t
*/
trng_capabilities_t csi_trng_get_capabilities(int32_t idx);
/**
\brief Get data from the TRNG.
\param[in] handle trng handle to operate.
\param[out] data Pointer to buffer with data get from TRNG
\param[in] num Number of data items to obtain
\return error code
*/
int32_t csi_trng_get_data(trng_handle_t handle, void *data, uint32_t num);
/**
\brief Get TRNG status.
\param[in] handle trng handle to operate.
\return TRNG status \ref trng_status_t
*/
trng_status_t csi_trng_get_status(trng_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_TRNG_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/trng.h | C | apache-2.0 | 2,978 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_usart.h
* @brief header file for usart driver
* @version V1.0
* @date 02. June 2017
* @model usart
******************************************************************************/
#ifndef _CSI_USART_H_
#define _CSI_USART_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for usart handle.
typedef void *usart_handle_t;
/****** USART specific error codes *****/
typedef enum {
USART_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
USART_ERROR_BAUDRATE, ///< Specified baudrate not supported
USART_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
USART_ERROR_PARITY, ///< Specified Parity not supported
USART_ERROR_STOP_BITS, ///< Specified number of Stop bits not supported
USART_ERROR_FLOW_CONTROL, ///< Specified Flow Control not supported
USART_ERROR_CPOL, ///< Specified Clock Polarity not supported
USART_ERROR_CPHA ///< Specified Clock Phase not supported
} usart_error_e;
/*----- USART Control Codes: Mode -----*/
typedef enum {
USART_MODE_ASYNCHRONOUS = 0, ///< USART (Asynchronous)
USART_MODE_SYNCHRONOUS_MASTER, ///< Synchronous Master
USART_MODE_SYNCHRONOUS_SLAVE, ///< Synchronous Slave (external clock signal)
USART_MODE_SINGLE_WIRE, ///< USART Single-wire (half-duplex)
USART_MODE_SINGLE_IRDA, ///< UART IrDA
USART_MODE_SINGLE_SMART_CARD, ///< UART Smart Card
} usart_mode_e;
/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
typedef enum {
USART_DATA_BITS_5 = 0, ///< 5 Data bits
USART_DATA_BITS_6, ///< 6 Data bit
USART_DATA_BITS_7, ///< 7 Data bits
USART_DATA_BITS_8, ///< 8 Data bits (default)
USART_DATA_BITS_9 ///< 9 Data bits
} usart_data_bits_e;
/*----- USART Control Codes: Mode Parameters: Parity -----*/
typedef enum {
USART_PARITY_NONE = 0, ///< No Parity (default)
USART_PARITY_EVEN, ///< Even Parity
USART_PARITY_ODD, ///< Odd Parity
USART_PARITY_1, ///< Parity forced to 1
USART_PARITY_0 ///< Parity forced to 0
} usart_parity_e;
/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
typedef enum {
USART_STOP_BITS_1 = 0, ///< 1 Stop bit (default)
USART_STOP_BITS_2, ///< 2 Stop bits
USART_STOP_BITS_1_5, ///< 1.5 Stop bits
USART_STOP_BITS_0_5 ///< 0.5 Stop bits
} usart_stop_bits_e;
/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
typedef enum {
USART_CPOL0 = 0, ///< CPOL = 0 (default). data are captured on rising edge (low->high transition)
USART_CPOL1 ///< CPOL = 1. data are captured on falling edge (high->lowh transition)
} usart_cpol_e;
/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
typedef enum {
USART_CPHA0 = 0, ///< CPHA = 0 (default). sample on first (leading) edge
USART_CPHA1 ///< CPHA = 1. sample on second (trailing) edge
} usart_cpha_e;
/*----- USART Control Codes: flush data type-----*/
typedef enum {
USART_FLUSH_WRITE,
USART_FLUSH_READ
} usart_flush_type_e;
/*----- USART Control Codes: flow control type-----*/
typedef enum {
USART_FLOWCTRL_NONE,
USART_FLOWCTRL_CTS,
USART_FLOWCTRL_RTS,
USART_FLOWCTRL_CTS_RTS
} usart_flowctrl_type_e;
/*----- USART Modem Control -----*/
typedef enum {
USART_RTS_CLEAR, ///< Deactivate RTS
USART_RTS_SET, ///< Activate RTS
USART_DTR_CLEAR, ///< Deactivate DTR
USART_DTR_SET ///< Activate DTR
} usart_modem_ctrl_e;
/*----- USART Modem Status -----*/
typedef struct {
uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
} usart_modem_stat_t;
/*----- USART Control Codes: on-off intrrupte type-----*/
typedef enum {
USART_INTR_WRITE,
USART_INTR_READ
} usart_intr_type_e;
/**
\brief USART Status
*/
typedef struct {
uint32_t tx_busy : 1; ///< Transmitter busy flag
uint32_t rx_busy : 1; ///< Receiver busy flag
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)(Synchronous Slave)
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
uint32_t tx_enable : 1; ///< Transmitter enable flag
uint32_t rx_enable : 1; ///< Receiver enbale flag
} usart_status_t;
/****** USART Event *****/
typedef enum {
USART_EVENT_SEND_COMPLETE = 0, ///< Send completed; however USART may still transmit data
USART_EVENT_RECEIVE_COMPLETE = 1, ///< Receive completed
USART_EVENT_TRANSFER_COMPLETE = 2, ///< Transfer completed
USART_EVENT_TX_COMPLETE = 3, ///< Transmit completed (optional)
USART_EVENT_TX_UNDERFLOW = 4, ///< Transmit data not available (Synchronous Slave)
USART_EVENT_RX_OVERFLOW = 5, ///< Receive data overflow
USART_EVENT_RX_TIMEOUT = 6, ///< Receive character timeout (optional)
USART_EVENT_RX_BREAK = 7, ///< Break detected on receive
USART_EVENT_RX_FRAMING_ERROR = 8, ///< Framing error detected on receive
USART_EVENT_RX_PARITY_ERROR = 9, ///< Parity error detected on receive
USART_EVENT_CTS = 10, ///< CTS state changed (optional)
USART_EVENT_DSR = 11, ///< DSR state changed (optional)
USART_EVENT_DCD = 12, ///< DCD state changed (optional)
USART_EVENT_RI = 13, ///< RI state changed (optional)
USART_EVENT_RECEIVED = 14, ///< Data Received, only in usart fifo, call receive()/transfer() get the data
} usart_event_e;
typedef void (*usart_event_cb_t)(int32_t idx, usart_event_e event); ///< Pointer to \ref usart_event_cb_t : USART Event call back.
/**
\brief USART Driver Capabilities.
*/
typedef struct {
uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
uint32_t single_wire : 1; ///< supports UART Single-wire mode
uint32_t irda : 1; ///< supports UART IrDA mode
uint32_t smart_card : 1; ///< supports UART Smart Card mode
uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
uint32_t flow_control_rts : 1; ///< RTS Flow Control available
uint32_t flow_control_cts : 1; ///< CTS Flow Control available
uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref USART_EVENT_TX_COMPLETE
uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref USART_EVENT_RX_TIMEOUT
uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
uint32_t event_cts : 1; ///< Signal CTS change event: \ref USART_EVENT_CTS
uint32_t event_dsr : 1; ///< Signal DSR change event: \ref USART_EVENT_DSR
uint32_t event_dcd : 1; ///< Signal DCD change event: \ref USART_EVENT_DCD
uint32_t event_ri : 1; ///< Signal RI change event: \ref USART_EVENT_RI
} usart_capabilities_t;
/**
\brief Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
\param[in] idx usart index
\param[in] cb_event event call back function \ref usart_event_cb_t
\return return usart handle if success
*/
usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event);
/**
\brief De-initialize USART Interface. stops operation and releases the software resources used by the interface
\param[in] handle usart handle to operate.
\return error code
*/
int32_t csi_usart_uninitialize(usart_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx usart index
\return \ref usart_capabilities_t
*/
usart_capabilities_t csi_usart_get_capabilities(int32_t idx);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.
\param[in] baud baud rate.
\param[in] mode \ref usart_mode_e .
\param[in] parity \ref usart_parity_e .
\param[in] stopbits \ref usart_stop_bits_e .
\param[in] bits \ref usart_data_bits_e .
\return error code
*/
int32_t csi_usart_config(usart_handle_t handle,
uint32_t baud,
usart_mode_e mode,
usart_parity_e parity,
usart_stop_bits_e stopbits,
usart_data_bits_e bits);
/**
\brief Start sending data to USART transmitter,(received data is ignored).
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref csi_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[in] data Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to send
\return error code
*/
int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num);
/**
\brief Abort Send data to USART transmitter
\param[in] handle usart handle to operate.
\return error code
*/
int32_t csi_usart_abort_send(usart_handle_t handle);
/**
\brief Start receiving data from USART receiver. \n
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref csi_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[out] data Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to receive
\return error code
*/
int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num);
/**
\brief query data from UART receiver FIFO.
\param[in] handle usart handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver
\param[in] num Number of data items to receive
\return fifo data num to receive
*/
int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num);
/**
\brief Abort Receive data from USART receiver
\param[in] handle usart handle to operate.
\return error code
*/
int32_t csi_usart_abort_receive(usart_handle_t handle);
/**
\brief Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref csi_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[in] data_out Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[out] data_in Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to transfer
\return error code
*/
int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num);
/**
\brief abort sending/receiving data to/from USART transmitter/receiver.
\param[in] handle usart handle to operate.
\return error code
*/
int32_t csi_usart_abort_transfer(usart_handle_t handle);
/**
\brief Get USART status.
\param[in] handle usart handle to operate.
\return USART status \ref usart_status_t
*/
usart_status_t csi_usart_get_status(usart_handle_t handle);
/**
\brief flush receive/send data.
\param[in] handle usart handle to operate.
\param[in] type \ref usart_flush_type_e .
\return error code
*/
int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type);
/**
\brief set interrupt mode.
\param[in] handle usart handle to operate.
\param[in] type \ref usart_intr_type_e.
\param[in] flag 0-OFF, 1-ON.
\return error code
*/
int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag);
/**
\brief set the baud rate of usart.
\param[in] baud usart base to operate.
\param[in] baudrate baud rate
\return error code
*/
int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.
\param[in] mode \ref usart_mode_e
\return error code
*/
int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode);
/**
\brief config usart parity.
\param[in] handle usart handle to operate.
\param[in] parity \ref usart_parity_e
\return error code
*/
int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity);
/**
\brief config usart stop bit number.
\param[in] handle usart handle to operate.
\param[in] stopbits \ref usart_stop_bits_e
\return error code
*/
int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit);
/**
\brief config usart data length.
\param[in] handle usart handle to operate.
\param[in] databits \ref usart_data_bits_e
\return error code
*/
int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits);
/**
\brief get character in query mode.
\param[in] handle usart handle to operate.
\param[out] ch the pointer to the received character.
\return error code
*/
int32_t csi_usart_getchar(usart_handle_t handle, uint8_t *ch);
/**
\brief transmit character in query mode.
\param[in] handle usart handle to operate.
\param[in] ch the input character
\return error code
*/
int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch);
/**
\brief Get usart send data count.
\param[in] handle usart handle to operate.
\return number of currently transmitted data bytes
*/
uint32_t csi_usart_get_tx_count(usart_handle_t handle);
/**
\brief Get usart received data count.
\param[in] handle usart handle to operate.
\return number of currently received data bytes
*/
uint32_t csi_usart_get_rx_count(usart_handle_t handle);
/**
\brief control usart power.
\param[in] handle usart handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_usart_power_control(usart_handle_t handle, csi_power_stat_e state);
/**
\brief config usart flow control type.
\param[in] handle usart handle to operate.
\param[in] flowctrl_type flow control type.\ref usart_flowctrl_type_e.
\return error code
*/
int32_t csi_usart_config_flowctrl(usart_handle_t handle,
usart_flowctrl_type_e flowctrl_type);
/**
\brief config usart clock Polarity and Phase.
\param[in] handle usart handle to operate.
\param[in] cpol Clock Polarity.\ref usart_cpol_e.
\param[in] cpha Clock Phase.\ref usart_cpha_e.
\return error code
*/
int32_t csi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha);
/**
\brief control the transmitter.
\param[in] handle usart handle to operate.
\param[in] enable 1 - enable the transmitter. 0 - disable the transmitter
\return error code
*/
int32_t csi_usart_control_tx(usart_handle_t handle, uint32_t enable);
/**
\brief control the receiver.
\param[in] handle usart handle to operate.
\param[in] enable 1 - enable the receiver. 0 - disable the receiver
\return error code
*/
int32_t csi_usart_control_rx(usart_handle_t handle, uint32_t enable);
/**
\brief control the break.
\param[in] handle usart handle to operate.
\param[in] enable 1- Enable continuous Break transmission,0 - disable continuous Break transmission
\return error code
*/
int32_t csi_usart_control_break(usart_handle_t handle, uint32_t enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_USART_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/usart.h | C | apache-2.0 | 18,300 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_usi_iic.h
* @brief header file for iic driver
* @version V1.0
* @date 02. June 2017
* @model usi_iic
******************************************************************************/
#ifndef _DRV_USI_IIC_H_
#define _DRV_USI_IIC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for iic handle.
typedef void *iic_handle_t;
/*----- IIC Control Codes: Mode -----*/
typedef enum {
IIC_MODE_MASTER, ///< IIC Master
IIC_MODE_SLAVE ///< IIC Slave
} iic_mode_e;
/*----- IIC Control Codes: IIC Bus Speed -----*/
typedef enum {
IIC_BUS_SPEED_STANDARD = 0, ///< Standard Speed (100kHz)
IIC_BUS_SPEED_FAST = 1, ///< Fast Speed (400kHz)
IIC_BUS_SPEED_FAST_PLUS = 2, ///< Fast+ Speed ( 1MHz)
IIC_BUS_SPEED_HIGH = 3 ///< High Speed (3.4MHz)
} iic_speed_e;
/*----- IIC Control Codes: IIC Address Mode -----*/
typedef enum {
IIC_ADDRESS_7BIT = 0, ///< 7-bit address mode
IIC_ADDRESS_10BIT = 1 ///< 10-bit address mode
} iic_address_mode_e;
/**
\brief IIC Status
*/
typedef struct {
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master
uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver
uint32_t general_call : 1; ///< General Call(address 0) indication (cleared on start of next Slave operation)
uint32_t arbitration_lost : 1; ///< Master lost arbitration(in case of multi-masters) (cleared on start of next Master operation)
uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation)
} iic_status_t;
/****** IIC Event *****/
typedef enum {
IIC_EVENT_TRANSFER_DONE = 0, ///< Master/Slave Transmit/Receive finished
IIC_EVENT_TRANSFER_INCOMPLETE = 1, ///< Master/Slave Transmit/Receive incomplete transfer
IIC_EVENT_SLAVE_TRANSMIT = 2, ///< Slave Transmit operation requested
IIC_EVENT_SLAVE_RECEIVE = 3, ///< Slave Receive operation requested
IIC_EVENT_ADDRESS_NACK = 4, ///< Address not acknowledged from Slave
IIC_EVENT_GENERAL_CALL = 5, ///< General Call indication
IIC_EVENT_ARBITRATION_LOST = 6, ///< Master lost arbitration
IIC_EVENT_BUS_ERROR = 7, ///< Bus error detected (START/STOP at illegal position)
IIC_EVENT_BUS_CLEAR = 8 ///< Bus clear finished
} iic_event_e;
typedef void (*iic_event_cb_t)(int32_t idx, iic_event_e event); ///< Pointer to \ref iic_event_cb_t : IIC Event call back.
/**
\brief IIC Driver Capabilities.
*/
typedef struct {
uint32_t address_10_bit : 1; ///< supports 10-bit addressing
} iic_capabilities_t;
/**
\brief Initialize IIC Interface specified by pins. \n
1. Initializes the resources needed for the IIC interface 2.registers event callback function
\param[in] idx iic index
\param[in] cb_event event callback function \ref iic_event_cb_t
\return 0 for success, negative for error code
*/
iic_handle_t drv_usi_iic_initialize(int32_t idx, iic_event_cb_t cb_event);
/**
\brief De-initialize IIC Interface. stops operation and releases the software resources used by the interface
\param[in] handle iic handle to operate.
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_uninitialize(iic_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx iic index
\return \ref iic_capabilities_t
*/
iic_capabilities_t drv_usi_iic_get_capabilities(int32_t idx);
/**
\brief config iic attributes.
\param[in] handle iic handle to operate.
\param[in] mode iic mode \ref iic_mode_e. if negative, then this attribute not changed.
\param[in] speed iic speed \ref iic_speed_e. if negative, then this attribute not changed.
\param[in] addr_mode iic address mode \ref iic_address_mode_e. if negative, then this attribute not changed.
\param[in] slave_addr iic address of slave. if negative, then this attribute not changed.
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_config(iic_handle_t handle,
iic_mode_e mode,
iic_speed_e speed,
iic_address_mode_e addr_mode,
int32_t slave_addr);
/**
\brief Start transmitting data as I2C Master.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_usi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] devaddr iic addrress of slave device.
\param[in] data data to send to I2C Slave
\param[in] num Number of data items to send
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
Master generates STOP condition (if xfer_pending is "false")
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_master_send(iic_handle_t handle, uint32_t devaddr, const void *data, uint32_t num, bool xfer_pending);
/**
\brief Start receiving data as I2C Master.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_usi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] devaddr iic addrress of slave device.
\param[out] data Pointer to buffer for data to receive from IIC receiver
\param[in] num Number of data items to receive
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_master_receive(iic_handle_t handle, uint32_t devaddr, void *data, uint32_t num, bool xfer_pending);
/**
\brief Start transmitting data as I2C Slave.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_usi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[in] data Pointer to buffer with data to transmit to I2C Master
\param[in] num Number of data items to send
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_slave_send(iic_handle_t handle, const void *data, uint32_t num);
/**
\brief Start receiving data as I2C Slave.
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
\ref drv_usi_iic_get_status can get operating status.
\param[in] handle iic handle to operate.
\param[out] data Pointer to buffer for data to receive from I2C Master
\param[in] num Number of data items to receive
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_slave_receive(iic_handle_t handle, void *data, uint32_t num);
/**
\brief abort transfer.
\param[in] handle iic handle to operate.
\return 0 for success, negative for error code
*/
int32_t drv_usi_iic_abort_transfer(iic_handle_t handle);
/**
\brief Get IIC status.
\param[in] handle iic handle to operate.
\return IIC status \ref iic_status_t
*/
iic_status_t drv_usi_iic_get_status(iic_handle_t handle);
/**
\brief control IIC power.
\param[in] handle iic handle to operate.
\param[in] state power state.\ref drv_usi_power_stat_e.
\return error code
*/
int32_t drv_usi_iic_power_control(iic_handle_t handle, csi_power_stat_e state);
/**
\brief config iic mode.
\param[in] handle iic handle to operate.
\param[in] mode \ref iic_mode_e
\return error code
*/
int32_t drv_usi_iic_config_mode(iic_handle_t handle, iic_mode_e mode);
/**
\brief config iic speed.
\param[in] handle iic handle to operate.
\param[in] speed \ref iic_speed_e
\return error code
*/
int32_t drv_usi_iic_config_speed(iic_handle_t handle, iic_speed_e speed);
/**
\brief config iic address mode.
\param[in] handle iic handle to operate.
\param[in] addr_mode \ref iic_address_mode_e
\return error code
*/
int32_t drv_usi_iic_config_addr_mode(iic_handle_t handle, iic_address_mode_e addr_mode);
/**
\brief config iic slave address.
\param[in] handle iic handle to operate.
\param[in] slave_addr slave address
\return error code
*/
int32_t drv_usi_iic_config_slave_addr(iic_handle_t handle, int32_t slave_addr);
/**
\brief Get IIC transferred data count.
\param[in] handle iic handle to operate.
\return the number of the currently transferred data items
*/
uint32_t drv_usi_iic_get_data_count(iic_handle_t handle);
/**
\brief Send START command.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t drv_usi_iic_send_start(iic_handle_t handle);
/**
\brief Send STOP command.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t drv_usi_iic_send_stop(iic_handle_t handle);
/**
\brief Reset I2C peripheral.
\param[in] handle iic handle to operate.
\return error code
*/
int32_t drv_usi_iic_reset(iic_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_USI_IIC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/usi_iic.h | C | apache-2.0 | 9,793 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_usi_spi.h
* @brief header file for spi driver
* @version V1.0
* @date 02. June 2017
* @model usi_spi
******************************************************************************/
#ifndef _DRV_SPU_USI_H_
#define _DRV_SPU_USI_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef CONFIG_SPI_DMA
#include <drv/dmac.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/// definition for spi handle.
typedef void *spi_handle_t;
/****** SPI specific error codes *****/
typedef enum {
SPI_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
SPI_ERROR_FRAME_FORMAT, ///< Specified Frame Format not supported
SPI_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
SPI_ERROR_BIT_ORDER, ///< Specified Bit order not supported
SPI_ERROR_SS_MODE ///< Specified Slave Select Mode not supported
} spi_error_e;
/*----- SPI Control Codes: Mode -----*/
typedef enum {
SPI_MODE_INACTIVE = 0, ///< SPI Inactive
SPI_MODE_MASTER, ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
SPI_MODE_SLAVE, ///< SPI Slave (Output on MISO, Input on MOSI)
SPI_MODE_MASTER_SIMPLEX, ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
SPI_MODE_SLAVE_SIMPLEX ///< SPI Slave (Output/Input on MISO)
} spi_mode_e;
/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
typedef enum {
SPI_FORMAT_CPOL0_CPHA0 = 0, ///< Clock Polarity 0, Clock Phase 0
SPI_FORMAT_CPOL0_CPHA1, ///< Clock Polarity 0, Clock Phase 1
SPI_FORMAT_CPOL1_CPHA0, ///< Clock Polarity 1, Clock Phase 0
SPI_FORMAT_CPOL1_CPHA1, ///< Clock Polarity 1, Clock Phase 1
} spi_format_e;
/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
typedef enum {
SPI_ORDER_MSB2LSB = 0, ///< SPI Bit order from MSB to LSB
SPI_ORDER_LSB2MSB ///< SPI Bit order from LSB to MSB
} spi_bit_order_e;
/*----- SPI Control Codes: Mode Parameters: Data Width in bits -----*/
#define SPI_DATAWIDTH_MAX 32 /* 1 ~ 32 bit*/
/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
typedef enum {
/*options for SPI_MODE_MASTER/SPI_MODE_MASTER_SIMPLEX */
SPI_SS_MASTER_UNUSED = 0, ///< SPI Slave Select when Master: Not used.SS line is not controlled by master, For example,SS line connected to a fixed low level
SPI_SS_MASTER_SW, ///< SPI Slave Select when Master: Software controlled. SS line is configured by software
SPI_SS_MASTER_HW_OUTPUT, ///< SPI Slave Select when Master: Hardware controlled Output.SS line is activated or deactivated automatically by hardware
SPI_SS_MASTER_HW_INPUT, ///< SPI Slave Select when Master: Hardware monitored Input.Used in multi-master configuration where a master does not drive the Slave Select when driving the bus, but rather monitors it
/*options for SPI_MODE_SLAVE/SPI_MODE_SLAVE_SIMPLEX */
SPI_SS_SLAVE_HW, ///< SPI Slave Select when Slave: Hardware monitored.Hardware monitors the Slave Select line and accepts transfers only when the line is active
SPI_SS_SLAVE_SW ///< SPI Slave Select when Slave: Software controlled.Used only when the Slave Select line is not used. Software controls if the slave is responding or not(enables or disables transfers)
} spi_ss_mode_e;
/****** SPI Slave Select Signal definitions *****/
typedef enum {
SPI_SS_INACTIVE = 0, ///< SPI Slave Select Signal/line Inactive
SPI_SS_ACTIVE ///< SPI Slave Select Signal/line Active
} spi_ss_stat_e;
/**
\brief SPI Status
*/
typedef struct {
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation)
} spi_status_t;
/****** SPI Event *****/
typedef enum {
SPI_EVENT_TRANSFER_COMPLETE = 0, ///< Data Transfer completed. Occurs after call to drv_usi_spi_send, drv_usi_spi_receive, or drv_usi_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_TX_COMPLETE, ///< Data Transfer completed. Occurs after call to drv_usi_spi_send, drv_usi_spi_receive, or drv_usi_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_RX_COMPLETE, ///< Data Transfer completed. Occurs after call to drv_usi_spi_send, drv_usi_spi_receive, or drv_usi_spi_transfer to indicate that all the data has been transferred. The driver is ready for the next transfer operation
SPI_EVENT_DATA_LOST, ///< Data lost: Receive overflow / Transmit underflow. Occurs in slave mode when data is requested/sent by master but send/receive/transfer operation has not been started and indicates that data is lost. Occurs also in master mode when driver cannot transfer data fast enough.
SPI_EVENT_MODE_FAULT ///< Master Mode Fault (SS deactivated when Master).Occurs in master mode when Slave Select is deactivated and indicates Master Mode Fault. The driver is ready for the next transfer operation.
} spi_event_e;
typedef void (*spi_event_cb_t)(int32_t idx, spi_event_e event); ///< Pointer to \ref spi_event_cb_t : SPI Event call back.
/**
\brief SPI Driver Capabilities.
*/
typedef struct {
uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave)
uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface
uint32_t microwire : 1; ///< supports Microwire Interface
uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref spi_event_e
} spi_capabilities_t;
/**
\brief Initialize SPI Interface. 1. Initializes the resources needed for the SPI interface 2.registers event callback function
\param[in] idx spi index
\param[in] cb_event event callback function \ref spi_event_cb_t
\param[in] cb_arg argument for call back function
\return return spi handle if success
*/
spi_handle_t drv_usi_spi_initialize(int32_t idx, spi_event_cb_t cb_event);
/**
\brief De-initialize SPI Interface. stops operation and releases the software resources used by the interface
\param[in] handle spi handle to operate.
\return error code
*/
int32_t drv_usi_spi_uninitialize(spi_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx spi index
\return \ref spi_capabilities_t
*/
spi_capabilities_t drv_usi_spi_get_capabilities(int32_t idx);
/**
\brief config spi mode.
\param[in] handle spi handle to operate.
\param[in] baud spi baud rate. if negative, then this attribute not changed
\param[in] mode \ref spi_mode_e . if negative, then this attribute not changed
\param[in] format \ref spi_format_e . if negative, then this attribute not changed
\param[in] order \ref spi_bit_order_e . if negative, then this attribute not changed
\param[in] ss_mode \ref spi_ss_mode_e . if negative, then this attribute not changed
\param[in] bit_width spi data bitwidth: (1 ~ SPI_DATAWIDTH_MAX) . if negative, then this attribute not changed
\return error code
*/
int32_t drv_usi_spi_config(spi_handle_t handle,
int32_t baud,
spi_mode_e mode,
spi_format_e format,
spi_bit_order_e order,
spi_ss_mode_e ss_mode,
int32_t bit_width);
/**
\brief sending data to SPI transmitter,(received data is ignored).
if non-blocking mode, this function only starts the sending,
\ref spi_event_e is signaled when operation completes or error happens.
\ref drv_usi_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[in] data Pointer to buffer with data to send to SPI transmitter. data_type is : uint8_t for 1..8 data bits, uint16_t for 9..16 data bits,uint32_t for 17..32 data bits,
\param[in] num Number of data items to send.
\return error code
*/
int32_t drv_usi_spi_send(spi_handle_t handle, const void *data, uint32_t num);
/**
\brief receiving data from SPI receiver. if non-blocking mode, this function only starts the receiving,
\ref spi_event_e is signaled when operation completes or error happens.
\ref drv_usi_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] num Number of data items to receive
\return error code
*/
int32_t drv_usi_spi_receive(spi_handle_t handle, void *data, uint32_t num);
/**
\brief sending/receiving data to/from SPI transmitter/receiver.
if non-blocking mode, this function only starts the transfer,
\ref spi_event_e is signaled when operation completes or error happens.
\ref drv_usi_spi_get_status can get operation status.
if blocking mode, this function returns after operation completes or error happens.
\param[in] handle spi handle to operate.
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] num_out Number of data items to send
\param[in] num_in Number of data items to receive
\return error code
*/
int32_t drv_usi_spi_transfer(spi_handle_t handle, const void *data_out, void *data_in, uint32_t num_out, uint32_t num_in);
/**
\brief abort spi transfer.
\param[in] handle spi handle to operate.
\return error code
*/
int32_t drv_usi_spi_abort_transfer(spi_handle_t handle);
/**
\brief Get SPI status.
\param[in] handle spi handle to operate.
\return SPI status \ref spi_status_t
*/
spi_status_t drv_usi_spi_get_status(spi_handle_t handle);
/**
\brief config the SPI mode.
\param[in] handle spi handle
\param[in] mode spi mode. \ref spi_mode_e
\return error code
*/
int32_t drv_usi_spi_config_mode(spi_handle_t handle, spi_mode_e mode);
/**
\brief config the SPI block mode.
\param[in] handle spi handle
\param[in] flag 1 - enbale the block mode. 0 - disable the block mode
\return error code
*/
int32_t drv_usi_spi_config_block_mode(spi_handle_t handle, int32_t flag);
/**
\brief Set the SPI baudrate.
\param[in] handle spi handle
\param[in] baud spi baud rate
\return error code
*/
int32_t drv_usi_spi_config_baudrate(spi_handle_t handle, uint32_t baud);
/**
\brief config the SPI bit order.
\param[in] handle spi handle
\param[in] order spi bit order.\ref spi_bit_order_e
\return error code
*/
int32_t drv_usi_spi_config_bit_order(spi_handle_t handle, spi_bit_order_e order);
/**
\brief Set the SPI datawidth.
\param[in] handle spi handle
\param[in] datawidth date frame size in bits
\return error code
*/
int32_t drv_usi_spi_config_datawidth(spi_handle_t handle, uint32_t datawidth);
/**
\brief config the SPI format.
\param[in] handle spi handle
\param[in] format spi format. \ref spi_format_e
\return error code
*/
int32_t drv_usi_spi_config_format(spi_handle_t handle, spi_format_e format);
/**
\brief config the SPI slave select mode.
\param[in] handle spi handle
\param[in] ss_mode spi slave select mode. \ref spi_ss_mode_e
\return error code
*/
int32_t drv_usi_spi_config_ss_mode(spi_handle_t handle, spi_ss_mode_e ss_mode);
/**
\brief Get the number of the currently transferred.
\param[in] handle spi handle to operate.
\return the number of the currently transferred data items
*/
uint32_t drv_usi_spi_get_data_count(spi_handle_t handle);
/**
\brief control spi power.
\param[in] handle spi handle to operate.
\param[in] state power state.\ref drv_usi_power_stat_e.
\return error code
*/
int32_t drv_usi_spi_power_control(spi_handle_t handle, csi_power_stat_e state);
/**
\brief Control the Slave Select signal (SS).
\param[in] handle spi handle to operate.
\param[in] stat SS state. \ref spi_ss_stat_e.
\return error code
*/
int32_t drv_usi_spi_ss_control(spi_handle_t handle, spi_ss_stat_e stat);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SPU_USI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/usi_spi.h | C | apache-2.0 | 13,301 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_usi_usart.h
* @brief header file for usart driver
* @version V1.0
* @date 02. June 2017
* @model usi_usart
******************************************************************************/
#ifndef _CSI_USART_H_
#define _CSI_USART_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for usart handle.
typedef void *usart_handle_t;
/****** USART specific error codes *****/
typedef enum {
USART_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported
USART_ERROR_BAUDRATE, ///< Specified baudrate not supported
USART_ERROR_DATA_BITS, ///< Specified number of Data bits not supported
USART_ERROR_PARITY, ///< Specified Parity not supported
USART_ERROR_STOP_BITS, ///< Specified number of Stop bits not supported
USART_ERROR_FLOW_CONTROL, ///< Specified Flow Control not supported
USART_ERROR_CPOL, ///< Specified Clock Polarity not supported
USART_ERROR_CPHA ///< Specified Clock Phase not supported
} usart_error_e;
/*----- USART Control Codes: Mode -----*/
typedef enum {
USART_MODE_ASYNCHRONOUS = 0, ///< USART (Asynchronous)
USART_MODE_SYNCHRONOUS_MASTER, ///< Synchronous Master
USART_MODE_SYNCHRONOUS_SLAVE, ///< Synchronous Slave (external clock signal)
USART_MODE_SINGLE_WIRE, ///< USART Single-wire (half-duplex)
USART_MODE_SINGLE_IRDA, ///< UART IrDA
USART_MODE_SINGLE_SMART_CARD, ///< UART Smart Card
} usart_mode_e;
/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
typedef enum {
USART_DATA_BITS_5 = 0, ///< 5 Data bits
USART_DATA_BITS_6, ///< 6 Data bit
USART_DATA_BITS_7, ///< 7 Data bits
USART_DATA_BITS_8, ///< 8 Data bits (default)
USART_DATA_BITS_9 ///< 9 Data bits
} usart_data_bits_e;
/*----- USART Control Codes: Mode Parameters: Parity -----*/
typedef enum {
USART_PARITY_NONE = 0, ///< No Parity (default)
USART_PARITY_EVEN, ///< Even Parity
USART_PARITY_ODD, ///< Odd Parity
USART_PARITY_1, ///< Parity forced to 1
USART_PARITY_0 ///< Parity forced to 0
} usart_parity_e;
/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
typedef enum {
USART_STOP_BITS_1 = 0, ///< 1 Stop bit (default)
USART_STOP_BITS_2, ///< 2 Stop bits
USART_STOP_BITS_1_5, ///< 1.5 Stop bits
USART_STOP_BITS_0_5 ///< 0.5 Stop bits
} usart_stop_bits_e;
/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
typedef enum {
USART_CPOL0 = 0, ///< CPOL = 0 (default). data are captured on rising edge (low->high transition)
USART_CPOL1 ///< CPOL = 1. data are captured on falling edge (high->lowh transition)
} usart_cpol_e;
/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
typedef enum {
USART_CPHA0 = 0, ///< CPHA = 0 (default). sample on first (leading) edge
USART_CPHA1 ///< CPHA = 1. sample on second (trailing) edge
} usart_cpha_e;
/*----- USART Control Codes: flush data type-----*/
typedef enum {
USART_FLUSH_WRITE,
USART_FLUSH_READ
} usart_flush_type_e;
/*----- USART Control Codes: flow control type-----*/
typedef enum {
USART_FLOWCTRL_NONE,
USART_FLOWCTRL_CTS,
USART_FLOWCTRL_RTS,
USART_FLOWCTRL_CTS_RTS
} usart_flowctrl_type_e;
/*----- USART Modem Control -----*/
typedef enum {
USART_RTS_CLEAR, ///< Deactivate RTS
USART_RTS_SET, ///< Activate RTS
USART_DTR_CLEAR, ///< Deactivate DTR
USART_DTR_SET ///< Activate DTR
} usart_modem_ctrl_e;
/*----- USART Modem Status -----*/
typedef struct {
uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
} usart_modem_stat_t;
/*----- USART Control Codes: on-off intrrupte type-----*/
typedef enum {
USART_INTR_WRITE,
USART_INTR_READ
} usart_intr_type_e;
/**
\brief USART Status
*/
typedef struct {
uint32_t tx_busy : 1; ///< Transmitter busy flag
uint32_t rx_busy : 1; ///< Receiver busy flag
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)(Synchronous Slave)
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
uint32_t tx_enable : 1; ///< Transmitter enable flag
uint32_t rx_enable : 1; ///< Receiver enbale flag
} usart_status_t;
/****** USART Event *****/
typedef enum {
USART_EVENT_SEND_COMPLETE = 0, ///< Send completed; however USART may still transmit data
USART_EVENT_RECEIVE_COMPLETE = 1, ///< Receive completed
USART_EVENT_TRANSFER_COMPLETE = 2, ///< Transfer completed
USART_EVENT_TX_COMPLETE = 3, ///< Transmit completed (optional)
USART_EVENT_TX_UNDERFLOW = 4, ///< Transmit data not available (Synchronous Slave)
USART_EVENT_RX_OVERFLOW = 5, ///< Receive data overflow
USART_EVENT_RX_TIMEOUT = 6, ///< Receive character timeout (optional)
USART_EVENT_RX_BREAK = 7, ///< Break detected on receive
USART_EVENT_RX_FRAMING_ERROR = 8, ///< Framing error detected on receive
USART_EVENT_RX_PARITY_ERROR = 9, ///< Parity error detected on receive
USART_EVENT_CTS = 10, ///< CTS state changed (optional)
USART_EVENT_DSR = 11, ///< DSR state changed (optional)
USART_EVENT_DCD = 12, ///< DCD state changed (optional)
USART_EVENT_RI = 13, ///< RI state changed (optional)
USART_EVENT_RECEIVED = 14, ///< Data Received, only in usart fifo, call receive()/transfer() get the data
} usart_event_e;
typedef void (*usart_event_cb_t)(int32_t idx, usart_event_e event); ///< Pointer to \ref usart_event_cb_t : USART Event call back.
/**
\brief USART Driver Capabilities.
*/
typedef struct {
uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
uint32_t single_wire : 1; ///< supports UART Single-wire mode
uint32_t irda : 1; ///< supports UART IrDA mode
uint32_t smart_card : 1; ///< supports UART Smart Card mode
uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
uint32_t flow_control_rts : 1; ///< RTS Flow Control available
uint32_t flow_control_cts : 1; ///< CTS Flow Control available
uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref USART_EVENT_TX_COMPLETE
uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref USART_EVENT_RX_TIMEOUT
uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
uint32_t event_cts : 1; ///< Signal CTS change event: \ref USART_EVENT_CTS
uint32_t event_dsr : 1; ///< Signal DSR change event: \ref USART_EVENT_DSR
uint32_t event_dcd : 1; ///< Signal DCD change event: \ref USART_EVENT_DCD
uint32_t event_ri : 1; ///< Signal RI change event: \ref USART_EVENT_RI
} usart_capabilities_t;
/**
\brief Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
\param[in] idx usart index
\param[in] cb_event event call back function \ref usart_event_cb_t
\return return usart handle if success
*/
usart_handle_t drv_usi_usart_initialize(int32_t idx, usart_event_cb_t cb_event);
/**
\brief De-initialize USART Interface. stops operation and releases the software resources used by the interface
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_usi_usart_uninitialize(usart_handle_t handle);
/**
\brief Get driver capabilities.
\param[in] idx usart index
\return \ref usart_capabilities_t
*/
usart_capabilities_t drv_usi_usart_get_capabilities(int32_t idx);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.
\param[in] baud baud rate.
\param[in] mode \ref usart_mode_e .
\param[in] parity \ref usart_parity_e .
\param[in] stopbits \ref usart_stop_bits_e .
\param[in] bits \ref usart_data_bits_e .
\return error code
*/
int32_t drv_usi_usart_config(usart_handle_t handle,
uint32_t baud,
usart_mode_e mode,
usart_parity_e parity,
usart_stop_bits_e stopbits,
usart_data_bits_e bits);
/**
\brief Start sending data to USART transmitter,(received data is ignored).
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref drv_usi_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[in] data Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to send
\return error code
*/
int32_t drv_usi_usart_send(usart_handle_t handle, const void *data, uint32_t num);
/**
\brief Abort Send data to USART transmitter
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_usi_usart_abort_send(usart_handle_t handle);
/**
\brief Start receiving data from USART receiver. \n
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref drv_usi_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[out] data Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to receive
\return error code
*/
int32_t drv_usi_usart_receive(usart_handle_t handle, void *data, uint32_t num);
/**
\brief query data from UART receiver FIFO.
\param[in] handle usart handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver
\param[in] num Number of data items to receive
\return fifo data num to receive
*/
int32_t drv_usi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num);
/**
\brief Abort Receive data from USART receiver
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_usi_usart_abort_receive(usart_handle_t handle);
/**
\brief Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode
This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
\ref drv_usi_usart_get_status can get operation status.
\param[in] handle usart handle to operate.
\param[in] data_out Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[out] data_in Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to transfer
\return error code
*/
int32_t drv_usi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num);
/**
\brief abort sending/receiving data to/from USART transmitter/receiver.
\param[in] handle usart handle to operate.
\return error code
*/
int32_t drv_usi_usart_abort_transfer(usart_handle_t handle);
/**
\brief Get USART status.
\param[in] handle usart handle to operate.
\return USART status \ref usart_status_t
*/
usart_status_t drv_usi_usart_get_status(usart_handle_t handle);
/**
\brief flush receive/send data.
\param[in] handle usart handle to operate.
\param[in] type \ref usart_flush_type_e .
\return error code
*/
int32_t drv_usi_usart_flush(usart_handle_t handle, usart_flush_type_e type);
/**
\brief set interrupt mode.
\param[in] handle usart handle to operate.
\param[in] type \ref usart_intr_type_e.
\param[in] flag 0-OFF, 1-ON.
\return error code
*/
int32_t drv_usi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag);
/**
\brief set the baud rate of usart.
\param[in] baud usart base to operate.
\param[in] baudrate baud rate
\return error code
*/
int32_t drv_usi_usart_config_baudrate(usart_handle_t handle, uint32_t baud);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.
\param[in] mode \ref usart_mode_e
\return error code
*/
int32_t drv_usi_usart_config_mode(usart_handle_t handle, usart_mode_e mode);
/**
\brief config usart parity.
\param[in] handle usart handle to operate.
\param[in] parity \ref usart_parity_e
\return error code
*/
int32_t drv_usi_usart_config_parity(usart_handle_t handle, usart_parity_e parity);
/**
\brief config usart stop bit number.
\param[in] handle usart handle to operate.
\param[in] stopbits \ref usart_stop_bits_e
\return error code
*/
int32_t drv_usi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit);
/**
\brief config usart data length.
\param[in] handle usart handle to operate.
\param[in] databits \ref usart_data_bits_e
\return error code
*/
int32_t drv_usi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits);
/**
\brief get character in query mode.
\param[in] handle usart handle to operate.
\param[out] ch the pointer to the received character.
\return error code
*/
int32_t drv_usi_usart_getchar(usart_handle_t handle, uint8_t *ch);
/**
\brief transmit character in query mode.
\param[in] handle usart handle to operate.
\param[in] ch the input character
\return error code
*/
int32_t drv_usi_usart_putchar(usart_handle_t handle, uint8_t ch);
/**
\brief Get usart send data count.
\param[in] handle usart handle to operate.
\return number of currently transmitted data bytes
*/
uint32_t drv_usi_usart_get_tx_count(usart_handle_t handle);
/**
\brief Get usart received data count.
\param[in] handle usart handle to operate.
\return number of currently received data bytes
*/
uint32_t drv_usi_usart_get_rx_count(usart_handle_t handle);
/**
\brief control usart power.
\param[in] handle usart handle to operate.
\param[in] state power state.\ref drv_usi_power_stat_e.
\return error code
*/
int32_t drv_usi_usart_power_control(usart_handle_t handle, csi_power_stat_e state);
/**
\brief config usart flow control type.
\param[in] handle usart handle to operate.
\param[in] flowctrl_type flow control type.\ref usart_flowctrl_type_e.
\return error code
*/
int32_t drv_usi_usart_config_flowctrl(usart_handle_t handle,
usart_flowctrl_type_e flowctrl_type);
/**
\brief config usart clock Polarity and Phase.
\param[in] handle usart handle to operate.
\param[in] cpol Clock Polarity.\ref usart_cpol_e.
\param[in] cpha Clock Phase.\ref usart_cpha_e.
\return error code
*/
int32_t drv_usi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha);
/**
\brief control the transmitter.
\param[in] handle usart handle to operate.
\param[in] enable 1 - enable the transmitter. 0 - disable the transmitter
\return error code
*/
int32_t drv_usi_usart_control_tx(usart_handle_t handle, uint32_t enable);
/**
\brief control the receiver.
\param[in] handle usart handle to operate.
\param[in] enable 1 - enable the receiver. 0 - disable the receiver
\return error code
*/
int32_t drv_usi_usart_control_rx(usart_handle_t handle, uint32_t enable);
/**
\brief control the break.
\param[in] handle usart handle to operate.
\param[in] enable 1- Enable continuous Break transmission,0 - disable continuous Break transmission
\return error code
*/
int32_t drv_usi_usart_control_break(usart_handle_t handle, uint32_t enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_USART_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/usi_usart.h | C | apache-2.0 | 18,464 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_vpu.h
* @brief header file for VPU driver
* @version V1.6
* @date 27. May 2019
* @model vpu
******************************************************************************/
#ifndef _DRV_VPU_H_
#define _DRV_VPU_H_
#include <stdint.h>
#include <io.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for vpu device handle.
typedef void *vpu_handle_t;
/// definition for vpu instance handle.
typedef void *vpu_instance_t;
/* vpu_inst_config_t is a composite struct pointer, different instance type
* using different private config struct, for example:
* when type=VPU_INSTANCE_TYPE_ENCODER_H264: vpu_h264enc_config_t*
*/
typedef void *vpu_inst_config_t;
/****** VPU events *****/
typedef enum {
VPU_EVENT_ENCODE_DONE = 0, ///< encode finished
VPU_EVENT_ENCODE_ERROR, ///< encode error
} vpu_event_e;
/****** VPU instance types *****/
typedef enum {
VPU_INSTANCE_TYPE_ENCODER_H264 = 0, ///< VPU instance type: H264 encoder
VPU_INSTANCE_TYPE_DECODER_H264, ///< VPU instance type: H264 decoder
} vpu_inst_type_e;
/****** VPU specific error number *****/
typedef enum {
VPU_ERROR_MEMORY_ALLOC = (DRV_ERROR_SPECIFIC + 1),
VPU_ERROR_CONFIG_PARAMETER,
} vpu_errno_e;
/****** H264 encode level ******/
typedef enum {
VPU_H264ENC_LEVEL_1 = 10, /* QCIF (176x144) 75kbits */
VPU_H264ENC_LEVEL_1_b = 99,
VPU_H264ENC_LEVEL_1_1 = 11,
VPU_H264ENC_LEVEL_1_2 = 12,
VPU_H264ENC_LEVEL_1_3 = 13,
VPU_H264ENC_LEVEL_2 = 20, /* CIF (352x288) 2.4Mbits\n" */
VPU_H264ENC_LEVEL_2_1 = 21,
VPU_H264ENC_LEVEL_2_2 = 22,
VPU_H264ENC_LEVEL_3 = 30, /* SD (720x576) 12Mbits */
VPU_H264ENC_LEVEL_3_1 = 31,
VPU_H264ENC_LEVEL_3_2 = 32,
VPU_H264ENC_LEVEL_4 = 40, /* 1080p (1920x1080) 24Mbits */
VPU_H264ENC_LEVEL_4_1 = 41,
VPU_H264ENC_LEVEL_4_2 = 42,
VPU_H264ENC_LEVEL_5 = 50,
VPU_H264ENC_LEVEL_5_1 = 51
} vpu_h264enc_level_e;
/****** VPU input color format ******/
typedef enum {
VPU_INPUT_FORMAT_YUV420_PLANAR = 0, ///< YYYYYYYY..UU..VV..
VPU_INPUT_FORMAT_YUV420_SEMIPLANAR, ///< YYYYYYYY..UVUV..
VPU_INPUT_FORMAT_YUYV422, ///< YUYVYUYV..
VPU_INPUT_FORMAT_UYVY422, ///< UYVYUYVY..
VPU_INPUT_FORMAT_RGB565,
VPU_INPUT_FORMAT_BGR565,
VPU_INPUT_FORMAT_RGB555,
VPU_INPUT_FORMAT_BGR555,
VPU_INPUT_FORMAT_RGB444,
VPU_INPUT_FORMAT_BGR444,
VPU_INPUT_FORMAT_RGB888,
VPU_INPUT_FORMAT_BGR888,
VPU_INPUT_FORMAT_RGB101010,
VPU_INPUT_FORMAT_BGR101010,
} vpu_input_format_e;
/****** VPU encode output frame type ******/
typedef enum {
VPU_FRAME_TYPE_IFRAME, /* I-Frame */
VPU_FRAME_TYPE_PFRAME, /* P-Frame */
} vpu_frame_type_e;
/**
\brief H264 encoder configure parameters
*/
typedef struct {
uint32_t input_width; ///< input picture width
uint32_t input_height; ///< input picture height
vpu_input_format_e format; ///< input picture format
uint32_t output_width; ///< output picture width
uint32_t output_height; ///< output picture height
vpu_h264enc_level_e level; ///< encode encode level
uint32_t framerate_numer; ///< encode frame rate's numer
uint32_t framerate_denom; ///< encode frame rate's denom
uint32_t gop_len; ///< encode group of picture length
} vpu_h264enc_config_t;
typedef struct {
uint8_t *input_addr; ///< input data address info
vpu_frame_type_e frame_type; ///< encode frame type
} vpu_picture_t;
typedef struct {
uint8_t *addr; ///< output stream buffer address
uint32_t size; ///< Output stream buffer size
} vpu_es_frame_t;
///< Pointer to \ref vpu_event_cb_t : VPU Event call back.
typedef void (*vpu_event_cb_t)(vpu_instance_t vpu_inst, vpu_event_e event, void *user_data);
/**
\brief Initialize VPU Interface.
Initialize the resources needed for the VPU interface
\param[in] idx vpu index
\param[in] cb_event event call back function \ref vpu_event_cb_t
\return pointer to vpu instance
*/
vpu_handle_t csi_vpu_initialize(int32_t idx, vpu_event_cb_t cb_event, void *user_data);
/**
\brief De-initialize VPU Interface.
Stop operation and release the resources used by the interface
\param[in] handle vpu handle to operate.
\return error code
*/
int32_t csi_vpu_uninitialize(vpu_handle_t handle);
/**
\brief Create vpu decoder/encoder instance with configuration parameter
\param[in] handle vpu handle to operate.
\param[in] type The instance type
\param[in] config The instance configuration parameter.
For H264 encoder, config should be vpu_h264enc_config_t
For JPEG encoder, config should be vpu_jpeg_config_t
\return error code
*/
vpu_instance_t csi_vpu_create_instance(vpu_handle_t handle,
vpu_inst_type_e type,
vpu_inst_config_t config);
/**
\brief Destory vpu decoder/encoder instance
\param[in] type The instance type
\return error code
*/
int32_t csi_vpu_destory_instance(vpu_instance_t vpu_inst);
/**
\brief Get vpu instance configuration info
\param[in] vpu_inst The VPU instance handle
\param[out] type The instance type
\param[out] config The instance configuration parameter.
For H264 encoder, config should be vpu_h264enc_config_t
For JPEG encoder, config should be vpu_jpeg_config_t
\return error code
*/
int32_t csi_vpu_get_config(vpu_instance_t vpu_inst,
vpu_inst_type_e *type,
vpu_inst_config_t **config);
/**
\brief start H264 encoder and get ES stream header
\param[in] vpu_inst The VPU instance handle
\param[out] output The pointer to output data information
\return error code
*/
int32_t csi_vpu_h264enc_start(vpu_instance_t vpu_inst,
vpu_es_frame_t *output);
/**
\brief Encode pictures
\param[in] vpu_inst The VPU instance handle
\param[in] input The pointer to input data information
\return error code
*/
int32_t csi_vpu_h264enc_encode(vpu_instance_t vpu_inst,
vpu_picture_t *input);
/**
\brief Get encoded output stream
\param[in] vpu_inst The VPU instance handle
\param[out] input The pointer to input data information
\param[out] output The pointer to output data information
\return error code
*/
int32_t csi_vpu_h264enc_get_stream(vpu_instance_t vpu_inst,
vpu_picture_t **input,
vpu_es_frame_t *output);
/**
\brief stop H264 encoder and get ES stream tail
\param[in] vpu_inst The VPU instance handle
\param[out] output The pointer to output data information
\return error code
*/
int32_t csi_vpu_h264enc_stop(vpu_instance_t vpu_inst,
vpu_es_frame_t *output);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_VPU_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/vpu.h | C | apache-2.0 | 7,396 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_wdt.h
* @brief header file for wdt driver
* @version V1.0
* @date 02. June 2017
* @model wdt
******************************************************************************/
#ifndef _CSI_WDT_H_
#define _CSI_WDT_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for wdt handle.
typedef void *wdt_handle_t;
/****** WDT Event *****/
typedef enum {
WDT_EVENT_TIMEOUT = 0 ///< generate the interrupt
} wdt_event_e;
typedef void (*wdt_event_cb_t)(int32_t idx, wdt_event_e event); ///< Pointer to \ref wdt_event_cb_t : WDT Event call back.
/**
\brief Initialize WDT Interface. 1. Initializes the resources needed for the WDT interface 2.registers event callback function
\param[in] idx wdt index
\param[in] cb_event event call back function \ref wdt_event_cb_t
\return pointer to wdt instance
*/
wdt_handle_t csi_wdt_initialize(int32_t idx, wdt_event_cb_t cb_event);
/**
\brief De-initialize WDT Interface. stops operation and releases the software resources used by the interface
\param[in] handle wdt handle to operate.
\return error code
*/
int32_t csi_wdt_uninitialize(wdt_handle_t handle);
/**
\brief control wdt power.
\param[in] handle wdt handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
int32_t csi_wdt_power_control(wdt_handle_t handle, csi_power_stat_e state);
/**
\brief Set the WDT value.
\param[in] handle wdt handle to operate.
\param[in] value the timeout value(ms).
\return error code
*/
int32_t csi_wdt_set_timeout(wdt_handle_t handle, uint32_t value);
/**
\brief Start the WDT.
\param[in] handle wdt handle to operate.
\return error code
*/
int32_t csi_wdt_start(wdt_handle_t handle);
/**
\brief Stop the WDT.
\param[in] handle wdt handle to operate.
\return error code
*/
int32_t csi_wdt_stop(wdt_handle_t handle);
/**
\brief Restart the WDT.
\param[in] handle wdt handle to operate.
\return error code
*/
int32_t csi_wdt_restart(wdt_handle_t handle);
/**
\brief Read the WDT Current value.
\param[in] handle wdt handle to operate.
\param[out] value Pointer to the Value.
\return error code
*/
int32_t csi_wdt_read_current_value(wdt_handle_t handle, uint32_t *value);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_WDT_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/drv/wdt.h | C | apache-2.0 | 2,660 |
/*
* Copyright (C) 2019-2020 AlibabaGroup Holding Limited
*/
/******************************************************************************
* @file ipc_mem.h
* @brief header file for the ipc mem
* @version V1.0
* @date 07. Aug 2019
* @vendor csky
* @chip pangu
******************************************************************************/
#ifndef _IPC_MEM_H_
#define _IPC_MEM_H_
#ifdef __cplusplus
extern "C" {
#endif
void drv_ipc_mem_init(void);
void *drv_ipc_mem_alloc(int *len);
void drv_ipc_mem_free(void *p);
int drv_ipc_mem_use_cache(void);
#ifdef __cplusplus
}
#endif
#endif /* _IPC_MEM_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/ipc_mem.h | C | apache-2.0 | 635 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file syslog.h
* @brief Defines syslog APIs and usage
* @version V1.1
* @date 14. February 2019
* @usage Add 3 lines codes below at head of source code file
* // 0: Err; 1: Err&Warn; 2: Err&Warn&Info; 3: Err&Warn&Info&Debug
* #define LOG_LEVEL 3
* #include <syslog.h>
******************************************************************************/
#include <stdio.h>
#ifndef _SYSLOG_H_
#define _SYSLOG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef LOG_LEVEL
#if (LOG_LEVEL >= 3) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG)
#define LOG_ENABLE_D
#endif
#if (LOG_LEVEL >= 2) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG || \
defined CONFIG_SYSLOG_LEVEL_INFO)
#define LOG_ENABLE_I
#endif
#if (LOG_LEVEL >= 1) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG || \
defined CONFIG_SYSLOG_LEVEL_INFO || \
defined CONFIG_SYSLOG_LEVEL_WARN)
#define LOG_ENABLE_W
#endif
#if (LOG_LEVEL >= 0) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG || \
defined CONFIG_SYSLOG_LEVEL_INFO || \
defined CONFIG_SYSLOG_LEVEL_WARN || \
defined CONFIG_SYSLOG_LEVEL_ERROR)
#define LOG_ENABLE_E
#endif
#endif /* #ifdef LOG_LEVEL */
/* [LogLevel:FileName:Function:Line] */
extern const char *PFORMAT_D;
extern const char *PFORMAT_I;
extern const char *PFORMAT_W;
extern const char *PFORMAT_E;
#define LOG_E_BASE_ARGS __FUNCTION__, __LINE__
#define LOG_W_BASE_ARGS __FUNCTION__, __LINE__
#define LOG_I_BASE_ARGS __FUNCTION__, __LINE__
#define LOG_D_BASE_ARGS __FUNCTION__, __LINE__
/* Log in freely format without prefix */
#define LOG_F(fmt, args...) printf(fmt,##args)
/* Log debug */
#ifdef LOG_ENABLE_D
#define LOG_D(fmt, args...) \
do {printf(PFORMAT_D,LOG_D_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_D(fmt, args...)
#endif
/* Log information */
#ifdef LOG_ENABLE_I
#define LOG_I(fmt, args...) \
do {printf(PFORMAT_I ,LOG_I_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_I(fmt, args...)
#endif
/* Log warning */
#ifdef LOG_ENABLE_W
#define LOG_W(fmt, args...) \
do {printf(PFORMAT_W,LOG_W_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_W(fmt, args...)
#endif
/* Log error */
#ifdef LOG_ENABLE_E
#define LOG_E(fmt, args...) \
do {printf(PFORMAT_E,LOG_E_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_E(fmt, args...)
#endif
#define ENTER() LOG_D("Enter\n")
#define EXIT_VOID() do { LOG_D("Exit\n"); return;} while(0)
#define EXIT_INT(val) do { LOG_D("Exit, return val=%d\n", (int)val); return val;} while(0)
#define EXIT_PTR(ptr) do { LOG_D("Exit, return ptr=%p\n", (void*)ptr); return ptr;} while(0)
#ifdef __cplusplus
}
#endif
#endif /* _SYSLOG_H_ */
| YifuLiu/AliOS-Things | components/csi/csi1/include/syslog.h | C | apache-2.0 | 2,898 |
#include <string.h>
#include <stdlib.h>
#include <stdbool.h>
#include <csi_core.h>
#include "dev_ringbuf.h"
#define min(a, b) (((a) < (b)) ? (a) : (b))
/**
* \brief Removes the entire FIFO contents.
* \param [in] fifo: The fifo to be emptied.
* \return None.
*/
void dev_ringbuff_reset(dev_ringbuf_t *fifo)
{
uint32_t stat = csi_irq_save();
fifo->write = fifo->read = 0;
fifo->data_len = 0;
csi_irq_restore(stat);
}
/**
* \brief Returns the size of the FIFO in bytes.
* \param [in] fifo: The fifo to be used.
* \return The size of the FIFO.
*/
static inline uint32_t ringbuffer_size(dev_ringbuf_t *fifo)
{
return fifo->size;
}
/**
* \brief Returns the number of used bytes in the FIFO.
* \param [in] fifo: The fifo to be used.
* \return The number of used bytes.
*/
uint32_t dev_ringbuf_len(dev_ringbuf_t *fifo)
{
return fifo->data_len;
}
/**
* \brief Returns the number of bytes available in the FIFO.
* \param [in] fifo: The fifo to be used.
* \return The number of bytes available.
*/
uint32_t dev_ringbuf_avail(dev_ringbuf_t *fifo)
{
return ringbuffer_size(fifo) - dev_ringbuf_len(fifo);
}
/**
* \brief Is the FIFO empty?
* \param [in] fifo: The fifo to be used.
* \retval true: Yes.
* \retval false: No.
*/
bool dev_ringbuf_is_empty(dev_ringbuf_t *fifo)
{
return dev_ringbuf_len(fifo) == 0;
}
/**
* \brief Is the FIFO full?
* \param [in] fifo: The fifo to be used.
* \retval true: Yes.
* \retval false: No.
*/
bool dev_ringbuf_is_full(dev_ringbuf_t *fifo)
{
return dev_ringbuf_avail(fifo) == 0;
}
/**
* \brief Puts some data into the FIFO.
* \param [in] fifo: The fifo to be used.
* \param [in] in: The data to be added.
* \param [in] len: The length of the data to be added.
* \return The number of bytes copied.
* \note This function copies at most @len bytes from the @in into
* the FIFO depending on the free space, and returns the number
* of bytes copied.
*/
uint32_t dev_ringbuf_in(dev_ringbuf_t *fifo, const void *datptr, uint32_t len)
{
uint32_t writelen = 0, tmplen = 0;
if(dev_ringbuf_is_full(fifo))
return 0;
tmplen = fifo->size - fifo->data_len;
writelen = tmplen > len ? len : tmplen;
if(fifo->write < fifo->read) {
memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, writelen);
} else {
tmplen = fifo->size - fifo->write;
if(writelen <= tmplen) {
memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, writelen);
} else {
memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, tmplen);
memcpy((void*)fifo->buffer, (uint8_t*)datptr + tmplen, writelen - tmplen);
}
}
uint32_t stat = csi_irq_save();
fifo->write = (fifo->write + writelen) % fifo->size;
fifo->data_len += writelen;
csi_irq_restore(stat);
return writelen;
}
/**
* \brief Gets some data from the FIFO.
* \param [in] fifo: The fifo to be used.
* \param [in] out: Where the data must be copied.
* \param [in] len: The size of the destination buffer.
* \return The number of copied bytes.
* \note This function copies at most @len bytes from the FIFO into
* the @out and returns the number of copied bytes.
*/
uint32_t dev_ringbuf_out(dev_ringbuf_t *fifo, void *outbuf, uint32_t len)
{
uint32_t readlen = 0, tmplen = 0;
if(dev_ringbuf_is_empty(fifo))
return 0;
uint32_t data_len = fifo->data_len;
readlen = len > data_len ? data_len : len;
tmplen = fifo->size - fifo->read;
if(NULL != outbuf) {
if(readlen <= tmplen) {
memcpy((void*)outbuf, (void*)&fifo->buffer[fifo->read], readlen);
} else {
memcpy((void*)outbuf,(void*)&fifo->buffer[fifo->read], tmplen);
memcpy((uint8_t*)outbuf + tmplen,(void*)fifo->buffer,readlen - tmplen);
}
}
uint32_t stat = csi_irq_save();
fifo->read = (fifo->read + readlen) % fifo->size;
fifo->data_len -= readlen;
csi_irq_restore(stat);
return readlen;
}
| YifuLiu/AliOS-Things | components/csi/csi1/src/dev_ringbuf.c | C | apache-2.0 | 4,132 |
/******************************************************************************
* @file csky_common_tables.h
* @brief This file has extern declaration for common tables like
* Bitreverse, reciprocal etc which are used across different functions.
* @version V1.0
* @date 20. Dec 2016
******************************************************************************/
/* ---------------------------------------------------------------------------
* Copyright (C) 2016 CSKY Limited. All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the following
* conditions are met:
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* * Neither the name of CSKY Ltd. nor the names of CSKY's contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission of CSKY Ltd.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */
#ifndef _CSKY_COMMON_TABLES_H
#define _CSKY_COMMON_TABLES_H
#include "csky_math.h"
extern const uint16_t cskyBitRevTable[1024];
extern const q15_t cskyRecipTableQ15[64];
extern const q31_t cskyRecipTableQ31[64];
extern const uint32_t twiddleCoef_16[32];
extern const uint32_t twiddleCoef_32[64];
extern const uint32_t twiddleCoef_64[128];
extern const uint32_t twiddleCoef_128[256];
extern const uint32_t twiddleCoef_256[512];
extern const uint32_t twiddleCoef_512[1024];
extern const uint32_t twiddleCoef_1024[2048];
extern const uint32_t twiddleCoef_2048[4096];
extern const uint32_t twiddleCoef_4096[8192];
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
extern const float32_t twiddleCoef_rfft_8192[8192];
extern const q15_t twiddleCoef_fast_16_q15[24];
extern const q15_t twiddleCoef_fast_32_q15[56];
extern const q15_t twiddleCoef_fast_64_q15[120];
extern const q15_t twiddleCoef_fast_128_q15[248];
extern const q15_t twiddleCoef_fast_256_q15[504];
extern const q15_t twiddleCoef_fast_512_q15[1016];
extern const q15_t twiddleCoef_fast_1024_q15[2040];
extern const q15_t twiddleCoef_fast_2048_q15[4088];
extern const q15_t twiddleCoef_fast_4096_q15[8184];
extern const q31_t twiddleCoef_fast_16_q31[24];
extern const q31_t twiddleCoef_fast_32_q31[56];
extern const q31_t twiddleCoef_fast_64_q31[120];
extern const q31_t twiddleCoef_fast_128_q31[248];
extern const q31_t twiddleCoef_fast_256_q31[504];
extern const q31_t twiddleCoef_fast_512_q31[1016];
extern const q31_t twiddleCoef_fast_1024_q31[2040];
extern const q31_t twiddleCoef_fast_2048_q31[4088];
extern const q31_t twiddleCoef_fast_4096_q31[8184];
extern const uint32_t twiddleCoef_fast_16[24];
extern const uint32_t twiddleCoef_fast_32[56];
extern const uint32_t twiddleCoef_fast_64[120];
extern const uint32_t twiddleCoef_fast_128[248];
extern const uint32_t twiddleCoef_fast_256[504];
extern const uint32_t twiddleCoef_fast_512[1016];
extern const uint32_t twiddleCoef_fast_1024[2040];
extern const uint32_t twiddleCoef_fast_2048[4088];
extern const uint32_t twiddleCoef_fast_4096[8184];
extern const q15_t realCoefAQ15_8192[8192];
extern const q31_t realCoefAQ31_8192[8192];
extern const q15_t realCoefBQ15_8192[8192];
extern const q31_t realCoefBQ31_8192[8192];
/*Tables for RFFT.*/
extern const q15_t ALIGN4 realCoefAQ15_32[32];
extern const q15_t ALIGN4 realCoefAQ15_64[64];
extern const q15_t ALIGN4 realCoefAQ15_128[128];
extern const q15_t ALIGN4 realCoefAQ15_256[256];
extern const q15_t ALIGN4 realCoefAQ15_512[512];
extern const q15_t ALIGN4 realCoefAQ15_1024[1024];
extern const q15_t ALIGN4 realCoefAQ15_2048[2048];
extern const q15_t ALIGN4 realCoefAQ15_4096[4096];
extern const q15_t ALIGN4 realCoefBQ15_32[32];
extern const q15_t ALIGN4 realCoefBQ15_64[64];
extern const q15_t ALIGN4 realCoefBQ15_128[128];
extern const q15_t ALIGN4 realCoefBQ15_256[256];
extern const q15_t ALIGN4 realCoefBQ15_512[512];
extern const q15_t ALIGN4 realCoefBQ15_1024[1024];
extern const q15_t ALIGN4 realCoefBQ15_2048[2048];
extern const q15_t ALIGN4 realCoefBQ15_4096[4096];
extern const q31_t realCoefAQ31_32[32];
extern const q31_t realCoefAQ31_64[64];
extern const q31_t realCoefAQ31_128[128];
extern const q31_t realCoefAQ31_256[256];
extern const q31_t realCoefAQ31_512[512];
extern const q31_t realCoefAQ31_1024[1024];
extern const q31_t realCoefAQ31_2048[2048];
extern const q31_t realCoefAQ31_4096[4096];
extern const q31_t realCoefBQ31_32[32];
extern const q31_t realCoefBQ31_64[64];
extern const q31_t realCoefBQ31_128[128];
extern const q31_t realCoefBQ31_256[256];
extern const q31_t realCoefBQ31_512[512];
extern const q31_t realCoefBQ31_1024[1024];
extern const q31_t realCoefBQ31_2048[2048];
extern const q31_t realCoefBQ31_4096[4096];
extern const float32_t realCoefA[8192];
extern const float32_t realCoefB[8192];
/*Tables for DCT4*/
extern const q15_t ALIGN4 WeightsQ15_128[128+2];
extern const q15_t ALIGN4 WeightsQ15_512[512+2];
extern const q15_t ALIGN4 WeightsQ15_2048[2048+2];
extern const q15_t ALIGN4 WeightsQ15_8192[8192+2];
extern const q15_t ALIGN4 cos_factorsQ15_128[128];
extern const q15_t ALIGN4 cos_factorsQ15_512[512];
extern const q15_t ALIGN4 cos_factorsQ15_2048[2048];
extern const q15_t ALIGN4 cos_factorsQ15_8192[8192];
extern const q31_t WeightsQ31_128[128+2];
extern const q31_t WeightsQ31_512[512+2];
extern const q31_t WeightsQ31_2048[2048+2];
extern const q31_t WeightsQ31_8192[8192+2];
extern const q31_t cos_factorsQ31_128[128];
extern const q31_t cos_factorsQ31_512[512];
extern const q31_t cos_factorsQ31_2048[2048];
extern const q31_t cos_factorsQ31_8192[8192];
extern const float32_t Weights_128[128+2];
extern const float32_t Weights_512[512+2];
extern const float32_t Weights_2048[2048+2];
extern const float32_t Weights_8192[8192+2];
extern const float32_t cos_factors_128[128];
extern const float32_t cos_factors_512[512];
extern const float32_t cos_factors_2048[2048];
extern const float32_t cos_factors_8192[8192];
/* floating-point bit reversal tables */
#define CSKYBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define CSKYBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define CSKYBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define CSKYBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define CSKYBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define CSKYBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define CSKYBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define CSKYBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define CSKYBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t cskyBitRevIndexTable16[CSKYBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable32[CSKYBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable64[CSKYBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable128[CSKYBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable256[CSKYBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable512[CSKYBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable1024[CSKYBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable2048[CSKYBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable4096[CSKYBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define CSKYBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define CSKYBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define CSKYBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define CSKYBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define CSKYBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define CSKYBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define CSKYBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define CSKYBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define CSKYBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t cskyBitRevIndexTable_fixed_16[CSKYBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_32[CSKYBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_64[CSKYBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_128[CSKYBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_256[CSKYBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_512[CSKYBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_1024[CSKYBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_2048[CSKYBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t cskyBitRevIndexTable_fixed_4096[CSKYBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* CSKY_COMMON_TABLES_H */
| YifuLiu/AliOS-Things | components/csi/csi2/dsp/include/csky_common_tables.h | C | apache-2.0 | 11,486 |
/******************************************************************************
* @file csky_const_structs.h
* @brief This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the csky_cfft_f32() function.
* @version V1.0
* @date 20. Dec 2016
******************************************************************************/
/* ---------------------------------------------------------------------------
* Copyright (C) 2016 CSKY Limited. All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the following
* conditions are met:
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* * Neither the name of CSKY Ltd. nor the names of CSKY's contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission of CSKY Ltd.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */
#ifndef _CSKY_CONST_STRUCTS_H
#define _CSKY_CONST_STRUCTS_H
#include "csky_math.h"
#include "csky_common_tables.h"
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len16;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len32;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len64;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len128;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len256;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len512;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len1024;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len2048;
extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len4096;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len16;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len32;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len64;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len128;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len256;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len512;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len1024;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len2048;
extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len4096;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len16;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len32;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len64;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len128;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len256;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len512;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len1024;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len2048;
extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len4096;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len32;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len64;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len128;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len256;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len512;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len1024;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len2048;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len4096;
extern csky_rfft_instance_q15 csky_rfft_sR_q15_len8192;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len32;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len64;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len128;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len256;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len512;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len1024;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len2048;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len4096;
extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len8192;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len32;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len64;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len128;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len256;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len512;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len1024;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len2048;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len4096;
extern csky_rfft_instance_q31 csky_rfft_sR_q31_len8192;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len32;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len64;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len128;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len256;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len512;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len1024;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len2048;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len4096;
extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len8192;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len32;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len64;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len128;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len256;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len512;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len1024;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len2048;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len4096;
extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len8192;
extern csky_dct4_instance_q15 csky_dct4_sR_q15_len128;
extern csky_dct4_instance_q15 csky_dct4_sR_q15_len512;
extern csky_dct4_instance_q15 csky_dct4_sR_q15_len2048;
extern csky_dct4_instance_q15 csky_dct4_sR_q15_len8192;
extern csky_dct4_instance_q31 csky_dct4_sR_q31_len128;
extern csky_dct4_instance_q31 csky_dct4_sR_q31_len512;
extern csky_dct4_instance_q31 csky_dct4_sR_q31_len2048;
extern csky_dct4_instance_q31 csky_dct4_sR_q31_len8192;
extern csky_dct4_instance_f32 csky_dct4_sR_f32_len128;
extern csky_dct4_instance_f32 csky_dct4_sR_f32_len512;
extern csky_dct4_instance_f32 csky_dct4_sR_f32_len2048;
extern csky_dct4_instance_f32 csky_dct4_sR_f32_len8192;
#endif
| YifuLiu/AliOS-Things | components/csi/csi2/dsp/include/csky_const_structs.h | C | apache-2.0 | 7,491 |
/******************************************************************************
* @file csky_math.h
* @brief Public header file for CSI DSP Library.
* @version V1.0
* @date 20. Dec 2016
******************************************************************************/
/* ---------------------------------------------------------------------------
* Copyright (C) 2016 CSKY Limited. All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the following
* conditions are met:
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* * Neither the name of CSKY Ltd. nor the names of CSKY's contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission of CSKY Ltd.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */
/**
* @defgroup groupMath Basic Math Functions
*/
/**
* @defgroup groupFastMath Fast Math Functions
* This set of functions provides a fast approximation to sine, cosine, and square root.
* As compared to most of the other functions in the CSI math library, the fast math functions
* operate on individual values and not arrays.
* There are separate functions for Q15, Q31, and floating-point data.
*
*/
/**
* @defgroup groupCmplxMath Complex Math Functions
* This set of functions operates on complex data vectors.
* The data in the complex arrays is stored in an interleaved fashion
* (real, imag, real, imag, ...).
* In the API functions, the number of samples in a complex array refers
* to the number of complex values; the array contains twice this number of
* real values.
*/
/**
* @defgroup groupFilters Filtering Functions
*/
/**
* @defgroup groupMatrix Matrix Functions
*
* This set of functions provides basic matrix math operations.
* The functions operate on matrix data structures. For example,
* the type
* definition for the floating-point matrix structure is shown
* below:
* <pre>
* typedef struct
* {
* uint16_t numRows; // number of rows of the matrix.
* uint16_t numCols; // number of columns of the matrix.
* float32_t *pData; // points to the data of the matrix.
* } csky_matrix_instance_f32;
* </pre>
* There are similar definitions for Q15 and Q31 data types.
*
* The structure specifies the size of the matrix and then points to
* an array of data. The array is of size <code>numRows X numCols</code>
* and the values are arranged in row order. That is, the
* matrix element (i, j) is stored at:
* <pre>
* pData[i*numCols + j]
* </pre>
*
* \par Init Functions
* There is an associated initialization function for each type of matrix
* data structure.
* The initialization function sets the values of the internal structure fields.
* Refer to the function <code>csky_mat_init_f32()</code>, <code>csky_mat_init_q31()</code>
* and <code>csky_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
*
* \par
* Use of the initialization function is optional. However, if initialization function is used
* then the instance structure cannot be placed into a const data section.
* To place the instance structure in a const data
* section, manually initialize the data structure. For example:
* <pre>
* <code>csky_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
* <code>csky_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
* <code>csky_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
* </pre>
* where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
* specifies the number of columns, and <code>pData</code> points to the
* data array.
*
* \par Size Checking
* By default all of the matrix functions perform size checking on the input and
* output matrices. For example, the matrix addition function verifies that the
* two input matrices and the output matrix all have the same number of rows and
* columns. If the size check fails the functions return:
* <pre>
* CSKY_MATH_SIZE_MISMATCH
* </pre>
* Otherwise the functions return
* <pre>
* CSKY_MATH_SUCCESS
* </pre>
* There is some overhead associated with this matrix size checking.
* The matrix size checking is enabled via the \#define
* <pre>
* CSKY_MATH_MATRIX_CHECK
* </pre>
* within the library project settings. By default this macro is defined
* and size checking is enabled. By changing the project settings and
* undefining this macro size checking is eliminated and the functions
* run a bit faster. With size checking disabled the functions always
* return <code>CSKY_MATH_SUCCESS</code>.
*/
/**
* @defgroup groupTransforms Transform Functions
*/
/**
* @defgroup groupController Controller Functions
*/
/**
* @defgroup groupStats Statistics Functions
*/
/**
* @defgroup groupSupport Support Functions
*/
/**
* @defgroup groupInterpolation Interpolation Functions
* These functions perform 1- and 2-dimensional interpolation of data.
* Linear interpolation is used for 1-dimensional data and
* bilinear interpolation is used for 2-dimensional data.
*/
/**
* @defgroup groupYunvoice Yunvoice Functions
* These functions are designed for Yunvoice project, which are modified
* according to the CEVA DSP functions. So, one can porting the software
* from CEVA to CSKY straightforwardly.
*/
/**
* @defgroup groupExamples Examples
*/
#ifndef _CSKY_MATH_H
#define _CSKY_MATH_H
#define __CSI_GENERIC /* disable NVIC and Systick functions */
#include "csi_core.h"
#include <float.h>
#undef __CSI_GENERIC /* enable NVIC and Systick functions */
#include "string.h"
#include "math.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief Macros required for reciprocal calculation in Normalized LMS
*/
#define DELTA_Q31 (0x100)
#define DELTA_Q15 0x5
#define INDEX_MASK 0x0000003F
#ifndef PI
#define PI 3.14159265358979f
#endif
/**
* @brief Macros required for SINE and COSINE Fast math approximations
*/
#define FAST_MATH_TABLE_SIZE 512
#define FAST_MATH_Q31_SHIFT (32 - 10)
#define FAST_MATH_Q15_SHIFT (16 - 10)
#define CONTROLLER_Q31_SHIFT (32 - 9)
#define TABLE_SIZE 256
#define TABLE_SPACING_Q31 0x400000
#define TABLE_SPACING_Q15 0x80
/**
* @brief Macros required for SINE and COSINE Controller functions
*/
/* 1.31(q31) Fixed value of 2/360 */
/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
#define INPUT_SPACING 0xB60B61
/**
* @brief Macro for Unaligned Support
*/
#ifndef UNALIGNED_SUPPORT_DISABLE
#define ALIGN4
#else
#define ALIGN4 __attribute__((aligned(4)))
#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
__ALWAYS_STATIC_INLINE int32_t __SSAT_31(int32_t x)
{
int32_t res = x;
if (x > 0x3fffffff) {
res = 0x3fffffff;
} else if (x < -1073741824) {
res = -1073741824;
}
return res;
}
__ALWAYS_STATIC_INLINE int32_t __SSAT_16(int32_t x)
{
int32_t res = x;
if (x > 0x7fff) {
res = 0x7fff;
} else if (x < -32768) {
res = -32768;
}
return res;
}
__ALWAYS_STATIC_INLINE int32_t __SSAT_8(int32_t x)
{
int32_t res = x;
if (x > 0x7f) {
res = 0x7f;
} else if (x < -128) {
res = -128;
}
return res;
}
#ifdef CSKY_SIMD
/* SMMLAR */
__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32_R(int32_t a, int32_t x, int32_t y)
{
__ASM volatile("mula.s32.rhs %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y) : "0" (a), "1" (x), "2" (y));
return a;
}
/* SMMLSR */
__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32_R(int32_t a, int32_t x, int32_t y)
{
__ASM volatile("muls.s32.rhs %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
/* SMMULR */
__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32_R(int32_t x, int32_t y)
{
int32_t a;
__ASM volatile("mul.s32.rh %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y));
return a;
}
/* SMMLA */
__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32(int32_t a, int32_t x, int32_t y)
{
__ASM volatile("mula.s32.hs %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
/* SMMLS */
__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32(int32_t a, int32_t x, int32_t y)
{
__ASM volatile("muls.s32.hs %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
/* SMMUL */
__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32(int32_t x, int32_t y)
{
int32_t a;
__ASM volatile("mul.s32.h %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int32_t multAcc_16x16_keep32(int32_t a, int16_t x, int16_t y)
{
__ASM volatile("mulall.s16 %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int64_t multAcc_16x16_keep64(int64_t a, int16_t x, int16_t y)
{
__ASM volatile("mulall.s16.e %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int64_t mult_32x32_keep64(int32_t x, int32_t y)
{
int64_t a;
__ASM volatile("mul.s32 %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int64_t multAcc_32x32_keep64(int64_t a, int32_t x, int32_t y)
{
__ASM volatile("mula.s32 %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_31(int32_t x, int32_t y)
{
int64_t tmp1;
int32_t tmp2;
__ASM volatile("mul.s32 %0, %1, %2\n\t"
"dexti %3, %0, %R0, 31"
:"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y));
return tmp2;
}
__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_30(int32_t x, int32_t y)
{
int64_t tmp1;
int32_t tmp2;
__ASM volatile("mul.s32 %0, %1, %2\n\t"
"dexti %3, %0, %R0, 30"
:"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y));
return tmp2;
}
__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_4(int32_t x, int32_t y)
{
int64_t tmp1;
int32_t tmp2;
__ASM volatile("mul.s32 %0, %1, %2\n\t"
"dexti %3, %0, %R0, 4"
:"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y));
return tmp2;
}
__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_33(int32_t x, int32_t y)
{
int64_t tmp1;
int32_t tmp2;
__ASM volatile("mul.s32 %0, %1, %2\n\t"
"asri %3, %R0, 1"
:"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y));
return tmp2;
}
__ALWAYS_STATIC_INLINE int32_t dext_31(int64_t x)
{
int32_t tmp1;
__ASM volatile(
"dexti %0, %1, %R1, 31"
:"=r" (tmp1), "=r" (x) : "1" (x));
return tmp1;
}
__ALWAYS_STATIC_INLINE int32_t mult_l16xl16_keep32(int32_t x, int32_t y)
{
int32_t a;
__ASM volatile("mulll.s16 %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int32_t mult_h16xl16_keep32(int32_t x, int32_t y)
{
int32_t a;
__ASM volatile("mulhl.s16 %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y));
return a;
}
__ALWAYS_STATIC_INLINE int32_t mult_h16xh16_keep32(int32_t x, int32_t y)
{
int32_t a;
__ASM volatile("mulhh.s16 %0, %1, %2\n\t"
:"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y));
return a;
}
#endif
/**
* @brief Error status returned by some functions in the library.
*/
typedef enum
{
CSKY_MATH_SUCCESS = 0, /**< No error */
CSKY_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
CSKY_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
CSKY_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
CSKY_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
CSKY_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
CSKY_MATH_TEST_FAILURE = -6 /**< Test Failed */
} csky_status;
/**
* @brief 8-bit fractional data type in 1.7 format.
*/
typedef int8_t q7_t;
/**
* @brief 16-bit fractional data type in 1.15 format.
*/
typedef int16_t q15_t;
/**
* @brief 32-bit fractional data type in 1.31 format.
*/
typedef int32_t q31_t;
/**
* @brief 64-bit fractional data type in 1.63 format.
*/
typedef int64_t q63_t;
/**
* @brief 32-bit floating-point type definition.
*/
typedef float float32_t;
/**
* @brief 64-bit floating-point type definition.
*/
typedef double float64_t;
/**
* @brief 32-bit fractional complex data type in 1.31 format.
*/
typedef struct
{
q31_t re;
q31_t im;
} cq31_t;
/**
* @brief 16-bit fractional complex data type in 1.15 format.
*/
typedef struct
{
q15_t re;
q15_t im;
} cq15_t;
/**
* @brief definition to read/write two 16 bit values.
*/
#define __SIMD32_TYPE int32_t
#define CSI_UNUSED __attribute__((unused))
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
#define __SIMD64(addr) (*(int64_t **) & (addr))
#if defined (CSKY_MATH_NO_SIMD)
/**
* @brief definition to pack two 16 bit values.
*/
#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
(((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
(((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
#endif
/**
* @brief definition to pack four 8 bit values.
*/
#ifndef CSKY_MATH_BIG_ENDIAN
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
#else
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
#endif
/**
* @brief Clips Q63 to Q31 values.
*/
static __INLINE q31_t clip_q63_to_q31(
q63_t x)
{
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
}
/**
* @brief Instance structure for the Q7 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
} csky_fir_instance_q7;
/**
* @brief Instance structure for the Q15 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
} csky_fir_instance_q15;
/**
* @brief Instance structure for the Q31 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
} csky_fir_instance_q31;
/**
* @brief Instance structure for the floating-point FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
} csky_fir_instance_f32;
void csky_fir_q7(
const csky_fir_instance_q7 * S,
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_fir_init_q7(
csky_fir_instance_q7 * S,
uint16_t numTaps,
q7_t * pCoeffs,
q7_t * pState,
uint32_t blockSize);
void csky_fir_q15(
const csky_fir_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_fir_fast_q15(
const csky_fir_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
csky_status csky_fir_init_q15(
csky_fir_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
void csky_fir_q31(
const csky_fir_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_fir_fast_q31(
const csky_fir_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_fir_init_q31(
csky_fir_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
void csky_fir_f32(
const csky_fir_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_fir_init_f32(
csky_fir_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 Biquad cascade filter.
*/
typedef struct
{
int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
} csky_biquad_casd_df1_inst_q15;
/**
* @brief Instance structure for the Q31 Biquad cascade filter.
*/
typedef struct
{
uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
} csky_biquad_casd_df1_inst_q31;
/**
* @brief Instance structure for the Q31 Biquad cascade filter.
*/
/**
* @brief Instance structure for the floating-point Biquad cascade filter.
*/
typedef struct
{
uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
} csky_biquad_casd_df1_inst_f32;
void csky_biquad_cascade_df1_q15(
const csky_biquad_casd_df1_inst_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df1_init_q15(
csky_biquad_casd_df1_inst_q15 * S,
uint8_t numStages,
q15_t * pCoeffs,
q15_t * pState,
int8_t postShift);
void csky_biquad_cascade_df1_fast_q15(
const csky_biquad_casd_df1_inst_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df1_q31(
const csky_biquad_casd_df1_inst_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df1_fast_q31(
const csky_biquad_casd_df1_inst_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df1_init_q31(
csky_biquad_casd_df1_inst_q31 * S,
uint8_t numStages,
q31_t * pCoeffs,
q31_t * pState,
int8_t postShift);
void csky_biquad_cascade_df1_f32(
const csky_biquad_casd_df1_inst_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df1_init_f32(
csky_biquad_casd_df1_inst_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
float32_t *pData; /**< points to the data of the matrix. */
} csky_matrix_instance_f32;
/**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
float64_t *pData; /**< points to the data of the matrix. */
} csky_matrix_instance_f64;
/**
* @brief Instance structure for the Q15 matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
q15_t *pData; /**< points to the data of the matrix. */
} csky_matrix_instance_q15;
/**
* @brief Instance structure for the Q31 matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
q31_t *pData; /**< points to the data of the matrix. */
} csky_matrix_instance_q31;
csky_status csky_mat_add_f32(
const csky_matrix_instance_f32 * pSrcA,
const csky_matrix_instance_f32 * pSrcB,
csky_matrix_instance_f32 * pDst);
csky_status csky_mat_add_q15(
const csky_matrix_instance_q15 * pSrcA,
const csky_matrix_instance_q15 * pSrcB,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_add_q31(
const csky_matrix_instance_q31 * pSrcA,
const csky_matrix_instance_q31 * pSrcB,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_cmplx_mult_f32(
const csky_matrix_instance_f32 * pSrcA,
const csky_matrix_instance_f32 * pSrcB,
csky_matrix_instance_f32 * pDst);
csky_status csky_mat_cmplx_mult_q15(
const csky_matrix_instance_q15 * pSrcA,
const csky_matrix_instance_q15 * pSrcB,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_cmplx_mult_q31(
const csky_matrix_instance_q31 * pSrcA,
const csky_matrix_instance_q31 * pSrcB,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_trans_f32(
const csky_matrix_instance_f32 * pSrc,
csky_matrix_instance_f32 * pDst);
csky_status csky_mat_trans_q15(
const csky_matrix_instance_q15 * pSrc,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_trans_q31(
const csky_matrix_instance_q31 * pSrc,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_mult_f32(
const csky_matrix_instance_f32 * pSrcA,
const csky_matrix_instance_f32 * pSrcB,
csky_matrix_instance_f32 * pDst);
csky_status csky_mat_mult_q15(
const csky_matrix_instance_q15 * pSrcA,
const csky_matrix_instance_q15 * pSrcB,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_mult_fast_q15(
const csky_matrix_instance_q15 * pSrcA,
const csky_matrix_instance_q15 * pSrcB,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_mult_q31(
const csky_matrix_instance_q31 * pSrcA,
const csky_matrix_instance_q31 * pSrcB,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_mult_trans_q31(
const csky_matrix_instance_q31 * pSrcA,
const csky_matrix_instance_q31 * pSrcB,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_mult_fast_q31(
const csky_matrix_instance_q31 * pSrcA,
const csky_matrix_instance_q31 * pSrcB,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_sub_f32(
const csky_matrix_instance_f32 * pSrcA,
const csky_matrix_instance_f32 * pSrcB,
csky_matrix_instance_f32 * pDst);
csky_status csky_mat_sub_q15(
const csky_matrix_instance_q15 * pSrcA,
const csky_matrix_instance_q15 * pSrcB,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_sub_q31(
const csky_matrix_instance_q31 * pSrcA,
const csky_matrix_instance_q31 * pSrcB,
csky_matrix_instance_q31 * pDst);
csky_status csky_mat_scale_f32(
const csky_matrix_instance_f32 * pSrc,
float32_t scale,
csky_matrix_instance_f32 * pDst);
csky_status csky_mat_scale_q15(
const csky_matrix_instance_q15 * pSrc,
q15_t scaleFract,
int32_t shift,
csky_matrix_instance_q15 * pDst);
csky_status csky_mat_scale_q31(
const csky_matrix_instance_q31 * pSrc,
q31_t scaleFract,
int32_t shift,
csky_matrix_instance_q31 * pDst);
void csky_mat_init_q31(
csky_matrix_instance_q31 * S,
uint16_t nRows,
uint16_t nColumns,
q31_t * pData);
void csky_mat_init_q15(
csky_matrix_instance_q15 * S,
uint16_t nRows,
uint16_t nColumns,
q15_t * pData);
void csky_mat_init_f32(
csky_matrix_instance_f32 * S,
uint16_t nRows,
uint16_t nColumns,
float32_t * pData);
/**
* @brief Instance structure for the Q15 PID Control.
*/
typedef struct
{
q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
q15_t A1;
q15_t A2;
q15_t state[3]; /**< The state array of length 3. */
q15_t Kp; /**< The proportional gain. */
q15_t Ki; /**< The integral gain. */
q15_t Kd; /**< The derivative gain. */
} csky_pid_instance_q15;
/**
* @brief Instance structure for the Q31 PID Control.
*/
typedef struct
{
q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
q31_t A2; /**< The derived gain, A2 = Kd . */
q31_t state[3]; /**< The state array of length 3. */
q31_t Kp; /**< The proportional gain. */
q31_t Ki; /**< The integral gain. */
q31_t Kd; /**< The derivative gain. */
} csky_pid_instance_q31;
/**
* @brief Instance structure for the floating-point PID Control.
*/
typedef struct
{
float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
float32_t A2; /**< The derived gain, A2 = Kd . */
float32_t state[3]; /**< The state array of length 3. */
float32_t Kp; /**< The proportional gain. */
float32_t Ki; /**< The integral gain. */
float32_t Kd; /**< The derivative gain. */
} csky_pid_instance_f32;
void csky_pid_init_f32(
csky_pid_instance_f32 * S,
int32_t resetStateFlag);
void csky_pid_reset_f32(
csky_pid_instance_f32 * S);
void csky_pid_init_q31(
csky_pid_instance_q31 * S,
int32_t resetStateFlag);
void csky_pid_reset_q31(
csky_pid_instance_q31 * S);
void csky_pid_init_q15(
csky_pid_instance_q15 * S,
int32_t resetStateFlag);
void csky_pid_reset_q15(
csky_pid_instance_q15 * S);
/**
* @brief Instance structure for the floating-point Linear Interpolate function.
*/
typedef struct
{
uint32_t nValues; /**< nValues */
float32_t x1; /**< x1 */
float32_t xSpacing; /**< xSpacing */
float32_t *pYData; /**< pointer to the table of Y values */
} csky_linear_interp_instance_f32;
/**
* @brief Instance structure for the floating-point bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /**< number of rows in the data table. */
uint16_t numCols; /**< number of columns in the data table. */
float32_t *pData; /**< points to the data table. */
} csky_bilinear_interp_instance_f32;
/**
* @brief Instance structure for the Q31 bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /**< number of rows in the data table. */
uint16_t numCols; /**< number of columns in the data table. */
q31_t *pData; /**< points to the data table. */
} csky_bilinear_interp_instance_q31;
/**
* @brief Instance structure for the Q15 bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /**< number of rows in the data table. */
uint16_t numCols; /**< number of columns in the data table. */
q15_t *pData; /**< points to the data table. */
} csky_bilinear_interp_instance_q15;
/**
* @brief Instance structure for the Q15 bilinear interpolation function.
*/
typedef struct
{
uint16_t numRows; /**< number of rows in the data table. */
uint16_t numCols; /**< number of columns in the data table. */
q7_t *pData; /**< points to the data table. */
} csky_bilinear_interp_instance_q7;
void csky_mult_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
void csky_mult_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_mult_rnd_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_mult_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
void csky_mult_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_cfft_radix2_instance_q15;
/**
* @brief Instance structure for the Q15 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q15_t *pTwiddle; /**< points to the twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_cfft_radix4_instance_q15;
/**
* @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q31_t *pTwiddle; /**< points to the Twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_cfft_radix2_instance_q31;
/**
* @brief Instance structure for the Q31 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q31_t *pTwiddle; /**< points to the twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_cfft_radix4_instance_q31;
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
float32_t *pTwiddle; /**< points to the Twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
float32_t onebyfftLen; /**< value of 1/fftLen. */
} csky_cfft_radix2_instance_f32;
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
float32_t *pTwiddle; /**< points to the Twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
float32_t onebyfftLen; /**< value of 1/fftLen. */
} csky_cfft_radix4_instance_f32;
/**
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t bitRevLength; /**< bit reversal table length. */
} csky_cfft_instance_q15;
void csky_cfft_q15(
const csky_cfft_instance_q15 * S,
q15_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t bitRevLength; /**< bit reversal table length. */
} csky_cfft_instance_q31;
void csky_cfft_q31(
const csky_cfft_instance_q31 * S,
q31_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t bitRevLength; /**< bit reversal table length. */
} csky_cfft_instance_f32;
void csky_cfft_f32(
const csky_cfft_instance_f32 * S,
float32_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the Q15 RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
const csky_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} csky_rfft_instance_q15;
csky_status csky_rfft_init_q15(
csky_rfft_instance_q15 * S,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void csky_rfft_q15(
const csky_rfft_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst);
/**
* @brief Instance structure for the Q31 RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
const csky_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} csky_rfft_instance_q31;
csky_status csky_rfft_init_q31(
csky_rfft_instance_q31 * S,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void csky_rfft_q31(
const csky_rfft_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst);
/**
* @brief Instance structure for the floating-point RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint16_t fftLenBy2; /**< length of the complex FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
csky_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
} csky_rfft_instance_f32;
csky_status csky_rfft_init_f32(
csky_rfft_instance_f32 * S,
csky_cfft_radix4_instance_f32 * S_CFFT,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void csky_rfft_f32(
const csky_rfft_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst);
/**
* @brief Instance structure for the floating-point RFFT/RIFFT function.
*/
typedef struct
{
csky_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
uint16_t fftLenRFFT; /**< length of the real sequence */
float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
} csky_rfft_fast_instance_f32 ;
csky_status csky_rfft_fast_init_f32 (
csky_rfft_fast_instance_f32 * S,
uint16_t fftLen);
void csky_rfft_fast_f32(
csky_rfft_fast_instance_f32 * S,
float32_t * p, float32_t * pOut,
uint8_t ifftFlag);
/**
* @brief Instance structure for the floating-point DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
float32_t normalize; /**< normalizing factor. */
float32_t *pTwiddle; /**< points to the twiddle factor table. */
float32_t *pCosFactor; /**< points to the cosFactor table. */
csky_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT fast instance. */
csky_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
} csky_dct4_instance_f32;
csky_status csky_dct4_init_f32(
csky_dct4_instance_f32 * S,
csky_rfft_fast_instance_f32 * S_RFFT,
csky_cfft_radix4_instance_f32 * S_CFFT,
uint16_t N,
uint16_t Nby2,
float32_t normalize);
void csky_dct4_f32(
const csky_dct4_instance_f32 * S,
float32_t * pState,
float32_t * pInlineBuffer);
/**
* @brief Instance structure for the Q31 DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
q31_t normalize; /**< normalizing factor. */
q31_t *pTwiddle; /**< points to the twiddle factor table. */
q31_t *pCosFactor; /**< points to the cosFactor table. */
csky_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
csky_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} csky_dct4_instance_q31;
csky_status csky_dct4_init_q31(
csky_dct4_instance_q31 * S,
csky_rfft_instance_q31 * S_RFFT,
csky_cfft_radix4_instance_q31 * S_CFFT,
uint16_t N,
uint16_t Nby2,
q31_t normalize);
void csky_dct4_q31(
const csky_dct4_instance_q31 * S,
q31_t * pState,
q31_t * pInlineBuffer);
/**
* @brief Instance structure for the Q15 DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
q15_t normalize; /**< normalizing factor. */
q15_t *pTwiddle; /**< points to the twiddle factor table. */
q15_t *pCosFactor; /**< points to the cosFactor table. */
csky_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
csky_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} csky_dct4_instance_q15;
csky_status csky_dct4_init_q15(
csky_dct4_instance_q15 * S,
csky_rfft_instance_q15 * S_RFFT,
csky_cfft_radix4_instance_q15 * S_CFFT,
uint16_t N,
uint16_t Nby2,
q15_t normalize);
void csky_dct4_q15(
const csky_dct4_instance_q15 * S,
q15_t * pState,
q15_t * pInlineBuffer);
void csky_add_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
void csky_add_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
void csky_add_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_add_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
void csky_sub_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
void csky_sub_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
void csky_sub_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_sub_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
void csky_scale_f32(
float32_t * pSrc,
float32_t scale,
float32_t * pDst,
uint32_t blockSize);
void csky_scale_q7(
q7_t * pSrc,
q7_t scaleFract,
int8_t shift,
q7_t * pDst,
uint32_t blockSize);
void csky_scale_q15(
q15_t * pSrc,
q15_t scaleFract,
int8_t shift,
q15_t * pDst,
uint32_t blockSize);
void csky_scale_q31(
q31_t * pSrc,
q31_t scaleFract,
int8_t shift,
q31_t * pDst,
uint32_t blockSize);
void csky_abs_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_abs_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_abs_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_abs_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_abs_max_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_abs_max_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_dot_prod_f32(
float32_t * pSrcA,
float32_t * pSrcB,
uint32_t blockSize,
float32_t * result);
void csky_dot_prod_q7(
q7_t * pSrcA,
q7_t * pSrcB,
uint32_t blockSize,
q31_t * result);
void csky_dot_prod_q15(
q15_t * pSrcA,
q15_t * pSrcB,
uint32_t blockSize,
q63_t * result);
void csky_dot_prod_q31(
q31_t * pSrcA,
q31_t * pSrcB,
uint32_t blockSize,
q63_t * result);
void csky_shift_q7(
q7_t * pSrc,
int8_t shiftBits,
q7_t * pDst,
uint32_t blockSize);
void csky_shift_q15(
q15_t * pSrc,
int8_t shiftBits,
q15_t * pDst,
uint32_t blockSize);
void csky_shift_q31(
q31_t * pSrc,
int8_t shiftBits,
q31_t * pDst,
uint32_t blockSize);
void csky_offset_f32(
float32_t * pSrc,
float32_t offset,
float32_t * pDst,
uint32_t blockSize);
void csky_offset_q7(
q7_t * pSrc,
q7_t offset,
q7_t * pDst,
uint32_t blockSize);
void csky_offset_q15(
q15_t * pSrc,
q15_t offset,
q15_t * pDst,
uint32_t blockSize);
void csky_offset_q31(
q31_t * pSrc,
q31_t offset,
q31_t * pDst,
uint32_t blockSize);
void csky_negate_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_negate_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_negate_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_negate_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_copy_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_copy_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_copy_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_copy_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_fill_f32(
float32_t value,
float32_t * pDst,
uint32_t blockSize);
void csky_fill_q7(
q7_t value,
q7_t * pDst,
uint32_t blockSize);
void csky_fill_q15(
q15_t value,
q15_t * pDst,
uint32_t blockSize);
void csky_fill_q31(
q31_t value,
q31_t * pDst,
uint32_t blockSize);
void csky_conv_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst);
void csky_conv_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_conv_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_conv_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_conv_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_conv_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_conv_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_conv_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_conv_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst);
csky_status csky_conv_partial_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_status csky_conv_partial_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
csky_status csky_conv_partial_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_status csky_conv_partial_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_status csky_conv_partial_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
csky_status csky_conv_partial_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_status csky_conv_partial_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_status csky_conv_partial_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
csky_status csky_conv_partial_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* functions for the yunVoice functions.
*/
q15_t csky_dsp_lib_vec_max_abs16(
q15_t * A,
uint32_t N);
q31_t csky_dsp_lib_vec_max_abs32(
q31_t * A,
uint32_t N);
void csky_dsp_lib_vec_abs16(
q15_t * A,
uint32_t N,
q15_t * C);
void csky_dsp_lib_vec_abs32(
q31_t * A,
uint32_t N,
q31_t * C);
void csky_dsp_lib_vec_add16(
q15_t * A,
q15_t * B,
uint32_t N,
q15_t * C);
void csky_dsp_lib_vec_add32(
q31_t * A,
q31_t * B,
uint32_t N,
q31_t * C);
void csky_dsp_lib_vec_cx_conj_q15(
q15_t * A,
uint32_t N,
q15_t * B);
void csky_dsp_lib_vec_cx_conj_q31(
q31_t * A,
uint32_t N,
q31_t * C);
q31_t csky_dsp_lib_vec_dot_q15(
q15_t * A,
q15_t * B,
uint32_t N);
q31_t csky_dsp_lib_vec_dot_q31(
q31_t * A,
q31_t * B,
uint32_t N);
void csky_dsp_lib_mat_cx_add16(
cq15_t * A,
cq15_t * B,
uint32_t N,
uint32_t M,
cq15_t * C);
void csky_dsp_lib_mat_cx_add32(
cq31_t * A,
cq31_t * B,
uint32_t N,
uint32_t M,
cq31_t * C);
void csky_dsp_lib_mat_cx_mul_q15(
cq15_t * A,
cq15_t * B,
uint32_t N,
uint32_t M,
uint32_t L,
cq15_t * C);
void csky_dsp_lib_mat_cx_mul_q31(
cq31_t * A,
cq31_t * B,
uint32_t N,
uint32_t M,
uint32_t L,
cq31_t * C);
void csky_dsp_lib_mat_cx_sub16(
cq15_t * A,
cq15_t * B,
uint32_t N,
uint32_t M,
cq15_t * C);
void csky_dsp_lib_mat_cx_sub32(
cq31_t * A,
cq31_t * B,
uint32_t N,
uint32_t M,
cq31_t * C);
void csky_dsp_lib_vec_mul_q15(
q15_t * A,
q15_t * B,
uint32_t N,
q15_t * C);
void csky_dsp_lib_vec_mul_q31(
q31_t * A,
q31_t * B,
uint32_t N,
q31_t * C);
q31_t csky_dsp_lib_pow_int32(
q31_t arg_in_x,
q15_t arg_exp_in_x,
q31_t arg_in_y,
q15_t arg_exp_in_y,
q31_t *arg_exp_out);
void csky_dsp_lib_vec_scale_q15(
q15_t * A,
q15_t scaleFract,
int8_t shift,
q15_t * B,
uint32_t N);
void csky_dsp_lib_vec_scale_q31(
q31_t * A,
q31_t scaleFract,
int8_t shift,
q31_t * B,
uint32_t N);
void csky_dsp_lib_vec_shf16(
q15_t * A,
int8_t shift_val,
uint32_t N,
q15_t * C);
void csky_dsp_lib_vec_shf32(
q31_t * A,
q31_t shift_val,
uint32_t N,
q31_t * C);
q15_t csky_dsp_lib_sqrt_int32(
q31_t x,
uint32_t rnd_flag);
void csky_dsp_lib_vec_sub16(
q15_t * A,
q15_t * B,
uint32_t N,
q15_t * C);
void csky_dsp_lib_vec_sub32(
q31_t * A,
q31_t * B,
uint32_t N,
q31_t * C);
q63_t csky_dsp_lib_vec_sum16(
q15_t * A,
uint32_t N);
q63_t csky_dsp_lib_vec_sum32(
q31_t * A,
uint32_t N);
void csky_fft_lib_cx16_fft(
q31_t log2_buf_len,
q15_t * in_buf,
q15_t * out_buf,
const q15_t * twi_table,
const uint16_t * bitrev_tbl,
q15_t * temp_buf,
q7_t * ScaleShift,
q31_t br);
void csky_fft_lib_cx32_fft(
q31_t log2_buf_len,
q31_t * in_buf,
q31_t * out_buf,
const q31_t * twi_table,
const uint16_t * bitrev_tbl,
q31_t * temp_buf,
q31_t br);
void csky_fft_lib_cx16_ifft(
q31_t log2_buf_len,
q15_t * in_buf,
q15_t * out_buf,
const q15_t * twi_table,
const uint16_t * bitrev_tbl,
q15_t * temp_buf,
q7_t * ScaleShift,
q31_t br);
void csky_fft_lib_cx32_ifft(
q31_t log2_buf_len,
q31_t * in_buf,
q31_t * out_buf,
const q31_t * twi_table,
const uint16_t * bitrev_tbl,
q31_t * temp_buf,
q31_t br);
void csky_fft_lib_int16_fft(
q31_t log2_buf_len,
q15_t * in_buf,
q15_t * out_buf,
const q15_t * twi_table,
const q15_t * last_stage_twi_table,
const uint16_t * bitrev_tbl,
q15_t * temp_buf,
q7_t * ScaleShift,
q31_t br);
void csky_fft_lib_int32_fft(
q31_t log2_buf_len,
q31_t * in_buf,
q31_t * out_buf,
const q31_t * twi_table,
const q31_t * last_stage_twi_table,
const uint16_t * bitrev_tbl,
q31_t * temp_buf,
q31_t br);
void csky_fft_lib_int16_ifft(
q31_t log2_buf_len,
q15_t * in_buf,
q15_t * out_buf,
const q15_t * twi_table,
const q15_t * last_stage_twi_table,
const uint16_t * bitrev_tbl,
q15_t * temp_buf,
q7_t * ScaleShift,
q31_t br);
void csky_fft_lib_int32_ifft(
q31_t log2_buf_len,
q31_t * in_buf,
q31_t * out_buf,
const q31_t * twi_table,
const q31_t * last_stage_twi_table,
const uint16_t * bitrev_tbl,
q31_t * temp_buf,
q31_t br);
/**
* @brief Instance structure for the Q15 FIR decimator.
*/
typedef struct
{
uint8_t M; /**< decimation factor. */
uint16_t numTaps; /**< number of coefficients in the filter. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} csky_fir_decimate_instance_q15;
/**
* @brief Instance structure for the Q31 FIR decimator.
*/
typedef struct
{
uint8_t M; /**< decimation factor. */
uint16_t numTaps; /**< number of coefficients in the filter. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} csky_fir_decimate_instance_q31;
/**
* @brief Instance structure for the floating-point FIR decimator.
*/
typedef struct
{
uint8_t M; /**< decimation factor. */
uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} csky_fir_decimate_instance_f32;
void csky_fir_decimate_f32(
const csky_fir_decimate_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
csky_status csky_fir_decimate_init_f32(
csky_fir_decimate_instance_f32 * S,
uint16_t numTaps,
uint8_t M,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
void csky_fir_decimate_q15(
const csky_fir_decimate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_fir_decimate_fast_q15(
const csky_fir_decimate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
csky_status csky_fir_decimate_init_q15(
csky_fir_decimate_instance_q15 * S,
uint16_t numTaps,
uint8_t M,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
void csky_fir_decimate_q31(
const csky_fir_decimate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_fir_decimate_fast_q31(
csky_fir_decimate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
csky_status csky_fir_decimate_init_q31(
csky_fir_decimate_instance_q31 * S,
uint16_t numTaps,
uint8_t M,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 FIR interpolator.
*/
typedef struct
{
uint8_t L; /**< upsample factor. */
uint16_t phaseLength; /**< length of each polyphase filter component. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
} csky_fir_interpolate_instance_q15;
/**
* @brief Instance structure for the Q31 FIR interpolator.
*/
typedef struct
{
uint8_t L; /**< upsample factor. */
uint16_t phaseLength; /**< length of each polyphase filter component. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
} csky_fir_interpolate_instance_q31;
/**
* @brief Instance structure for the floating-point FIR interpolator.
*/
typedef struct
{
uint8_t L; /**< upsample factor. */
uint16_t phaseLength; /**< length of each polyphase filter component. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
} csky_fir_interpolate_instance_f32;
void csky_fir_interpolate_q15(
const csky_fir_interpolate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
csky_status csky_fir_interpolate_init_q15(
csky_fir_interpolate_instance_q15 * S,
uint8_t L,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
void csky_fir_interpolate_q31(
const csky_fir_interpolate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
csky_status csky_fir_interpolate_init_q31(
csky_fir_interpolate_instance_q31 * S,
uint8_t L,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
void csky_fir_interpolate_f32(
const csky_fir_interpolate_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
csky_status csky_fir_interpolate_init_f32(
csky_fir_interpolate_instance_f32 * S,
uint8_t L,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the high precision Q31 Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
} csky_biquad_cas_df1_32x64_ins_q31;
void csky_biquad_cas_df1_32x64_q31(
const csky_biquad_cas_df1_32x64_ins_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_biquad_cas_df1_32x64_init_q31(
csky_biquad_cas_df1_32x64_ins_q31 * S,
uint8_t numStages,
q31_t * pCoeffs,
q63_t * pState,
uint8_t postShift);
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
} csky_biquad_cascade_df2T_instance_f32;
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
} csky_biquad_cascade_stereo_df2T_instance_f32;
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
} csky_biquad_cascade_df2T_instance_f64;
void csky_biquad_cascade_df2T_f32(
const csky_biquad_cascade_df2T_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_stereo_df2T_f32(
const csky_biquad_cascade_stereo_df2T_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df2T_f64(
const csky_biquad_cascade_df2T_instance_f64 * S,
float64_t * pSrc,
float64_t * pDst,
uint32_t blockSize);
void csky_biquad_cascade_df2T_init_f32(
csky_biquad_cascade_df2T_instance_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
void csky_biquad_cascade_stereo_df2T_init_f32(
csky_biquad_cascade_stereo_df2T_instance_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
void csky_biquad_cascade_df2T_init_f64(
csky_biquad_cascade_df2T_instance_f64 * S,
uint8_t numStages,
float64_t * pCoeffs,
float64_t * pState);
/**
* @brief Instance structure for the Q15 FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of filter stages. */
q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
} csky_fir_lattice_instance_q15;
/**
* @brief Instance structure for the Q31 FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of filter stages. */
q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
} csky_fir_lattice_instance_q31;
/**
* @brief Instance structure for the floating-point FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of filter stages. */
float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
} csky_fir_lattice_instance_f32;
void csky_fir_lattice_init_q15(
csky_fir_lattice_instance_q15 * S,
uint16_t numStages,
q15_t * pCoeffs,
q15_t * pState);
void csky_fir_lattice_q15(
const csky_fir_lattice_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_fir_lattice_init_q31(
csky_fir_lattice_instance_q31 * S,
uint16_t numStages,
q31_t * pCoeffs,
q31_t * pState);
void csky_fir_lattice_q31(
const csky_fir_lattice_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_fir_lattice_init_f32(
csky_fir_lattice_instance_f32 * S,
uint16_t numStages,
float32_t * pCoeffs,
float32_t * pState);
void csky_fir_lattice_f32(
const csky_fir_lattice_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of stages in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
} csky_iir_lattice_instance_q15;
/**
* @brief Instance structure for the Q31 IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of stages in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
} csky_iir_lattice_instance_q31;
/**
* @brief Instance structure for the floating-point IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of stages in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
} csky_iir_lattice_instance_f32;
void csky_iir_lattice_f32(
const csky_iir_lattice_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_iir_lattice_init_f32(
csky_iir_lattice_instance_f32 * S,
uint16_t numStages,
float32_t * pkCoeffs,
float32_t * pvCoeffs,
float32_t * pState,
uint32_t blockSize);
void csky_iir_lattice_q31(
const csky_iir_lattice_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_iir_lattice_init_q31(
csky_iir_lattice_instance_q31 * S,
uint16_t numStages,
q31_t * pkCoeffs,
q31_t * pvCoeffs,
q31_t * pState,
uint32_t blockSize);
void csky_iir_lattice_q15(
const csky_iir_lattice_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_iir_lattice_init_q15(
csky_iir_lattice_instance_q15 * S,
uint16_t numStages,
q15_t * pkCoeffs,
q15_t * pvCoeffs,
q15_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the floating-point LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
float32_t mu; /**< step size that controls filter coefficient updates. */
} csky_lms_instance_f32;
void csky_lms_f32(
const csky_lms_instance_f32 * S,
float32_t * pSrc,
float32_t * pRef,
float32_t * pOut,
float32_t * pErr,
uint32_t blockSize);
void csky_lms_init_f32(
csky_lms_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
float32_t mu,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q15_t mu; /**< step size that controls filter coefficient updates. */
uint32_t postShift; /**< bit shift applied to coefficients. */
} csky_lms_instance_q15;
void csky_lms_init_q15(
csky_lms_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
q15_t mu,
uint32_t blockSize,
uint32_t postShift);
void csky_lms_q15(
const csky_lms_instance_q15 * S,
q15_t * pSrc,
q15_t * pRef,
q15_t * pOut,
q15_t * pErr,
uint32_t blockSize);
/**
* @brief Instance structure for the Q31 LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q31_t mu; /**< step size that controls filter coefficient updates. */
uint32_t postShift; /**< bit shift applied to coefficients. */
} csky_lms_instance_q31;
void csky_lms_q31(
const csky_lms_instance_q31 * S,
q31_t * pSrc,
q31_t * pRef,
q31_t * pOut,
q31_t * pErr,
uint32_t blockSize);
void csky_lms_init_q31(
csky_lms_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
q31_t mu,
uint32_t blockSize,
uint32_t postShift);
/**
* @brief Instance structure for the floating-point normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
float32_t mu; /**< step size that control filter coefficient updates. */
float32_t energy; /**< saves previous frame energy. */
float32_t x0; /**< saves previous input sample. */
} csky_lms_norm_instance_f32;
void csky_lms_norm_f32(
csky_lms_norm_instance_f32 * S,
float32_t * pSrc,
float32_t * pRef,
float32_t * pOut,
float32_t * pErr,
uint32_t blockSize);
void csky_lms_norm_init_f32(
csky_lms_norm_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
float32_t mu,
uint32_t blockSize);
/**
* @brief Instance structure for the Q31 normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q31_t mu; /**< step size that controls filter coefficient updates. */
uint8_t postShift; /**< bit shift applied to coefficients. */
q31_t *recipTable; /**< points to the reciprocal initial value table. */
q31_t energy; /**< saves previous frame energy. */
q31_t x0; /**< saves previous input sample. */
} csky_lms_norm_instance_q31;
void csky_lms_norm_q31(
csky_lms_norm_instance_q31 * S,
q31_t * pSrc,
q31_t * pRef,
q31_t * pOut,
q31_t * pErr,
uint32_t blockSize);
void csky_lms_norm_init_q31(
csky_lms_norm_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
q31_t mu,
uint32_t blockSize,
uint8_t postShift);
/**
* @brief Instance structure for the Q15 normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< Number of coefficients in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q15_t mu; /**< step size that controls filter coefficient updates. */
uint8_t postShift; /**< bit shift applied to coefficients. */
q15_t *recipTable; /**< Points to the reciprocal initial value table. */
q15_t energy; /**< saves previous frame energy. */
q15_t x0; /**< saves previous input sample. */
} csky_lms_norm_instance_q15;
void csky_lms_norm_q15(
csky_lms_norm_instance_q15 * S,
q15_t * pSrc,
q15_t * pRef,
q15_t * pOut,
q15_t * pErr,
uint32_t blockSize);
void csky_lms_norm_init_q15(
csky_lms_norm_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
q15_t mu,
uint32_t blockSize,
uint8_t postShift);
void csky_correlate_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst);
void csky_correlate_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch);
void csky_correlate_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_correlate_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_correlate_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch);
void csky_correlate_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_correlate_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_correlate_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_correlate_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst);
/**
* @brief Instance structure for the floating-point sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_fir_sparse_instance_f32;
/**
* @brief Instance structure for the Q31 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_fir_sparse_instance_q31;
/**
* @brief Instance structure for the Q15 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_fir_sparse_instance_q15;
/**
* @brief Instance structure for the Q7 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_fir_sparse_instance_q7;
void csky_fir_sparse_f32(
csky_fir_sparse_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
float32_t * pScratchIn,
uint32_t blockSize);
void csky_fir_sparse_init_f32(
csky_fir_sparse_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_fir_sparse_q31(
csky_fir_sparse_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
q31_t * pScratchIn,
uint32_t blockSize);
void csky_fir_sparse_init_q31(
csky_fir_sparse_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_fir_sparse_q15(
csky_fir_sparse_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
q15_t * pScratchIn,
q31_t * pScratchOut,
uint32_t blockSize);
void csky_fir_sparse_init_q15(
csky_fir_sparse_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_fir_sparse_q7(
csky_fir_sparse_instance_q7 * S,
q7_t * pSrc,
q7_t * pDst,
q7_t * pScratchIn,
q31_t * pScratchOut,
uint32_t blockSize);
void csky_fir_sparse_init_q7(
csky_fir_sparse_instance_q7 * S,
uint16_t numTaps,
q7_t * pCoeffs,
q7_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_sin_cos_f32(
float32_t theta,
float32_t * pSinVal,
float32_t * pCosVal);
void csky_sin_cos_q31(
q31_t theta,
q31_t * pSinVal,
q31_t * pCosVal);
void csky_cmplx_conj_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_cmplx_conj_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_cmplx_conj_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_cmplx_mag_squared_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_cmplx_mag_squared_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_cmplx_mag_squared_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_vsqrt_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_vsqrt_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_vsqrt_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t numSamples);
/**
* @ingroup groupController
*/
/**
* @defgroup PID PID Motor Control
*
* A Proportional Integral Derivative (PID) controller is a generic feedback control
* loop mechanism widely used in industrial control systems.
* A PID controller is the most commonly used type of feedback controller.
*
* This set of functions implements (PID) controllers
* for Q15, Q31, and floating-point data types. The functions operate on a single sample
* of data and each call to the function returns a single processed value.
* <code>S</code> points to an instance of the PID control data structure. <code>in</code>
* is the input sample value. The functions return the output value.
*
* \par Algorithm:
* <pre>
* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
* A0 = Kp + Ki + Kd
* A1 = (-Kp ) - (2 * Kd )
* A2 = Kd </pre>
*
* \par
* where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
*
* \par
* \image html PID.gif "Proportional Integral Derivative Controller"
*
* \par
* The PID controller calculates an "error" value as the difference between
* the measured output and the reference input.
* The controller attempts to minimize the error by adjusting the process control inputs.
* The proportional value determines the reaction to the current error,
* the integral value determines the reaction based on the sum of recent errors,
* and the derivative value determines the reaction based on the rate at which the error has been changing.
*
* \par Instance Structure
* The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
* A separate instance structure must be defined for each PID Controller.
* There are separate instance structure declarations for each of the 3 supported data types.
*
* \par Reset Functions
* There is also an associated reset function for each data type which clears the state array.
*
* \par Initialization Functions
* There is also an associated initialization function for each data type.
* The initialization function performs the following operations:
* - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
* - Zeros out the values in the state buffer.
*
* \par
* Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
*
* \par Fixed-Point Behavior
* Care must be taken when using the fixed-point versions of the PID Controller functions.
* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup PID
* @{
*/
/**
* @brief Process function for the floating-point PID Control.
* @param[in,out] S is an instance of the floating-point PID Control structure
* @param[in] in input sample to process
* @return out processed output sample.
*/
__ALWAYS_STATIC_INLINE float32_t csky_pid_f32(
csky_pid_instance_f32 * S,
float32_t in)
{
float32_t out;
/* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
out = (S->A0 * in) +
(S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
/* Update state */
S->state[1] = S->state[0];
S->state[0] = in;
S->state[2] = out;
/* return to application */
return (out);
}
/**
* @}
*/ // end of PID group
/**
* @addtogroup PID
* @{
*/
/**
* @brief Process function for the Q31 PID Control.
* @param[in,out] S points to an instance of the Q31 PID Control structure
* @param[in] in input sample to process
* @return out processed output sample.
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is implemented using an internal 64-bit accumulator.
* The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
* Thus, if the accumulator result overflows it wraps around rather than clip.
* In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
* After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
*/
__ALWAYS_STATIC_INLINE q31_t csky_pid_q31(
csky_pid_instance_q31 * S,
q31_t in)
{
q63_t acc;
q31_t out;
#ifdef CSKY_SIMD
/* acc = A0 * x[n] */
acc = mult_32x32_keep64(S->A0, in);
/* acc += A1 * x[n-1] */
acc = multAcc_32x32_keep64(acc, S->A1, S->state[0]);
/* acc += A2 * x[n-2] */
acc = multAcc_32x32_keep64(acc, S->A2, S->state[1]);
/* convert output to 1.31 format to add y[n-1] */
out = dext_31(acc);
#else
/* acc = A0 * x[n] */
acc = (q63_t) S->A0 * in;
/* acc += A1 * x[n-1] */
acc += (q63_t) S->A1 * S->state[0];
/* acc += A2 * x[n-2] */
acc += (q63_t) S->A2 * S->state[1];
/* convert output to 1.31 format to add y[n-1] */
out = (q31_t) (acc >> 31u);
#endif
/* out += y[n-1] */
out += S->state[2];
/* Update state */
S->state[1] = S->state[0];
S->state[0] = in;
S->state[2] = out;
/* return to application */
return (out);
}
/**
* @}
*/ // end of PID group
/**
* @addtogroup PID
* @{
*/
/**
* @brief Process function for the Q15 PID Control.
* @param[in,out] S points to an instance of the Q15 PID Control structure
* @param[in] in input sample to process
* @return out processed output sample.
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is implemented using a 64-bit internal accumulator.
* Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
* The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
* There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
* After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
* Lastly, the accumulator is saturated to yield a result in 1.15 format.
*/
__ALWAYS_STATIC_INLINE q15_t csky_pid_q15(
csky_pid_instance_q15 * S,
q15_t in)
{
q63_t acc;
q15_t out;
/* acc = A0 * x[n] */
acc = ((q31_t) S->A0) * in;
/* acc += A1 * x[n-1] + A2 * x[n-2] */
acc += (q31_t) S->A1 * S->state[0];
acc += (q31_t) S->A2 * S->state[1];
/* acc += y[n-1] */
acc += (q31_t) S->state[2] << 15;
/* saturate the output */
out = (q15_t) (__SSAT_16((acc >> 15)));
/* Update state */
S->state[1] = S->state[0];
S->state[0] = in;
S->state[2] = out;
/* return to application */
return (out);
}
/**
* @}
*/ // end of PID group
csky_status csky_mat_inverse_f32(
const csky_matrix_instance_f32 * src,
csky_matrix_instance_f32 * dst);
csky_status csky_mat_inverse_f64(
const csky_matrix_instance_f64 * src,
csky_matrix_instance_f64 * dst);
/**
* @ingroup groupController
*/
/**
* @defgroup clarke Vector Clarke Transform
* Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
* Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
* in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
* When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
* \image html clarke.gif Stator current space vector and its components in (a,b).
* and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
* can be calculated using only <code>Ia</code> and <code>Ib</code>.
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html clarkeFormula.gif
* where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
* <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Clarke transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup clarke
* @{
*/
/**
*
* @brief Floating-point Clarke transform
* @param[in] Ia input three-phase coordinate a
* @param[in] Ib input three-phase coordinate b
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
*/
__ALWAYS_STATIC_INLINE void csky_clarke_f32(
float32_t Ia,
float32_t Ib,
float32_t * pIalpha,
float32_t * pIbeta)
{
/* Calculate pIalpha using the equation, pIalpha = Ia */
*pIalpha = Ia;
/* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
*pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
}
/**
* @}
*/ // end of clarke group
/**
* @addtogroup clarke
* @{
*/
/**
* @brief Clarke transform for Q31 version
* @param[in] Ia input three-phase coordinate a
* @param[in] Ib input three-phase coordinate b
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the addition, hence there is no risk of overflow.
*/
__ALWAYS_STATIC_INLINE void csky_clarke_q31(
q31_t Ia,
q31_t Ib,
q31_t * pIalpha,
q31_t * pIbeta)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
/* Calculating pIalpha from Ia by equation pIalpha = Ia */
*pIalpha = Ia;
#ifdef CSKY_SIMD
/* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
product1 = mult_32x32_dext_30(Ia, 0x24F34E8B);
/* Intermediate product is calculated by (2/sqrt(3) * Ib) */
product2 = mult_32x32_dext_30(Ib, 0x49E69D16);
#else
/* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
/* Intermediate product is calculated by (2/sqrt(3) * Ib) */
product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
#endif
/* pIbeta is calculated by adding the intermediate products */
*pIbeta = __QADD(product1, product2);
}
/**
* @}
*/ // end of clarke group
void csky_q7_to_q31(
q7_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupController
*/
/**
* @defgroup inv_clarke Vector Inverse Clarke Transform
* Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html clarkeInvFormula.gif
* where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
* <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Clarke transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup inv_clarke
* @{
*/
/**
* @brief Floating-point Inverse Clarke transform
* @param[in] Ialpha input two-phase orthogonal vector axis alpha
* @param[in] Ibeta input two-phase orthogonal vector axis beta
* @param[out] pIa points to output three-phase coordinate <code>a</code>
* @param[out] pIb points to output three-phase coordinate <code>b</code>
*/
__ALWAYS_STATIC_INLINE void csky_inv_clarke_f32(
float32_t Ialpha,
float32_t Ibeta,
float32_t * pIa,
float32_t * pIb)
{
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
*pIa = Ialpha;
/* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
*pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
}
/**
* @}
*/ // end of inv_clarke group
/**
* @addtogroup inv_clarke
* @{
*/
/**
* @brief Inverse Clarke transform for Q31 version
* @param[in] Ialpha input two-phase orthogonal vector axis alpha
* @param[in] Ibeta input two-phase orthogonal vector axis beta
* @param[out] pIa points to output three-phase coordinate <code>a</code>
* @param[out] pIb points to output three-phase coordinate <code>b</code>
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the subtraction, hence there is no risk of overflow.
*/
__ALWAYS_STATIC_INLINE void csky_inv_clarke_q31(
q31_t Ialpha,
q31_t Ibeta,
q31_t * pIa,
q31_t * pIb)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
*pIa = Ialpha;
#ifdef CSKY_SIMD
/* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
product1 = mult_32x32_dext_31(Ialpha, 0x40000000);
/* Intermediate product is calculated by (1/sqrt(3) * pIb) */
product2 = mult_32x32_dext_31(Ibeta, 0x6ED9EBA1);
#else
/* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
/* Intermediate product is calculated by (1/sqrt(3) * pIb) */
product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
#endif
/* pIb is calculated by subtracting the products */
*pIb = __QSUB(product2, product1);
}
/**
* @}
*/ // end of inv_clarke group
void csky_q7_to_q15(
q7_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupController
*/
/**
* @defgroup park Vector Park Transform
*
* Forward Park transform converts the input two-coordinate vector to flux and torque components.
* The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
* from the stationary to the moving reference frame and control the spatial relationship between
* the stator vector current and rotor flux vector.
* If we consider the d axis aligned with the rotor flux, the diagram below shows the
* current vector and the relationship from the two reference frames:
* \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html parkFormula.gif
* where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
* <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
* cosine and sine values of theta (rotor flux position).
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Park transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup park
* @{
*/
/**
* @brief Floating-point Park transform
* @param[in] Ialpha input two-phase vector coordinate alpha
* @param[in] Ibeta input two-phase vector coordinate beta
* @param[out] pId points to output rotor reference frame d
* @param[out] pIq points to output rotor reference frame q
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*
* The function implements the forward Park transform.
*
*/
__ALWAYS_STATIC_INLINE void csky_park_f32(
float32_t Ialpha,
float32_t Ibeta,
float32_t * pId,
float32_t * pIq,
float32_t sinVal,
float32_t cosVal)
{
/* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
*pId = Ialpha * cosVal + Ibeta * sinVal;
/* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
*pIq = -Ialpha * sinVal + Ibeta * cosVal;
}
/**
* @}
*/ // end of park group
/**
* @addtogroup park
* @{
*/
/**
* @brief Park transform for Q31 version
* @param[in] Ialpha input two-phase vector coordinate alpha
* @param[in] Ibeta input two-phase vector coordinate beta
* @param[out] pId points to output rotor reference frame d
* @param[out] pIq points to output rotor reference frame q
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the addition and subtraction, hence there is no risk of overflow.
*/
__ALWAYS_STATIC_INLINE void csky_park_q31(
q31_t Ialpha,
q31_t Ibeta,
q31_t * pId,
q31_t * pIq,
q31_t sinVal,
q31_t cosVal)
{
#ifdef CSKY_SIMD
__ASM volatile(
"rmul.s32.h t0, %0, %3\n\t"
"rmul.s32.h t1, %1, %2\n\t"
"add.s32.s t0, t0, t1\n\t"
"st.w t0, (%4, 0x0)\n\t"
"rmul.s32.h t0, %0, %2\n\t"
"rmul.s32.h t1, %1, %3\n\t"
"sub.s32.s t1, t1, t0\n\t"
"st.w t1, (%5, 0x0)\n\t"
::"r"(Ialpha),"r"(Ibeta),"r"(sinVal),"r"(cosVal),"r"(pId),"r"(pIq)
:"t0","t1", "memory");
#else
q31_t product1, product2; /* Temporary variables used to store intermediate results */
q31_t product3, product4; /* Temporary variables used to store intermediate results */
/* Intermediate product is calculated by (Ialpha * cosVal) */
product1 = clip_q63_to_q31 (((q63_t) (Ialpha) * (cosVal)) >> 31);
/* Intermediate product is calculated by (Ibeta * sinVal) */
product2 = clip_q63_to_q31 (((q63_t) (Ibeta) * (sinVal)) >> 31);
/* Intermediate product is calculated by (Ialpha * sinVal) */
product3 = clip_q63_to_q31 (((q63_t) (Ialpha) * (sinVal)) >> 31);
/* Intermediate product is calculated by (Ibeta * cosVal) */
product4 = clip_q63_to_q31 (((q63_t) (Ibeta) * (cosVal)) >> 31);
/* Calculate pId by adding the two intermediate products 1 and 2 */
*pId = __QADD(product1, product2);
/* Calculate pIq by subtracting the two intermediate products 3 from 4 */
*pIq = __QSUB(product4, product3);
#endif
}
/**
* @}
*/ // end of park group
void csky_q7_to_float(
q7_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupController
*/
/**
* @defgroup inv_park Vector Inverse Park transform
* Inverse Park transform converts the input flux and torque components to two-coordinate vector.
*
* The function operates on a single sample of data and each call to the function returns the processed output.
* The library provides separate functions for Q31 and floating-point data types.
* \par Algorithm
* \image html parkInvFormula.gif
* where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
* <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
* cosine and sine values of theta (rotor flux position).
* \par Fixed-Point Behavior
* Care must be taken when using the Q31 version of the Park transform.
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
* Refer to the function specific documentation below for usage guidelines.
*/
/**
* @addtogroup inv_park
* @{
*/
/**
* @brief Floating-point Inverse Park transform
* @param[in] Id input coordinate of rotor reference frame d
* @param[in] Iq input coordinate of rotor reference frame q
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*/
__ALWAYS_STATIC_INLINE void csky_inv_park_f32(
float32_t Id,
float32_t Iq,
float32_t * pIalpha,
float32_t * pIbeta,
float32_t sinVal,
float32_t cosVal)
{
/* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
*pIalpha = Id * cosVal - Iq * sinVal;
/* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
*pIbeta = Id * sinVal + Iq * cosVal;
}
/**
* @}
*/ // end of inv_park group
/**
* @addtogroup inv_park
* @{
*/
/**
* @brief Inverse Park transform for Q31 version
* @param[in] Id input coordinate of rotor reference frame d
* @param[in] Iq input coordinate of rotor reference frame q
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is implemented using an internal 32-bit accumulator.
* The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
* There is saturation on the addition, hence there is no risk of overflow.
*/
__ALWAYS_STATIC_INLINE void csky_inv_park_q31(
q31_t Id,
q31_t Iq,
q31_t * pIalpha,
q31_t * pIbeta,
q31_t sinVal,
q31_t cosVal)
{
#ifdef CSKY_SIMD
__ASM volatile(
"rmul.s32.h t0, %0, %3\n\t"
"rmul.s32.h t1, %1, %2\n\t"
"sub.s32.s t0, t0, t1\n\t"
"st.w t0, (%4, 0x0)\n\t"
"rmul.s32.h t0, %0, %2\n\t"
"rmul.s32.h t1, %1, %3\n\t"
"add.s32.s t0, t0, t1\n\t"
"st.w t0, (%5, 0x0)\n\t"
::"r"(Id),"r"(Iq),"r"(sinVal),"r"(cosVal),"r"(pIalpha),"r"(pIbeta)
:"t0","t1", "memory");
#else
q31_t product1, product2; /* Temporary variables used to store intermediate results */
q31_t product3, product4; /* Temporary variables used to store intermediate results */
/* Intermediate product is calculated by (Id * cosVal) */
product1 = clip_q63_to_q31 (((q63_t) (Id) * (cosVal)) >> 31);
/* Intermediate product is calculated by (Iq * sinVal) */
product2 = clip_q63_to_q31 (((q63_t) (Iq) * (sinVal)) >> 31);
/* Intermediate product is calculated by (Id * sinVal) */
product3 = clip_q63_to_q31 (((q63_t) (Id) * (sinVal)) >> 31);
/* Intermediate product is calculated by (Iq * cosVal) */
product4 = clip_q63_to_q31 (((q63_t) (Iq) * (cosVal)) >> 31);
/* Calculate pIalpha by using the two intermediate products 1 and 2 */
*pIalpha = __QSUB(product1, product2);
/* Calculate pIbeta by using the two intermediate products 3 and 4 */
*pIbeta = __QADD(product4, product3);
#endif
}
/**
* @}
*/ // end of inv_park group
void csky_q31_to_float(
q31_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupInterpolation
*/
/**
* @defgroup LinearInterpolate Linear Interpolation
*
* Linear interpolation is a method of curve fitting using linear polynomials.
* Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
*
* \par
* \image html LinearInterp.gif "Linear interpolation"
*
* \par
* A Linear Interpolate function calculates an output value(y), for the input(x)
* using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
*
* \par Algorithm:
* <pre>
* y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
* where x0, x1 are nearest values of input x
* y0, y1 are nearest values to output y
* </pre>
*
* \par
* This set of functions implements Linear interpolation process
* for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
* sample of data and each call to the function returns a single processed value.
* <code>S</code> points to an instance of the Linear Interpolate function data structure.
* <code>x</code> is the input sample value. The functions returns the output value.
*
* \par
* if x is outside of the table boundary, Linear interpolation returns first value of the table
* if x is below input range and returns last value of table if x is above range.
*/
/**
* @addtogroup LinearInterpolate
* @{
*/
/**
* @brief Process function for the floating-point Linear Interpolation Function.
* @param[in,out] S is an instance of the floating-point Linear Interpolation structure
* @param[in] x input sample to process
* @return y processed output sample.
*
*/
__ALWAYS_STATIC_INLINE float32_t csky_linear_interp_f32(
csky_linear_interp_instance_f32 * S,
float32_t x)
{
float32_t y;
float32_t x0, x1; /* Nearest input values */
float32_t y0, y1; /* Nearest output values */
float32_t xSpacing = S->xSpacing; /* spacing between input values */
int32_t i; /* Index variable */
float32_t *pYData = S->pYData; /* pointer to output table */
/* Calculation of index */
i = (int32_t) ((x - S->x1) / xSpacing);
if(i < 0)
{
/* Iniatilize output for below specified range as least output value of table */
y = pYData[0];
}
else if((uint32_t)i >= S->nValues)
{
/* Iniatilize output for above specified range as last output value of table */
y = pYData[S->nValues - 1];
}
else
{
/* Calculation of nearest input values */
x0 = S->x1 + i * xSpacing;
x1 = S->x1 + (i + 1) * xSpacing;
/* Read of nearest output values */
y0 = pYData[i];
y1 = pYData[i + 1];
/* Calculation of output */
y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
}
/* returns output value */
return (y);
}
/**
* @}
*/ // end of LinearInterpolate group
/**
* @addtogroup LinearInterpolate
* @{
*/
/**
* @brief Process function for the Q31 Linear Interpolation Function.
* @param[in] pYData pointer to Q31 Linear Interpolation table
* @param[in] x input sample to process
* @param[in] nValues number of table values
* @return y processed output sample.
*
* \par
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
* This function can support maximum of table size 2^12.
*
*/
__ALWAYS_STATIC_INLINE q31_t csky_linear_interp_q31(
q31_t * pYData,
q31_t x,
uint32_t nValues)
{
q31_t y; /* output */
q31_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
int32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
index = ((x & (q31_t)0xFFF00000) >> 20);
if(index >= (int32_t)(nValues - 1))
{
return (pYData[nValues - 1]);
}
else if(index < 0)
{
return (pYData[0]);
}
else
{
/* 20 bits for the fractional part */
/* shift left by 11 to keep fract in 1.31 format */
fract = (x & 0x000FFFFF) << 11;
/* Read two nearest output values from the index in 1.31(q31) format */
y0 = pYData[index];
y1 = pYData[index + 1];
#ifdef CSKY_SIMD
/* Calculation of y0 * (1-fract) and y is in 2.30 format */
y = mult_32x32_keep32(y0, (0x7FFFFFFF - fract));
/* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
y = multAcc_32x32_keep32(y, y1, fract);
#else
/* Calculation of y0 * (1-fract) and y is in 2.30 format */
y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
/* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
y += ((q31_t) (((q63_t) y1 * fract) >> 32));
#endif
/* Convert y to 1.31 format */
return (y << 1u);
}
}
/**
* @}
*/ // end of LinearInterpolate group
/**
* @addtogroup LinearInterpolate
* @{
*/
/**
*
* @brief Process function for the Q15 Linear Interpolation Function.
* @param[in] pYData pointer to Q15 Linear Interpolation table
* @param[in] x input sample to process
* @param[in] nValues number of table values
* @return y processed output sample.
*
* \par
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
* This function can support maximum of table size 2^12.
*
*/
__ALWAYS_STATIC_INLINE q15_t csky_linear_interp_q15(
q15_t * pYData,
q31_t x,
uint32_t nValues)
{
q63_t y; /* output */
q15_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
int32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
index = ((x & (int32_t)0xFFF00000) >> 20);
if(index >= (int32_t)(nValues - 1))
{
return (pYData[nValues - 1]);
}
else if(index < 0)
{
return (pYData[0]);
}
else
{
/* 20 bits for the fractional part */
/* fract is in 12.20 format */
fract = (x & 0x000FFFFF);
/* Read two nearest output values from the index */
y0 = pYData[index];
y1 = pYData[index + 1];
#ifdef CSKY_SIMD
/* Calculation of y0 * (1-fract) and y is in 13.35 format */
y = mult_32x32_keep64(y0, (0xFFFFF - fract));
/* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
y = multAcc_32x32_keep64(y, y1, (fract));
#else
/* Calculation of y0 * (1-fract) and y is in 13.35 format */
y = ((q63_t) y0 * (0xFFFFF - fract));
/* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
y += ((q63_t) y1 * (fract));
#endif
/* convert y to 1.15 format */
return (q15_t) (y >> 20);
}
}
/**
* @}
*/ // end of LinearInterpolate group
/**
* @addtogroup LinearInterpolate
* @{
*/
/**
*
* @brief Process function for the Q7 Linear Interpolation Function.
* @param[in] pYData pointer to Q7 Linear Interpolation table
* @param[in] x input sample to process
* @param[in] nValues number of table values
* @return y processed output sample.
*
* \par
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
* This function can support maximum of table size 2^12.
*/
__ALWAYS_STATIC_INLINE q7_t csky_linear_interp_q7(
q7_t * pYData,
q31_t x,
uint32_t nValues)
{
q31_t y; /* output */
q7_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
uint32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
if (x < 0)
{
return (pYData[0]);
}
index = (x >> 20) & 0xfff;
if(index >= (nValues - 1))
{
return (pYData[nValues - 1]);
}
else
{
/* 20 bits for the fractional part */
/* fract is in 12.20 format */
fract = (x & 0x000FFFFF);
/* Read two nearest output values from the index and are in 1.7(q7) format */
y0 = pYData[index];
y1 = pYData[index + 1];
/* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
y = ((y0 * (0xFFFFF - fract)));
/* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
y += (y1 * fract);
/* convert y to 1.7(q7) format */
return (q7_t) (y >> 20);
}
}
/**
* @}
*/ // end of LinearInterpolate group
float32_t csky_sin_f32(
float32_t x);
q31_t csky_sin_q31(
q31_t x);
q15_t csky_sin_q15(
q15_t x);
float32_t csky_cos_f32(
float32_t x);
q31_t csky_cos_q31(
q31_t x);
q15_t csky_cos_q15(
q15_t x);
csky_status csky_sqrt_f32(
float32_t in,
float32_t * pOut);
csky_status csky_sqrt_q31(
q31_t in,
q31_t * pOut);
csky_status csky_sqrt_q15(
q15_t in,
q15_t * pOut);
void csky_power_q31(
q31_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_power_int32(
int32_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_power_int32(
int32_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_power_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_power_q15(
q15_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_power_q7(
q7_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_mean_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * pResult);
void csky_mean_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_mean_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_mean_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_var_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_var_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_var_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_rms_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_rms_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_rms_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_std_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_std_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_std_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_cmplx_mag_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_cmplx_mag_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_cmplx_mag_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_cmplx_dot_prod_q15(
q15_t * pSrcA,
q15_t * pSrcB,
uint32_t numSamples,
q31_t * realResult,
q31_t * imagResult);
void csky_cmplx_dot_prod_q31(
q31_t * pSrcA,
q31_t * pSrcB,
uint32_t numSamples,
q63_t * realResult,
q63_t * imagResult);
void csky_cmplx_dot_prod_f32(
float32_t * pSrcA,
float32_t * pSrcB,
uint32_t numSamples,
float32_t * realResult,
float32_t * imagResult);
void csky_cmplx_mult_real_q15(
q15_t * pSrcCmplx,
q15_t * pSrcReal,
q15_t * pCmplxDst,
uint32_t numSamples);
void csky_cmplx_mult_real_q31(
q31_t * pSrcCmplx,
q31_t * pSrcReal,
q31_t * pCmplxDst,
uint32_t numSamples);
void csky_cmplx_mult_real_f32(
float32_t * pSrcCmplx,
float32_t * pSrcReal,
float32_t * pCmplxDst,
uint32_t numSamples);
void csky_min_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * result,
uint32_t * index);
void csky_min_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult,
uint32_t * pIndex);
void csky_min_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult,
uint32_t * pIndex);
void csky_min_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult,
uint32_t * pIndex);
void csky_max_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * pResult,
uint32_t * pIndex);
void csky_max_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult,
uint32_t * pIndex);
void csky_max_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult,
uint32_t * pIndex);
void csky_max_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult,
uint32_t * pIndex);
void csky_cmplx_mult_cmplx_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t numSamples);
void csky_cmplx_mult_cmplx_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t numSamples);
void csky_cmplx_mult_cmplx_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t numSamples);
void csky_cmplx_mult_cmplx_re_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t numSamples);
void csky_cmplx_mult_cmplx_re_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t numSamples);
void csky_cmplx_mult_cmplx_re_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t numSamples);
void csky_float_to_q31(
float32_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_float_to_q15(
float32_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_float_to_q7(
float32_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_q31_to_q15(
q31_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_q31_to_q7(
q31_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_q15_to_float(
q15_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_q15_to_q31(
q15_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_q15_to_q7(
q15_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
/**
* @ingroup groupInterpolation
*/
/**
* @defgroup BilinearInterpolate Bilinear Interpolation
*
* Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
* The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
* determines values between the grid points.
* Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
* Bilinear interpolation is often used in image processing to rescale images.
* The CSI DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
*
* <b>Algorithm</b>
* \par
* The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
* For floating-point, the instance structure is defined as:
* <pre>
* typedef struct
* {
* uint16_t numRows;
* uint16_t numCols;
* float32_t *pData;
* } csky_bilinear_interp_instance_f32;
* </pre>
*
* \par
* where <code>numRows</code> specifies the number of rows in the table;
* <code>numCols</code> specifies the number of columns in the table;
* and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
* The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
* That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
*
* \par
* Let <code>(x, y)</code> specify the desired interpolation point. Then define:
* <pre>
* XF = floor(x)
* YF = floor(y)
* </pre>
* \par
* The interpolated output point is computed as:
* <pre>
* f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
* + f(XF+1, YF) * (x-XF)*(1-(y-YF))
* + f(XF, YF+1) * (1-(x-XF))*(y-YF)
* + f(XF+1, YF+1) * (x-XF)*(y-YF)
* </pre>
* Note that the coordinates (x, y) contain integer and fractional components.
* The integer components specify which portion of the table to use while the
* fractional components control the interpolation processor.
*
* \par
* if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
*/
/**
* @addtogroup BilinearInterpolate
* @{
*/
/**
*
* @brief Floating-point bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate.
* @param[in] Y interpolation coordinate.
* @return out interpolated value.
*/
__ALWAYS_STATIC_INLINE float32_t csky_bilinear_interp_f32(
const csky_bilinear_interp_instance_f32 * S,
float32_t X,
float32_t Y)
{
float32_t out;
float32_t f00, f01, f10, f11;
float32_t *pData = S->pData;
int32_t xIndex, yIndex, index;
float32_t xdiff, ydiff;
float32_t b1, b2, b3, b4;
xIndex = (int32_t) X;
yIndex = (int32_t) Y;
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
{
return (0);
}
/* Calculation of index for two nearest points in X-direction */
index = (xIndex - 1) + (yIndex - 1) * S->numCols;
/* Read two nearest points in X-direction */
f00 = pData[index];
f01 = pData[index + 1];
/* Calculation of index for two nearest points in Y-direction */
index = (xIndex - 1) + (yIndex) * S->numCols;
/* Read two nearest points in Y-direction */
f10 = pData[index];
f11 = pData[index + 1];
/* Calculation of intermediate values */
b1 = f00;
b2 = f01 - f00;
b3 = f10 - f00;
b4 = f00 - f01 - f10 + f11;
/* Calculation of fractional part in X */
xdiff = X - xIndex;
/* Calculation of fractional part in Y */
ydiff = Y - yIndex;
/* Calculation of bi-linear interpolated output */
out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
/* return to application */
return (out);
}
/**
* @}
*/ // end of BilinearInterpolate group
/**
* @addtogroup BilinearInterpolate
* @{
*/
/**
*
* @brief Q31 bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate in 12.20 format.
* @param[in] Y interpolation coordinate in 12.20 format.
* @return out interpolated value.
*/
__ALWAYS_STATIC_INLINE q31_t csky_bilinear_interp_q31(
csky_bilinear_interp_instance_q31 * S,
q31_t X,
q31_t Y)
{
q31_t out; /* Temporary output */
q31_t acc = 0; /* output */
q31_t xfract, yfract; /* X, Y fractional parts */
q31_t x1, x2, y1, y2; /* Nearest output values */
int32_t rI, cI; /* Row and column indices */
q31_t *pYData = S->pData; /* pointer to output table values */
uint32_t nCols = S->numCols; /* num of rows */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
rI = ((X & (q31_t)0xFFF00000) >> 20);
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
cI = ((Y & (q31_t)0xFFF00000) >> 20);
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
{
return (0);
}
/* 20 bits for the fractional part */
/* shift left xfract by 11 to keep 1.31 format */
xfract = (X & 0x000FFFFF) << 11u;
/* Read two nearest output values from the index */
x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
/* 20 bits for the fractional part */
/* shift left yfract by 11 to keep 1.31 format */
yfract = (Y & 0x000FFFFF) << 11u;
/* Read two nearest output values from the index */
y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
#ifdef CSKY_SIMD
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
out = mult_32x32_keep32(x1, (0x7FFFFFFF - xfract));
acc = mult_32x32_keep32(out, (0x7FFFFFFF - yfract));
/* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
out = mult_32x32_keep32(x2, (0x7FFFFFFF - yfract));
acc = multAcc_32x32_keep32(acc, out, xfract);
/* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
out = mult_32x32_keep32(y1, (0x7FFFFFFF - xfract));
acc = multAcc_32x32_keep32(acc, out, yfract);
/* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
out = mult_32x32_keep32(y2, xfract);
acc = multAcc_32x32_keep32(acc, out, yfract);
#else
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
/* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
/* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
/* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
#endif
/* Convert acc to 1.31(q31) format */
return ((q31_t)(acc << 2));
}
/**
* @}
*/ // end of BilinearInterpolate group
/**
* @addtogroup BilinearInterpolate
* @{
*/
/**
* @brief Q15 bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate in 12.20 format.
* @param[in] Y interpolation coordinate in 12.20 format.
* @return out interpolated value.
*/
__ALWAYS_STATIC_INLINE q15_t csky_bilinear_interp_q15(
csky_bilinear_interp_instance_q15 * S,
q31_t X,
q31_t Y)
{
q63_t acc = 0; /* output */
q31_t out; /* Temporary output */
q15_t x1, x2, y1, y2; /* Nearest output values */
q31_t xfract, yfract; /* X, Y fractional parts */
int32_t rI, cI; /* Row and column indices */
q15_t *pYData = S->pData; /* pointer to output table values */
uint32_t nCols = S->numCols; /* num of rows */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
rI = ((X & (q31_t)0xFFF00000) >> 20);
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
cI = ((Y & (q31_t)0xFFF00000) >> 20);
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
{
return (0);
}
/* 20 bits for the fractional part */
/* xfract should be in 12.20 format */
xfract = (X & 0x000FFFFF);
/* Read two nearest output values from the index */
x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
/* 20 bits for the fractional part */
/* yfract should be in 12.20 format */
yfract = (Y & 0x000FFFFF);
/* Read two nearest output values from the index */
y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
/* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
/* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
#ifdef CSKY_SIMD
out = mult_32x32_dext_4(x1, (0xFFFFF - xfract));
acc = mult_32x32_keep64(out, (0xFFFFF - yfract));
/* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
out = mult_32x32_dext_4(x2, (0xFFFFF - yfract));
acc = multAcc_32x32_keep64(acc, out, (xfract));
/* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
out = mult_32x32_dext_4(y1, (0xFFFFF - xfract));
acc = multAcc_32x32_keep64(acc, out, (yfract));
/* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
out = mult_32x32_dext_4(y2, (xfract));
acc = multAcc_32x32_keep64(acc, out, (yfract));
#else
out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
acc = ((q63_t) out * (0xFFFFF - yfract));
/* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
acc += ((q63_t) out * (xfract));
/* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
acc += ((q63_t) out * (yfract));
/* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
acc += ((q63_t) out * (yfract));
#endif
/* acc is in 13.51 format and down shift acc by 36 times */
/* Convert out to 1.15 format */
return ((q15_t)(acc >> 36));
}
/**
* @}
*/ // end of BilinearInterpolate group
/**
* @addtogroup BilinearInterpolate
* @{
*/
/**
* @brief Q7 bilinear interpolation.
* @param[in,out] S points to an instance of the interpolation structure.
* @param[in] X interpolation coordinate in 12.20 format.
* @param[in] Y interpolation coordinate in 12.20 format.
* @return out interpolated value.
*/
__ALWAYS_STATIC_INLINE q7_t csky_bilinear_interp_q7(
csky_bilinear_interp_instance_q7 * S,
q31_t X,
q31_t Y)
{
q63_t acc = 0; /* output */
q31_t out; /* Temporary output */
q31_t xfract, yfract; /* X, Y fractional parts */
q7_t x1, x2, y1, y2; /* Nearest output values */
int32_t rI, cI; /* Row and column indices */
q7_t *pYData = S->pData; /* pointer to output table values */
uint32_t nCols = S->numCols; /* num of rows */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
rI = ((X & (q31_t)0xFFF00000) >> 20);
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
cI = ((Y & (q31_t)0xFFF00000) >> 20);
/* Care taken for table outside boundary */
/* Returns zero output when values are outside table boundary */
if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
{
return (0);
}
/* 20 bits for the fractional part */
/* xfract should be in 12.20 format */
xfract = (X & (q31_t)0x000FFFFF);
/* Read two nearest output values from the index */
x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
/* 20 bits for the fractional part */
/* yfract should be in 12.20 format */
yfract = (Y & (q31_t)0x000FFFFF);
/* Read two nearest output values from the index */
y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
/* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
out = ((x1 * (0xFFFFF - xfract)));
#ifdef CSKY_SIMD
acc = multAcc_32x32_keep64(acc, out, (0xFFFFF - yfract));
/* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
out = ((x2 * (0xFFFFF - yfract)));
acc = multAcc_32x32_keep64(acc, out, xfract);
/* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
out = ((y1 * (0xFFFFF - xfract)));
acc = multAcc_32x32_keep64(acc, out, yfract);
/* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
out = ((y2 * (yfract)));
acc = multAcc_32x32_keep64(acc, out, xfract);
#else
acc = (((q63_t) out * (0xFFFFF - yfract)));
/* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
out = ((x2 * (0xFFFFF - yfract)));
acc += (((q63_t) out * (xfract)));
/* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
out = ((y1 * (0xFFFFF - xfract)));
acc += (((q63_t) out * (yfract)));
/* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
out = ((y2 * (yfract)));
acc += (((q63_t) out * (xfract)));
#endif
/* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
return ((q7_t)(acc >> 40));
}
/**
* @}
*/ // end of BilinearInterpolate group
/**
* @ingroup groupMath
*/
/**
* @defgroup ShiftRight Right Shift
*
* Shift the input value to right with appointed bits, its basic format is:
* <pre>
* a = (a) >> (shift), 1 =< shift <= bitof(a) - 1.
* </pre>
* The basic format is only designed for q31.
*
* and the extended format should be rounding to +inf:
* <pre>
* a = (a + (1<<(shift - 1)) >> (shift), 1 =< shift <= bitof(a) - 1.
* </pre>
*
* which are designed for q31, q31 positive and q63.
*/
/**
* @addtogroup ShiftRight
* @{
*/
/**
* @brief right shift Q31 version
* @param[in] a input value to be shift.
* @param[in] shift input positive value, the number of bits to be shift.
* @param[out] result the shifted a.
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is only used for right shift. So, the value of shift is
* between[1,31].
*/
__ALWAYS_STATIC_INLINE q31_t csky_shr_q31(
q31_t a,
q31_t shift)
{
q31_t res;
#ifdef CSKY_SIMD
__ASM volatile(
"asr %0, %1, %2\n\t"
:"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift));
#else
res = ((a) >> (shift));
#endif
return res;
}
#define SHR(a, shift) csky_shr_q31(a, shift)
/**
* @}
*/ // end of ShiftRight group
/**
* @addtogroup ShiftRight
* @{
*/
/**
* @brief right shift Q31 version
* @param[in] a input value to be shift.
* @param[in] shift input positive value, the number of bits to be shift.
* @param[out] result the shifted a.
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is only used for right shift. So, the value of shift is
* between[1,31]. And the output value is rounding to +inf.
*/
__ALWAYS_STATIC_INLINE q31_t csky_pshr_q31(
q31_t a,
q31_t shift)
{
q31_t res;
#ifdef CSKY_SIMD
__ASM volatile(
"asr.s32.r %0, %1, %2\n\t"
:"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift));
#else
res = (a >= 0?(SHR((a) + (1<<(shift - 1)), shift))\
:(SHR((a) + ((1<<shift)>>1) -1, shift)));
#endif
return res;
}
/**
* @}
*/ // end of ShiftRight group
/**
* @addtogroup ShiftRight
* @{
*/
/**
* @brief right shift Q31 version
* @param[in] a input positive value to be shift.
* @param[in] shift input positive value, the number of bits to be shift.
* @param[out] result the shifted a.
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is only used for right shift. So, the value of shift is
* between[1,31]. And the output value is rounding to +inf.
*/
__ALWAYS_STATIC_INLINE q31_t csky_pshr_pos_q31(
q31_t a,
q31_t shift)
{
q31_t res;
#ifdef CSKY_SIMD
__ASM volatile(
"asr.s32.r %0, %1, %2\n\t"
:"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift));
#else
res = SHR((a) + (1<<(shift - 1)), shift);
#endif
return res;
}
/**
* @}
*/ // end of ShiftRight group
/**
* @addtogroup ShiftRight
* @{
*/
/**
* @brief right shift Q63 version
* @param[in] a input value to be shift.
* @param[in] shift input positive value, the number of bits to be shift.
* @param[out] result the shifted a.
*
* <b>Scaling and Overflow Behavior:</b>
* \par
* The function is only used for right shift. So, the value of shift is
* between[1,63]. And the output value is rounding to +inf.
*/
__ALWAYS_STATIC_INLINE q63_t csky_pshr_q63(
q63_t a,
q31_t shift)
{
q63_t res;
#ifdef CSKY_SIMD
__ASM volatile(
"subi t0, %2, 1\n\t"
"cmphsi t0, 32\n\t"
"bt 1f\n\t"
"movi t1, 1\n\t"
"lsl t0, t1, t0\n\t"
"movi t1, 0\n\t"
"add.s64.s %1, %1, t0\n\t"
"dext %0, %1, %R1, %2\n\t"
"asr %R0, %R1, %2\n\t"
"br 2f\n\t"
"1:\n\t"
"subi %2, %2, 32\n\t"
"subi t0, t0, 32\n\t"
"movi t1, 1\n\t"
"lsl t1, t1, t0\n\t"
"add.s32.s %R1, %R1, t1\n\t"
"asr %0, %R1, %2\n\t"
"asri %R0, %R1, 31\n\t"
"2:\n\t"
:"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift):"t0", "t1");
#else
res = (a >= 0?(SHR((a) + ((q63_t)1<<(shift - 1)), shift))\
:(SHR((a) + (((q63_t)1<<shift)>>1) -1, shift)));
#endif
return res;
}
/**
* @}
*/ // end of ShiftRight group
//#define SHR(a, shift) csky_shr_q31(a, shift)
#define PSHR(a, shift) csky_pshr_q31(a, shift)
#define PSHR_POSITIVE(a, shift) csky_pshr_pos_q31(a, shift)
#define PSHR64(a, shift) csky_pshr_q63(a, shift)
#ifdef CSKY_SIMD
#else
/* SMMLAR */
#define multAcc_32x32_keep32_R(a, x, y) \
a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
/* SMMLSR */
#define multSub_32x32_keep32_R(a, x, y) \
a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
/* SMMULR */
#define mult_32x32_keep32_R(a, x, y) \
a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
/* SMMLA */
#define multAcc_32x32_keep32(a, x, y) \
a += (q31_t) (((q63_t) x * y) >> 32)
/* SMMLS */
#define multSub_32x32_keep32(a, x, y) \
a -= (q31_t) (((q63_t) x * y) >> 32)
/* SMMUL */
#define mult_32x32_keep32(a, x, y) \
a = (q31_t) (((q63_t) x * y ) >> 32)
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CSKY_MATH_H */
/**
*
* End of file.
*/
| YifuLiu/AliOS-Things | components/csi/csi2/dsp/include/csky_math.h | C | apache-2.0 | 140,634 |
/******************************************************************************
* @file csky_vdsp2_const_structs.h
* @brief This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the csky_vdsp2_cfft_f32() function.
* @version V1.0
* @date 20. Dec 2016
******************************************************************************/
/* ---------------------------------------------------------------------------
* Copyright (C) 2016 CSKY Limited. All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the following
* conditions are met:
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* * Neither the name of CSKY Ltd. nor the names of CSKY's contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission of CSKY Ltd.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */
#ifndef _CSKY_CONST_STRUCTS_H
#define _CSKY_CONST_STRUCTS_H
#include "csky_vdsp2_math.h"
#include "csky_common_tables.h"
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len16;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len32;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len64;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len128;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len256;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len512;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len1024;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len2048;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len4096;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len16;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len32;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len64;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len128;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len256;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len512;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len1024;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len2048;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len4096;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len16;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len32;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len64;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len128;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len256;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len512;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len1024;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len2048;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len4096;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len16;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len32;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len64;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len128;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len256;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len512;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len1024;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len2048;
extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len4096;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len16;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len32;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len64;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len128;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len256;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len512;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len1024;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len2048;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len4096;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len16;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len32;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len64;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len128;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len256;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len512;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len1024;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len2048;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len4096;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len16;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len32;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len64;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len128;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len256;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len512;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len1024;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len2048;
extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len4096;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len16;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len32;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len64;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len128;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len256;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len512;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len1024;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len2048;
extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len4096;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len32;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len64;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len128;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len256;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len512;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len1024;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len2048;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len4096;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len8192;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len32;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len64;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len128;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len256;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len512;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len1024;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len2048;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len4096;
extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len8192;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len32;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len64;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len128;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len256;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len512;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len1024;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len2048;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len4096;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len8192;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len32;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len64;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len128;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len256;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len512;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len1024;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len2048;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len4096;
extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len8192;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len32;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len64;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len128;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len256;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len512;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len1024;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len2048;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len4096;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len8192;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len32;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len64;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len128;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len256;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len512;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len1024;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len2048;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len4096;
extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len8192;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len32;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len64;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len128;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len256;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len512;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len1024;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len2048;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len4096;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len8192;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len32;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len64;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len128;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len256;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len512;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len1024;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len2048;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len4096;
extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len8192;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len32;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len64;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len128;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len256;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len512;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len1024;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len2048;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len4096;
extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len8192;
extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len128;
extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len512;
extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len2048;
extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len8192;
extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len128;
extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len512;
extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len2048;
extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len8192;
extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len128;
extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len512;
extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len2048;
extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len8192;
extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len128;
extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len512;
extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len2048;
extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len8192;
extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len128;
extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len512;
extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len2048;
extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len8192;
#endif
| YifuLiu/AliOS-Things | components/csi/csi2/dsp/include/csky_vdsp2_const_structs.h | C | apache-2.0 | 15,877 |
/******************************************************************************
* @file csky_vdsp2_math.h
* @brief Public header file for CSI DSP Library.
* @version V1.0
* @date 20. Dec 2016
******************************************************************************/
/* ---------------------------------------------------------------------------
* Copyright (C) 2016 CSKY Limited. All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the following
* conditions are met:
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* * Neither the name of CSKY Ltd. nor the names of CSKY's contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission of CSKY Ltd.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */
#ifndef _CSKY_VDSP2_MATH_H
#define _CSKY_VDSP2_MATH_H
#include <stdint.h>
#include <string.h>
#ifdef CSKY_VDSP2_MATH_DSP
#include "csi_core.h"
#endif
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief 8-bit fractional data type in 1.7 format.
*/
typedef int8_t q7_t;
/**
* @brief 16-bit fractional data type in 1.15 format.
*/
typedef int16_t q15_t;
/**
* @brief 32-bit fractional data type in 1.31 format.
*/
typedef int32_t q31_t;
/**
* @brief 64-bit fractional data type in 1.63 format.
*/
typedef int64_t q63_t;
/**
* @brief 32-bit floating-point type definition.
*/
typedef float float32_t;
/**
* @brief Error status returned by some functions in the library.
*/
typedef enum
{
CSKY_VDSP2_MATH_SUCCESS = 0, /**< No error */
CSKY_VDSP2_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
CSKY_VDSP2_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
CSKY_VDSP2_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
CSKY_VDSP2_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
CSKY_VDSP2_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
CSKY_VDSP2_MATH_TEST_FAILURE = -6 /**< Test Failed */
} csky_vdsp2_status;
/**
* @brief Instance structure for the Q7 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
} csky_vdsp2_fir_instance_q7;
/**
* @brief Instance structure for the Q15 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
} csky_vdsp2_fir_instance_q15;
/**
* @brief Instance structure for the Q31 FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
} csky_vdsp2_fir_instance_q31;
/**
* @brief Instance structure for the floating-point FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of filter coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
} csky_vdsp2_fir_instance_f32;
void csky_vdsp2_fir_q7(
const csky_vdsp2_fir_instance_q7 * S,
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_init_q7(
csky_vdsp2_fir_instance_q7 * S,
uint16_t numTaps,
q7_t * pCoeffs,
q7_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_q15(
const csky_vdsp2_fir_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_fast_q15(
const csky_vdsp2_fir_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_init_q15(
csky_vdsp2_fir_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_q31(
const csky_vdsp2_fir_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_fast_q31(
const csky_vdsp2_fir_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_init_q31(
csky_vdsp2_fir_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_f32(
const csky_vdsp2_fir_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_init_f32(
csky_vdsp2_fir_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 Biquad cascade filter.
*/
typedef struct
{
int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
} csky_vdsp2_biquad_casd_df1_inst_q15;
/**
* @brief Instance structure for the Q31 Biquad cascade filter.
*/
typedef struct
{
uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
} csky_vdsp2_biquad_casd_df1_inst_q31;
/**
* @brief Instance structure for the Q31 Biquad cascade filter.
*/
/**
* @brief Instance structure for the floating-point Biquad cascade filter.
*/
typedef struct
{
uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
} csky_vdsp2_biquad_casd_df1_inst_f32;
void csky_vdsp2_biquad_cascade_df1_q15(
const csky_vdsp2_biquad_casd_df1_inst_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_df1_init_q15(
csky_vdsp2_biquad_casd_df1_inst_q15 * S,
uint8_t numStages,
q15_t * pCoeffs,
q15_t * pState,
int8_t postShift);
void csky_vdsp2_biquad_cascade_df1_fast_q15(
const csky_vdsp2_biquad_casd_df1_inst_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_df1_q31(
const csky_vdsp2_biquad_casd_df1_inst_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_df1_fast_q31(
const csky_vdsp2_biquad_casd_df1_inst_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_df1_init_q31(
csky_vdsp2_biquad_casd_df1_inst_q31 * S,
uint8_t numStages,
q31_t * pCoeffs,
q31_t * pState,
int8_t postShift);
void csky_vdsp2_biquad_cascade_df1_f32(
const csky_vdsp2_biquad_casd_df1_inst_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_df1_init_f32(
csky_vdsp2_biquad_casd_df1_inst_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Instance structure for the floating-point matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
float32_t *pData; /**< points to the data of the matrix. */
} csky_vdsp2_matrix_instance_f32;
/**
* @brief Instance structure for the Q15 matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
q15_t *pData; /**< points to the data of the matrix. */
} csky_vdsp2_matrix_instance_q15;
/**
* @brief Instance structure for the Q31 matrix structure.
*/
typedef struct
{
uint16_t numRows; /**< number of rows of the matrix. */
uint16_t numCols; /**< number of columns of the matrix. */
q31_t *pData; /**< points to the data of the matrix. */
} csky_vdsp2_matrix_instance_q31;
csky_vdsp2_status csky_vdsp2_mat_add_f32(
const csky_vdsp2_matrix_instance_f32 * pSrcA,
const csky_vdsp2_matrix_instance_f32 * pSrcB,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_add_q15(
const csky_vdsp2_matrix_instance_q15 * pSrcA,
const csky_vdsp2_matrix_instance_q15 * pSrcB,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_add_q31(
const csky_vdsp2_matrix_instance_q31 * pSrcA,
const csky_vdsp2_matrix_instance_q31 * pSrcB,
csky_vdsp2_matrix_instance_q31 * pDst);
csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_f32(
const csky_vdsp2_matrix_instance_f32 * pSrcA,
const csky_vdsp2_matrix_instance_f32 * pSrcB,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_q15(
const csky_vdsp2_matrix_instance_q15 * pSrcA,
const csky_vdsp2_matrix_instance_q15 * pSrcB,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_q31(
const csky_vdsp2_matrix_instance_q31 * pSrcA,
const csky_vdsp2_matrix_instance_q31 * pSrcB,
csky_vdsp2_matrix_instance_q31 * pDst);
csky_vdsp2_status csky_vdsp2_mat_trans_f32(
const csky_vdsp2_matrix_instance_f32 * pSrc,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_trans_q15(
const csky_vdsp2_matrix_instance_q15 * pSrc,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_trans_q31(
const csky_vdsp2_matrix_instance_q31 * pSrc,
csky_vdsp2_matrix_instance_q31 * pDst);
csky_vdsp2_status csky_vdsp2_mat_mult_f32(
const csky_vdsp2_matrix_instance_f32 * pSrcA,
const csky_vdsp2_matrix_instance_f32 * pSrcB,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_mult_trans_f32(
const csky_vdsp2_matrix_instance_f32 * pSrcA,
const csky_vdsp2_matrix_instance_f32 * pSrcB,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_mult_q15(
const csky_vdsp2_matrix_instance_q15 * pSrcA,
const csky_vdsp2_matrix_instance_q15 * pSrcB,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_mult_trans_q15(
const csky_vdsp2_matrix_instance_q15 * pSrcA,
const csky_vdsp2_matrix_instance_q15 * pSrcB,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_mult_q31(
const csky_vdsp2_matrix_instance_q31 * pSrcA,
const csky_vdsp2_matrix_instance_q31 * pSrcB,
csky_vdsp2_matrix_instance_q31 * pDst);
csky_vdsp2_status csky_vdsp2_mat_mult_trans_q31(
const csky_vdsp2_matrix_instance_q31 * pSrcA,
const csky_vdsp2_matrix_instance_q31 * pSrcB,
csky_vdsp2_matrix_instance_q31 * pDst);
csky_vdsp2_status csky_vdsp2_mat_sub_f32(
const csky_vdsp2_matrix_instance_f32 * pSrcA,
const csky_vdsp2_matrix_instance_f32 * pSrcB,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_sub_q15(
const csky_vdsp2_matrix_instance_q15 * pSrcA,
const csky_vdsp2_matrix_instance_q15 * pSrcB,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_sub_q31(
const csky_vdsp2_matrix_instance_q31 * pSrcA,
const csky_vdsp2_matrix_instance_q31 * pSrcB,
csky_vdsp2_matrix_instance_q31 * pDst);
csky_vdsp2_status csky_vdsp2_mat_scale_f32(
const csky_vdsp2_matrix_instance_f32 * pSrc,
float32_t scale,
csky_vdsp2_matrix_instance_f32 * pDst);
csky_vdsp2_status csky_vdsp2_mat_scale_q15(
const csky_vdsp2_matrix_instance_q15 * pSrc,
q15_t scaleFract,
int32_t shift,
csky_vdsp2_matrix_instance_q15 * pDst);
csky_vdsp2_status csky_vdsp2_mat_scale_q31(
const csky_vdsp2_matrix_instance_q31 * pSrc,
q31_t scaleFract,
int32_t shift,
csky_vdsp2_matrix_instance_q31 * pDst);
void csky_vdsp2_mat_init_q31(
csky_vdsp2_matrix_instance_q31 * S,
uint16_t nRows,
uint16_t nColumns,
q31_t * pData);
void csky_vdsp2_mat_init_q15(
csky_vdsp2_matrix_instance_q15 * S,
uint16_t nRows,
uint16_t nColumns,
q15_t * pData);
void csky_vdsp2_mat_init_f32(
csky_vdsp2_matrix_instance_f32 * S,
uint16_t nRows,
uint16_t nColumns,
float32_t * pData);
void csky_vdsp2_mult_q15xq31_sht(
q15_t * pSrcA,
q31_t * pSrcB,
uint32_t shiftValue,
uint32_t blockSize);
void csky_vdsp2_mult_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_mult_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_mult_rnd_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_mult_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_mult_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_vdsp2_cfft_radix2_instance_q15;
/**
* @brief Instance structure for the Q15 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q15_t *pTwiddle; /**< points to the twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_vdsp2_cfft_radix4_instance_q15;
/**
* @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q31_t *pTwiddle; /**< points to the Twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_vdsp2_cfft_radix2_instance_q31;
/**
* @brief Instance structure for the Q31 CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
q31_t *pTwiddle; /**< points to the twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} csky_vdsp2_cfft_radix4_instance_q31;
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
float32_t *pTwiddle; /**< points to the Twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
float32_t onebyfftLen; /**< value of 1/fftLen. */
} csky_vdsp2_cfft_radix2_instance_f32;
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
float32_t *pTwiddle; /**< points to the Twiddle factor table. */
uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
float32_t onebyfftLen; /**< value of 1/fftLen. */
} csky_vdsp2_cfft_radix4_instance_f32;
/**
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t bitRevLength; /**< bit reversal table length. */
} csky_vdsp2_cfft_instance_q15;
void csky_vdsp2_cfft_q15(
const csky_vdsp2_cfft_instance_q15 * S,
q15_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
void csky_vdsp2_cfft_fast_q15(
const csky_vdsp2_cfft_instance_q15 * S,
q15_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the fixed-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t bitRevLength; /**< bit reversal table length. */
} csky_vdsp2_cfft_instance_q31;
void csky_vdsp2_cfft_q31(
const csky_vdsp2_cfft_instance_q31 * S,
q31_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
void csky_vdsp2_cfft_fast_q31(
const csky_vdsp2_cfft_instance_q31 * S,
q31_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
uint16_t fftLen; /**< length of the FFT. */
const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
uint16_t bitRevLength; /**< bit reversal table length. */
} csky_vdsp2_cfft_instance_f32;
void csky_vdsp2_cfft_f32(
const csky_vdsp2_cfft_instance_f32 * S,
float32_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
/**
* @brief Instance structure for the Q15 RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
const csky_vdsp2_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_rfft_instance_q15;
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
q15_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */
q15_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */
const csky_vdsp2_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_rfft_fast_instance_q15;
csky_vdsp2_status csky_vdsp2_rfft_init_q15(
csky_vdsp2_rfft_instance_q15 * S,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void csky_vdsp2_rfft_q15(
const csky_vdsp2_rfft_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst);
void csky_vdsp2_rfft_fast_q15(
const csky_vdsp2_rfft_fast_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst);
/**
* @brief Instance structure for the Q31 RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
const csky_vdsp2_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_rfft_instance_q31;
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
q31_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */
q31_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */
const csky_vdsp2_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_rfft_fast_instance_q31;
csky_vdsp2_status csky_vdsp2_rfft_init_q31(
csky_vdsp2_rfft_instance_q31 * S,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void csky_vdsp2_rfft_q31(
const csky_vdsp2_rfft_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst);
void csky_vdsp2_rfft_fast_q31(
const csky_vdsp2_rfft_fast_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst);
/**
* @brief Instance structure for the floating-point RFFT/RIFFT function.
*/
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
uint16_t fftLenBy2; /**< length of the complex FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
csky_vdsp2_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_rfft_instance_f32;
csky_vdsp2_status csky_vdsp2_rfft_init_f32(
csky_vdsp2_rfft_instance_f32 * S,
csky_vdsp2_cfft_radix4_instance_f32 * S_CFFT,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
void csky_vdsp2_cfft_radix4_f32(
const csky_vdsp2_cfft_instance_f32 * S,
float32_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag,
float32_t onebyfftLen);
void csky_vdsp2_cfft_fast_radix4_f32(
const csky_vdsp2_cfft_instance_f32 * S,
float32_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag,
float32_t onebyfftLen);
void csky_vdsp2_cfft_radix2_f32(
const csky_vdsp2_cfft_instance_f32 * S,
float32_t * p1,
uint8_t ifftFlag,
uint8_t bitReverseFlag,
float32_t onebyfftLen);
void csky_vdsp2_rfft_f32(
const csky_vdsp2_rfft_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst);
/**
* @brief Instance structure for the floating-point RFFT/RIFFT function.
*/
typedef struct
{
csky_vdsp2_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
uint16_t fftLenRFFT; /**< length of the real sequence */
float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
} csky_vdsp2_rfft_fast_instance_f32 ;
csky_vdsp2_status csky_vdsp2_rfft_fast_init_f32 (
csky_vdsp2_rfft_fast_instance_f32 * S,
uint16_t fftLen);
void csky_vdsp2_rfft_fast_f32(
csky_vdsp2_rfft_fast_instance_f32 * S,
float32_t * p, float32_t * pOut,
uint8_t ifftFlag);
/**
* @brief Instance structure for the floating-point DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
float32_t normalize; /**< normalizing factor. */
float32_t *pTwiddle; /**< points to the twiddle factor table. */
float32_t *pCosFactor; /**< points to the cosFactor table. */
csky_vdsp2_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT fast instance. */
csky_vdsp2_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_dct4_instance_f32;
csky_vdsp2_status csky_vdsp2_dct4_init_f32(
csky_vdsp2_dct4_instance_f32 * S,
csky_vdsp2_rfft_fast_instance_f32 * S_RFFT,
csky_vdsp2_cfft_radix4_instance_f32 * S_CFFT,
uint16_t N,
uint16_t Nby2,
float32_t normalize);
void csky_vdsp2_dct4_f32(
const csky_vdsp2_dct4_instance_f32 * S,
float32_t * pState,
float32_t * pInlineBuffer);
/**
* @brief Instance structure for the Q31 DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
q31_t normalize; /**< normalizing factor. */
q31_t *pTwiddle; /**< points to the twiddle factor table. */
q31_t *pCosFactor; /**< points to the cosFactor table. */
csky_vdsp2_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
csky_vdsp2_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_dct4_instance_q31;
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
q31_t normalize; /**< normalizing factor. */
q31_t *pTwiddle; /**< points to the twiddle factor table. */
q31_t *pCosFactor; /**< points to the cosFactor table. */
csky_vdsp2_rfft_fast_instance_q31 *pRfft; /**< points to the real FFT instance. */
csky_vdsp2_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_dct4_fast_instance_q31;
csky_vdsp2_status csky_vdsp2_dct4_init_q31(
csky_vdsp2_dct4_instance_q31 * S,
csky_vdsp2_rfft_instance_q31 * S_RFFT,
csky_vdsp2_cfft_radix4_instance_q31 * S_CFFT,
uint16_t N,
uint16_t Nby2,
q31_t normalize);
void csky_vdsp2_dct4_q31(
const csky_vdsp2_dct4_instance_q31 * S,
q31_t * pState,
q31_t * pInlineBuffer);
void csky_vdsp2_dct4_fast_q31(
const csky_vdsp2_dct4_fast_instance_q31 * S,
q31_t * pState,
q31_t * pInlineBuffer);
/**
* @brief Instance structure for the Q15 DCT4/IDCT4 function.
*/
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
q15_t normalize; /**< normalizing factor. */
q15_t *pTwiddle; /**< points to the twiddle factor table. */
q15_t *pCosFactor; /**< points to the cosFactor table. */
csky_vdsp2_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
csky_vdsp2_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_dct4_instance_q15;
typedef struct
{
uint16_t N; /**< length of the DCT4. */
uint16_t Nby2; /**< half of the length of the DCT4. */
q15_t normalize; /**< normalizing factor. */
q15_t *pTwiddle; /**< points to the twiddle factor table. */
q15_t *pCosFactor; /**< points to the cosFactor table. */
csky_vdsp2_rfft_fast_instance_q15 *pRfft; /**< points to the real FFT instance. */
csky_vdsp2_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} csky_vdsp2_dct4_fast_instance_q15;
csky_vdsp2_status csky_vdsp2_dct4_init_q15(
csky_vdsp2_dct4_instance_q15 * S,
csky_vdsp2_rfft_instance_q15 * S_RFFT,
csky_vdsp2_cfft_radix4_instance_q15 * S_CFFT,
uint16_t N,
uint16_t Nby2,
q15_t normalize);
void csky_vdsp2_dct4_q15(
const csky_vdsp2_dct4_instance_q15 * S,
q15_t * pState,
q15_t * pInlineBuffer);
void csky_vdsp2_dct4_fast_q15(
const csky_vdsp2_dct4_fast_instance_q15 * S,
q15_t * pState,
q15_t * pInlineBuffer);
void csky_vdsp2_add_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_add_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_add_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_add_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_sub_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_sub_q7(
q7_t * pSrcA,
q7_t * pSrcB,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_sub_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_sub_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_sum_q15(
q15_t * pSrcA,
q63_t * pDst,
uint32_t blockSize);
void csky_vdsp2_scale_f32(
float32_t * pSrc,
float32_t scale,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_scale_q7(
q7_t * pSrc,
q7_t scaleFract,
int8_t shift,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_scale_q15(
q15_t * pSrc,
q15_t scaleFract,
int8_t shift,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_scale_q31(
q31_t * pSrc,
q31_t scaleFract,
int8_t shift,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_abs_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_abs_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_abs_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_abs_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_abs_max_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_abs_max_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_dot_prod_f32(
float32_t * pSrcA,
float32_t * pSrcB,
uint32_t blockSize,
float32_t * result);
void csky_vdsp2_dot_prod_q7(
q7_t * pSrcA,
q7_t * pSrcB,
uint32_t blockSize,
q31_t * result);
void csky_vdsp2_dot_prod_q15(
q15_t * pSrcA,
q15_t * pSrcB,
uint32_t blockSize,
q63_t * result);
void csky_vdsp2_dot_prod_q31(
q31_t * pSrcA,
q31_t * pSrcB,
uint32_t blockSize,
q63_t * result);
void csky_vdsp2_dot_prod_u64xu8(
uint8_t * pSrcA,
uint64_t * pSrcB,
uint32_t blockSize,
uint64_t * result);
void csky_vdsp2_shift_q7(
q7_t * pSrc,
int8_t shiftBits,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_shift_q15(
q15_t * pSrc,
int8_t shiftBits,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_shift_q31(
q31_t * pSrc,
int8_t shiftBits,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_offset_f32(
float32_t * pSrc,
float32_t offset,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_offset_q7(
q7_t * pSrc,
q7_t offset,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_offset_q15(
q15_t * pSrc,
q15_t offset,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_offset_q31(
q31_t * pSrc,
q31_t offset,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_negate_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_negate_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_negate_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_negate_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_copy_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_copy_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_copy_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_copy_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fill_f32(
float32_t value,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fill_q7(
q7_t value,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fill_q15(
q15_t value,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fill_q31(
q31_t value,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_conv_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst);
void csky_vdsp2_conv_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_vdsp2_conv_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_vdsp2_conv_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_vdsp2_conv_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_vdsp2_conv_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_vdsp2_conv_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_vdsp2_conv_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_vdsp2_conv_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst);
csky_vdsp2_status csky_vdsp2_conv_partial_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_vdsp2_status csky_vdsp2_conv_partial_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
csky_vdsp2_status csky_vdsp2_conv_partial_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_vdsp2_status csky_vdsp2_conv_partial_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_vdsp2_status csky_vdsp2_conv_partial_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
csky_vdsp2_status csky_vdsp2_conv_partial_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_vdsp2_status csky_vdsp2_conv_partial_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
csky_vdsp2_status csky_vdsp2_conv_partial_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
uint32_t firstIndex,
uint32_t numPoints,
q15_t * pScratch1,
q15_t * pScratch2);
csky_vdsp2_status csky_vdsp2_conv_partial_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
* @brief Instance structure for the Q15 FIR decimator.
*/
typedef struct
{
uint8_t M; /**< decimation factor. */
uint16_t numTaps; /**< number of coefficients in the filter. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} csky_vdsp2_fir_decimate_instance_q15;
/**
* @brief Instance structure for the Q31 FIR decimator.
*/
typedef struct
{
uint8_t M; /**< decimation factor. */
uint16_t numTaps; /**< number of coefficients in the filter. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} csky_vdsp2_fir_decimate_instance_q31;
/**
* @brief Instance structure for the floating-point FIR decimator.
*/
typedef struct
{
uint8_t M; /**< decimation factor. */
uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} csky_vdsp2_fir_decimate_instance_f32;
void csky_vdsp2_fir_decimate_f32(
const csky_vdsp2_fir_decimate_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_decimate_init_f32(
csky_vdsp2_fir_decimate_instance_f32 * S,
uint16_t numTaps,
uint8_t M,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_decimate_q15(
const csky_vdsp2_fir_decimate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_decimate_fast_q15(
const csky_vdsp2_fir_decimate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_decimate_init_q15(
csky_vdsp2_fir_decimate_instance_q15 * S,
uint16_t numTaps,
uint8_t M,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_decimate_q31(
const csky_vdsp2_fir_decimate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_decimate_fast_q31(
csky_vdsp2_fir_decimate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_decimate_init_q31(
csky_vdsp2_fir_decimate_instance_q31 * S,
uint16_t numTaps,
uint8_t M,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 FIR interpolator.
*/
typedef struct
{
uint8_t L; /**< upsample factor. */
uint16_t phaseLength; /**< length of each polyphase filter component. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
} csky_vdsp2_fir_interpolate_instance_q15;
/**
* @brief Instance structure for the Q31 FIR interpolator.
*/
typedef struct
{
uint8_t L; /**< upsample factor. */
uint16_t phaseLength; /**< length of each polyphase filter component. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
} csky_vdsp2_fir_interpolate_instance_q31;
/**
* @brief Instance structure for the floating-point FIR interpolator.
*/
typedef struct
{
uint8_t L; /**< upsample factor. */
uint16_t phaseLength; /**< length of each polyphase filter component. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
} csky_vdsp2_fir_interpolate_instance_f32;
void csky_vdsp2_fir_interpolate_q15(
const csky_vdsp2_fir_interpolate_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_interpolate_init_q15(
csky_vdsp2_fir_interpolate_instance_q15 * S,
uint8_t L,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_interpolate_q31(
const csky_vdsp2_fir_interpolate_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_interpolate_init_q31(
csky_vdsp2_fir_interpolate_instance_q31 * S,
uint8_t L,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
uint32_t blockSize);
void csky_vdsp2_fir_interpolate_f32(
const csky_vdsp2_fir_interpolate_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_fir_interpolate_init_f32(
csky_vdsp2_fir_interpolate_instance_f32 * S,
uint8_t L,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
} csky_vdsp2_biquad_cascade_df2T_instance_f32;
/**
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
*/
typedef struct
{
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
} csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32;
void csky_vdsp2_biquad_cascade_df2T_f32(
const csky_vdsp2_biquad_cascade_df2T_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_stereo_df2T_f32(
const csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_biquad_cascade_df2T_init_f32(
csky_vdsp2_biquad_cascade_df2T_instance_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
void csky_vdsp2_biquad_cascade_stereo_df2T_init_f32(
csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32 * S,
uint8_t numStages,
float32_t * pCoeffs,
float32_t * pState);
/**
* @brief Instance structure for the Q15 FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of filter stages. */
q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
} csky_vdsp2_fir_lattice_instance_q15;
/**
* @brief Instance structure for the Q31 FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of filter stages. */
q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
} csky_vdsp2_fir_lattice_instance_q31;
/**
* @brief Instance structure for the floating-point FIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of filter stages. */
float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
} csky_vdsp2_fir_lattice_instance_f32;
void csky_vdsp2_fir_lattice_init_q15(
csky_vdsp2_fir_lattice_instance_q15 * S,
uint16_t numStages,
q15_t * pCoeffs,
q15_t * pState);
void csky_vdsp2_fir_lattice_q15(
const csky_vdsp2_fir_lattice_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_lattice_init_q31(
csky_vdsp2_fir_lattice_instance_q31 * S,
uint16_t numStages,
q31_t * pCoeffs,
q31_t * pState);
void csky_vdsp2_fir_lattice_q31(
const csky_vdsp2_fir_lattice_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_fir_lattice_init_f32(
csky_vdsp2_fir_lattice_instance_f32 * S,
uint16_t numStages,
float32_t * pCoeffs,
float32_t * pState);
void csky_vdsp2_fir_lattice_f32(
const csky_vdsp2_fir_lattice_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of stages in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
} csky_vdsp2_iir_lattice_instance_q15;
/**
* @brief Instance structure for the Q31 IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of stages in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
} csky_vdsp2_iir_lattice_instance_q31;
/**
* @brief Instance structure for the floating-point IIR lattice filter.
*/
typedef struct
{
uint16_t numStages; /**< number of stages in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
} csky_vdsp2_iir_lattice_instance_f32;
void csky_vdsp2_iir_lattice_f32(
const csky_vdsp2_iir_lattice_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_iir_lattice_init_f32(
csky_vdsp2_iir_lattice_instance_f32 * S,
uint16_t numStages,
float32_t * pkCoeffs,
float32_t * pvCoeffs,
float32_t * pState,
uint32_t blockSize);
void csky_vdsp2_iir_lattice_q31(
const csky_vdsp2_iir_lattice_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_iir_lattice_init_q31(
csky_vdsp2_iir_lattice_instance_q31 * S,
uint16_t numStages,
q31_t * pkCoeffs,
q31_t * pvCoeffs,
q31_t * pState,
uint32_t blockSize);
void csky_vdsp2_iir_lattice_q15(
const csky_vdsp2_iir_lattice_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_iir_lattice_init_q15(
csky_vdsp2_iir_lattice_instance_q15 * S,
uint16_t numStages,
q15_t * pkCoeffs,
q15_t * pvCoeffs,
q15_t * pState,
uint32_t blockSize);
/**
* @brief Instance structure for the floating-point LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
float32_t mu; /**< step size that controls filter coefficient updates. */
} csky_vdsp2_lms_instance_f32;
void csky_vdsp2_lms_f32(
const csky_vdsp2_lms_instance_f32 * S,
float32_t * pSrc,
float32_t * pRef,
float32_t * pOut,
float32_t * pErr,
uint32_t blockSize);
void csky_vdsp2_lms_init_f32(
csky_vdsp2_lms_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
float32_t mu,
uint32_t blockSize);
/**
* @brief Instance structure for the Q15 LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q15_t mu; /**< step size that controls filter coefficient updates. */
uint32_t postShift; /**< bit shift applied to coefficients. */
} csky_vdsp2_lms_instance_q15;
void csky_vdsp2_lms_init_q15(
csky_vdsp2_lms_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
q15_t mu,
uint32_t blockSize,
uint32_t postShift);
void csky_vdsp2_lms_q15(
const csky_vdsp2_lms_instance_q15 * S,
q15_t * pSrc,
q15_t * pRef,
q15_t * pOut,
q15_t * pErr,
uint32_t blockSize);
/**
* @brief Instance structure for the Q31 LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q31_t mu; /**< step size that controls filter coefficient updates. */
uint32_t postShift; /**< bit shift applied to coefficients. */
} csky_vdsp2_lms_instance_q31;
void csky_vdsp2_lms_q31(
const csky_vdsp2_lms_instance_q31 * S,
q31_t * pSrc,
q31_t * pRef,
q31_t * pOut,
q31_t * pErr,
uint32_t blockSize);
void csky_vdsp2_lms_init_q31(
csky_vdsp2_lms_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
q31_t mu,
uint32_t blockSize,
uint32_t postShift);
/**
* @brief Instance structure for the floating-point normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
float32_t mu; /**< step size that control filter coefficient updates. */
float32_t energy; /**< saves previous frame energy. */
float32_t x0; /**< saves previous input sample. */
} csky_vdsp2_lms_norm_instance_f32;
void csky_vdsp2_lms_norm_f32(
csky_vdsp2_lms_norm_instance_f32 * S,
float32_t * pSrc,
float32_t * pRef,
float32_t * pOut,
float32_t * pErr,
uint32_t blockSize);
void csky_vdsp2_lms_norm_init_f32(
csky_vdsp2_lms_norm_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
float32_t mu,
uint32_t blockSize);
/**
* @brief Instance structure for the Q31 normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q31_t mu; /**< step size that controls filter coefficient updates. */
uint8_t postShift; /**< bit shift applied to coefficients. */
q31_t *recipTable; /**< points to the reciprocal initial value table. */
q31_t energy; /**< saves previous frame energy. */
q31_t x0; /**< saves previous input sample. */
} csky_vdsp2_lms_norm_instance_q31;
void csky_vdsp2_lms_norm_q31(
csky_vdsp2_lms_norm_instance_q31 * S,
q31_t * pSrc,
q31_t * pRef,
q31_t * pOut,
q31_t * pErr,
uint32_t blockSize);
void csky_vdsp2_lms_norm_init_q31(
csky_vdsp2_lms_norm_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
q31_t mu,
uint32_t blockSize,
uint8_t postShift);
/**
* @brief Instance structure for the Q15 normalized LMS filter.
*/
typedef struct
{
uint16_t numTaps; /**< Number of coefficients in the filter. */
q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
q15_t mu; /**< step size that controls filter coefficient updates. */
uint8_t postShift; /**< bit shift applied to coefficients. */
q15_t *recipTable; /**< Points to the reciprocal initial value table. */
q15_t energy; /**< saves previous frame energy. */
q15_t x0; /**< saves previous input sample. */
} csky_vdsp2_lms_norm_instance_q15;
void csky_vdsp2_lms_norm_q15(
csky_vdsp2_lms_norm_instance_q15 * S,
q15_t * pSrc,
q15_t * pRef,
q15_t * pOut,
q15_t * pErr,
uint32_t blockSize);
void csky_vdsp2_lms_norm_init_q15(
csky_vdsp2_lms_norm_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
q15_t mu,
uint32_t blockSize,
uint8_t postShift);
void csky_vdsp2_correlate_f32(
float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst);
void csky_vdsp2_correlate_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch);
void csky_vdsp2_correlate_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_vdsp2_correlate_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
void csky_vdsp2_correlate_fast_opt_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch);
void csky_vdsp2_correlate_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_vdsp2_correlate_fast_q31(
q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst);
void csky_vdsp2_correlate_opt_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2);
void csky_vdsp2_correlate_q7(
q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst);
/**
* @brief Instance structure for the floating-point sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_vdsp2_fir_sparse_instance_f32;
/**
* @brief Instance structure for the Q31 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_vdsp2_fir_sparse_instance_q31;
/**
* @brief Instance structure for the Q15 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_vdsp2_fir_sparse_instance_q15;
/**
* @brief Instance structure for the Q7 sparse FIR filter.
*/
typedef struct
{
uint16_t numTaps; /**< number of coefficients in the filter. */
uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
} csky_vdsp2_fir_sparse_instance_q7;
void csky_vdsp2_fir_sparse_f32(
csky_vdsp2_fir_sparse_instance_f32 * S,
float32_t * pSrc,
float32_t * pDst,
float32_t * pScratchIn,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_init_f32(
csky_vdsp2_fir_sparse_instance_f32 * S,
uint16_t numTaps,
float32_t * pCoeffs,
float32_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_q31(
csky_vdsp2_fir_sparse_instance_q31 * S,
q31_t * pSrc,
q31_t * pDst,
q31_t * pScratchIn,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_init_q31(
csky_vdsp2_fir_sparse_instance_q31 * S,
uint16_t numTaps,
q31_t * pCoeffs,
q31_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_q15(
csky_vdsp2_fir_sparse_instance_q15 * S,
q15_t * pSrc,
q15_t * pDst,
q15_t * pScratchIn,
q31_t * pScratchOut,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_init_q15(
csky_vdsp2_fir_sparse_instance_q15 * S,
uint16_t numTaps,
q15_t * pCoeffs,
q15_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_q7(
csky_vdsp2_fir_sparse_instance_q7 * S,
q7_t * pSrc,
q7_t * pDst,
q7_t * pScratchIn,
q31_t * pScratchOut,
uint32_t blockSize);
void csky_vdsp2_fir_sparse_init_q7(
csky_vdsp2_fir_sparse_instance_q7 * S,
uint16_t numTaps,
q7_t * pCoeffs,
q7_t * pState,
int32_t * pTapDelay,
uint16_t maxDelay,
uint32_t blockSize);
void csky_vdsp2_sin_cos_f32(
float32_t theta,
float32_t * pSinVal,
float32_t * pCosVal);
void csky_vdsp2_sin_cos_q31(
q31_t theta,
q31_t * pSinVal,
q31_t * pCosVal);
void csky_vdsp2_cmplx_conj_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_conj_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_conj_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mag_squared_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mag_squared_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mag_squared_q31_basic(
q31_t * pSrc,
q63_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mag_squared_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_vdsp2_vsqrt_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_vdsp2_vsqrt_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_vdsp2_vsqrt_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_vdsp2_vsqrt_q7(
q7_t * pSrc,
q7_t * pDst,
uint32_t numSamples);
void csky_vdsp2_q7_to_q31(
q7_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q7_to_q15(
q7_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q7_to_float(
q7_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q31_to_float(
q31_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
csky_vdsp2_status csky_vdsp2_sqrt_f32(
float32_t in,
float32_t * pOut);
csky_vdsp2_status csky_vdsp2_sqrt_q31(
q31_t in,
q31_t * pOut);
csky_vdsp2_status csky_vdsp2_sqrt_q15(
q15_t in,
q15_t * pOut);
void csky_vdsp2_power_q31(
q31_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_vdsp2_power_int32(
int32_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_vdsp2_power_int32(
int32_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_vdsp2_power_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_vdsp2_power_q15(
q15_t * pSrc,
uint32_t blockSize,
q63_t * pResult);
void csky_vdsp2_power_q7(
q7_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_vdsp2_mean_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * pResult);
void csky_vdsp2_mean_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_vdsp2_mean_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_vdsp2_mean_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_vdsp2_var_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_vdsp2_var_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_vdsp2_var_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_vdsp2_rms_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_vdsp2_rms_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_vdsp2_rms_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_vdsp2_std_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult);
void csky_vdsp2_std_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult);
void csky_vdsp2_std_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult);
void csky_vdsp2_cmplx_mag_f32(
float32_t * pSrc,
float32_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mag_q31(
q31_t * pSrc,
q31_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mag_q15(
q15_t * pSrc,
q15_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_dot_prod_q15(
q15_t * pSrcA,
q15_t * pSrcB,
uint32_t numSamples,
q31_t * realResult,
q31_t * imagResult);
void csky_vdsp2_cmplx_dot_prod_q31(
q31_t * pSrcA,
q31_t * pSrcB,
uint32_t numSamples,
q63_t * realResult,
q63_t * imagResult);
void csky_vdsp2_cmplx_dot_prod_f32(
float32_t * pSrcA,
float32_t * pSrcB,
uint32_t numSamples,
float32_t * realResult,
float32_t * imagResult);
void csky_vdsp2_cmplx_mult_real_q15(
q15_t * pSrcCmplx,
q15_t * pSrcReal,
q15_t * pCmplxDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_real_q31(
q31_t * pSrcCmplx,
q31_t * pSrcReal,
q31_t * pCmplxDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_real_f32(
float32_t * pSrcCmplx,
float32_t * pSrcReal,
float32_t * pCmplxDst,
uint32_t numSamples);
void csky_vdsp2_min_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * result,
uint32_t * index);
void csky_vdsp2_min_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_min_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_min_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_max_q7(
q7_t * pSrc,
uint32_t blockSize,
q7_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_max_q15(
q15_t * pSrc,
uint32_t blockSize,
q15_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_max_q31(
q31_t * pSrc,
uint32_t blockSize,
q31_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_max_f32(
float32_t * pSrc,
uint32_t blockSize,
float32_t * pResult,
uint32_t * pIndex);
void csky_vdsp2_cmplx_mult_cmplx_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_cmplx_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_cmplx_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_cmplx_re_q15(
q15_t * pSrcA,
q15_t * pSrcB,
q15_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_cmplx_re_q31(
q31_t * pSrcA,
q31_t * pSrcB,
q31_t * pDst,
uint32_t numSamples);
void csky_vdsp2_cmplx_mult_cmplx_re_f32(
float32_t * pSrcA,
float32_t * pSrcB,
float32_t * pDst,
uint32_t numSamples);
void csky_vdsp2_float_to_q31(
float32_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_float_to_q15(
float32_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_float_to_q7(
float32_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q31_to_q15(
q31_t * pSrc,
q15_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q31_to_q7(
q31_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q31_to_q7_rs(
q31_t * pSrc,
q7_t * pDst,
uint32_t shiftValue,
uint32_t blockSize);
void csky_vdsp2_q63_to_q31_rs(
q63_t * pSrc,
q31_t * pDst,
uint32_t shiftValue,
uint32_t blockSize);
void csky_vdsp2_q15_to_float(
q15_t * pSrc,
float32_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q15_to_q31(
q15_t * pSrc,
q31_t * pDst,
uint32_t blockSize);
void csky_vdsp2_q15_to_q7(
q15_t * pSrc,
q7_t * pDst,
uint32_t blockSize);
#ifdef __cplusplus
}
#endif
#endif /* _CSKY_VDSP2_MATH_H */
/**
*
* End of file.
*/
| YifuLiu/AliOS-Things | components/csi/csi2/dsp/include/csky_vdsp2_math.h | C | apache-2.0 | 72,332 |
/**************************************************************************//**
* @file ARMCM0.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ARMCM0_H
#define ARMCM0_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ------------------- Processor Interrupt Numbers ------------------------------ */
Interrupt0_IRQn = 0,
Interrupt1_IRQn = 1,
Interrupt2_IRQn = 2,
Interrupt3_IRQn = 3,
Interrupt4_IRQn = 4,
Interrupt5_IRQn = 5,
Interrupt6_IRQn = 6,
Interrupt7_IRQn = 7,
Interrupt8_IRQn = 8,
Interrupt9_IRQn = 9
/* Interrupts 10 .. 31 are left out */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM0_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 0U /* no MPU present */
#define __VTOR_PRESENT 0U /* no VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include "core_cm0.h" /* Processor and core peripherals */
#include "system_ARMCM0.h" /* System Header */
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
#endif /* ARMCM0_H */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/ARMCM0.h | C | apache-2.0 | 4,430 |
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/cmsis_compiler.h | C | apache-2.0 | 8,890 |
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler GCC header file
* @version V5.1.0
* @date 20. December 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
}
#endif
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Stack Pointer (non-secure)
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
\return SP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return(result);
}
/**
\brief Set Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
\param [in] topOfStack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
{
__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
return(result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
}
#endif
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
{
__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
{
__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return(result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
}
#endif
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief Get Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return result;
#endif
}
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Process Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return result;
#endif
}
#endif
/**
\brief Set Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Process Stack Pointer (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
#endif
}
#endif
/**
\brief Get Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return result;
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Get Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
return 0U;
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return result;
#endif
}
#endif
/**
\brief Set Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
#endif
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief Set Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
#endif
}
#endif
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#endif
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
#endif
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_RW_REG(r) "+l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_RW_REG(r) "+r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP() __ASM volatile ("nop")
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI() __ASM volatile ("wfi")
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE() __ASM volatile ("wfe")
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV() __ASM volatile ("sev")
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__STATIC_FORCEINLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
#endif
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (int16_t)__builtin_bswap16(value);
#else
int16_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
#endif
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U)
{
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
#else
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
__STATIC_FORCEINLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] ARG1 Value to be saturated
\param [in] ARG2 Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
__extension__ \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] ARG1 Value to be saturated
\param [in] ARG2 Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
}
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t) result);
}
/**
\brief Load-Acquire (16 bit)
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t) result);
}
/**
\brief Load-Acquire (32 bit)
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief Store-Release (8 bit)
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Store-Release (16 bit)
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Store-Release (32 bit)
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief Load-Acquire Exclusive (8 bit)
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t) result);
}
/**
\brief Load-Acquire Exclusive (16 bit)
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t) result);
}
/**
\brief Load-Acquire Exclusive (32 bit)
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
}
/**
\brief Store-Release Exclusive (8 bit)
\details Executes a STLB exclusive instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief Store-Release Exclusive (16 bit)
\details Executes a STLH exclusive instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief Store-Release Exclusive (32 bit)
\details Executes a STL exclusive instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
return(result);
}
#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ /* Little endian */
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else /* Big endian */
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
{
int32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#if 0
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#endif
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#endif /* (__ARM_FEATURE_DSP == 1) */
/*@} end of group CMSIS_SIMD_intrinsics */
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_H */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/cmsis_gcc.h | C | apache-2.0 | 60,853 |