code stringlengths 1 1.05M | repo_name stringlengths 6 83 | path stringlengths 3 242 | language stringclasses 222
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/cmsis_version.h | C | apache-2.0 | 1,677 |
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/core_cm0.h | C | apache-2.0 | 41,283 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_core.h
* @brief Header File for csi_core
* @version V1.0
* @date 12. june 2019
******************************************************************************/
#ifndef _CSI_CORE_H_
#define _CSI_CORE_H_
#include <stddef.h>
#include <cmsis_gcc.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __GNUC__
__STATIC_INLINE size_t csi_irq_save(void)
{
uint32_t result;
result = __get_PRIMASK();
__disable_irq();
return (result);
}
__STATIC_INLINE void csi_irq_restore(size_t irq_state)
{
__set_PRIMASK(irq_state);
}
#else
static inline __asm size_t csi_irq_save(void)
{
MRS R0, PRIMASK
CPSID I
BX LR
return 0;
}
static inline __asm void csi_irq_restore(size_t irq_state)
{
MSR PRIMASK, R0
BX LR
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CSI_CORE_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/csi_core.h | C | apache-2.0 | 1,035 |
/**************************************************************************//**
* @file system_ARMCM0.h
* @brief CMSIS Device System Header File for
* ARMCM0 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_ARMCM0_H
#define SYSTEM_ARMCM0_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_ARMCM0_H */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/cmsis/system_ARMCM0.h | C | apache-2.0 | 1,528 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_801.h
* @brief CSI 801 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_801_H_GENERIC
#define __CORE_801_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck801
@{
*/
/* CSI CK801 definitions */
#define __CK801_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK801_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK801_CSI_VERSION ((__CK801_CSI_VERSION_MAIN << 16U) | \
__CK801_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x01U) /*!< CK80X Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK801_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK801_H_DEPENDANT
#define __CORE_CK801_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK801_REV
#define __CK801_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK801 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 1.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t Size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 1; /*!< bit: 6 Reserved */
uint32_t base_addr: 25; /*!< bit: 7..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 7U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0x1FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 4; /*!< bit: 0.. 3 Reserved */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 11; /*!< bit: 5..15 Reserved */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[15U];
__IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[15U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[15U];
__IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[15U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[15U];
__IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[15U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[15U];
__IOM uint32_t ICSR[1U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[15U];
__IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[63U];
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[504U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK801 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
VIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
VIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
VIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
VIC->ISSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
VIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
VIC->ICSR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return Interrput status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
return ((uint32_t)(((VIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
return ((uint32_t)(((VIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
VIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
VIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
return ((uint32_t)(((VIC->IWER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wakeup Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
VIC->IWER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
VIC->IWDR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
return ((uint32_t)(((VIC->IABR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vecter threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 32) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 32) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
(void)IRQn;
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/**
\brief clean CORE timer interrupt flag
*/
__STATIC_INLINE void csi_coret_clear_irq(void)
{
CORET->CTRL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_128B = 0x6,
REGION_SIZE_256B = 0x7,
REGION_SIZE_512B = 0x8,
REGION_SIZE_1KB = 0x9,
REGION_SIZE_2KB = 0xA,
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0x3FFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_128B) {
pacr.w &= ~(((1u << (size -6)) - 1) << 7);
}
pacr.b.Size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
/*@} end of Old Interfaces */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_801_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_801.h | C | apache-2.0 | 46,845 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_802.h
* @brief CSI 802 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_802_H_GENERIC
#define __CORE_802_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck802
@{
*/
/* CSI CK802 definitions */
#define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \
__CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x02U) /*!< CK80X Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK802_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK802_H_DEPENDANT
#define __CORE_CK802_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK802_REV
#define __CK802_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK802 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 3; /*!< bit: 24..26 Reserved */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 5; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 1; /*!< bit: 6 Reserved */
uint32_t base_addr: 25; /*!< bit: 7..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 7U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0x1FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 4; /*!< bit: 0.. 3 Reserved */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK802 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
VectThreshold &= 0x7FUL;
if (VectThreshold <= 31) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
}
if (VectThreshold > 31 && VectThreshold < 96) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x7) << 5);
}
if (VectThreshold > 95) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0xF) << 4);
}
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/**
\brief clean CORE timer interrupt flag
*/
__STATIC_INLINE void csi_coret_clear_irq(void)
{
CORET->CTRL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk & (~CACHE_CER_CFIG_Msk)); /* enable all Cache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/*@} end of CSI_core_DebugFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_128B = 0x6,
REGION_SIZE_256B = 0x7,
REGION_SIZE_512B = 0x8,
REGION_SIZE_1KB = 0x9,
REGION_SIZE_2KB = 0xA,
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
if (idx > 7) {
return;
}
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0x3FFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_128B) {
pacr.w &= ~(((1u << (size -6)) - 1) << 7);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define HAD_SendChar(ch) csi_had_send_char(ch)
#define HAD_ReceiveChar() csi_had_receive_char()
#define HAD_CheckChar() csi_had_check_char()
/*@} end of Old Interfaces */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_802_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_802.h | C | apache-2.0 | 63,812 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_803.h
* @brief CSI 803 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_803_H_GENERIC
#define __CORE_803_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck803
@{
*/
/* CSI CK803 definitions */
#define __CK803_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK803_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK803_CSI_VERSION ((__CK803_CSI_VERSION_MAIN << 16U) | \
__CK803_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x03U) /*!< CK80X Core */
#endif
/* __FPU_USED indicates whether an FPU is used or not. */
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK803_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK803_H_DEPENDANT
#define __CORE_CK803_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK803_REV
#define __CK803_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK803 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
uint32_t SV: 1; /*!< bit: 25 Stacked valid */
uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_BE_Pos 1U /*!< CHR: BE Position */
#define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
#define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
#define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
#define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
#define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
#define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK803 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
VectThreshold &= 0x7FUL;
if (VectThreshold <= 31) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
}
if (VectThreshold > 31 && VectThreshold < 96) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x7) << 5);
}
if (VectThreshold > 95) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0xF) << 4);
}
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/**
\brief clean CORE timer interrupt flag
*/
__STATIC_INLINE void csi_coret_clear_irq(void)
{
CORET->CTRL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define SCB_EnableICache() csi_icache_enable()
#define SCB_DisableICache() csi_icache_disable()
#define SCB_InvalidateICache() csi_icache_invalid()
#define SCB_EnableDCache() csi_dcache_enable()
#define SCB_DisableDCache() csi_dcache_disable()
#define SCB_InvalidateDCache() csi_dcache_invalid()
#define SCB_CleanDCache() csi_dcache_clean()
#define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
#define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
#define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
#define SCB_EnableCacheProfile() csi_cache_enable_profile()
#define SCB_DisableCacheProfile() csi_cache_disable_profile()
#define SCB_ResetCacheProfile() csi_cache_reset_profile()
#define SCB_CacheAccessTime() csi_cache_get_access_time()
#define SCB_CacheMissTime() csi_cache_get_miss_time()
#define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
#define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
#define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
#define SCB_CleanCache() csi_dcache_clean()
#define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
#define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
#define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_803_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_803.h | C | apache-2.0 | 67,675 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_804.h
* @brief CSI 804 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_804_H_GENERIC
#define __CORE_804_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck804
@{
*/
/* CSI CK804 definitions */
#define __CK804_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK804_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK804_CSI_VERSION ((__CK804_CSI_VERSION_MAIN << 16U) | \
__CK804_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x03U) /*!< CK80X Core */
#endif
/* __FPU_USED indicates whether an FPU is used or not. */
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK804_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK804_H_DEPENDANT
#define __CORE_CK804_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK804_REV
#define __CK804_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK804 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
uint32_t SV: 1; /*!< bit: 25 Stacked valid */
uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_T_Pos 30U /*!< PSR: T Position */
#define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_BE_Pos 1U /*!< CHR: BE Position */
#define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
#define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
#define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
#define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
#define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
#define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK804 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
VectThreshold &= 0x7FUL;
if (VectThreshold <= 31) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
}
if (VectThreshold > 31 && VectThreshold < 96) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x7) << 5);
}
if (VectThreshold > 95) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0xF) << 4);
}
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/**
\brief clean CORE timer interrupt flag
*/
__STATIC_INLINE void csi_coret_clear_irq(void)
{
CORET->CTRL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define SCB_EnableICache() csi_icache_enable()
#define SCB_DisableICache() csi_icache_disable()
#define SCB_InvalidateICache() csi_icache_invalid()
#define SCB_EnableDCache() csi_dcache_enable()
#define SCB_DisableDCache() csi_dcache_disable()
#define SCB_InvalidateDCache() csi_dcache_invalid()
#define SCB_CleanDCache() csi_dcache_clean()
#define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
#define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
#define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
#define SCB_EnableCacheProfile() csi_cache_enable_profile()
#define SCB_DisableCacheProfile() csi_cache_disable_profile()
#define SCB_ResetCacheProfile() csi_cache_reset_profile()
#define SCB_CacheAccessTime() csi_cache_get_access_time()
#define SCB_CacheMissTime() csi_cache_get_miss_time()
#define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
#define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
#define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
#define SCB_CleanCache() csi_dcache_clean()
#define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
#define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
#define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_804_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_804.h | C | apache-2.0 | 67,901 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_805.h
* @brief CSI 805 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_805_H_GENERIC
#define __CORE_805_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck805
@{
*/
/* CSI CK805 definitions */
#define __CK805_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK805_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK805_CSI_VERSION ((__CK805_CSI_VERSION_MAIN << 16U) | \
__CK805_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK80X
#define __CK80X (0x03U) /*!< CK80X Core */
#endif
/* __FPU_USED indicates whether an FPU is used or not. */
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK805_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK805_H_DEPENDANT
#define __CORE_CK805_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK805_REV
#define __CK805_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK805 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core VIC Register
- Core Cache Register
- Core CoreTIM Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 1; /*!< bit: 24 Reserved */
uint32_t SV: 1; /*!< bit: 25 Stacked valid */
uint32_t SD: 1; /*!< bit: 26 Stacked dirty */
uint32_t SC: 1; /*!< bit: 27 Secure call bit */
uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 1; /*!< bit: 0.. 1 memory protection settings */
uint32_t _reserved0: 6; /*!< bit: 2.. 6 Reserved */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
#define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
*/
typedef union {
struct {
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t BE: 1; /*!< bit: 1 System bus support burst transer */
uint32_t IPE: 1; /*!< bit: 2 Instruction prefetch function enable */
uint32_t RPE: 1; /*!< bit: 3 Function return instruction RTS will speculate execution */
uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
} b;
uint32_t w;
} CHR_Type;
/* CHR Register Definitions */
#define CHR_BE_Pos 1U /*!< CHR: BE Position */
#define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
#define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
#define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
#define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
#define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
#define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
#define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
#define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
#define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
#define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
#define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
#define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
#define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_VIC Vectored Interrupt Controller (VIC)
\brief Type definitions for the VIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
uint32_t RESERVED0[12U];
__IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
uint32_t RESERVED1[12U];
__IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
uint32_t RESERVED2[12U];
__IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
uint32_t RESERVED3[12U];
__IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
uint32_t RESERVED4[12U];
__IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
uint32_t RESERVED5[12U];
__IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
uint32_t RESERVED6[12U];
__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
uint32_t RESERVED7[12U];
__IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
uint32_t RESERVED8[60U];
__IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
uint32_t RESERVED9[480U];
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
__IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
__IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
__IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
} VIC_Type;
/*@} end of group CSI_VIC */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_DCEN_Pos 0U /*!< CACHE CER: DCEN Position */
#define CACHE_CER_DCEN_Msk (0x1UL << CACHE_CER_DCEN_Pos) /*!< CACHE CER: DCEN Mask */
#define CACHE_CER_ICEN_Pos 1U /*!< CACHE CER: ICEN Position */
#define CACHE_CER_ICEN_Msk (0x1UL << CACHE_CER_ICEN_Pos) /*!< CACHE CER: ICEN Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_WA_Pos 5U /*!< CACHE CER: WA Position */
#define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /*!< CACHE CER: WA Mask */
#define CACHE_CIR_D_INV_Pos 0U /*!< CACHE CIR: D_INV Position */
#define CACHE_CIR_D_INV_Msk (0x1UL << CACHE_CIR_D_INV_Pos) /*!< CACHE CIR: D_INV Mask */
#define CACHE_CIR_I_INV_Pos 1U /*!< CACHE CIR: I_INV Position */
#define CACHE_CIR_I_INV_Msk (0x1UL << CACHE_CIR_I_INV_Pos) /*!< CACHE CIR: I_INV Mask */
#define CACHE_CIR_D_CLR_Pos 2U /*!< CACHE CIR: D_CLR Position */
#define CACHE_CIR_D_CLR_Msk (0x1UL << CACHE_CIR_D_CLR_Pos) /*!< CACHE CIR: D_CLR Mask */
#define CACHE_CIR_LINE_MODE_Pos 3U /*!< CACHE CIR: LINE_MODE Position */
#define CACHE_CIR_LINE_MODE_Msk (0x1UL << CACHE_CIR_LINE_MODE_Pos) /*!< CACHE CIR: LINE_MODE Mask */
#define CACHE_CIR_OP_ADDR_Pos 4U /*!< CACHE CIR: OP_ADDR Position */
#define CACHE_CIR_OP_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_OP_ADDR_Pos) /*!< CACHE CIR: OP_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK805 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Check Interrupt is Wakeup or not
\details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
__STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
IRQn &= 0x7FUL;
VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
}
/**
\brief Get Interrupt is Active or not
\details Read the active register in the VIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
{
IRQn &= 0x7FUL;
return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Threshold register
\details set the threshold register in the VIC.
\param [in] VectThreshold specific vector threshold.
\param [in] PrioThreshold specific priority threshold.
*/
__STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
{
VectThreshold &= 0x7FUL;
if (VectThreshold <= 31) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
}
if (VectThreshold > 31 && VectThreshold < 96) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x7) << 5);
}
if (VectThreshold > 95) {
VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0xF) << 4);
}
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 128) {
uint32_t *vectors = (uint32_t *)__get_VBR();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/**
\brief clean CORE timer interrupt flag
*/
__STATIC_INLINE void csi_coret_clear_irq(void)
{
CORET->CTRL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_I_INV_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_ICEN_Msk); /* enable icache Cache */
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)(CACHE_CER_ICEN_Msk); /* disable icache */
CACHE->CIR = CACHE_CIR_I_INV_Msk; /* invalidate icache */
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_I_INV_Msk; /* invalidate icache */
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_INV_Msk; /* invalidate dcache */
CACHE->CER |= (uint32_t)(CACHE_CER_DCEN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk); /* enable dcache */
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CER &= ~(uint32_t)CACHE_CER_DCEN_Msk; /* disable dcache */
CACHE->CIR = CACHE_CIR_D_INV_Msk; /* invalidate dcache */
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_INV_Msk; /* invalidate dcache */
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_CLR_Msk; /* clean dcache */
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
CACHE->CIR = CACHE_CIR_D_CLR_Msk | CACHE_CIR_D_INV_Msk; /* clean and inv all Cache */
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_OP_ADDR_Msk;
int32_t linesize = 16;
op_addr |= (CACHE_CIR_D_INV_Msk | CACHE_CIR_LINE_MODE_Msk);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_OP_ADDR_Msk;
int32_t linesize = 16;
op_addr |= (CACHE_CIR_D_CLR_Msk | CACHE_CIR_LINE_MODE_Msk);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_OP_ADDR_Msk;
int32_t linesize = 16;
op_addr |= (CACHE_CIR_D_CLR_Msk | CACHE_CIR_D_INV_Msk | CACHE_CIR_LINE_MODE_Msk);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1; /* instruction fetched excution */
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1; /* security */
} mpu_region_attr_t;
/**
\brief enable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu.
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 7) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 7).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 7) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void csi_system_reset(void)
{
CHR_Type chr;
chr.w = __get_CHR();
#ifdef __RESET_CONST
chr.b.SRST_VAL = __RESET_CONST;
#else
chr.b.SRST_VAL = 0xABCD;
#endif
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
__set_CHR(chr.w);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/* ################################## Old Interfaces ############################################ */
/* These interfaces are deprecated */
#define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
#define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
#define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
#define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
#define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
#define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
#define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
#define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
#define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
#define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
#define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
#define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
#define NVIC_SystemReset() csi_system_reset()
#define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
#define SCB_EnableICache() csi_icache_enable()
#define SCB_DisableICache() csi_icache_disable()
#define SCB_InvalidateICache() csi_icache_invalid()
#define SCB_EnableDCache() csi_dcache_enable()
#define SCB_DisableDCache() csi_dcache_disable()
#define SCB_InvalidateDCache() csi_dcache_invalid()
#define SCB_CleanDCache() csi_dcache_clean()
#define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
#define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
#define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
#define SCB_EnableCacheProfile() csi_cache_enable_profile()
#define SCB_DisableCacheProfile() csi_cache_disable_profile()
#define SCB_ResetCacheProfile() csi_cache_reset_profile()
#define SCB_CacheAccessTime() csi_cache_get_access_time()
#define SCB_CacheMissTime() csi_cache_get_miss_time()
#define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
#define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
#define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
#define SCB_CleanCache() csi_dcache_clean()
#define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
#define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
#define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
#define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_805_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_805.h | C | apache-2.0 | 67,320 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck807.h
* @brief CSI CK807 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK807_H_GENERIC
#define __CORE_CK807_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK807
@{
*/
/* CSI CK807 definitions */
#define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
__CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK807
#define __CK807 (0x07U) /*!< CK807 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK807_H_DEPENDANT
#define __CORE_CK807_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK807_REV
#define __CK807_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK807 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK807 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t NX0: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t NX1: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t NX2: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t NX3: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t NX4: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t NX5: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t NX6: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t NX7: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S0: 1; /*!< bit: 24 Security property settings */
uint32_t S1: 1; /*!< bit: 25 Security property settings */
uint32_t S2: 1; /*!< bit: 26 Security property settings */
uint32_t S3: 1; /*!< bit: 27 Security property settings */
uint32_t S4: 1; /*!< bit: 28 Security property settings */
uint32_t S5: 1; /*!< bit: 29 Security property settings */
uint32_t S6: 1; /*!< bit: 30 Security property settings */
uint32_t S7: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_NX7_Pos 7U /*!< CAPR: NX7 Position */
#define CAPR_NX7_Msk (0x1UL << CAPR_NX7_Pos) /*!< CAPR: NX7 Mask */
#define CAPR_NX6_Pos 6U /*!< CAPR: NX6 Position */
#define CAPR_NX6_Msk (0x1UL << CAPR_NX6_Pos) /*!< CAPR: NX6 Mask */
#define CAPR_NX5_Pos 5U /*!< CAPR: NX5 Position */
#define CAPR_NX5_Msk (0x1UL << CAPR_NX5_Pos) /*!< CAPR: NX5 Mask */
#define CAPR_NX4_Pos 4U /*!< CAPR: NX4 Position */
#define CAPR_NX4_Msk (0x1UL << CAPR_NX4_Pos) /*!< CAPR: NX4 Mask */
#define CAPR_NX3_Pos 3U /*!< CAPR: NX3 Position */
#define CAPR_NX3_Msk (0x1UL << CAPR_NX3_Pos) /*!< CAPR: NX3 Mask */
#define CAPR_NX2_Pos 2U /*!< CAPR: NX2 Position */
#define CAPR_NX2_Msk (0x1UL << CAPR_NX2_Pos) /*!< CAPR: NX2 Mask */
#define CAPR_NX1_Pos 1U /*!< CAPR: NX1 Position */
#define CAPR_NX1_Msk (0x1UL << CAPR_NX1_Pos) /*!< CAPR: NX1 Mask */
#define CAPR_NX0_Pos 0U /*!< CAPR: NX0 Position */
#define CAPR_NX0_Msk (0x1UL << CAPR_NX0_Pos) /*!< CAPR: NX0 Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR1, CR<16,0>)
*/
typedef union {
struct {
uint32_t NX8: 1; /*!< bit: 0 Non executable attribute setting */
uint32_t NX9: 1; /*!< bit: 1 Non executable attribute setting */
uint32_t NX10: 1; /*!< bit: 2 Non executable attribute setting */
uint32_t NX11: 1; /*!< bit: 3 Non executable attribute setting */
uint32_t NX12: 1; /*!< bit: 4 Non executable attribute setting */
uint32_t NX13: 1; /*!< bit: 5 Non executable attribute setting */
uint32_t NX14: 1; /*!< bit: 6 Non executable attribute setting */
uint32_t NX15: 1; /*!< bit: 7 Non executable attribute setting */
uint32_t AP8: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP9: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP10: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP11: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t AP12: 2; /*!< bit: 16..17 access permissions settings bit */
uint32_t AP13: 2; /*!< bit: 18..19 access permissions settings bit */
uint32_t AP14: 2; /*!< bit: 20..21 access permissions settings bit */
uint32_t AP15: 2; /*!< bit: 22..23 access permissions settings bit */
uint32_t S8: 1; /*!< bit: 24 Security property settings */
uint32_t S9: 1; /*!< bit: 25 Security property settings */
uint32_t S10: 1; /*!< bit: 26 Security property settings */
uint32_t S11: 1; /*!< bit: 27 Security property settings */
uint32_t S12: 1; /*!< bit: 28 Security property settings */
uint32_t S13: 1; /*!< bit: 29 Security property settings */
uint32_t S14: 1; /*!< bit: 30 Security property settings */
uint32_t S15: 1; /*!< bit: 31 Security property settings */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR1_Type;
/* CAPR1 Register Definitions */
#define CAPR1_S15_Pos 31U /*!< CAPR1: S15 Position */
#define CAPR1_S15_Msk (1UL << CAPR1_S15_Pos) /*!< CAPR1: S15 Mask */
#define CAPR1_S14_Pos 30U /*!< CAPR1: S14 Position */
#define CAPR1_S14_Msk (1UL << CAPR1_S14_Pos) /*!< CAPR1: S14 Mask */
#define CAPR1_S13_Pos 29U /*!< CAPR1: S13 Position */
#define CAPR1_S13_Msk (1UL << CAPR1_S13_Pos) /*!< CAPR1: S13 Mask */
#define CAPR1_S12_Pos 28U /*!< CAPR1: S12 Position */
#define CAPR1_S12_Msk (1UL << CAPR1_S12_Pos) /*!< CAPR1: S12 Mask */
#define CAPR1_S11_Pos 27U /*!< CAPR1: S11 Position */
#define CAPR1_S11_Msk (1UL << CAPR1_S11_Pos) /*!< CAPR1: S11 Mask */
#define CAPR1_S10_Pos 26U /*!< CAPR1: S10 Position */
#define CAPR1_S10_Msk (1UL << CAPR1_S10_Pos) /*!< CAPR1: S10 Mask */
#define CAPR1_S9_Pos 25U /*!< CAPR1: S9 Position */
#define CAPR1_S9_Msk (1UL << CAPR1_S9_Pos) /*!< CAPR1: S9 Mask */
#define CAPR1_S8_Pos 24U /*!< CAPR1: S8 Position */
#define CAPR1_S8_Msk (1UL << CAPR1_S8_Pos) /*!< CAPR1: S8 Mask */
#define CAPR1_AP15_Pos 22U /*!< CAPR1: AP15 Position */
#define CAPR1_AP15_Msk (0x3UL << CAPR1_AP15_Pos) /*!< CAPR1: AP15 Mask */
#define CAPR1_AP14_Pos 20U /*!< CAPR1: AP14 Position */
#define CAPR1_AP14_Msk (0x3UL << CAPR1_AP14_Pos) /*!< CAPR1: AP14 Mask */
#define CAPR1_AP13_Pos 18U /*!< CAPR1: AP13 Position */
#define CAPR1_AP13_Msk (0x3UL << CAPR1_AP13_Pos) /*!< CAPR1: AP13 Mask */
#define CAPR1_AP12_Pos 16U /*!< CAPR1: AP12 Position */
#define CAPR1_AP12_Msk (0x3UL << CAPR1_AP12_Pos) /*!< CAPR1: AP12 Mask */
#define CAPR1_AP11_Pos 14U /*!< CAPR1: AP11 Position */
#define CAPR1_AP11_Msk (0x3UL << CAPR1_AP11_Pos) /*!< CAPR1: AP11 Mask */
#define CAPR1_AP10_Pos 12U /*!< CAPR1: AP10 Position */
#define CAPR1_AP10_Msk (0x3UL << CAPR1_AP10_Pos) /*!< CAPR1: AP10 Mask */
#define CAPR1_AP9_Pos 10U /*!< CAPR1: AP9 Position */
#define CAPR1_AP9_Msk (0x3UL << CAPR1_AP9_Pos) /*!< CAPR1: AP9 Mask */
#define CAPR1_AP8_Pos 8U /*!< CAPR1: AP8 Position */
#define CAPR1_AP8_Msk (0x3UL << CAPR1_AP8_Pos) /*!< CAPR1: AP8 Mask */
#define CAPR1_NX15_Pos 7U /*!< CAPR1: NX15 Position */
#define CAPR1_NX15_Msk (0x1UL << CAPR1_NX15_Pos) /*!< CAPR1: NX15 Mask */
#define CAPR1_NX14_Pos 6U /*!< CAPR1: NX14 Position */
#define CAPR1_NX14_Msk (0x1UL << CAPR1_NX14_Pos) /*!< CAPR1: NX14 Mask */
#define CAPR1_NX13_Pos 5U /*!< CAPR1: NX13 Position */
#define CAPR1_NX13_Msk (0x1UL << CAPR1_NX13_Pos) /*!< CAPR1: NX13 Mask */
#define CAPR1_NX12_Pos 4U /*!< CAPR1: NX12 Position */
#define CAPR1_NX12_Msk (0x1UL << CAPR1_NX12_Pos) /*!< CAPR1: NX12 Mask */
#define CAPR1_NX11_Pos 3U /*!< CAPR1: NX11 Position */
#define CAPR1_NX11_Msk (0x1UL << CAPR1_NX11_Pos) /*!< CAPR1: NX11 Mask */
#define CAPR1_NX10_Pos 2U /*!< CAPR1: NX10 Position */
#define CAPR1_NX10_Msk (0x1UL << CAPR1_NX10_Pos) /*!< CAPR1: NX10 Mask */
#define CAPR1_NX9_Pos 1U /*!< CAPR1: NX9 Position */
#define CAPR1_NX9_Msk (0x1UL << CAPR1_NX9_Pos) /*!< CAPR1: NX9 Mask */
#define CAPR1_NX8_Pos 0U /*!< CAPR1: NX8 Position */
#define CAPR1_NX8_Msk (0x1UL << CAPR1_NX8_Pos) /*!< CAPR1: NX8 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t base_addr: 26; /*!< bit: 6..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 6U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0x3FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 4; /*!< bit: 0.. 3 Protected area index value */
uint32_t _reserved0: 28; /*!< bit: 2..28 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for accessing protection area selection register(ATTR0,CR<26,0>).
*/
typedef union {
struct {
uint32_t Attr0_reserved: 1; /*!< bit: 0 Reserved */
uint32_t Attr0_B: 1; /*!< bit: 1 Bufferable attribute setting */
uint32_t Attr0_SO: 1; /*!< bit: 2 Strong-Order attribute setting */
uint32_t Attr0_C: 1; /*!< bit: 3 Cacheable attribute setting */
uint32_t Attr1_reserved: 1; /*!< bit: 4 Reserved */
uint32_t Attr1_B: 1; /*!< bit: 5 Bufferable attribute setting */
uint32_t Attr1_SO: 1; /*!< bit: 6 Strong-Order attribute setting */
uint32_t Attr1_C: 1; /*!< bit: 7 Cacheable attribute setting */
uint32_t Attr2_reserved: 1; /*!< bit: 8 Reserved */
uint32_t Attr2_B: 1; /*!< bit: 9 Bufferable attribute setting */
uint32_t Attr2_SO: 1; /*!< bit: 10 Strong-Order attribute setting */
uint32_t Attr2_C: 1; /*!< bit: 11 Bufferable attribute setting */
uint32_t Attr3_reserved: 1; /*!< bit: 12 Reserved */
uint32_t Attr3_B: 1; /*!< bit: 13 Bufferable attribute setting */
uint32_t Attr3_SO: 1; /*!< bit: 14 Strong-Order attribute setting */
uint32_t Attr3_C: 1; /*!< bit: 15 Bufferable attribute setting */
uint32_t Attr4_reserved: 1; /*!< bit: 16 Reserved */
uint32_t Attr4_B: 1; /*!< bit: 17 Bufferable attribute setting */
uint32_t Attr4_SO: 1; /*!< bit: 18 Strong-Order attribute setting */
uint32_t Attr4_C: 1; /*!< bit: 19 Bufferable attribute setting */
uint32_t Attr5_reserved: 1; /*!< bit: 20 Reserved */
uint32_t Attr5_B: 1; /*!< bit: 21 Bufferable attribute setting */
uint32_t Attr5_SO: 1; /*!< bit: 22 Strong-Order attribute setting */
uint32_t Attr5_C: 1; /*!< bit: 23 Bufferable attribute setting */
uint32_t Attr6_reserved: 1; /*!< bit: 24 Reserved */
uint32_t Attr6_B: 1; /*!< bit: 25 Bufferable attribute setting */
uint32_t Attr6_SO: 1; /*!< bit: 26 Strong-Order attribute setting */
uint32_t Attr6_C: 1; /*!< bit: 27 Bufferable attribute setting */
uint32_t Attr7_reserved: 1; /*!< bit: 28 Reserved */
uint32_t Attr7_B: 1; /*!< bit: 29 Bufferable attribute setting */
uint32_t Attr7_SO: 1; /*!< bit: 30 Strong-Order attribute setting */
uint32_t Attr7_C: 1; /*!< bit: 31 Bufferable attribute setting */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ATTR0_Type;
/* ATTR0 Register Definitions */
#define ATTR0_RESERVED_Pos 0U /*!< ATTR0: RESERVED Position */
#define ATTR0_RESERVED_Msk (0x1UL << ATTR0_RESERVED_Pos) /*!< ATTR0: RESERVED Mask */
#define ATTR0_B_Pos 1U /*!< ATTR0: BUFFERABLE Position */
#define ATTR0_B_Msk (0x1UL << ATTR0_B_Pos) /*!< ATTR0: BUFFERABLE Mask */
#define ATTR0_SO_Pos 2U /*!< ATTR0: STRONG-ORDER Position */
#define ATTR0_SO_Msk (0x1UL << ATTR0_SO_Pos) /*!< ATTR0: STRONG-ORDER Mask */
#define ATTR0_C_Pos 3U /*!< ATTR0: CACHEABLE Position */
#define ATTR0_C_Msk (0x1UL << ATTR0_C_Pos) /*!< ATTR0: CACHEABLE Mask */
#define ATTR1_RESERVED_Pos 4U /*!< ATTR1: RESERVED Position */
#define ATTR1_RESERVED_Msk (0x1UL << ATTR1_RESERVED_Pos) /*!< ATTR1: RESERVED Mask */
#define ATTR1_B_Pos 5U /*!< ATTR1: BUFFERABLE Position */
#define ATTR1_B_Msk (0x1UL << ATTR1_B_Pos) /*!< ATTR1: BUFFERABLE Mask */
#define ATTR1_SO_Pos 6U /*!< ATTR1: STRONG-ORDER Position */
#define ATTR1_SO_Msk (0x1UL << ATTR1_SO_Pos) /*!< ATTR1: STRONG-ORDER Mask */
#define ATTR1_C_Pos 7U /*!< ATTR1: CACHEABLE Position */
#define ATTR1_C_Msk (0x1UL << ATTR1_C_Pos) /*!< ATTR1: CACHEABLE Mask */
#define ATTR2_RESERVED_Pos 8U /*!< ATTR2: RESERVED Position */
#define ATTR2_RESERVED_Msk (0x1UL << ATTR2_RESERVED_Pos) /*!< ATTR2: RESERVED Mask */
#define ATTR2_B_Pos 9U /*!< ATTR2: BUFFERABLE Position */
#define ATTR2_B_Msk (0x1UL << ATTR2_B_Pos) /*!< ATTR2: BUFFERABLE Mask */
#define ATTR2_SO_Pos 10U /*!< ATTR2: STRONG-ORDER Position */
#define ATTR2_SO_Msk (0x1UL << ATTR2_SO_Pos) /*!< ATTR2: STRONG-ORDER Mask */
#define ATTR2_C_Pos 11U /*!< ATTR2: CACHEABLE Position */
#define ATTR2_C_Msk (0x1UL << ATTR2_C_Pos) /*!< ATTR2: CACHEABLE Mask */
#define ATTR3_RESERVED_Pos 12U /*!< ATTR3: RESERVED Position */
#define ATTR3_RESERVED_Msk (0x1UL << ATTR3_RESERVED_Pos) /*!< ATTR3: RESERVED Mask */
#define ATTR3_B_Pos 13U /*!< ATTR3: BUFFERABLE Position */
#define ATTR3_B_Msk (0x1UL << ATTR3_B_Pos) /*!< ATTR3: BUFFERABLE Mask */
#define ATTR3_SO_Pos 14U /*!< ATTR3: STRONG-ORDER Position */
#define ATTR3_SO_Msk (0x1UL << ATTR3_SO_Pos) /*!< ATTR3: STRONG-ORDER Mask */
#define ATTR3_C_Pos 15U /*!< ATTR3: CACHEABLE Position */
#define ATTR3_C_Msk (0x1UL << ATTR3_C_Pos) /*!< ATTR3: CACHEABLE Mask */
#define ATTR4_RESERVED_Pos 16U /*!< ATTR4: RESERVED Position */
#define ATTR4_RESERVED_Msk (0x1UL << ATTR4_RESERVED_Pos) /*!< ATTR4: RESERVED Mask */
#define ATTR4_B_Pos 17U /*!< ATTR4: BUFFERABLE Position */
#define ATTR4_B_Msk (0x1UL << ATTR4_B_Pos) /*!< ATTR4: BUFFERABLE Mask */
#define ATTR4_SO_Pos 18U /*!< ATTR4: STRONG-ORDER Position */
#define ATTR4_SO_Msk (0x1UL << ATTR4_SO_Pos /*!< ATTR4: STRONG-ORDER Mask */
#define ATTR4_C_Pos 19U /*!< ATTR4: CACHEABLE Position */
#define ATTR4_C_Msk (0x1UL << ATTR4_C_Pos) /*!< ATTR4: CACHEABLE Mask */
#define ATTR5_RESERVED_Pos 20U /*!< ATTR5: RESERVED Position */
#define ATTR5_RESERVED_Msk (0x1UL << ATTR5_RESERVED_Pos) /*!< ATTR5: RESERVED Mask */
#define ATTR5_B_Pos 21U /*!< ATTR5: BUFFERABLE Position */
#define ATTR5_B_Msk (0x1UL << ATTR5_B_Pos) /*!< ATTR5: BUFFERABLE Mask */
#define ATTR5_SO_Pos 22U /*!< ATTR5: STRONG-ORDER Position */
#define ATTR5_SO_Msk (0x1UL << ATTR5_SO_Pos) /*!< ATTR5: STRONG-ORDER Mask */
#define ATTR5_C_Pos 23U /*!< ATTR5: CACHEABLE Position */
#define ATTR5_C_Msk (0x1UL << ATTR5_C_Pos) /*!< ATTR5: CACHEABLE Mask */
#define ATTR6_RESERVED_Pos 24U /*!< ATTR6: RESERVED Position */
#define ATTR6_RESERVED_Msk (0x1UL << ATTR6_RESERVED_Pos) /*!< ATTR6: RESERVED Mask */
#define ATTR6_B_Pos 25U /*!< ATTR6: BUFFERABLE Position */
#define ATTR6_B_Msk (0x1UL << ATTR6_B_Pos) /*!< ATTR6: BUFFERABLE Mask */
#define ATTR6_SO_Pos 26U /*!< ATTR6: STRONG-ORDER Position */
#define ATTR6_SO_Msk (0x1UL << ATTR6_SO_Pos) /*!< ATTR6: STRONG-ORDER Mask */
#define ATTR6_C_Pos 27U /*!< ATTR6: CACHEABLE Position */
#define ATTR6_C_Msk (0x1UL << ATTR6_C_Pos) /*!< ATTR6: CACHEABLE Mask */
#define ATTR7_RESERVED_Pos 28U /*!< ATTR7: RESERVED Position */
#define ATTR7_RESERVED_Msk (0x1UL << ATTR7_RESERVED_Pos) /*!< ATTR7: RESERVED Mask */
#define ATTR7_B_Pos 29U /*!< ATTR7: BUFFERABLE Position */
#define ATTR7_B_Msk (0x1UL << ATTR7_B_Pos) /*!< ATTR7: BUFFERABLE Mask */
#define ATTR7_SO_Pos 30U /*!< ATTR7: STRONG-ORDER Position */
#define ATTR7_SO_Msk (0x1UL << ATTR7_SO_Pos) /*!< ATTR7: STRONG-ORDER Mask */
#define ATTR7_C_Pos 31U /*!< ATTR7: CACHEABLE Position */
#define ATTR7_C_Msk (0x1UL << ATTR7_C_Pos) /*!< ATTR7: CACHEABLE Mask */
/**
\brief Consortium definition for accessing protection area selection register(ATTR1,CR<27,0>).
*/
typedef union {
struct {
uint32_t Attr8_reserved: 1; /*!< bit: 0 Reserved */
uint32_t Attr8_B: 1; /*!< bit: 1 Bufferable attribute setting */
uint32_t Attr8_SO: 1; /*!< bit: 2 Strong-Order attribute setting */
uint32_t Attr8_C: 1; /*!< bit: 3 Cacheable attribute setting */
uint32_t Attr9_reserved: 1; /*!< bit: 4 Reserved */
uint32_t Attr9_B: 1; /*!< bit: 5 Bufferable attribute setting */
uint32_t Attr9_SO: 1; /*!< bit: 6 Strong-Order attribute setting */
uint32_t Attr9_C: 1; /*!< bit: 7 Cacheable attribute setting */
uint32_t Attr10_reserved: 1; /*!< bit: 8 Reserved */
uint32_t Attr10_B: 1; /*!< bit: 9 Bufferable attribute setting */
uint32_t Attr10_SO: 1; /*!< bit: 10 Strong-Order attribute setting */
uint32_t Attr10_C: 1; /*!< bit: 11 Bufferable attribute setting */
uint32_t Attr11_reserved: 1; /*!< bit: 12 Reserved */
uint32_t Attr11_B: 1; /*!< bit: 13 Bufferable attribute setting */
uint32_t Attr11_SO: 1; /*!< bit: 14 Strong-Order attribute setting */
uint32_t Attr11_C: 1; /*!< bit: 15 Bufferable attribute setting */
uint32_t Attr12_reserved: 1; /*!< bit: 16 Reserved */
uint32_t Attr12_B: 1; /*!< bit: 17 Bufferable attribute setting */
uint32_t Attr12_SO: 1; /*!< bit: 18 Strong-Order attribute setting */
uint32_t Attr12_C: 1; /*!< bit: 19 Bufferable attribute setting */
uint32_t Attr13_reserved: 1; /*!< bit: 20 Reserved */
uint32_t Attr13_B: 1; /*!< bit: 21 Bufferable attribute setting */
uint32_t Attr13_SO: 1; /*!< bit: 22 Strong-Order attribute setting */
uint32_t Attr13_C: 1; /*!< bit: 23 Bufferable attribute setting */
uint32_t Attr14_reserved: 1; /*!< bit: 24 Reserved */
uint32_t Attr14_B: 1; /*!< bit: 25 Bufferable attribute setting */
uint32_t Attr14_SO: 1; /*!< bit: 26 Strong-Order attribute setting */
uint32_t Attr14_C: 1; /*!< bit: 27 Bufferable attribute setting */
uint32_t Attr15_reserved: 1; /*!< bit: 28 Reserved */
uint32_t Attr15_B: 1; /*!< bit: 29 Bufferable attribute setting */
uint32_t Attr15_SO: 1; /*!< bit: 30 Strong-Order attribute setting */
uint32_t Attr15_C: 1; /*!< bit: 31 Bufferable attribute setting */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ATTR1_Type;
/* ATTR0 Register Definitions */
#define ATTR8_RESERVED_Pos 0U /*!< ATTR8: RESERVED Position */
#define ATTR8_RESERVED_Msk (0x1UL << ATTR8_RESERVED_Pos) /*!< ATTR8: RESERVED Mask */
#define ATTR8_B_Pos 1U /*!< ATTR8: BUFFERABLE Position */
#define ATTR8_B_Msk (0x1UL << ATTR8_B_Pos) /*!< ATTR8: BUFFERABLE Mask */
#define ATTR8_SO_Pos 2U /*!< ATTR8: STRONG-ORDER Position */
#define ATTR8_SO_Msk (0x1UL << ATTR8_SO_Pos) /*!< ATTR8: STRONG-ORDER Mask */
#define ATTR8_C_Pos 3U /*!< ATTR8: CACHEABLE Position */
#define ATTR8_C_Msk (0x1UL << ATTR8_C_Pos) /*!< ATTR8: CACHEABLE Mask */
#define ATTR9_RESERVED_Pos 4U /*!< ATTR9: RESERVED Position */
#define ATTR9_RESERVED_Msk (0x1UL << ATTR9_RESERVED_Pos) /*!< ATTR9: RESERVED Mask */
#define ATTR9_B_Pos 5U /*!< ATTR9: BUFFERABLE Position */
#define ATTR9_B_Msk (0x1UL << ATTR9_B_Pos) /*!< ATTR9: BUFFERABLE Mask */
#define ATTR9_SO_Pos 6U /*!< ATTR9: STRONG-ORDER Position */
#define ATTR9_SO_Msk (0x1UL << ATTR9_SO_Pos) /*!< ATTR9: STRONG-ORDER Mask */
#define ATTR9_C_Pos 7U /*!< ATTR9: CACHEABLE Position */
#define ATTR9_C_Msk (0x1UL << ATTR9_C_Pos) /*!< ATTR9: CACHEABLE Mask */
#define ATTR10_RESERVED_Pos 8U /*!< ATTR10: RESERVED Position */
#define ATTR10_RESERVED_Msk (0x1UL << ATTR10_RESERVED_Pos) /*!< ATTR10: RESERVED Mask */
#define ATTR10_B_Pos 9U /*!< ATTR10: BUFFERABLE Position */
#define ATTR10_B_Msk (0x1UL << ATTR10_B_Pos) /*!< ATTR10: BUFFERABLE Mask */
#define ATTR10_SO_Pos 10U /*!< ATTR10: STRONG-ORDER Position */
#define ATTR10_SO_Msk (0x1UL << ATTR10_SO_Pos) /*!< ATTR10: STRONG-ORDER Mask */
#define ATTR10_C_Pos 11U /*!< ATTR10: CACHEABLE Position */
#define ATTR10_C_Msk (0x1UL << ATTR10_C_Pos) /*!< ATTR10: CACHEABLE Mask */
#define ATTR11_RESERVED_Pos 12U /*!< ATTR11: RESERVED Position */
#define ATTR11_RESERVED_Msk (0x1UL << ATTR11_RESERVED_Pos) /*!< ATTR11: RESERVED Mask */
#define ATTR11_B_Pos 13U /*!< ATTR11: BUFFERABLE Position */
#define ATTR11_B_Msk (0x1UL << ATTR11_B_Pos) /*!< ATTR11: BUFFERABLE Mask */
#define ATTR11_SO_Pos 14U /*!< ATTR11: STRONG-ORDER Position */
#define ATTR11_SO_Msk (0x1UL << ATTR11_SO_Pos) /*!< ATTR11: STRONG-ORDER Mask */
#define ATTR11_C_Pos 15U /*!< ATTR11: CACHEABLE Position */
#define ATTR11_C_Msk (0x1UL << ATTR11_C_Pos) /*!< ATTR11: CACHEABLE Mask */
#define ATTR12_RESERVED_Pos 16U /*!< ATTR12: RESERVED Position */
#define ATTR12_RESERVED_Msk (0x1UL << ATTR12_RESERVED_Pos) /*!< ATTR12: RESERVED Mask */
#define ATTR12_B_Pos 17U /*!< ATTR12: BUFFERABLE Position */
#define ATTR12_B_Msk (0x1UL << ATTR12_B_Pos) /*!< ATTR12: BUFFERABLE Mask */
#define ATTR12_SO_Pos 18U /*!< ATTR12: STRONG-ORDER Position */
#define ATTR12_SO_Msk (0x1UL << ATTR12_SO_Pos /*!< ATTR12: STRONG-ORDER Mask */
#define ATTR12_C_Pos 19U /*!< ATTR12: CACHEABLE Position */
#define ATTR12_C_Msk (0x1UL << ATTR12_C_Pos) /*!< ATTR12: CACHEABLE Mask */
#define ATTR13_RESERVED_Pos 20U /*!< ATTR13: RESERVED Position */
#define ATTR13_RESERVED_Msk (0x1UL << ATTR13_RESERVED_Pos) /*!< ATTR13: RESERVED Mask */
#define ATTR13_B_Pos 21U /*!< ATTR13: BUFFERABLE Position */
#define ATTR13_B_Msk (0x1UL << ATTR13_B_Pos) /*!< ATTR13: BUFFERABLE Mask */
#define ATTR13_SO_Pos 22U /*!< ATTR13: STRONG-ORDER Position */
#define ATTR13_SO_Msk (0x1UL << ATTR13_SO_Pos) /*!< ATTR13: STRONG-ORDER Mask */
#define ATTR13_C_Pos 23U /*!< ATTR13: CACHEABLE Position */
#define ATTR13_C_Msk (0x1UL << ATTR13_C_Pos) /*!< ATTR13: CACHEABLE Mask */
#define ATTR14_RESERVED_Pos 24U /*!< ATTR14: RESERVED Position */
#define ATTR14_RESERVED_Msk (0x1UL << ATTR14_RESERVED_Pos) /*!< ATTR14: RESERVED Mask */
#define ATTR14_B_Pos 25U /*!< ATTR14: BUFFERABLE Position */
#define ATTR14_B_Msk (0x1UL << ATTR14_B_Pos) /*!< ATTR14: BUFFERABLE Mask */
#define ATTR14_SO_Pos 26U /*!< ATTR14: STRONG-ORDER Position */
#define ATTR14_SO_Msk (0x1UL << ATTR14_SO_Pos) /*!< ATTR14: STRONG-ORDER Mask */
#define ATTR14_C_Pos 27U /*!< ATTR14: CACHEABLE Position */
#define ATTR14_C_Msk (0x1UL << ATTR14_C_Pos) /*!< ATTR14: CACHEABLE Mask */
#define ATTR15_RESERVED_Pos 28U /*!< ATTR15: RESERVED Position */
#define ATTR15_RESERVED_Msk (0x1UL << ATTR15_RESERVED_Pos) /*!< ATTR15: RESERVED Mask */
#define ATTR15_B_Pos 29U /*!< ATTR15: BUFFERABLE Position */
#define ATTR15_B_Msk (0x1UL << ATTR15_B_Pos) /*!< ATTR15: BUFFERABLE Mask */
#define ATTR15_SO_Pos 30U /*!< ATTR15: STRONG-ORDER Position */
#define ATTR15_SO_Msk (0x1UL << ATTR15_SO_Pos) /*!< ATTR15: STRONG-ORDER Mask */
#define ATTR15_C_Pos 31U /*!< ATTR15: CACHEABLE Position */
#define ATTR15_C_Msk (0x1UL << ATTR15_C_Pos) /*!< ATTR15: CACHEABLE Mask */
/* CCR2 Register Definitions */
#define CCR2_CRECC_Pos 7U /*!< CCR2: CRECC Position */
#define CCR2_CRECC_Msk (0x1UL << CCR2_CRECC_Pos) /*!< CCR2: CRECC Mask */
#define CCR2_ECC_Pos 6U /*!< CCR2: ECC Position */
#define CCR2_ECC_Msk (0x1UL << CCR2_ECC_Pos) /*!< CCR2: ECC Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_tcm_register
\defgroup CSI_TCM
\brief Type definitions for the tcm Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(ITCMCR,CR<22,1>).
*/
typedef union {
struct {
uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */
uint32_t _reserved0: 1; /*!< bit: 1 Reserved */
uint32_t SIF: 1; /*!< bit: 2 Slave interface access ITCM */
uint32_t _reserved1: 1; /*!< bit: 3 Reserved */
uint32_t Size: 4; /*!< bit: 4..7 Size of ITCM */
uint32_t _reserved2: 1; /*!< bit: 8 Reserved */
uint32_t Delay: 1; /*!< bit: 9 The time from access ITCM to data come back. */
uint32_t _reserved3: 2; /*!< bit: 10..11 Reserved */
uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ITCMCR_Type;
#define ITCMCR_Base_Address_Pos 12U /*!< ITCMCR: Base_Address Position */
#define ITCMCR_Base_Address_Msk (0xfffffUL << ITCMCR_Base_Address_Pos) /*!< ITCMCR: Base_Address Mask */
#define ITCMCR_Delay_Pos 9U /*!< ITCMCR: Delay Position */
#define ITCMCR_Delay_Msk (0x1UL << ITCMCR_Delay_Pos) /*!< ITCMCR: Delay Mask */
#define ITCMCR_Size_Pos 4U /*!< ITCMCR: Size Position */
#define ITCMCR_Size_Msk (0xfUL << ITCMCR_Size_Pos) /*!< ITCMCR: Size Mask */
#define ITCMCR_SIF_Pos 2U /*!< ITCMCR: SIF Position */
#define ITCMCR_SIF_Msk (0x1UL << ITCMCR_SIF_Pos) /*!< ITCMCR: SIF Mask */
#define ITCMCR_EN_Pos 0U /*!< ITCMCR: EN Position */
#define ITCMCR_EN_Msk (0x1UL << ITCMCR_EN_Pos) /*!< ITCMCR: EN Mask */
/**
\brief Consortium definition for accessing protection area selection register(DTCMCR,CR<23,1>).
*/
typedef union {
struct {
uint32_t EN: 1; /*!< bit: 0 Data Tightly-Coupled Memory enable */
uint32_t _reserved0: 1; /*!< bit: 1 Reserved */
uint32_t SIF: 1; /*!< bit: 2 Slave interface access DTCM */
uint32_t _reserved1: 1; /*!< bit: 3 Reserved */
uint32_t Size: 4; /*!< bit: 4..7 Size of DTCM */
uint32_t _reserved2: 1; /*!< bit: 8 Reserved */
uint32_t Delay: 1; /*!< bit: 9 The time from access DTCM to data come back.*/
uint32_t _reserved3: 2; /*!< bit: 10..11 Reserved */
uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} DTCMCR_Type;
#define DTCMCR_Base_Address_Pos 12U /*!< DTCMCR: Base_Address Position */
#define DTCMCR_Base_Address_Msk (0xfffffUL << DTCMCR_Base_Address_Pos) /*!< DTCMCR: Base_Address Mask */
#define DTCMCR_Delay_Pos 9U /*!< DTCMCR: Delay Position */
#define DTCMCR_Delay_Msk (0x1UL << DTCMCR_Delay_Pos) /*!< DTCMCR: Delay Mask */
#define DTCMCR_Size_Pos 4U /*!< DTCMCR: Size Position */
#define DTCMCR_Size_Msk (0xfUL << DTCMCR_Size_Pos) /*!< DTCMCR: Size Mask */
#define DTCMCR_SIF_Pos 2U /*!< DTCMCR: SIF Position */
#define DTCMCR_SIF_Msk (0x1UL << DTCMCR_SIF_Pos) /*!< DTCMCR: SIF Mask */
#define DTCMCR_EN_Pos 0U /*!< DTCMCR: EN Position */
#define DTCMCR_EN_Msk (0x1UL << DTCMCR_EN_Pos) /*!< DTCMCR: EN Mask */
/*@} end of group CSI_TCM_bitfield */
/**
\ingroup CSI_ECC_register
\defgroup CSI_ECC
\brief Type definitions for the ECC Registers
@{
*/
typedef union {
struct {
uint32_t Index: 17; /*!< bit: 0..16 RAM index */
uint32_t _reserved0: 1; /*!< bit: 2..23 Reserved */
uint32_t Way: 2; /*!< bit: 18..19 ICACHE/DCACHE WAY */
uint32_t _reserved1: 2; /*!< bit: 20..21 Reserved */
uint32_t RAMID: 8; /*!< bit: 22..29 ECC RAM ID */
uint32_t ERR_TYPE: 2; /*!< bit: 30..31 ECC ERR TYPE */
} b;
uint32_t w;
} ERRLC_Type;
#define ERRLC_ERR_TYPE_Pos 30U /*!< ERRLC: ERR_TYPE Position */
#define ERRLC_ERR_TYPE_Msk (0x3UL << ERRLC_ERR_TYPE_Pos) /*!< ERRLC: ERR_TYPE Mask */
#define ERRLC_RAMID_Pos 22U /*!< ERRLC: RAMID Position */
#define ERRLC_RAMID_Msk (0xFFUL << ERRLC_RAMID_Pos) /*!< ERRLC: RAMID Mask */
#define ERRLC_Way_Pos 18U /*!< ERRLC: Way Position */
#define ERRLC_Way_Msk (0x3UL << ERRLC_Way_Pos) /*!< ERRLC: Way Mask */
#define ERRLC_Index_Pos 0U /*!< ERRLC: Index Position */
#define ERRLC_Index_Msk (0x1FFFFUL << ERRLC_Index_Pos) /*!< ERRLC: Index Mask */
typedef union {
struct {
uint32_t INJ_EN: 1; /*!< bit: 0 ECC inject enable */
uint32_t ERR_TYPE: 1; /*!< bit: 1 ECC error type */
uint32_t _reserved0: 22; /*!< bit: 2..23 Reserved */
uint32_t RAMID: 8; /*!< bit: 24..31 ECC RAMID */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} ERRINJCR_Type;
#define ERRINJCR_RAMID_Pos 24U /*!< ERRINJCR: RAMID Position */
#define ERRINJCR_RAMID_Msk (0xFFUL << ERRINJCR_RAMID_Pos) /*!< ERRINJCR: RAMID Mask */
#define ERRINJCR_ERR_TYPE_Pos 1U /*!< ERRINJCR: ERR_TYPE Position */
#define ERRINJCR_ERR_TYPE_Msk (0x1UL << ERRINJCR_ERR_TYPE_Pos) /*!< ERRINJCR: ERR_TYPE Mask */
#define ERRINJCR_INJ_EN_Pos 0U /*!< ERRINJCR: INJ_EN Position */
#define ERRINJCR_INJ_EN_Msk (0x1UL << ERRINJCR_INJ_EN_Pos) /*!< ERRINJCR: INJ_EN Mask */
/*@} end of group CSI_ECC_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_128B = 0x6,
REGION_SIZE_256B = 0x7,
REGION_SIZE_512B = 0x8,
REGION_SIZE_1KB = 0x9,
REGION_SIZE_2KB = 0xA,
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
uint32_t nx: 1;
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t s: 1;
uint32_t c: 1; /* cacheable */
uint32_t so: 1;
uint32_t b: 1;
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
uint32_t op_idx;
if (idx > 15) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
ATTR0_Type reg_attr;
if (idx <= 7) {
capr.w = __get_CAPR();
reg_attr.w = __get_ATTR0();
op_idx = idx;
} else {
capr.w = __get_CAPR1();
reg_attr.w = __get_ATTR1();
op_idx = idx - 8;
}
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.w = (base_addr & PACR_BASE_ADDR_Msk) | (size << PACR_SIZE_Pos);
pacr.w &= ~(((1u << (size - 6)) - 1) << 7);
pacr.b.E = enable;
prsr.b.RID = idx;
__set_PRSR(prsr.w);
capr.w &= ~((0x1 << op_idx) | (0x3 << (op_idx * 2 + 8)) | (0x1 << (op_idx + 24)));
capr.w = (capr.w | (attr.nx << op_idx) | (attr.ap << (op_idx * 2 + 8)) | (attr.s << (op_idx + 24)));
reg_attr.w &= ~(0x7 << (op_idx << 2));
reg_attr.w |= ((attr.c | (attr.so << 1) | (attr.b << 2)) << (op_idx << 2));
if (idx <= 7) {
__set_CAPR(capr.w);
__set_ATTR0(reg_attr.w);
} else {
__set_CAPR1(capr.w);
__set_ATTR1(reg_attr.w);
}
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 15) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 15) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MPUFunctions */
/* ########################## TCM functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_TCMFunctions TCM Functions
\brief Functions that configure TCM.
@{
*/
/**
\brief Enable ITCM
\details Turns on ITCM
*/
__STATIC_INLINE void csi_itcm_enable (void)
{
__set_ITCMCR(__get_ITCMCR() | ITCMCR_EN_Msk);
}
/**
\brief Enable DTCM
\details Turns on DTCM
*/
__STATIC_INLINE void csi_dtcm_enable (void)
{
__set_DTCMCR(__get_DTCMCR() | DTCMCR_EN_Msk);
}
/**
\brief Enable ITCM
\details Turns on ITCM
*/
__STATIC_INLINE void csi_itcm_disable (void)
{
__set_ITCMCR(__get_ITCMCR() & (~ITCMCR_EN_Msk));
}
/**
\brief Enable DTCM
\details Turns on DTCM
*/
__STATIC_INLINE void csi_dtcm_disable (void)
{
__set_DTCMCR(__get_DTCMCR() & (~DTCMCR_EN_Msk));
}
/**
\brief Enable ITCM slave interface access
\details Enable ITCM slave interface access
*/
__STATIC_INLINE void csi_itcm_enable_slave_access(void)
{
__set_ITCMCR(__get_ITCMCR() | ITCMCR_SIF_Msk);
}
/**
\brief Disable ITCM slave interface access
\details Disable ITCM slave interface access
*/
__STATIC_INLINE void csi_itcm_disable_slave_access(void)
{
__set_ITCMCR(__get_ITCMCR() & (~ITCMCR_SIF_Msk));
}
/**
\brief Enable DTCM slave interface access
\details Enable DTCM slave interface access
*/
__STATIC_INLINE void csi_dtcm_enable_slave_access(void)
{
__set_DTCMCR(__get_DTCMCR() | DTCMCR_SIF_Msk);
}
/**
\brief Disable DTCM slave interface access
\details Disable DTCM slave interface access
*/
__STATIC_INLINE void csi_dtcm_disable_slave_access(void)
{
__set_DTCMCR(__get_DTCMCR() & (~DTCMCR_SIF_Msk));
}
/**
\brief Get ITCM Size
\details Get ITCM Size
\return ITCM size (bytes).
*/
__STATIC_INLINE uint32_t csi_itcm_get_size(void)
{
ITCMCR_Type sizemask;
uint32_t ret;
sizemask.w = __get_ITCMCR();
ret = sizemask.b.Size;
return (1 << ret) << 10;
}
/**
\brief Get DTCM Size
\details Get DTCM Size
\return DTCM size (bytes).
*/
__STATIC_INLINE uint32_t csi_dtcm_get_size(void)
{
DTCMCR_Type sizemask;
uint32_t ret;
sizemask.w = __get_DTCMCR();
ret = sizemask.b.Size;
return (1 << ret) << 10;
}
/**
\brief Get ITCM Delay
\details Get ITCM Delay
\return delay time.
*/
__STATIC_INLINE uint32_t csi_itcm_get_delay(void)
{
ITCMCR_Type delaymask;
uint32_t ret;
delaymask.w = __get_ITCMCR();
ret = delaymask.b.Delay;
return ret;
}
/**
\brief Get DTCM Delay
\details Get DTCM Delay
\return delay time.
*/
__STATIC_INLINE uint32_t csi_dtcm_get_delay(void)
{
DTCMCR_Type delaymask;
uint32_t ret;
delaymask.w = __get_DTCMCR();
ret = delaymask.b.Delay;
return ret;
}
/**
\brief Set ITCM Base Address
\details Set ITCM Base Address
\param [in] base_addr itcm base address.
*/
__STATIC_INLINE void csi_itcm_set_base_addr(uint32_t base_addr)
{
__set_ITCMCR((__get_ITCMCR() & (~ITCMCR_Base_Address_Msk)) | (base_addr & ITCMCR_Base_Address_Msk));
}
/**
\brief Set DTCM Base Address
\details Set DTCM Base Address
\param [in] base_addr dtcm base address.
*/
__STATIC_INLINE void csi_dtcm_set_base_addr(uint32_t base_addr)
{
__set_DTCMCR((__get_DTCMCR() & (~DTCMCR_Base_Address_Msk)) | (base_addr & DTCMCR_Base_Address_Msk));
}
/*@} end of CSI_Core_TCMFunctions */
/* ########################## ECC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_ECCFunctions ECC Functions
\brief Functions that configure ECC.
@{
*/
typedef enum {
ECC_ERROR_CORRECTABLE = 0,
ECC_ERROR_FATAL = 1
} ecc_error_type_e;
typedef enum {
ECC_DTCM_RAM = 0,
ECC_ITCM_RAM = 1,
ECC_DCACHE_DATA_RAM = 4,
ECC_DCACHE_TAG_RAM = 5,
ECC_ICACHE_DATA_RAM = 6,
ECC_ICACHE_TAG_RAM = 7
} ecc_ramid_e;
typedef struct {
uint32_t erraddr;
uint32_t index;
uint8_t way;
ecc_ramid_e ramid: 8;
ecc_error_type_e err_type: 8;
} ecc_error_info_t;
/**
\brief Enable ECC
\details Turns on ECC
*/
__STATIC_INLINE void csi_ecc_enable (void)
{
__set_CCR2(__get_CCR2() | CCR2_ECC_Msk);
}
/**
\brief Disable ECC
\details Turns off ECC
*/
__STATIC_INLINE void csi_ecc_disable (void)
{
__set_CCR2(__get_CCR2() & ~CCR2_ECC_Msk);
}
/**
\brief Enable ECC error fix function
\details Turns on ECC error fix function
*/
__STATIC_INLINE void csi_ecc_enable_error_fix (void)
{
__set_CCR2(__get_CCR2() | CCR2_CRECC_Msk);
}
/**
\brief Disable ECC error fix function
\details Turns off ECC error fix function
*/
__STATIC_INLINE void csi_ecc_disable_error_fix (void)
{
__set_CCR2(__get_CCR2() & ~CCR2_CRECC_Msk);
}
/**
\brief Inject ECC error
\details Inject ECC error
\param [in] type ECC error type.
\param [in] ramid ECC ram id.
*/
__STATIC_INLINE void csi_ecc_inject_error(ecc_error_type_e type, ecc_ramid_e ramid)
{
ERRINJCR_Type errinjcr;
errinjcr.b.ERR_TYPE = type;
errinjcr.b.RAMID = (1U << ramid);
errinjcr.b.INJ_EN = 1U;
errinjcr.b._reserved0 = 0;
__set_ERRINJCR(errinjcr.w);
}
/**
\brief Get ECC error info
\details Inject ECC error info
\param [out] info ECC error info
*/
__STATIC_INLINE void csi_ecc_get_error_info(ecc_error_info_t *info)
{
ERRLC_Type errlc;
if (info != NULL) {
errlc.w = __get_ERRLC();
info->erraddr = __get_ERRADDR();
info->index = errlc.b.Index;
info->way = errlc.b.Way;
info->ramid = 31 - __FF1(errlc.b.RAMID);
info->err_type = errlc.b.ERR_TYPE;
}
}
/*@} end of CSI_Core_ECCFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_807.h | C | apache-2.0 | 96,525 |
/*
* @file core_810.h
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck810.h
* @brief CSI CK810 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK810_H_GENERIC
#define __CORE_CK810_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK810
@{
*/
/* CSI CK810 definitions */
#define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
__CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK810
#define __CK810 (0x0aU) /*!< CK810 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK810_H_DEPENDANT
#define __CORE_CK810_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK810_REV
#define __CK810_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK810 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK810 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
#define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
#define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_810.h | C | apache-2.0 | 35,462 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck610.h
* @brief CSI CK610 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK610_H_GENERIC
#define __CORE_CK610_H_GENERIC
#include <stdint.h>
#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup Ck610
@{
*/
/* CSI CK610 definitions */
#define __CK610_CSI_VERSION_MAIN (0x01U) /*!< [31:16] CSI HAL main version */
#define __CK610_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK610_CSI_VERSION ((__CK610_CSI_VERSION_MAIN << 16U) | \
__CK610_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#define __CK610 (0x01U) /*!< CK610 Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK610_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK610_H_DEPENDANT
#define __CORE_CK610_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK610_REV
#define __CK610_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK610 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core MGU Register
- Core MMU Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK610 processor based devices.
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t CPID: 4; /*!< bit: 24..27 Number of processor currently running */
uint32_t _reserved3: 3; /*!< bit: 28..30 Reserved */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_CPID_Pos 24U /*!< PSR: CPID Position */
#define PSR_CPID_Msk (0xFUL << PSR_CPID_Pos) /*!< PSR: CPID Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_TM_Pos 14U /*!< PSR: TM Position */
#define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
#define PSR_TP_Pos 13U /*!< PSR: TP Position */
#define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
#define PSR_TE_Pos 12U /*!< PSR: TE Position */
#define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_FE_Pos 4U /*!< PSR: FE Position */
#define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
#define PSR_AF_Pos 1U /*!< PSR: AF Position */
#define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0..1 Memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Endian mode */
uint32_t DE: 1; /*!< bit: 3 Endian mode */
uint32_t WB: 1; /*!< bit: 4 Endian mode */
uint32_t RS: 1; /*!< bit: 5 Endian mode */
uint32_t Z: 1; /*!< bit: 6 Endian mode */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 The clock ratio of the system and the processor */
uint32_t _reserved0: 21; /*!< bit: 11..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x7UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_Z_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_RS_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_WB_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_DE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_IE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
*/
typedef union {
struct {
uint32_t C0: 1; /*!< bit: 0 Cacheable setting */
uint32_t C1: 1; /*!< bit: 1 Cacheable setting */
uint32_t C2: 1; /*!< bit: 2 Cacheable setting */
uint32_t C3: 1; /*!< bit: 3 Cacheable setting */
uint32_t _reserved0: 4; /*!< bit: 4.. 7 Reserved */
uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CAPR_Type;
/* CAPR Register Definitions */
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
/**
\brief Consortium definition for accessing control register(PACR, CR<20,0>).
*/
typedef union {
struct {
uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PACR_Type;
/* PACR Register Definitions */
#define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
#define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
#define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
#define PACR_E_Pos 0U /*!< PACR: E Position */
#define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
/**
\brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
*/
typedef union {
struct {
uint32_t RID: 2; /*!< bit: 0.. 1 Protected area index value */
uint32_t _reserved0: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PRSR_Type;
/* PRSR Register Definitions */
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
#define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CP15_CR0).
*/
typedef union {
struct {
uint32_t Index: 10;
uint32_t _reserved: 20;
uint32_t TF: 1;
uint32_t P: 1;
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
*/
typedef union {
struct {
uint32_t G: 1;
uint32_t V: 1;
uint32_t D: 1;
uint32_t C: 3;
uint32_t PFN: 20;
uint32_t _reserved: 6;
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 6 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x7UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
*/
typedef union {
struct {
uint32_t ASID :8;
uint32_t _reserved :4;
uint32_t VPN :20;
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
*/
typedef union {
struct {
uint32_t _reserved0: 13;
uint32_t page_mask: 12;
uint32_t _reserved1: 7;
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
*/
typedef union {
struct {
uint32_t ASID: 8;
uint32_t _reserved: 17;
uint32_t TLBINV_INDEX: 1;
uint32_t TLBINV_ALL: 1;
uint32_t TLBINV: 1;
uint32_t TLBWR: 1;
uint32_t TLBWI: 1;
uint32_t TLBR: 1;
uint32_t TLBP: 1;
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEL_Type mel;
MEH_Type meh;
uint32_t vaddr_bit = 0;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
pgmask.w = __FF1(__get_MPR());
vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
meh.b.ASID = asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
} else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type mpr;
mpr.w = __get_MPR();
mpr.b.page_mask = size;
__set_MPR(mpr.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ########################## MPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MPUFunctions MPU Functions
\brief Functions that configure MPU.
@{
*/
typedef enum {
REGION_SIZE_4KB = 0xB,
REGION_SIZE_8KB = 0xC,
REGION_SIZE_16KB = 0xD,
REGION_SIZE_32KB = 0xE,
REGION_SIZE_64KB = 0xF,
REGION_SIZE_128KB = 0x10,
REGION_SIZE_256KB = 0x11,
REGION_SIZE_512KB = 0x12,
REGION_SIZE_1MB = 0x13,
REGION_SIZE_2MB = 0x14,
REGION_SIZE_4MB = 0x15,
REGION_SIZE_8MB = 0x16,
REGION_SIZE_16MB = 0x17,
REGION_SIZE_32MB = 0x18,
REGION_SIZE_64MB = 0x19,
REGION_SIZE_128MB = 0x1A,
REGION_SIZE_256MB = 0x1B,
REGION_SIZE_512MB = 0x1C,
REGION_SIZE_1GB = 0x1D,
REGION_SIZE_2GB = 0x1E,
REGION_SIZE_4GB = 0x1F
} region_size_e;
typedef enum {
AP_BOTH_INACCESSIBLE = 0,
AP_SUPER_RW_USER_INACCESSIBLE,
AP_SUPER_RW_USER_RDONLY,
AP_BOTH_RW
} access_permission_e;
typedef struct {
access_permission_e ap: 2; /* super user and normal user access.*/
uint32_t c: 1; /* cacheable */
} mpu_region_attr_t;
/**
\brief enable mpu
\details
*/
__STATIC_INLINE void csi_mpu_enable(void)
{
__set_CCR(__get_CCR() | CCR_MP_Msk);
}
/**
\brief disable mpu
\details
*/
__STATIC_INLINE void csi_mpu_disable(void)
{
__set_CCR(__get_CCR() & (~CCR_MP_Msk));
}
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
if (idx > 3) {
return;
}
CAPR_Type capr;
PACR_Type pacr;
PRSR_Type prsr;
capr.w = __get_CAPR();
pacr.w = __get_PACR();
prsr.w = __get_PRSR();
pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
prsr.b.RID = idx;
__set_PRSR(prsr.w);
if (size != REGION_SIZE_4KB) {
pacr.w &= ~(((1u << (size -11)) - 1) << 12);
}
pacr.b.size = size;
capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
__set_CAPR(capr.w);
pacr.b.E = enable;
__set_PACR(pacr.w);
}
/**
\brief enable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
{
if (idx > 3) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() | PACR_E_Msk);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, 3.).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
if (idx > 3) {
return;
}
__set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
__set_PACR(__get_PACR() & (~PACR_E_Msk));
}
/*@} end of CSI_Core_MMUFunctions */
/*@} */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK610_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_ck610.h | C | apache-2.0 | 35,725 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck801.h
* @brief CSI CK801 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK801_H_GENERIC
#define __CORE_CK801_H_GENERIC
#include <core_801.h>
#endif /* __CORE_CK801_H_DEPENDANT */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_ck801.h | C | apache-2.0 | 526 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck802.h
* @brief CSI CK802 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK802_H_GENERIC
#define __CORE_CK802_H_GENERIC
#include <core_802.h>
#endif /* __CORE_CK802_H_DEPENDANT */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_ck802.h | C | apache-2.0 | 526 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck803.h
* @brief CSI CK803 Core Peripheral Access Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef __CORE_CK803_H_GENERIC
#define __CORE_CK803_H_GENERIC
#include <core_803.h>
#endif /* __CORE_CK803_H_DEPENDANT */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_ck803.h | C | apache-2.0 | 526 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck807.h
* @brief CSI CK807 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK807_H_GENERIC
#define __CORE_CK807_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK807
@{
*/
/* CSI CK807 definitions */
#define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
__CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK807
#define __CK807 (0x07U) /*!< CK807 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK807_H_DEPENDANT
#define __CORE_CK807_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK807_REV
#define __CK807_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK807 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK807 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK807_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_ck807.h | C | apache-2.0 | 33,217 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_ck810.h
* @brief CSI CK810 Core Peripheral Access Layer Header File
* @version V1.0
* @date 26. Jan 2018
******************************************************************************/
#ifndef __CORE_CK810_H_GENERIC
#define __CORE_CK810_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup CK810
@{
*/
/* CSI CK810 definitions */
#define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
#define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
#define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
__CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
#ifndef __CK810
#define __CK810 (0x0aU) /*!< CK810 Core */
#endif
/** __FPU_USED indicates whether an FPU is used or not.
*/
#define __FPU_USED 1U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_CK810_H_DEPENDANT
#define __CORE_CK810_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __CK810_REV
#define __CK810_REV 0x0000U
#endif
#ifndef __GSR_GCR_PRESENT
#define __GSR_GCR_PRESENT 0U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK810 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK810 processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Access Processor Status Register(PSR)struct definition.
*/
typedef union {
struct {
uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
uint32_t T: 1; /*!< bit: 30 TEE mode bit */
uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} PSR_Type;
/* PSR Register Definitions */
#define PSR_S_Pos 31U /*!< PSR: S Position */
#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
#define PSR_MM_Pos 9U /*!< PSR: MM Position */
#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
#define PSR_EE_Pos 8U /*!< PSR: EE Position */
#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
#define PSR_IC_Pos 7U /*!< PSR: IC Position */
#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
#define PSR_IE_Pos 6U /*!< PSR: IE Position */
#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
#define PSR_C_Pos 0U /*!< PSR: C Position */
#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
/**
\brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
*/
typedef union {
struct {
uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
uint32_t DE: 1; /*!< bit: 3 Data cache enable */
uint32_t WB: 1; /*!< bit: 4 Cache write back */
uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
uint32_t BE: 1; /*!< bit: 7 Endian mode */
uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CCR_Type;
/* CCR Register Definitions */
#define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
#define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
#define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
#define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
#define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
#define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
#define CCR_WA_Pos 12u /*!< CCR: WA Position */
#define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
#define CCR_BE_Pos 7U /*!< CCR: BE Position */
#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
#define CCR_Z_Pos 6U /*!< CCR: Z Position */
#define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
#define CCR_RS_Pos 5U /*!< CCR: RS Position */
#define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
#define CCR_WB_Pos 4U /*!< CCR: WB Position */
#define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
#define CCR_DE_Pos 3U /*!< CCR: DE Position */
#define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
#define CCR_IE_Pos 2U /*!< CCR: IE Position */
#define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
#define CCR_MP_Pos 0U /*!< CCR: MP Position */
#define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
/**
\brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
*/
typedef union {
struct {
uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
uint32_t P: 1; /*!< bit: 31 TLBP instruction */
} b;
uint32_t w;
} MIR_Type;
/* MIR Register Definitions */
#define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
#define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
#define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
#define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
#define MIR_Index_Pos 0 /*!< PRSR: Index Position */
#define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
*/
typedef union {
struct {
uint32_t G: 1; /*!< bit: 0 Global enbale bit */
uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
} b;
uint32_t w;
} MEL_Type;
/* MEL Register Definitions */
#define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
#define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
#define MEL_B_Pos 6 /*!< MEL: B Position */
#define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
#define MEL_SO_Pos 5 /*!< MEL: SO Position */
#define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
#define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
#define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
#define MEL_C_Pos 3 /*!< MEL: C Position */
#define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
#define MEL_D_Pos 2 /*!< MEL: D Position */
#define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
#define MEL_V_Pos 1 /*!< MEL: V Position */
#define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
#define MEL_G_Pos 0 /*!< MEL: G Position */
#define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
*/
typedef union {
struct {
uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
} b;
uint32_t w;
} MEH_Type;
/* MEH Register Definitions */
#define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
#define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
#define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
#define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
*/
typedef union {
struct {
uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
} b;
uint32_t w;
} MPR_Type;
/* MPR Register Definitions */
#define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
#define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
/**
\brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
*/
typedef union {
struct {
uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
uint32_t TLBR: 1; /*!< bit: 30 TLBR */
uint32_t TLBP: 1; /*!< bit: 31 TLBP */
} b;
uint32_t w;
} MCIR_Type;
/* MCIR Register Definitions */
#define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
#define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
#define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
#define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
#define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
#define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
#define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
#define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
#define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
#define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
#define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
#define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
#define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
#define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
#define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
#define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
/*@} end of group CSI_CORE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
*/
typedef union {
struct {
uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
} b; /*!< Structure Access by bit */
uint32_t w; /*!< Type Access by whole register */
} CFR_Type;
#define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
#define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
#define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
#define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
#define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
#define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
#define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
#define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
#define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
#define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
#define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
#define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
#define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
#define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
#define CFR_INV_Pos 4U /*!< CFR: INV Position */
#define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
#define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
#define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
/* CFR Register Definitions */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
#define SSEG0_BASE_ADDR 0x80000000
#define CACHE_RANGE_MAX_SIZE 0x80000
#define INS_CACHE (1 << 0)
#define DATA_CACHE (1 << 1)
#define CACHE_INV (1 << 4)
#define CACHE_CLR (1 << 5)
#define CACHE_OMS (1 << 6)
#define CACHE_ITS (1 << 7)
#define CACHE_LICF (1 << 31)
#define L1_CACHE_SHIFT 4 /* 16 Bytes */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000004);
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFFB);
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
__set_CFR(0x11);
__set_CFR(INS_CACHE | CACHE_INV);
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
__set_CCR(__get_CCR() | 0x00000008);
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
__set_CCR(__get_CCR() & 0xFFFFFFF7);
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_INV);
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR);
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
__set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
}
__STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
{
if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
__set_CFR(value);
}
if (value & INS_CACHE) {
csi_icache_disable();
}
uint32_t i;
for (i = start; i < end; i += L1_CACHE_BYTES) {
__set_CIR(i);
__set_CFR(CACHE_OMS | value);
}
if (end & (L1_CACHE_BYTES-1)) {
__set_CIR(end);
__set_CFR(CACHE_OMS | value);
}
if (value & INS_CACHE) {
csi_icache_enable();
}
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
}
/*@} end of CSI_Core_CacheFunctions */
/* ########################## MMU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_MMUFunctions MMU Functions
\brief Functions that configure MMU.
@{
*/
typedef struct {
uint32_t global: 1; /* tlb page global access. */
uint32_t valid: 1; /* tlb page valid */
uint32_t writeable: 1; /* tlb page writeable */
uint32_t cacheable: 1; /* tlb page cacheable*/
uint32_t is_secure: 1; /* tlb page security access */
uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
uint32_t bufferable: 1; /* tlb page bufferable */
} page_attr_t;
typedef enum {
PAGE_SIZE_4KB = 0x000,
PAGE_SIZE_16KB = 0x003,
PAGE_SIZE_64KB = 0x00F,
PAGE_SIZE_256KB = 0x03F,
PAGE_SIZE_1MB = 0x0FF,
PAGE_SIZE_4MB = 0x3FF,
PAGE_SIZE_16MB = 0xFFF
} page_size_e;
/**
\brief enable mmu
\details
*/
__STATIC_INLINE void csi_mmu_enable(void)
{
__set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
}
/**
\brief disable mmu
\details
*/
__STATIC_INLINE void csi_mmu_disable(void)
{
__set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
}
/**
\brief create page with feature.
\details
\param [in] vaddr virtual address.
\param [in] paddr physical address.
\param [in] asid address sapce id (default: 0).
\param [in] attr \ref page_attr_t. tlb page attribute.
*/
__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
{
MPR_Type pgmask;
MEH_Type meh;
MEL_Type mel;
uint32_t vaddr_bit;
uint32_t page_feature = 0;
page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
attr.bufferable << MEL_B_Pos;
pgmask.w = __get_MPR();
vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
meh.b.ASID = (uint8_t)asid;
meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
__set_MEH(meh.w);
__set_MCIR(1u << MCIR_TLBP_Pos);
mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
if (vaddr & (1 << vaddr_bit)) {
__set_MEL1(mel.w);
}
else {
__set_MEL0(mel.w);
}
if (__get_MIR() & (1 << MIR_P_Pos)) {
__set_MCIR(1u << MCIR_TLBWR_Pos);
} else {
__set_MCIR(1u << MCIR_TLBWI_Pos);
}
}
/**
\brief enble mmu
\details
\param [in] size tlb page size.
*/
__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
{
MPR_Type pgmask;
pgmask.b.page_mask = size;
__set_MPR(pgmask.w);
}
/**
\brief read MEH, MEL0, MEL1 by tlb index.
\details
\param [in] index tlb index(0, 1, 2, ...)
\param [out] meh pointer to variable for retrieving MEH.
\param [out] mel0 pointer to variable for retrieving MEL0.
\param [out] mel1 pointer to variable for retrieving MEL1.
*/
__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
{
MIR_Type mir;
if (meh == NULL || mel0 == NULL || mel1 == NULL) {
return;
}
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBR_Pos);
*meh = __get_MEH();
*mel0 = __get_MEL0();
*mel1 = __get_MEL1();
}
/**
\brief flush all mmu tlb.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
{
__set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
}
/**
\brief flush mmu tlb by index.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
{
MIR_Type mir;
mir.b.Index = index;
__set_MIR(mir.w);
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
/**
\brief flush mmu tlb by virtual address.
\details
*/
__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
{
__set_MEH(vaddr | (asid & MEH_ASID_Msk));
__set_MCIR(1u << MCIR_TLBP_Pos);
if (__get_MIR() & (1 << MIR_P_Pos)) {
return;
} else {
__set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
}
}
/*@} end of CSI_Core_MMUFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
\param [in] irq_num External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_PSR();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_PSR(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CK810_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_ck810.h | C | apache-2.0 | 33,879 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_rv32.h
* @brief CSI RV32 Core Peripheral Access Layer Header File
* @version V1.0
* @date 01. Sep 2018
******************************************************************************/
#ifndef __CORE_RV32_H_GENERIC
#define __CORE_RV32_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup RV32
@{
*/
#ifndef __RV32
#define __RV32 (0x01U)
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_RV32_H_DEPENDANT
#define __CORE_RV32_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __RV32_REV
#define __RV32_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <core/csi_rv32_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK802 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core CLIC Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC)
\brief Type definitions for the CLIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */
__IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */
__IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */
__IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */
} CLIC_INT_Control;
typedef struct {
__IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */
__IM uint32_t CLICINFO;
__IOM uint32_t MINTTHRESH;
uint32_t RESERVED[1021];
CLIC_INT_Control CLICINT[4096];
} CLIC_Type;
#define CLIC_INFO_CLICINTCTLBITS_Pos 21U
#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos)
#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */
#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */
#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */
#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */
#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */
#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */
#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */
#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */
#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */
#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */
#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */
#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */
#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */
#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */
/*@} end of group CSI_CLIC */
/**
\ingroup CSI_core_register
\defgroup CSI_PMP Physical Memory Protection (PMP)
\brief Type definitions for the PMP Registers
@{
*/
#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
typedef enum {
REGION_SIZE_4B = -1,
REGION_SIZE_8B = 0,
REGION_SIZE_16B = 1,
REGION_SIZE_32B = 2,
REGION_SIZE_64B = 3,
REGION_SIZE_128B = 4,
REGION_SIZE_256B = 5,
REGION_SIZE_512B = 6,
REGION_SIZE_1KB = 7,
REGION_SIZE_2KB = 8,
REGION_SIZE_4KB = 9,
REGION_SIZE_8KB = 10,
REGION_SIZE_16KB = 11,
REGION_SIZE_32KB = 12,
REGION_SIZE_64KB = 13,
REGION_SIZE_128KB = 14,
REGION_SIZE_256KB = 15,
REGION_SIZE_512KB = 16,
REGION_SIZE_1MB = 17,
REGION_SIZE_2MB = 18,
REGION_SIZE_4MB = 19,
REGION_SIZE_8MB = 20,
REGION_SIZE_16MB = 21,
REGION_SIZE_32MB = 22,
REGION_SIZE_64MB = 23,
REGION_SIZE_128MB = 24,
REGION_SIZE_256MB = 25,
REGION_SIZE_512MB = 26,
REGION_SIZE_1GB = 27,
REGION_SIZE_2GB = 28,
REGION_SIZE_4GB = 29,
REGION_SIZE_8GB = 30,
REGION_SIZE_16GB = 31
} region_size_e;
typedef enum {
ADDRESS_MATCHING_TOR = 1,
ADDRESS_MATCHING_NAPOT = 3
} address_matching_e;
typedef struct {
uint32_t r: 1; /* readable enable */
uint32_t w: 1; /* writeable enable */
uint32_t x: 1; /* execable enable */
address_matching_e a: 2; /* address matching mode */
uint32_t reserved: 2; /* reserved */
uint32_t l: 1; /* lock enable */
} mpu_region_attr_t;
/*@} end of group CSI_PMP */
/* CACHE Register Definitions */
#define CACHE_MHCR_L0BTB_Pos 12U /*!< CACHE MHCR: L0BTB Position */
#define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */
#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */
#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */
#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */
#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */
#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */
#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */
#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */
#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */
#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */
#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */
#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */
#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */
#define CACHE_INV_ADDR_Pos 5U
#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos)
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t MTIMECMPLO; /*!< Offset: 0x000 (R/W) Timer compare low 32-bits register */
__IOM uint32_t MTIMECMPHI; /*!< Offset: 0x004 (R/W) Timer compare high 32-bits register */
uint32_t RESERVED[8188];
__IM uint32_t MTIMELO; /*!< Offset: 0x7FF8 (R) Timer current low 32-bits register */
__IM uint32_t MTIMEHI; /*!< Offset: 0x7FFC (R) Timer current high 32-bits register */
} CORET_Type;
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
uint32_t RESERVED1;
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED2[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK802 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (0xE0004000UL) /*!< CORET Base Address */
#define CLIC_BASE (0xE0800000UL) /*!< CLIC Base Address */
#define DCC_BASE (0xE4010000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk;
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk;
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IE &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk);
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk);
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk;
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk;
}
/**
\brief Set Wake up Interrupt
\details Set the wake up bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
{
}
/**
\brief Clear Wake up Interrupt
\details Clear the wake up bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
{
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
uint8_t val = 0xFFU;
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~val)) | ((priority << (8 - nlbits)) & 0xFFU);
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits);
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
vectors[IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
return (uint32_t)vectors[IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ########################## PMP functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_PMPFunctions PMP Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
uint8_t pmpxcfg = 0;
uint32_t addr = 0;
if (idx > 15) {
return;
}
if (!enable) {
attr.a = 0;
}
if (attr.a == ADDRESS_MATCHING_TOR) {
addr = base_addr >> 2;
} else {
if (size == REGION_SIZE_4B) {
addr = base_addr >> 2;
attr.a = 2;
} else {
addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1);
}
}
__set_PMPADDRx(idx, addr);
pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) |
(attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) |
(attr.l << PMP_PMPCFG_L_Pos);
__set_PMPxCFG(idx, pmpxcfg);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
__set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk));
}
/*@} end of CSI_Core_PMPFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if (CORET->MTIMECMPLO || CORET->MTIMECMPHI) {
CORET->MTIMECMPLO = CORET->MTIMECMPLO + ticks;
} else {
CORET->MTIMECMPLO = CORET->MTIMELO + ticks;
CORET->MTIMECMPHI = CORET->MTIMEHI;
}
if (CORET->MTIMECMPLO < ticks) {
CORET->MTIMECMPHI++;
}
return (0UL);
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->MTIMECMPLO;
}
/**
\brief get CORE timer reload high value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_loadh(void)
{
return CORET->MTIMECMPHI;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->MTIMELO;
}
/**
\brief get CORE timer counter high value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_valueh(void)
{
return CORET->MTIMEHI;
}
/**
\brief clean CORE timer interrupt flag
*/
__STATIC_INLINE void csi_coret_clear_irq(void)
{
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
__ICACHE_IALL();
cache = __get_MHCR();
cache |= CACHE_MHCR_IE_Msk;
__set_MHCR(cache);
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */
__set_MHCR(cache);
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all dcache */
cache = __get_MHCR();
cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */
__set_MHCR(cache);
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
__set_MHCR(cache);
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CALL(); /* clean all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CIALL(); /* clean and inv all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t)addr;
int32_t linesize = 32;
__DSB();
while (op_size > 0) {
__DCACHE_IPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk;
int32_t linesize = 32;
__DSB();
while (op_size > 0) {
__DCACHE_CPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t) addr;
int32_t linesize = 32;
__DSB();
while (op_size > 0) {
__DCACHE_CIPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief setup cacheable range Cache
\param [in] index cache scope index (0, 1, 2, 3).
\param [in] baseAddr base address must be aligned with size.
\param [in] size \ref CACHE Register Definitions. cache scope size.
\param [in] enable enable or disable cache scope.
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
;
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return 0;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return 0;
}
/*@} end of CSI_Core_CacheFunctions */
/*@} end of CSI_core_DebugFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_MSTATUS();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_MSTATUS(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_rv32.h | C | apache-2.0 | 35,343 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file core_rv32.h
* @brief CSI RV32 Core Peripheral Access Layer Header File
* @version V1.0
* @date 01. Sep 2018
******************************************************************************/
#ifndef __CORE_RV32_H_GENERIC
#define __CORE_RV32_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* CSI definitions
******************************************************************************/
/**
\ingroup RV32
@{
*/
#ifndef __RV32
#define __RV32 (0x01U)
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_GENERIC */
#ifndef __CSI_GENERIC
#ifndef __CORE_RV32_H_DEPENDANT
#define __CORE_RV32_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#ifndef __RV32_REV
#define __RV32_REV 0x0000U
#endif
#ifndef __VIC_PRIO_BITS
#define __VIC_PRIO_BITS 2U
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 1U
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 1U
#endif
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 1U
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 1U
#endif
#include <csi_rv32_gcc.h>
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CSI_glob_defs CSI Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group CK802 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core CLIC Register
******************************************************************************/
/**
\defgroup CSI_core_register Defines and Type Definitions
\brief Type definitions and defines for CK80X processor based devices.
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\ingroup CSI_core_register
\defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC)
\brief Type definitions for the CLIC Registers
@{
*/
/**
\brief Access to the structure of a vector interrupt controller.
*/
typedef struct {
__IOM uint8_t INTIP[1024U]; /*!< Offset: 0x000 (R/W) Interrupt set pending register */
__IOM uint8_t INTIE[1024U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
__IOM uint8_t INTCFG[768U]; /*!< Offset: 0x000 (R/W) Interrupt configure register */
__IOM uint8_t CLICCFG; /*!< Offset: 0x000 (R/W) CLIC configure register */
} CLIC_Type;
#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */
#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */
#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */
#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */
#define CLIC_INTCFG_PRIO_Pos 6U /*!< CLIC INTCFG: INTCFG Position */
#define CLIC_INTCFG_PRIO_Msk (0x1UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */
#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */
#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */
#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */
#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */
/*@} end of group CSI_CLIC */
/**
\ingroup CSI_core_register
\defgroup CSI_PMP Physical Memory Protection (PMP)
\brief Type definitions for the PMP Registers
@{
*/
#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
typedef enum {
REGION_SIZE_4B = -1,
REGION_SIZE_8B = 0,
REGION_SIZE_16B = 1,
REGION_SIZE_32B = 2,
REGION_SIZE_64B = 3,
REGION_SIZE_128B = 4,
REGION_SIZE_256B = 5,
REGION_SIZE_512B = 6,
REGION_SIZE_1KB = 7,
REGION_SIZE_2KB = 8,
REGION_SIZE_4KB = 9,
REGION_SIZE_8KB = 10,
REGION_SIZE_16KB = 11,
REGION_SIZE_32KB = 12,
REGION_SIZE_64KB = 13,
REGION_SIZE_128KB = 14,
REGION_SIZE_256KB = 15,
REGION_SIZE_512KB = 16,
REGION_SIZE_1MB = 17,
REGION_SIZE_2MB = 18,
REGION_SIZE_4MB = 19,
REGION_SIZE_8MB = 20,
REGION_SIZE_16MB = 21,
REGION_SIZE_32MB = 22,
REGION_SIZE_64MB = 23,
REGION_SIZE_128MB = 24,
REGION_SIZE_256MB = 25,
REGION_SIZE_512MB = 26,
REGION_SIZE_1GB = 27,
REGION_SIZE_2GB = 28,
REGION_SIZE_4GB = 29,
REGION_SIZE_8GB = 30,
REGION_SIZE_16GB = 31
} region_size_e;
typedef enum {
ADDRESS_MATCHING_TOR = 1,
ADDRESS_MATCHING_NAPOT = 3
} address_matching_e;
typedef struct {
uint32_t r: 1; /* readable enable */
uint32_t w: 1; /* writeable enable */
uint32_t x: 1; /* execable enable */
address_matching_e a: 2; /* address matching mode */
uint32_t reserved: 2; /* reserved */
uint32_t l: 1; /* lock enable */
} mpu_region_attr_t;
/*@} end of group CSI_PMP */
/**
\ingroup CSI_core_register
\defgroup CSI_CACHE
\brief Type definitions for the cache Registers
@{
*/
/**
\brief On chip cache structure.
*/
typedef struct
{
__IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
__IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
__IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
uint32_t RSERVED0[1015U];
__IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
__IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
__IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
} CACHE_Type;
/* CACHE Register Definitions */
#define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
#define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
#define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
#define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
#define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
#define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
#define CACHE_CER_WCFIG_Pos 3U /*!< CACHE CER: WCFIG Position */
#define CACHE_CER_WCFIG_Msk (0x1UL << CACHE_CER_WCFIG_Pos) /*!< CACHE CER: WCFIG Mask */
#define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
#define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
#define CACHE_CER_CS_Pos 31U /*!< CACHE CER: CS Position */
#define CACHE_CER_CS_Msk (0x1UL << CACHE_CER_CS_Pos) /*!< CACHE CER: CS Mask */
#define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
#define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
#define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
#define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
#define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
#define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
#define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
#define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
#define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
#define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
#define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
#define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
#define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
#define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
#define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
#define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
#define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
#define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
#define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
#define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
#define CACHE_CRCR_4K 0xB /* 01011 */
#define CACHE_CRCR_8K 0xC /* 01100 */
#define CACHE_CRCR_16K 0xD /* 01101 */
#define CACHE_CRCR_32K 0xE /* 01110 */
#define CACHE_CRCR_64K 0xF /* 01111 */
#define CACHE_CRCR_128K 0x10 /* 10000 */
#define CACHE_CRCR_256K 0x11 /* 10001 */
#define CACHE_CRCR_512K 0x12 /* 10010 */
#define CACHE_CRCR_1M 0x13 /* 10011 */
#define CACHE_CRCR_2M 0x14 /* 10100 */
#define CACHE_CRCR_4M 0x15 /* 10101 */
#define CACHE_CRCR_8M 0x16 /* 10110 */
#define CACHE_CRCR_16M 0x17 /* 10111 */
#define CACHE_CRCR_32M 0x18 /* 11000 */
#define CACHE_CRCR_64M 0x19 /* 11001 */
#define CACHE_CRCR_128M 0x1A /* 11010 */
#define CACHE_CRCR_256M 0x1B /* 11011 */
#define CACHE_CRCR_512M 0x1C /* 11100 */
#define CACHE_CRCR_1G 0x1D /* 11101 */
#define CACHE_CRCR_2G 0x1E /* 11110 */
#define CACHE_CRCR_4G 0x1F /* 11111 */
/*@} end of group CSI_CACHE */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief The data structure of the access system timer.
*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
} CORET_Type;
/* CORET Control / Status Register Definitions */
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
/* CORET Reload Register Definitions */
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
/* CORET Current Register Definitions */
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
/* CORET Calibration Register Definitions */
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
/*@} end of group CSI_SysTick */
/**
\ingroup CSI_core_register
\defgroup CSI_DCC
\brief Type definitions for the DCC.
@{
*/
/**
\brief Access to the data structure of DCC.
*/
typedef struct {
uint32_t RESERVED0[13U];
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
uint32_t RESERVED1[6U];
union {
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
};
} DCC_Type;
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
/*@} end of group CSI_DCC */
/**
\ingroup CSI_core_register
\defgroup CSI_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CSI_core_bitfield */
/**
\ingroup CSI_core_register
\defgroup CSI_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of CK802 Hardware */
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
#define CLIC_BASE (TCIP_BASE + 0x0100UL) /*!< CLIC Base Address */
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core VIC Functions
- Core CORET Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## VIC functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_VICFunctions VIC Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
{
CLIC->INTIE[IRQn] |= CLIC_INTIE_IE_Msk;
}
/**
\brief Disable External Interrupt
\details Disable a device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
{
CLIC->INTIE[IRQn] &= ~CLIC_INTIE_IE_Msk;
}
/**
\brief Enable External Secure Interrupt
\details Enable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
{
CLIC->INTIE[IRQn] |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Disable External Secure Interrupt
\details Disable a secure device-specific interrupt in the VIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
{
CLIC->INTIE[IRQn] &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
}
/**
\brief Check Interrupt is Enabled or not
\details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not enabled.
\return 1 Interrupt status is enabled.
*/
__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->INTIE[IRQn] & CLIC_INTIE_IE_Msk);
}
/**
\brief Check Interrupt is Pending or not
\details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
return (uint32_t)(CLIC->INTIP[IRQn] & CLIC_INTIP_IP_Msk);
}
/**
\brief Set Pending Interrupt
\details Set the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
CLIC->INTIP[IRQn] |= CLIC_INTIP_IP_Msk;
}
/**
\brief Clear Pending Interrupt
\details Clear the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
CLIC->INTIP[IRQn] &= ~CLIC_INTIP_IP_Msk;
}
/**
\brief Set Interrupt Priority
\details Set the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
CLIC->INTCFG[IRQn] = (CLIC->INTCFG[IRQn] & (~CLIC_INTCFG_PRIO_Msk)) | (priority << CLIC_INTCFG_PRIO_Pos);
}
/**
\brief Get Interrupt Priority
\details Read the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
return CLIC->INTCFG[IRQn] >> CLIC_INTCFG_PRIO_Pos;
}
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
\param [in] IRQn Interrupt number.
\param [in] handler Interrupt handler.
*/
__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
vectors[32 + IRQn] = handler;
}
}
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param [in] IRQn Interrupt number.
*/
__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
{
if (IRQn >= 0 && IRQn < 1024) {
uint32_t *vectors = (uint32_t *)__get_MTVT();
return (uint32_t)vectors[32 + IRQn];
}
return 0;
}
/*@} end of CSI_Core_VICFunctions */
/* ########################## PMP functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_PMPFunctions PMP Functions
\brief Functions that manage interrupts and exceptions via the VIC.
@{
*/
/**
\brief configure memory protected region.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
\param [in] base_addr base address must be aligned with page size.
\param [in] size \ref region_size_e. memory protected region size.
\param [in] attr \ref region_size_t. memory protected region attribute.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
mpu_region_attr_t attr, uint32_t enable)
{
uint8_t pmpxcfg = 0;
uint32_t addr = 0;
if (idx > 15) {
return;
}
if (!enable) {
attr.a = 0;
}
if (attr.a == ADDRESS_MATCHING_TOR) {
addr = base_addr >> 2;
} else {
if (size == REGION_SIZE_4B) {
addr = base_addr >> 2;
attr.a = 2;
} else {
addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1);
}
}
__set_PMPADDRx(idx, addr);
pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) |
(attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) |
(attr.l << PMP_PMPCFG_L_Pos);
__set_PMPxCFG(idx, pmpxcfg);
}
/**
\brief disable mpu region by idx.
\details
\param [in] idx memory protected region (0, 1, 2, ..., 15).
*/
__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
{
__set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk));
}
/*@} end of CSI_Core_PMPFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
/**
\brief CORE timer Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\param [in] IRQn core timer Interrupt number.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
CORET->VAL = 0UL; /* Load the CORET Counter Value */
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
return (0UL); /* Function successful */
}
/**
\brief get CORE timer reload value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_load(void)
{
return CORET->LOAD;
}
/**
\brief get CORE timer counter value
\return CORE timer counter value.
*/
__STATIC_INLINE uint32_t csi_coret_get_value(void)
{
return CORET->VAL;
}
/*@} end of CSI_Core_SysTickFunctions */
/* ##################################### DCC function ########################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_core_DebugFunctions HAD Functions
\brief Functions that access the HAD debug interface.
@{
*/
/**
\brief HAD Send Character
\details Transmits a character via the HAD channel 0, and
\li Just returns when no debugger is connected that has booked the output.
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
{
DCC->DERJR = (uint8_t)ch;
return (ch);
}
/**
\brief HAD Receive Character
\details Inputs a character via the external variable \ref HAD_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t csi_had_receive_char(void)
{
int32_t ch = -1; /* no character available */
if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
ch = DCC->DERJW;
}
return (ch);
}
/**
\brief HAD Check Character
\details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t csi_had_check_char(void)
{
return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
}
/*@} end of CSI_core_DebugFunctions */
/* ########################## Cache functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
\note I-Cache also turns on.
*/
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
\note I-Cache also turns off.
*/
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
\note I-Cache also invalid
*/
__STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
\note I-Cache also cleans
*/
__STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
\note I-Cache also flush.
*/
__STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 16-byte boundary)
\param[in] dsize size of memory block (aligned to 16-byte boundary)
*/
__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 16;
uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
int32_t linesize = 16;
op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
while (op_size >= 128) {
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= 128;
}
while (op_size > 0) {
CACHE->CIR = op_addr;
op_addr += linesize;
op_size -= linesize;
}
#endif
}
/**
\brief setup cacheable range Cache
\details setup Cache range
*/
__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
{
CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
(_VAL2FLD(CACHE_CRCR_SIZE, size)) |
(_VAL2FLD(CACHE_CRCR_EN, enable)));
}
/**
\brief Enable cache profile
\details Turns on Cache profile
*/
__STATIC_INLINE void csi_cache_enable_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Disable cache profile
\details Turns off Cache profile
*/
__STATIC_INLINE void csi_cache_disable_profile (void)
{
CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
}
/**
\brief Reset cache profile
\details Reset Cache profile
*/
__STATIC_INLINE void csi_cache_reset_profile (void)
{
CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
}
/**
\brief cache access times
\details Cache access times
\note every 256 access add 1.
\return cache access times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
{
return CACHE->CPFATR;
}
/**
\brief cache miss times
\details Cache miss times
\note every 256 miss add 1.
\return cache miss times, actual times should be multiplied by 256
*/
__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
{
return CACHE->CPFMTR;
}
/*@} end of CSI_Core_CacheFunctions */
/*@} end of CSI_core_DebugFunctions */
/* ################################## IRQ Functions ############################################ */
/**
\brief Save the Irq context
\details save the psr result before disable irq.
*/
__STATIC_INLINE uint32_t csi_irq_save(void)
{
uint32_t result;
result = __get_MSTATUS();
__disable_irq();
return(result);
}
/**
\brief Restore the Irq context
\details restore saved primask state.
\param [in] irq_state psr irq state.
*/
__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
{
__set_MSTATUS(irq_state);
}
/*@} end of IRQ Functions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RV32_H_DEPENDANT */
#endif /* __CSI_GENERIC */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/core_rv32_old.h | C | apache-2.0 | 42,882 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_gcc.h
* @brief CSI Header File for GCC.
* @version V1.0
* @date 02. June 2020
******************************************************************************/
#ifndef _CSI_GCC_H_
#define _CSI_GCC_H_
#include <stdlib.h>
#include <stdint.h>
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
#ifndef __ALWAYS_STATIC_INLINE
#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by setting the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("psrset ie");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by clearing the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("psrclr ie");
}
/**
\brief Get PSR
\details Returns the content of the PSR Register.
\return PSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PSR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, psr" : "=r"(result));
return (result);
}
/**
\brief Set PSR
\details Writes the given value to the PSR Register.
\param [in] psr PSR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PSR(uint32_t psr)
{
__ASM volatile("mtcr %0, psr" : : "r"(psr));
}
/**
\brief Get SP
\details Returns the content of the SP Register.
\return SP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("mov %0, sp" : "=r"(result));
return (result);
}
/**
\brief Set SP
\details Writes the given value to the SP Register.
\param [in] sp SP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp)
{
__ASM volatile("mov sp, %0" : : "r"(sp): "sp");
}
/**
\brief Get Int SP
\details Returns the content of the Int SP Register.
\return Int SP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_Int_SP(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<15, 1>" : "=r"(result));
return (result);
}
/**
\brief Set Int SP
\details Writes the given value to the Int SP Register.
\param [in] sp Int SP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_Int_SP(uint32_t sp)
{
__ASM volatile("mtcr %0, cr<15, 1>" : : "r"(sp));
}
/**
\brief Get VBR Register
\details Returns the content of the VBR Register.
\return VBR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_VBR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, vbr" : "=r"(result));
return (result);
}
/**
\brief Set VBR
\details Writes the given value to the VBR Register.
\param [in] vbr VBR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_VBR(uint32_t vbr)
{
__ASM volatile("mtcr %0, vbr" : : "r"(vbr));
}
/**
\brief Get EPC Register
\details Returns the content of the EPC Register.
\return EPC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_EPC(void)
{
uint32_t result;
__ASM volatile("mfcr %0, epc" : "=r"(result));
return (result);
}
/**
\brief Set EPC
\details Writes the given value to the EPC Register.
\param [in] epc EPC Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_EPC(uint32_t epc)
{
__ASM volatile("mtcr %0, epc" : : "r"(epc));
}
/**
\brief Get EPSR
\details Returns the content of the EPSR Register.
\return EPSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_EPSR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, epsr" : "=r"(result));
return (result);
}
/**
\brief Set EPSR
\details Writes the given value to the EPSR Register.
\param [in] epsr EPSR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_EPSR(uint32_t epsr)
{
__ASM volatile("mtcr %0, epsr" : : "r"(epsr));
}
/**
\brief Get CPUID Register
\details Returns the content of the CPUID Register.
\return CPUID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CPUID(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr13" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<13, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Get CCR
\details Returns the current value of the CCR.
\return CCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CCR(void)
{
register uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr18\n" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<18, 0>\n" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CCR
\details Assigns the given value to the CCR.
\param [in] ccr CCR value to set
*/
__ALWAYS_STATIC_INLINE void __set_CCR(uint32_t ccr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr18\n" : : "r"(ccr));
#else
__ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr));
#endif
}
/**
\brief Get CCR2
\details Returns the current value of the CCR2.
\return CCR2 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CCR2(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<31, 0>\n" : "=r"(result));
return (result);
}
/**
\brief Set CCR2
\details Assigns the given value to the CCR2.
\param [in] ccr2 CCR2 value to set
*/
__ALWAYS_STATIC_INLINE void __set_CCR2(uint32_t ccr2)
{
__ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(ccr2));
}
/**
\brief Get DCSR
\details Returns the content of the DCSR Register.
\return DCSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_DCSR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr14" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<14, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set DCSR
\details Writes the given value to the DCSR Register.
\param [in] dcsr DCSR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_DCSR(uint32_t dcsr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr14" : : "r"(dcsr));
#else
__ASM volatile("mtcr %0, cr<14, 0>" : : "r"(dcsr));
#endif
}
/**
\brief Get CFR
\details Returns the content of the CFR Register.
\return CFR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CFR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr17" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<17, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CFR
\details Writes the given value to the CFR Register.
\param [in] cfr CFR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_CFR(uint32_t cfr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr17" : : "r"(cfr));
#else
__ASM volatile("mtcr %0, cr<17, 0>" : : "r"(cfr));
#endif
}
/**
\brief Get CIR
\details Returns the content of the CIR Register.
\return CIR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CIR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr22" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<22, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CIR
\details Writes the given value to the CIR Register.
\param [in] cir CIR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_CIR(uint32_t cir)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr22" : : "r"(cir));
#else
__ASM volatile("mtcr %0, cr<22, 0>" : : "r"(cir));
#endif
}
/**
\brief Get ERRLC
\details Returns the current value of the ERRLC.
\return ERRLC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRLC(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<6, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRLC
\details Assigns the given value to the ERRLC.
\param [in] errlc ERRLC value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRLC(uint32_t errlc)
{
__ASM volatile("mtcr %0, cr<6, 1>\n" : : "r"(errlc));
}
/**
\brief Get ERRADDR
\details Returns the current value of the ERRADDR.
\return ERRADDR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRADDR(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<7, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRADDR
\details Assigns the given value to the ERRADDR.
\param [in] erraddr ERRADDR value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRADDR(uint32_t erraddr)
{
__ASM volatile("mtcr %0, cr<7, 1>\n" : : "r"(erraddr));
}
/**
\brief Get ERRSTS
\details Returns the current value of the ERRSTS.
\return ERRSTS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRSTS(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<8, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRSTS
\details Assigns the given value to the ERRSTS.
\param [in] errsts ERRSTS value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRSTS(uint32_t errsts)
{
__ASM volatile("mtcr %0, cr<8, 1>\n" : : "r"(errsts));
}
/**
\brief Get ERRINJCR
\details Returns the current value of the ERRINJCR.
\return ERRINJCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCR(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<9, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRINJCR
\details Assigns the given value to the ERRINJCR.
\param [in] errinjcr ERRINJCR value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRINJCR(uint32_t errinjcr)
{
__ASM volatile("mtcr %0, cr<9, 1>\n" : : "r"(errinjcr));
}
/**
\brief Get ERRINJCNT
\details Returns the current value of the ERRINJCNT.
\return ERRINJCNT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCNT(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<10, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set ERRINJCNT
\details Assigns the given value to the ERRINJCNT.
\param [in] errinjcnt ERRINJCNT value to set
*/
__ALWAYS_STATIC_INLINE void __set_ERRINJCNT(uint32_t errinjcnt)
{
__ASM volatile("mtcr %0, cr<10, 1>\n" : : "r"(errinjcnt));
}
/**
\brief Get ITCMCR
\details Returns the content of the ITCMCR Register.
\return ITCMCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ITCMCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<22, 1>" : "=r"(result));
return (result);
}
/**
\brief Set ITCMCR
\details Writes the given value to the ITCMCR Register.
\param [in] itcmcr ITCMCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_ITCMCR(uint32_t itcmcr)
{
__ASM volatile("mtcr %0, cr<22, 1>" : : "r"(itcmcr));
}
/**
\brief Get DTCMCR
\details Returns the content of the DTCMCR Register.
\return DTCMCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_DTCMCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<23, 1>" : "=r"(result));
return (result);
}
/**
\brief Set DTCMCR
\details Writes the given value to the DTCMCR Register.
\param [in] dtcmcr DTCMCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_DTCMCR(uint32_t dtcmcr)
{
__ASM volatile("mtcr %0, cr<23, 1>" : : "r"(dtcmcr));
}
/**
\brief Get CINDEX
\details Returns the current value of the CINDEX.
\return CINDEX Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CINDEX(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<26, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set CINDEX
\details Assigns the given value to the CINDEX.
\param [in] cindex CINDEX value to set
*/
__ALWAYS_STATIC_INLINE void __set_CINDEX(uint32_t cindex)
{
__ASM volatile("mtcr %0, cr<26, 1>\n" : : "r"(cindex));
}
/**
\brief Get CDATAx
\details Returns the current value of the CDATAx.
\return CDATAx Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CDATA0(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<27, 1>\n" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_CDATA1(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<28, 1>\n" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_CDATA2(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<29, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set CDATAx
\details Assigns the given value to the CDATAx.
\param [in] cdata CDATAx value to set
*/
__ALWAYS_STATIC_INLINE void __set_CDATA0(uint32_t cdata)
{
__ASM volatile("mtcr %0, cr<27, 1>\n" : : "r"(cdata));
}
__ALWAYS_STATIC_INLINE void __set_CDATA1(uint32_t cdata)
{
__ASM volatile("mtcr %0, cr<28, 1>\n" : : "r"(cdata));
}
__ALWAYS_STATIC_INLINE void __set_CDATA2(uint32_t cdata)
{
__ASM volatile("mtcr %0, cr<29, 1>\n" : : "r"(cdata));
}
/**
\brief Get CINS
\details Returns the current value of the CINS.
\return CINS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CINS(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<31, 1>\n" : "=r"(result));
return (result);
}
/**
\brief Set CINS
\details Assigns the given value to the CINS.
\param [in] cins CINS value to set
*/
__ALWAYS_STATIC_INLINE void __set_CINS(uint32_t cins)
{
__ASM volatile("mtcr %0, cr<31, 1>\n" : : "r"(cins));
}
/**
\brief Get CAPR
\details Returns the current value of the CAPR.
\return CAPR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CAPR(void)
{
register uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr19\n" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<19, 0>\n" : "=r"(result));
#endif
return (result);
}
/**
\brief Set CAPR
\details Assigns the given value to the CAPR.
\param [in] capr CAPR value to set
*/
__ALWAYS_STATIC_INLINE void __set_CAPR(uint32_t capr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr19\n" : : "r"(capr));
#else
__ASM volatile("mtcr %0, cr<19, 0>\n" : : "r"(capr));
#endif
}
/**
\brief Get CAPR1
\details Returns the current value of the CAPR1.
\return CAPR1 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CAPR1(void)
{
register uint32_t result;
__ASM volatile("mfcr %0, cr<16, 0>\n" : "=r"(result));
return (result);
}
/**
\brief Set CAPR1
\details Assigns the given value to the CAPR1.
\param [in] capr1 CAPR1 value to set
*/
__ALWAYS_STATIC_INLINE void __set_CAPR1(uint32_t capr1)
{
__ASM volatile("mtcr %0, cr<16, 0>\n" : : "r"(capr1));
}
/**
\brief Set PACR
\details Assigns the given value to the PACR.
\param [in] pacr PACR value to set
*/
__ALWAYS_STATIC_INLINE void __set_PACR(uint32_t pacr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr20\n" : : "r"(pacr));
#else
__ASM volatile("mtcr %0, cr<20, 0>\n" : : "r"(pacr));
#endif
}
/**
\brief Get PACR
\details Returns the current value of PACR.
\return PACR value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PACR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr20" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<20, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set PRSR
\details Assigns the given value to the PRSR.
\param [in] prsr PRSR value to set
*/
__ALWAYS_STATIC_INLINE void __set_PRSR(uint32_t prsr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr21\n" : : "r"(prsr));
#else
__ASM volatile("mtcr %0, cr<21, 0>\n" : : "r"(prsr));
#endif
}
/**
\brief Get PRSR
\details Returns the current value of PRSR.
\return PRSR value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PRSR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr21" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<21, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set ATTR0
\details Assigns the given value to the ATTR0.
\param [in] attr0 ATTR0 value to set
*/
__ALWAYS_STATIC_INLINE void __set_ATTR0(uint32_t attr0)
{
__ASM volatile("mtcr %0, cr<26, 0>\n" : : "r"(attr0));
}
/**
\brief Get ATTR0
\details Returns the current value of ATTR0.
\return ATTR0 value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ATTR0(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<26, 0>" : "=r"(result));
return (result);
}
/**
\brief Set ATTR1
\details Assigns the given value to the ATTR1.
\param [in] attr0 ATTR1 value to set
*/
__ALWAYS_STATIC_INLINE void __set_ATTR1(uint32_t attr1)
{
__ASM volatile("mtcr %0, cr<27, 0>\n" : : "r"(attr1));
}
/**
\brief Get ATTR1
\details Returns the current value of ATTR1.
\return ATTR1 value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_ATTR1(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<27, 0>" : "=r"(result));
return (result);
}
/**
\brief Get user sp
\details Returns the current value of user r14.
\return UR14 value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_UR14(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mov %0, sp" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<14, 1>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set UR14
\details Assigns the given value to the UR14.
\param [in] ur14 UR14 value to set
*/
__ALWAYS_STATIC_INLINE void __set_UR14(uint32_t ur14)
{
#ifdef __CK610
__ASM volatile("mov sp, %0" : "=r"(ur14));
#else
__ASM volatile("mtcr %0, cr<14, 1>\n" : : "r"(ur14));
#endif
}
/**
\brief Get CHR Register
\details Returns the content of the CHR Register.
\return CHR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_CHR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<31, 0>\n" :"=r"(result));
return (result);
}
/**
\brief Set CHR
\details Assigns the given value to the CHR.
\param [in] chr CHR value to set
*/
__ALWAYS_STATIC_INLINE void __set_CHR(uint32_t chr)
{
__ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(chr));
}
/**
\brief Get HINT
\details Returns the content of the HINT Register.
\return HINT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_HINT(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr<30, 0>" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<31, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set HINT
\details Writes the given value to the HINT Register.
\param [in] hint HINT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_HINT(uint32_t hint)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr<30, 0>" : "=r"(hint));
#else
__ASM volatile("mtcr %0, cr<31, 0>" : : "r"(hint));
#endif
}
/**
\brief Get MIR
\details Returns the content of the MIR Register.
\return MIR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr0" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<0, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MIR
\details Writes the given value to the MIR Register.
\param [in] mir MIR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MIR(uint32_t mir)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr0" : : "b"(mir));
#else
__ASM volatile("mtcr %0, cr<0, 15>" : : "r"(mir));
#endif
}
/**
\brief Get MEL0
\details Returns the content of the MEL0 Register.
\return MEL0 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEL0(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr2" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<2, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MEL0
\details Writes the given value to the MEL0 Register.
\param [in] mel0 MEL0 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEL0(uint32_t mel0)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr2" : : "b"(mel0));
#else
__ASM volatile("mtcr %0, cr<2, 15>" : : "r"(mel0));
#endif
}
/**
\brief Get MEL1
\details Returns the content of the MEL1 Register.
\return MEL1 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEL1(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr3" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<3, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MEL1
\details Writes the given value to the MEL1 Register.
\param [in] mel1 MEL1 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEL1(uint32_t mel1)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr3" : : "b"(mel1));
#else
__ASM volatile("mtcr %0, cr<3, 15>" : : "r"(mel1));
#endif
}
/**
\brief Get MEH
\details Returns the content of the MEH Register.
\return MEH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEH(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr4" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<4, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MEH
\details Writes the given value to the MEH Register.
\param [in] meh MEH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEH(uint32_t meh)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr4" : : "b"(meh));
#else
__ASM volatile("mtcr %0, cr<4, 15>" : : "r"(meh));
#endif
}
/**
\brief Get MPR
\details Returns the content of the MPR Register.
\return MPR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MPR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr6" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<6, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MPR
\details Writes the given value to the MPR Register.
\param [in] mpr MPR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MPR(uint32_t mpr)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr6" : : "b"(mpr));
#else
__ASM volatile("mtcr %0, cr<6, 15>" : : "r"(mpr));
#endif
}
/**
\brief Get MCIR
\details Returns the content of the MCIR Register.
\return MCIR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCIR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr8" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<8, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MCIR
\details Writes the given value to the MCIR Register.
\param [in] mcir MCIR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MCIR(uint32_t mcir)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr8" : : "b"(mcir));
#else
__ASM volatile("mtcr %0, cr<8, 15>" : : "r"(mcir));
#endif
}
/**
\brief Get MPGD
\details Returns the content of the MPGD Register.
\return MPGD Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MPGD(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr29" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<29, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MPGD
\details Writes the given value to the MPGD Register.
\param [in] mpgd MPGD Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MPGD(uint32_t mpgd)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr29" : : "b"(mpgd));
#else
__ASM volatile("mtcr %0, cr<29, 15>" : : "r"(mpgd));
#endif
}
/**
\brief Get MSA0
\details Returns the content of the MSA0 Register.
\return MSA0 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSA0(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr30" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<30, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MSA0
\details Writes the given value to the MSA0 Register.
\param [in] msa0 MSA0 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSA0(uint32_t msa0)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr30" : : "b"(msa0));
#else
__ASM volatile("mtcr %0, cr<30, 15>" : : "r"(msa0));
#endif
}
/**
\brief Get MSA1
\details Returns the content of the MSA1 Register.
\return MSA1 Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSA1(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cprcr %0, cpcr31" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<31, 15>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set MSA1
\details Writes the given value to the MSA1 Register.
\param [in] msa1 MSA1 Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSA1(uint32_t msa1)
{
#ifdef __CK610
__ASM volatile("cpseti 15");
__ASM volatile("cpwcr %0, cpcr31" : : "b"(msa1));
#else
__ASM volatile("mtcr %0, cr<31, 15>" : : "r"(msa1));
#endif
}
/**
\brief Enable interrupts and exceptions
\details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_excp_irq(void)
{
__ASM volatile("psrset ee, ie");
}
/**
\brief Disable interrupts and exceptions
\details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_excp_irq(void)
{
__ASM volatile("psrclr ee, ie");
}
/**
\brief Get GSR
\details Returns the content of the GSR Register.
\return GSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_GSR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr12" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<12, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Get GCR
\details Returns the content of the GCR Register.
\return GCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_GCR(void)
{
uint32_t result;
#ifdef __CK610
__ASM volatile("mfcr %0, cr11" : "=r"(result));
#else
__ASM volatile("mfcr %0, cr<11, 0>" : "=r"(result));
#endif
return (result);
}
/**
\brief Set GCR
\details Writes the given value to the GCR Register.
\param [in] gcr GCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_GCR(uint32_t gcr)
{
#ifdef __CK610
__ASM volatile("mtcr %0, cr11" : : "r"(gcr));
#else
__ASM volatile("mtcr %0, cr<11, 0>" : : "r"(gcr));
#endif
}
/**
\brief Get WSSR
\details Returns the content of the WSSR Register, must be accessed in TEE
\return WSSR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_WSSR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<0, 3>" : "=r"(result));
return (result);
}
/**
\brief Get WRCR
\details Returns the content of the WRCR Register, must be accessed in TEE
\return WRCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_WRCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<1, 3>" : "=r"(result));
return (result);
}
/**
\brief Set WRCR
\details Writes the given value to the WRCR Register, must be accessed in TEE
\param [in] wrcr WRCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_WRCR(uint32_t wrcr)
{
__ASM volatile("mtcr %0, cr<1, 3>" : : "r"(wrcr));
}
/**
\brief Get DCR
\details Returns the content of the DCR Register, must be accessed in TEE
\return DCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_DCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<8, 3>" : "=r"(result));
return (result);
}
/**
\brief Set DCR
\details Writes the given value to the DCR Register, must be accessed in TEE
\param [in] dcr DCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_DCR(uint32_t dcr)
{
__ASM volatile("mtcr %0, cr<8, 3>" : : "r"(dcr));
}
/**
\brief Get PCR
\details Returns the content of the PCR Register, must be accessed in TEE
\return PCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PCR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<9, 3>" : "=r"(result));
return (result);
}
/**
\brief Set PCR
\details Writes the given value to the PCR Register, must be accessed in TEE
\param [in] pcr PCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PCR(uint32_t pcr)
{
__ASM volatile("mtcr %0, cr<9, 3>" : : "r"(pcr));
}
/**
\brief Get EBR
\details Returns the content of the EBR Register.
\return EBR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_EBR(void)
{
uint32_t result;
__ASM volatile("mfcr %0, cr<1, 1>" : "=r"(result));
return (result);
}
/**
\brief Set EBR
\details Writes the given value to the EBR Register.
\param [in] ebr EBR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_EBR(uint32_t ebr)
{
__ASM volatile("mtcr %0, cr<1, 1>" : : "r"(ebr));
}
/*@} end of CSI_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CSI_Core_InstructionInterface CSI Core Instruction Interface
Access to dedicated instructions
@{
*/
#define __CSI_GCC_OUT_REG(r) "=r" (r)
#define __CSI_GCC_USE_REG(r) "r" (r)
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__ALWAYS_STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
__ALWAYS_STATIC_INLINE void __WFI(void)
{
__ASM volatile("wait");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __WAIT(void)
{
__ASM volatile("wait");
}
/**
\brief Doze For Interrupt
\details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __DOZE(void)
{
__ASM volatile("doze");
}
/**
\brief Stop For Interrupt
\details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __STOP(void)
{
__ASM volatile("stop");
}
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__ALWAYS_STATIC_INLINE void __ISB(void)
{
__ASM volatile("sync"::: "memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("sync"::: "memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__ALWAYS_STATIC_INLINE void __DMB(void)
{
__ASM volatile("sync"::: "memory");
}
/**
\brief Search from the highest bit that the very first bit which's value is 1.
\param [in] value Value to bit search.
\return if the highest bit' value is 1, return 0, and if lowest bit's value is 1, return 31, otherwise return 32.
*/
#if !defined(__CK610) || !(__CK80X == 1)
__ALWAYS_STATIC_INLINE uint32_t __FF0(uint32_t value)
{
uint32_t ret;
__ASM volatile("ff0 %0, %1" : "=r"(ret) : "r"(value));
return ret;
}
#endif
/**
\brief Search from the highest bit that the very first bit which's value is 0.
\param [in] value Value to bit search.
\return if the highest bit' value is 0, return 0, and if lowest bit's value is 0, return 31, otherwise return 32.
*/
#if !(__CK80X == 1)
__ALWAYS_STATIC_INLINE uint32_t __FF1(uint32_t value)
{
uint32_t ret;
#if !defined (__CK610)
__ASM volatile("ff1 %0, %1" : "=r"(ret) : "r"(value));
#else
ret = value;
__ASM volatile("ff1 %0" : "=r"(ret):);
#endif
return ret;
}
#endif
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value)
{
return __builtin_bswap32(value);
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
#if (__CK80X >= 2)
__ASM volatile("revh %0, %1" : __CSI_GCC_OUT_REG(result) : __CSI_GCC_USE_REG(value));
#else
result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) |
((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8);
#endif
return (result);
}
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value)
{
return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8));
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
*/
__ALWAYS_STATIC_INLINE void __BKPT(void)
{
__ASM volatile("bkpt");
}
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if (__CK80X >= 0x03U)
__ASM volatile("brev %0, %1" : "=r"(result) : "r"(value));
#else
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return (result);
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
/**
\details This function saturates a signed value.
\param [in] x Value to be saturated
\param [in] y Bit position to saturate to [1..32]
\return Saturated value.
*/
__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
{
int32_t posMax, negMin;
uint32_t i;
posMax = 1;
for (i = 0; i < (y - 1); i++) {
posMax = posMax * 2;
}
if (x > 0) {
posMax = (posMax - 1);
if (x > posMax) {
x = posMax;
}
// x &= (posMax * 2 + 1);
} else {
negMin = -posMax;
if (x < negMin) {
x = negMin;
}
// x &= (posMax * 2 - 1);
}
return (x);
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Unsigned Saturate for internal use
\details Saturates an unsigned value, should not call directly.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Rotate Right with Extend
\details This function moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\note carry input will always 0.
\param [in] op1 Value to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1)
{
#if (__CK80X >= 2)
uint32_t res = 0;
__ASM volatile("bgeni t0, 31\n\t"
"lsri %0, 1\n\t"
"movt %1, t0\n\t"
"or %1, %1, %0\n\t"
: "=r"(op1), "=r"(res): "0"(op1), "1"(res): "t0");
return res;
#else
uint32_t res = 0;
__ASM volatile("movi r7, 0\n\t"
"bseti r7, 31\n\t"
"lsri %0, 1\n\t"
"bf 1f\n\t"
"mov %1, r7\n\t"
"1:\n\t"
"or %1, %1, %0\n\t"
: "=r"(op1), "=r"(res): "0"(op1), "1"(res): "r7");
return res;
#endif
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] addr Pointer to location
\return value of type uint8_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
//#warning "__LDRBT"
__ASM volatile("ldb %0, (%1, 0)" : "=r"(result) : "r"(addr));
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] addr Pointer to location
\return value of type uint16_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
//#warning "__LDRHT"
__ASM volatile("ldh %0, (%1, 0)" : "=r"(result) : "r"(addr));
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] addr Pointer to location
\return value of type uint32_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
//#warning "__LDRT"
__ASM volatile("ldw %0, (%1, 0)" : "=r"(result) : "r"(addr));
return (result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
//#warning "__STRBT"
__ASM volatile("stb %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
//#warning "__STRHT"
__ASM volatile("sth %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
//#warning "__STRT"
__ASM volatile("stw %1, (%0, 0)" :: "r"(addr), "r"(value) : "memory");
}
/*@}*/ /* end of group CSI_Core_InstructionInterface */
/* ########################## FPU functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type, always 0.
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__ALWAYS_STATIC_INLINE uint32_t __get_FPUType(void)
{
//FIXME:
return 0;
}
/*@} end of CSI_Core_FpuFunctions */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics
Access to dedicated SIMD instructions \n
Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
@{
*/
/**
\brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16]
of val2 levitated with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be left-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for left-shifting val2. Value range [0..31].
\return the combination of halfwords.
\remark
res[15:0] = val1[15:0] \n
res[31:16] = val2[31:16] << val3
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000));
}
/**
\brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0]
of val2 right-shifted with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be right-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for right-shifting val2. Value range [1..32].
\return the combination of halfwords.
\remark
res[15:0] = val2[15:0] >> val3 \n
res[31:16] = val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF));
}
/**
\brief Dual 16-bit signed saturate.
\details This function saturates a signed value.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:\n
the signed saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the signed saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF;
s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturate.
\details This function enables you to saturate two signed 16-bit values to a selected unsigned range.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the saturation of the two signed 16-bit values, as non-negative values:
the saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF;
s = __IUSAT(((x) >> 16), y) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit saturating addition.
\details This function enables you to perform four 8-bit integer additions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating addition.
\details This function enables you to perform four unsigned 8-bit integer additions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed addition.
\details This function performs four 8-bit signed integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition.
\details This function performs four unsigned 8-bit integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit saturating subtract.
\details This function enables you to perform four 8-bit integer subtractions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating subtraction.
\details This function enables you to perform four unsigned 8-bit integer subtractions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed subtraction.
\details This function enables you to perform four 8-bit signed integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtract.
\details This function enables you to perform four 8-bit unsigned integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences together, returning the result as a single unsigned integer.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n
The sum is returned as a single unsigned integer.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
*/
__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return (u + t + s + r);
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences to a 32-bit accumulate operand.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\param [in] sum accumulation value.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:
the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n
res[31:0] = sum[31:0] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
{
int32_t r, s, t, u;
#ifdef __cplusplus
r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#else
r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#endif
return (u + t + s + r + sum);
}
/**
\brief Dual 16-bit saturating addition.
\details This function enables you to perform two 16-bit integer arithmetic additions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition.
\details This function enables you to perform two unsigned 16-bit integer additions, saturating
the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition.
\details This function enables you to perform two 16-bit signed integer additions.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition
\details This function enables you to perform two 16-bit unsigned integer additions.
\param [in] x first two 16-bit summands for each addition.
\param [in] y second two 16-bit summands for each addition.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition with halved results.
\details This function enables you to perform two signed 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition with halved results.
\details This function enables you to perform two unsigned 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition with halved results.
\details This function enables you to perform four unsigned 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit saturating subtract.
\details This function enables you to perform two 16-bit integer subtractions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction.
\details This function enables you to perform two unsigned 16-bit integer subtractions,
saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit operands for each subtraction.
\param [in] y second two 16-bit operands for each subtraction.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction.
\details This function enables you to perform two 16-bit signed integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtract.
\details This function enables you to perform two 16-bit unsigned integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction with halved results.
\details This function enables you to perform two signed 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction with halved results.
\details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtraction with halved results.
\details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit add and subtract with exchange.
\details This function enables you to exchange the halfwords of the one operand,
then add the high halfwords and subtract the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition and subtraction with exchange.
\details This function enables you to exchange the halfwords of the second operand and
perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction,
saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit addition and subtraction with exchange.
\details It enables you to exchange the halfwords of the second operand, add the high halfwords
and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with exchange.
\details This function enables you to exchange the two halfwords of the second operand,
add the high halfwords and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition and subtraction with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one
signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
add the high halfwords and subtract the low halfwords, halving the results.
\param [in] x first operand for the subtraction in the low halfword, and
the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword, and
the second operand for the addition in the low halfword.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit subtract and add with exchange.
\details This function enables you to exchange the halfwords of one operand,
then subtract the high halfwords and add the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction and addition with exchange.
\details This function enables you to exchange the halfwords of the second operand and perform
one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating
the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit unsigned subtract and add with exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction and addition with exchange.
\details This function enables you to exchange the two halfwords of one operand and perform one
16-bit integer subtraction and one 16-bit addition.
\param [in] x first operand for the addition in the low halfword, and the first operand
for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and the second
operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit signed subtraction and addition with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one signed
16-bit integer subtraction and one signed 16-bit addition, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction and addition with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords, halving the results.
\param [in] x first operand for the addition in the low halfword, and
the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and
the second operand for the subtraction in the low halfword.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed multiply with exchange returning difference.
\details This function enables you to perform two 16-bit signed multiplications, subtracting
one of the products from the other. The halfwords of the second operand are exchanged
before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Sum of dual 16-bit signed multiply with exchange.
\details This function enables you to perform two 16-bit signed multiplications with exchanged
halfwords of the second operand, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Saturating add.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 + SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if (x + y >= x) {
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if (x + y < x) {
result = x + y;
} else {
result = 0x80000000;
}
}
return result;
}
/**
\brief Saturating subtract.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 - SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
{
int64_t tmp;
int32_t result;
tmp = (int64_t)x - (int64_t)y;
if (tmp > 0x7fffffff) {
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
tmp = -2147483647 - 1;
}
result = tmp;
return result;
}
/**
\brief Dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications,
adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications with exchanged
halfwords of the second operand, adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication with exchanged halfwords of the second
operand added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to perform two 16-bit signed multiplications, take the
difference of the products, subtracting the high halfword product from the low
halfword product, and add the difference to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit
signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with single 64-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications, adding both results
to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition.
This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
\details This function enables you to exchange the halfwords of the second operand, and perform two
signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow
is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs.
Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief dual 16-bit signed multiply subtract with 64-bit accumulate.
\details This function It enables you to perform two 16-bit signed multiplications, take the difference
of the products, subtracting the high halfword product from the low halfword product, and add the
difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the
subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not
detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
\details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications,
adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the
multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow
is not detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief 32-bit signed multiply with 32-bit truncated accumulator.
\details This function enables you to perform a signed 32-bit multiplications, adding the most
significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
\param [in] x first operand for multiplication.
\param [in] y second operand for multiplication.
\param [in] sum accumulate value.
\return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
\remark
p = val1 * val2 \n
res[31:0] = p[63:32] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum)
{
return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum);
}
/**
\brief Sum of dual 16-bit signed multiply.
\details This function enables you to perform two 16-bit signed multiplications, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual 16-bit signed multiply returning difference.
\details This function enables you to perform two 16-bit signed multiplications, taking the difference
of the products by subtracting the high halfword product from the low halfword product.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual extracted 8-bit to 16-bit signed addition.
\details This function enables you to extract two 8-bit values from the second operand (at bit positions
[7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
\param [in] x values added to the sign-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and sign-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and sign-extended prior to the addition.
\remark
res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) |
(((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000)));
}
/**
\brief Extracted 16-bit to 32-bit unsigned addition.
\details This function enables you to extract two 8-bit values from one operand, zero-extend
them to 16 bits each, and add the results to two 16-bit values from another operand.
\param [in] x values added to the zero-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and zero-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and zero-extended prior to the addition.
\remark
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) |
((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and sign extend each to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x)
{
return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) |
((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and zero-extend to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
{
return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) |
(((x << 8) >> 8) & 0xFFFF0000)));
}
#endif /* _CSI_GCC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/csi_gcc.h | C | apache-2.0 | 116,418 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_rv32_gcc.h
* @brief CSI Header File for GCC.
* @version V1.0
* @date 01. Sep 2020
******************************************************************************/
#ifndef _CSI_RV32_GCC_H_
#define _CSI_RV32_GCC_H_
#include <stdlib.h>
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
#ifndef __ALWAYS_STATIC_INLINE
#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by setting the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("csrs mstatus, 8");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by clearing the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("csrc mstatus, 8");
}
/**
\brief Get MXSTATUS
\details Returns the content of the MXSTATUS Register.
\return MXSTATUS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MXSTATUS(void)
{
uint32_t result;
__ASM volatile("csrr %0, mxstatus" : "=r"(result));
return (result);
}
/**
\brief Set MXSTATUS
\details Writes the given value to the MXSTATUS Register.
\param [in] mxstatus MXSTATUS Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MXSTATUS(uint32_t mxstatus)
{
__ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus));
}
/**
\brief Get MSTATUS
\details Returns the content of the MSTATUS Register.
\return MSTATUS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSTATUS(void)
{
uint32_t result;
__ASM volatile("csrr %0, mstatus" : "=r"(result));
return (result);
}
/**
\brief Set MSTATUS
\details Writes the given value to the MSTATUS Register.
\param [in] mstatus MSTATUS Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSTATUS(uint32_t mstatus)
{
__ASM volatile("csrw mstatus, %0" : : "r"(mstatus));
}
/**
\brief Get MHCR
\details Returns the content of the MHCR Register.
\return MHCR Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MHCR(void)
{
uint32_t result;
__ASM volatile("csrr %0, mhcr" : "=r"(result));
return (result);
}
/**
\brief Set MHCR
\details Writes the given value to the MHCR Register.
\param [in] mstatus MHCR Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr)
{
__ASM volatile("csrw mhcr, %0" : : "r"(mhcr));
}
/**
\brief Get MISA Register
\details Returns the content of the MISA Register.
\return MISA Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MISA(void)
{
uint32_t result;
__ASM volatile("csrr %0, misa" : "=r"(result));
return (result);
}
/**
\brief Set MISA
\details Writes the given value to the MISA Register.
\param [in] misa MISA Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MISA(uint32_t misa)
{
__ASM volatile("csrw misa, %0" : : "r"(misa));
}
/**
\brief Get MIE Register
\details Returns the content of the MIE Register.
\return MIE Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIE(void)
{
uint32_t result;
__ASM volatile("csrr %0, mie" : "=r"(result));
return (result);
}
/**
\brief Set MIE
\details Writes the given value to the MIE Register.
\param [in] mie MIE Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MIE(uint32_t mie)
{
__ASM volatile("csrw mie, %0" : : "r"(mie));
}
/**
\brief Get MTVEC Register
\details Returns the content of the MTVEC Register.
\return MTVEC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MTVEC(void)
{
uint32_t result;
__ASM volatile("csrr %0, mtvec" : "=r"(result));
return (result);
}
/**
\brief Set MTVEC
\details Writes the given value to the MTVEC Register.
\param [in] mtvec MTVEC Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MTVEC(uint32_t mtvec)
{
__ASM volatile("csrw mtvec, %0" : : "r"(mtvec));
}
/**
\brief Set MTVT
\details Writes the given value to the MTVT Register.
\param [in] mtvt MTVT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MTVT(uint32_t mtvt)
{
__ASM volatile("csrw mtvt, %0" : : "r"(mtvt));
}
/**
\brief Get MTVT Register
\details Returns the content of the MTVT Register.
\return MTVT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MTVT(void)
{
uint32_t result;
__ASM volatile("csrr %0, mtvt" : "=r"(result));
return (result);
}
/**
\brief Get SP
\details Returns the content of the SP Register.
\return SP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("mv %0, sp" : "=r"(result));
return (result);
}
/**
\brief Set SP
\details Writes the given value to the SP Register.
\param [in] sp SP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp)
{
__ASM volatile("mv sp, %0" : : "r"(sp): "sp");
}
/**
\brief Get MSCRATCH Register
\details Returns the content of the MSCRATCH Register.
\return MSCRATCH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MSCRATCH(void)
{
uint32_t result;
__ASM volatile("csrr %0, mscratch" : "=r"(result));
return (result);
}
/**
\brief Set MSCRATCH
\details Writes the given value to the MSCRATCH Register.
\param [in] mscratch MSCRATCH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MSCRATCH(uint32_t mscratch)
{
__ASM volatile("csrw mscratch, %0" : : "r"(mscratch));
}
/**
\brief Get MEPC Register
\details Returns the content of the MEPC Register.
\return MEPC Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MEPC(void)
{
uint32_t result;
__ASM volatile("csrr %0, mepc" : "=r"(result));
return (result);
}
/**
\brief Set MEPC
\details Writes the given value to the MEPC Register.
\param [in] mepc MEPC Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MEPC(uint32_t mepc)
{
__ASM volatile("csrw mepc, %0" : : "r"(mepc));
}
/**
\brief Get MCAUSE Register
\details Returns the content of the MCAUSE Register.
\return MCAUSE Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCAUSE(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcause" : "=r"(result));
return (result);
}
/**
\brief Get MNXTI Register
\details Returns the content of the MNXTI Register.
\return MNXTI Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MNXTI(void)
{
uint32_t result;
__ASM volatile("csrr %0, mnxti" : "=r"(result));
return (result);
}
/**
\brief Set MNXTI
\details Writes the given value to the MNXTI Register.
\param [in] mnxti MNXTI Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MNXTI(uint32_t mnxti)
{
__ASM volatile("csrw mnxti, %0" : : "r"(mnxti));
}
/**
\brief Get MINTSTATUS Register
\details Returns the content of the MINTSTATUS Register.
\return MINTSTATUS Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MINTSTATUS(void)
{
uint32_t result;
__ASM volatile("csrr %0, mintstatus" : "=r"(result));
return (result);
}
/**
\brief Get MTVAL Register
\details Returns the content of the MTVAL Register.
\return MTVAL Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MTVAL(void)
{
uint32_t result;
__ASM volatile("csrr %0, mtval" : "=r"(result));
return (result);
}
/**
\brief Get MIP Register
\details Returns the content of the MIP Register.
\return MIP Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIP(void)
{
uint32_t result;
__ASM volatile("csrr %0, mip" : "=r"(result));
return (result);
}
/**
\brief Set MIP
\details Writes the given value to the MIP Register.
\param [in] mip MIP Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MIP(uint32_t mip)
{
__ASM volatile("csrw mip, %0" : : "r"(mip));
}
/**
\brief Get MCYCLEL Register
\details Returns the content of the MCYCLEL Register.
\return MCYCLE Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLE(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcycle" : "=r"(result));
return (result);
}
/**
\brief Get MCYCLEH Register
\details Returns the content of the MCYCLEH Register.
\return MCYCLEH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLEH(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcycleh" : "=r"(result));
return (result);
}
/**
\brief Get MINSTRET Register
\details Returns the content of the MINSTRET Register.
\return MINSTRET Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRET(void)
{
uint32_t result;
__ASM volatile("csrr %0, minstret" : "=r"(result));
return (result);
}
/**
\brief Get MINSTRETH Register
\details Returns the content of the MINSTRETH Register.
\return MINSTRETH Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRETH(void)
{
uint32_t result;
__ASM volatile("csrr %0, minstreth" : "=r"(result));
return (result);
}
/**
\brief Get MVENDORID Register
\details Returns the content of the MVENDROID Register.
\return MVENDORID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MVENDORID(void)
{
uint32_t result;
__ASM volatile("csrr %0, mvendorid" : "=r"(result));
return (result);
}
/**
\brief Get MARCHID Register
\details Returns the content of the MARCHID Register.
\return MARCHID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MARCHID(void)
{
uint32_t result;
__ASM volatile("csrr %0, marchid" : "=r"(result));
return (result);
}
/**
\brief Get MIMPID Register
\details Returns the content of the MIMPID Register.
\return MIMPID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MIMPID(void)
{
uint32_t result;
__ASM volatile("csrr %0, mimpid" : "=r"(result));
return (result);
}
/**
\brief Get MHARTID Register
\details Returns the content of the MHARTID Register.
\return MHARTID Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MHARTID(void)
{
uint32_t result;
__ASM volatile("csrr %0, mhartid" : "=r"(result));
return (result);
}
/**
\brief Get PMPCFGx Register
\details Returns the content of the PMPCFGx Register.
\return PMPCFGx Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG0(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg0" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG1(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg1" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG2(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg2" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG3(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpcfg3" : "=r"(result));
return (result);
}
/**
\brief Get PMPxCFG Register by index
\details Returns the content of the PMPxCFG Register.
\param [in] idx PMP region index
\return PMPxCFG Register value
*/
__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
{
uint32_t pmpcfgx = 0;
if (idx < 4) {
pmpcfgx = __get_PMPCFG0();
} else if (idx >=4 && idx < 8) {
idx -= 4;
pmpcfgx = __get_PMPCFG1();
} else if (idx >=8 && idx < 12) {
idx -= 8;
pmpcfgx = __get_PMPCFG2();
} else if (idx >=12 && idx < 16) {
idx -= 12;
pmpcfgx = __get_PMPCFG3();
} else {
return 0;
}
return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3));
}
/**
\brief Set PMPCFGx
\details Writes the given value to the PMPCFGx Register.
\param [in] pmpcfg PMPCFGx Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PMPCFG0(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg));
}
__ALWAYS_STATIC_INLINE void __set_PMPCFG1(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg));
}
__ALWAYS_STATIC_INLINE void __set_PMPCFG2(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg));
}
__ALWAYS_STATIC_INLINE void __set_PMPCFG3(uint32_t pmpcfg)
{
__ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg));
}
/**
\brief Set PMPxCFG by index
\details Writes the given value to the PMPxCFG Register.
\param [in] idx PMPx region index
\param [in] pmpxcfg PMPxCFG Register value to set
*/
__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
{
uint32_t pmpcfgx = 0;
if (idx < 4) {
pmpcfgx = __get_PMPCFG0();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG0(pmpcfgx);
} else if (idx >=4 && idx < 8) {
idx -= 4;
pmpcfgx = __get_PMPCFG1();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG1(pmpcfgx);
} else if (idx >=8 && idx < 12) {
idx -= 8;
pmpcfgx = __get_PMPCFG2();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG2(pmpcfgx);
} else if (idx >=12 && idx < 16) {
idx -= 12;
pmpcfgx = __get_PMPCFG3();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG3(pmpcfgx);
} else {
return;
}
}
/**
\brief Get PMPADDRx Register
\details Returns the content of the PMPADDRx Register.
\return PMPADDRx Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR0(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr0" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR1(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr1" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR2(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr2" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR3(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr3" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR4(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr4" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR5(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr5" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR6(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr6" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR7(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr7" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR8(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr8" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR9(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr9" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR10(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr10" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR11(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr11" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR12(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr12" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR13(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr13" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR14(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr14" : "=r"(result));
return (result);
}
__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR15(void)
{
uint32_t result;
__ASM volatile("csrr %0, pmpaddr15" : "=r"(result));
return (result);
}
/**
\brief Get PMPADDRx Register by index
\details Returns the content of the PMPADDRx Register.
\param [in] idx PMP region index
\return PMPADDRx Register value
*/
__STATIC_INLINE uint32_t __get_PMPADDRx(uint32_t idx)
{
switch (idx) {
case 0: return __get_PMPADDR0();
case 1: return __get_PMPADDR1();
case 2: return __get_PMPADDR2();
case 3: return __get_PMPADDR3();
case 4: return __get_PMPADDR4();
case 5: return __get_PMPADDR5();
case 6: return __get_PMPADDR6();
case 7: return __get_PMPADDR7();
case 8: return __get_PMPADDR8();
case 9: return __get_PMPADDR9();
case 10: return __get_PMPADDR10();
case 11: return __get_PMPADDR11();
case 12: return __get_PMPADDR12();
case 13: return __get_PMPADDR13();
case 14: return __get_PMPADDR14();
case 15: return __get_PMPADDR15();
default: return 0;
}
}
/**
\brief Set PMPADDRx
\details Writes the given value to the PMPADDRx Register.
\param [in] pmpaddr PMPADDRx Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_PMPADDR0(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR1(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR2(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR3(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR4(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR5(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR6(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR7(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR8(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR9(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR10(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR11(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR12(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR13(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR14(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr));
}
__ALWAYS_STATIC_INLINE void __set_PMPADDR15(uint32_t pmpaddr)
{
__ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr));
}
/**
\brief Set PMPADDRx by index
\details Writes the given value to the PMPADDRx Register.
\param [in] idx PMP region index
\param [in] pmpaddr PMPADDRx Register value to set
*/
__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, uint32_t pmpaddr)
{
switch (idx) {
case 0: __set_PMPADDR0(pmpaddr); break;
case 1: __set_PMPADDR1(pmpaddr); break;
case 2: __set_PMPADDR2(pmpaddr); break;
case 3: __set_PMPADDR3(pmpaddr); break;
case 4: __set_PMPADDR4(pmpaddr); break;
case 5: __set_PMPADDR5(pmpaddr); break;
case 6: __set_PMPADDR6(pmpaddr); break;
case 7: __set_PMPADDR7(pmpaddr); break;
case 8: __set_PMPADDR8(pmpaddr); break;
case 9: __set_PMPADDR9(pmpaddr); break;
case 10: __set_PMPADDR10(pmpaddr); break;
case 11: __set_PMPADDR11(pmpaddr); break;
case 12: __set_PMPADDR12(pmpaddr); break;
case 13: __set_PMPADDR13(pmpaddr); break;
case 14: __set_PMPADDR14(pmpaddr); break;
case 15: __set_PMPADDR15(pmpaddr); break;
default: return;
}
}
/**
\brief Enable interrupts and exceptions
\details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_excp_irq(void)
{
__enable_irq();
}
/**
\brief Disable interrupts and exceptions
\details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_excp_irq(void)
{
__disable_irq();
}
#define __CSI_GCC_OUT_REG(r) "=r" (r)
#define __CSI_GCC_USE_REG(r) "r" (r)
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__ALWAYS_STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
__ALWAYS_STATIC_INLINE void __WFI(void)
{
__ASM volatile("wfi");
}
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __WAIT(void)
{
__ASM volatile("wfi");
}
/**
\brief Doze For Interrupt
\details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __DOZE(void)
{
__ASM volatile("wfi");
}
/**
\brief Stop For Interrupt
\details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
*/
__ALWAYS_STATIC_INLINE void __STOP(void)
{
__ASM volatile("wfi");
}
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__ALWAYS_STATIC_INLINE void __ISB(void)
{
__ASM volatile("fence");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("fence");
}
/**
\brief Invalid all icache
\details invalid all icache.
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("icache.iall");
#endif
}
/**
\brief Invalid Icache by addr
\details Invalid Icache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint32_t addr)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("icache.ipa %0" : : "r"(addr));
#endif
}
/**
\brief Invalid all dcache
\details invalid all dcache.
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("dcache.iall");
#endif
}
/**
\brief Clear all dcache
\details clear all dcache.
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("dcache.call");
#endif
}
/**
\brief Clear&invalid all dcache
\details clear & invalid all dcache.
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("dcache.ciall");
#endif
}
/**
\brief Invalid Dcache by addr
\details Invalid Dcache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint32_t addr)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("dcache.ipa %0" : : "r"(addr));
#endif
}
/**
\brief Clear Dcache by addr
\details Clear Dcache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint32_t addr)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("dcache.cpa %0" : : "r"(addr));
#endif
}
/**
\brief Clear & Invalid Dcache by addr
\details Clear & Invalid Dcache by addr.
\param [in] addr operate addr
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint32_t addr)
{
#if defined(__riscv_xtheade) || defined(__riscv_xtheadc)
__ASM volatile("dcache.cipa %0" : : "r"(addr));
#endif
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__ALWAYS_STATIC_INLINE void __DMB(void)
{
__ASM volatile("fence");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value)
{
return __builtin_bswap32(value);
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) |
((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8);
return (result);
}
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value)
{
return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8));
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\details Causes the processor to enter Debug state
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
*/
__ALWAYS_STATIC_INLINE void __BKPT(void)
{
__ASM volatile("ebreak");
}
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return (result);
}
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
/**
\details This function saturates a signed value.
\param [in] x Value to be saturated
\param [in] y Bit position to saturate to [1..32]
\return Saturated value.
*/
__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
{
int32_t posMax, negMin;
uint32_t i;
posMax = 1;
for (i = 0; i < (y - 1); i++) {
posMax = posMax * 2;
}
if (x > 0) {
posMax = (posMax - 1);
if (x > posMax) {
x = posMax;
}
// x &= (posMax * 2 + 1);
} else {
negMin = -posMax;
if (x < negMin) {
x = negMin;
}
// x &= (posMax * 2 - 1);
}
return (x);
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Unsigned Saturate for internal use
\details Saturates an unsigned value, should not call directly.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
}
return (result);
}
/**
\brief Rotate Right with Extend
\details This function moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\note carry input will always 0.
\param [in] op1 Value to rotate
\return Rotated value
*/
__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1)
{
return 0;
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] addr Pointer to location
\return value of type uint8_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr));
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] addr Pointer to location
\return value of type uint16_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr));
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] addr Pointer to location
\return value of type uint32_t at (*ptr)
*/
__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr));
return (result);
}
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] addr Pointer to location
*/
__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory");
}
/*@}*/ /* end of group CSI_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics
Access to dedicated SIMD instructions \n
Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
@{
*/
/**
\brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16]
of val2 levitated with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be left-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for left-shifting val2. Value range [0..31].
\return the combination of halfwords.
\remark
res[15:0] = val1[15:0] \n
res[31:16] = val2[31:16] << val3
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000));
}
/**
\brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0]
of val2 right-shifted with the val3.
\details Combine a halfword from one register with a halfword from another register.
The second argument can be right-shifted before extraction of the halfword.
\param [in] val1 first 16-bit operands
\param [in] val2 second 16-bit operands
\param [in] val3 value for right-shifting val2. Value range [1..32].
\return the combination of halfwords.
\remark
res[15:0] = val2[15:0] >> val3 \n
res[31:16] = val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3)
{
return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF));
}
/**
\brief Dual 16-bit signed saturate.
\details This function saturates a signed value.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:\n
the signed saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the signed saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF;
s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturate.
\details This function enables you to saturate two signed 16-bit values to a selected unsigned range.
\param [in] x two signed 16-bit values to be saturated.
\param [in] y bit position for saturation, an integral constant expression in the range 1 to 16.
\return the saturation of the two signed 16-bit values, as non-negative values:
the saturation of the low halfword in val1, saturated to the bit position specified in
val2 and returned in the low halfword of the return value.\n
the saturation of the high halfword in val1, saturated to the bit position specified in
val2 and returned in the high halfword of the return value.
*/
__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF;
s = __IUSAT(((x) >> 16), y) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit saturating addition.
\details This function enables you to perform four 8-bit integer additions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating addition.
\details This function enables you to perform four unsigned 8-bit integer additions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the saturated addition of the first byte of each operand in the first byte of the return value.\n
the saturated addition of the second byte of each operand in the second byte of the return value.\n
the saturated addition of the third byte of each operand in the third byte of the return value.\n
the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed addition.
\details This function performs four 8-bit signed integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition.
\details This function performs four unsigned 8-bit integer additions.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the addition of the first bytes from each operand, in the first byte of the return value.\n
the addition of the second bytes of each operand, in the second byte of the return value.\n
the addition of the third bytes of each operand, in the third byte of the return value.\n
the addition of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] + val2[7:0] \n
res[15:8] = val1[15:8] + val2[15:8] \n
res[23:16] = val1[23:16] + val2[23:16] \n
res[31:24] = val1[31:24] + val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit saturating subtract.
\details This function enables you to perform four 8-bit integer subtractions,
saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned saturating subtraction.
\details This function enables you to perform four unsigned 8-bit integer subtractions,
saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the subtraction of the first byte of each operand in the first byte of the return value.\n
the subtraction of the second byte of each operand in the second byte of the return value.\n
the subtraction of the third byte of each operand in the third byte of the return value.\n
the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF;
s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF;
t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF;
u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Quad 8-bit signed subtraction.
\details This function enables you to perform four 8-bit signed integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF;
u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtract.
\details This function enables you to perform four 8-bit unsigned integer subtractions.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
res[7:0] = val1[7:0] - val2[7:0] \n
res[15:8] = val1[15:8] - val2[15:8] \n
res[23:16] = val1[23:16] - val2[23:16] \n
res[31:24] = val1[31:24] - val2[31:24]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences together, returning the result as a single unsigned integer.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\return the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n
The sum is returned as a single unsigned integer.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
*/
__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF;
u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
return (u + t + s + r);
}
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
of the differences to a 32-bit accumulate operand.
\param [in] x first four 8-bit operands of each subtraction.
\param [in] y second four 8-bit operands of each subtraction.
\param [in] sum accumulation value.
\return the sum of the absolute differences of the following bytes, added to the accumulation value:
the subtraction of the first bytes from each operand, in the first byte of the return value.\n
the subtraction of the second bytes of each operand, in the second byte of the return value.\n
the subtraction of the third bytes of each operand, in the third byte of the return value.\n
the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
\remark
absdiff1 = val1[7:0] - val2[7:0] \n
absdiff2 = val1[15:8] - val2[15:8] \n
absdiff3 = val1[23:16] - val2[23:16] \n
absdiff4 = val1[31:24] - val2[31:24] \n
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n
res[31:0] = sum[31:0] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
{
int32_t r, s, t, u;
#ifdef __cplusplus
r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#else
r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF;
#endif
return (u + t + s + r + sum);
}
/**
\brief Dual 16-bit saturating addition.
\details This function enables you to perform two 16-bit integer arithmetic additions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition.
\details This function enables you to perform two unsigned 16-bit integer additions, saturating
the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated addition of the low halfwords, in the low halfword of the return value.\n
the saturated addition of the high halfwords, in the high halfword of the return value.\n
The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition.
\details This function enables you to perform two 16-bit signed integer additions.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition
\details This function enables you to perform two 16-bit unsigned integer additions.
\param [in] x first two 16-bit summands for each addition.
\param [in] y second two 16-bit summands for each addition.
\return the addition of the low halfwords in the low halfword of the return value.\n
the addition of the high halfwords in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] + val2[15:0] \n
res[31:16] = val1[31:16] + val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y)
{
int32_t r = 0, s = 0;
r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition with halved results.
\details This function enables you to perform two signed 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition with halved results.
\details This function enables you to perform two unsigned 16-bit integer additions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved addition of the low halfwords, in the low halfword of the return value.\n
the halved addition of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] + val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned addition with halved results.
\details This function enables you to perform four unsigned 8-bit integer additions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved addition of the first bytes from each operand, in the first byte of the return value.\n
the halved addition of the second bytes from each operand, in the second byte of the return value.\n
the halved addition of the third bytes from each operand, in the third byte of the return value.\n
the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] + val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit saturating subtract.
\details This function enables you to perform two 16-bit integer subtractions in parallel,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction.
\details This function enables you to perform two unsigned 16-bit integer subtractions,
saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
\param [in] x first two 16-bit operands for each subtraction.
\param [in] y second two 16-bit operands for each subtraction.
\return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction.
\details This function enables you to perform two 16-bit signed integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtract.
\details This function enables you to perform two 16-bit unsigned integer subtractions.
\param [in] x first two 16-bit operands of each subtraction.
\param [in] y second two 16-bit operands of each subtraction.
\return the subtraction of the low halfword in the second operand from the low
halfword in the first operand, in the low halfword of the return value. \n
the subtraction of the high halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[15:0] \n
res[31:16] = val1[31:16] - val2[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction with halved results.
\details This function enables you to perform two signed 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction with halved results.
\details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
\param [in] x first two 16-bit summands.
\param [in] y second two 16-bit summands.
\return the halved subtraction of the low halfwords, in the low halfword of the return value.\n
the halved subtraction of the high halfwords, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n
res[31:16] = (val1[31:16] - val2[31:16]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Quad 8-bit signed addition with halved results.
\details This function enables you to perform four signed 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF;
u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}
/**
\brief Quad 8-bit unsigned subtraction with halved results.
\details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
\param [in] x first four 8-bit summands.
\param [in] y second four 8-bit summands.
\return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
\remark
res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n
res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n
res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n
res[31:24] = (val1[31:24] - val2[31:24]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y)
{
int32_t r, s, t, u;
r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF;
s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF;
t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF;
u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF;
return ((u << 24) | (t << 16) | (s << 8) | (r));
}
/**
\brief Dual 16-bit add and subtract with exchange.
\details This function enables you to exchange the halfwords of the one operand,
then add the high halfwords and subtract the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating addition and subtraction with exchange.
\details This function enables you to exchange the halfwords of the second operand and
perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction,
saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the saturated subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the saturated addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit addition and subtraction with exchange.
\details It enables you to exchange the halfwords of the second operand, add the high halfwords
and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with exchange.
\details This function enables you to exchange the two halfwords of the second operand,
add the high halfwords and subtract the low halfwords.
\param [in] x first operand for the subtraction in the low halfword,
and the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword,
and the second operand for the addition in the low halfword.
\return the subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the addition of the high halfword in the first operand and the
low halfword in the second operand, in the high halfword of the return value.
\remark
res[15:0] = val1[15:0] - val2[31:16] \n
res[31:16] = val1[31:16] + val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed addition and subtraction with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one
signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned addition and subtraction with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
add the high halfwords and subtract the low halfwords, halving the results.
\param [in] x first operand for the subtraction in the low halfword, and
the first operand for the addition in the high halfword.
\param [in] y second operand for the subtraction in the high halfword, and
the second operand for the addition in the low halfword.
\return the halved subtraction of the high halfword in the second operand from the
low halfword in the first operand, in the low halfword of the return value.\n
the halved addition of the low halfword in the second operand from the high
halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] + val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit subtract and add with exchange.
\details This function enables you to exchange the halfwords of one operand,
then subtract the high halfwords and add the low halfwords,
saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned saturating subtraction and addition with exchange.
\details This function enables you to exchange the halfwords of the second operand and perform
one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating
the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the saturated addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the saturated subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit unsigned subtract and add with exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords.
\param [in] x first operand for the addition in the low halfword,
and the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword,
and the second operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF;
s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed subtraction and addition with exchange.
\details This function enables you to exchange the two halfwords of one operand and perform one
16-bit integer subtraction and one 16-bit addition.
\param [in] x first operand for the addition in the low halfword, and the first operand
for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and the second
operand for the subtraction in the low halfword.
\return the addition of the low halfword of the first operand and the high
halfword of the second operand, in the low halfword of the return value.\n
the subtraction of the low halfword of the second operand from the
high halfword of the first operand, in the high halfword of the return value.\n
\remark
res[15:0] = val1[15:0] + val2[31:16] \n
res[31:16] = val1[31:16] - val2[15:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit signed subtraction and addition with halved results.
\details This function enables you to exchange the two halfwords of one operand, perform one signed
16-bit integer subtraction and one signed 16-bit addition, and halve the results.
\param [in] x first 16-bit operands.
\param [in] y second 16-bit operands.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
return ((uint32_t)((s << 16) | (r)));
}
/**
\brief Dual 16-bit unsigned subtraction and addition with halved results and exchange.
\details This function enables you to exchange the halfwords of the second operand,
subtract the high halfwords and add the low halfwords, halving the results.
\param [in] x first operand for the addition in the low halfword, and
the first operand for the subtraction in the high halfword.
\param [in] y second operand for the addition in the high halfword, and
the second operand for the subtraction in the low halfword.
\return the halved addition of the low halfword in the first operand and the
high halfword in the second operand, in the low halfword of the return value.\n
the halved subtraction of the low halfword in the second operand from the
high halfword in the first operand, in the high halfword of the return value.
\remark
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n
res[31:16] = (val1[31:16] - val2[15:0]) >> 1
*/
__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y)
{
int32_t r, s;
r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
return ((s << 16) | (r));
}
/**
\brief Dual 16-bit signed multiply with exchange returning difference.
\details This function enables you to perform two 16-bit signed multiplications, subtracting
one of the products from the other. The halfwords of the second operand are exchanged
before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Sum of dual 16-bit signed multiply with exchange.
\details This function enables you to perform two 16-bit signed multiplications with exchanged
halfwords of the second operand, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
}
/**
\brief Saturating add.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 + SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) {
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if ((int32_t)((uint32_t)x + (uint32_t)y) < x) {
result = x + y;
} else {
result = 0x80000000;
}
}
return result;
}
/**
\brief Saturating subtract.
\details This function enables you to obtain the saturating add of two integers.
\param [in] x first summand of the saturating add operation.
\param [in] y second summand of the saturating add operation.
\return the saturating addition of val1 and val2.
\remark
res[31:0] = SAT(val1 - SAT(val2))
*/
__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
{
int64_t tmp;
int32_t result;
tmp = (int64_t)x - (int64_t)y;
if (tmp > 0x7fffffff) {
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
tmp = -2147483647 - 1;
}
result = tmp;
return result;
}
/**
\brief Dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications,
adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications with exchanged
halfwords of the second operand, adding both results to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication with exchanged halfwords of the second
operand added to the accumulate value, as a 32-bit integer.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 + p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to perform two 16-bit signed multiplications, take the
difference of the products, subtracting the high halfword product from the low
halfword product, and add the difference to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
\details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit
signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[31:0] = p1 - p2 + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((int32_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with single 64-bit accumulator.
\details This function enables you to perform two signed 16-bit multiplications, adding both results
to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition.
This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
\details This function enables you to exchange the halfwords of the second operand, and perform two
signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow
is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs.
Instead, the result wraps around modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the product of each multiplication added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
sum = p1 + p2 + val3[63:32][31:0] \n
res[63:32] = sum[63:32] \n
res[31:0] = sum[31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief dual 16-bit signed multiply subtract with 64-bit accumulate.
\details This function It enables you to perform two 16-bit signed multiplications, take the difference
of the products, subtracting the high halfword product from the low halfword product, and add the
difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the
subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not
detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
\details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications,
adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the
multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow
is not detected. Instead, the result wraps round to modulo2^64.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\param [in] sum accumulate value.
\return the difference of the product of each multiplication, added to the accumulate value.
\remark
p1 = val1[15:0] * val2[31:16] \n
p2 = val1[31:16] * val2[15:0] \n
res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
*/
__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum)
{
return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
(((uint64_t)sum))));
}
/**
\brief 32-bit signed multiply with 32-bit truncated accumulator.
\details This function enables you to perform a signed 32-bit multiplications, adding the most
significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
\param [in] x first operand for multiplication.
\param [in] y second operand for multiplication.
\param [in] sum accumulate value.
\return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
\remark
p = val1 * val2 \n
res[31:0] = p[63:32] + val3[31:0]
*/
__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum)
{
return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum);
}
/**
\brief Sum of dual 16-bit signed multiply.
\details This function enables you to perform two 16-bit signed multiplications, adding the products together.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the sum of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 + p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual 16-bit signed multiply returning difference.
\details This function enables you to perform two 16-bit signed multiplications, taking the difference
of the products by subtracting the high halfword product from the low halfword product.
\param [in] x first 16-bit operands for each multiplication.
\param [in] y second 16-bit operands for each multiplication.
\return the difference of the products of the two 16-bit signed multiplications.
\remark
p1 = val1[15:0] * val2[15:0] \n
p2 = val1[31:16] * val2[31:16] \n
res[31:0] = p1 - p2
*/
__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
}
/**
\brief Dual extracted 8-bit to 16-bit signed addition.
\details This function enables you to extract two 8-bit values from the second operand (at bit positions
[7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
\param [in] x values added to the sign-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and sign-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and sign-extended prior to the addition.
\remark
res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) |
(((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000)));
}
/**
\brief Extracted 16-bit to 32-bit unsigned addition.
\details This function enables you to extract two 8-bit values from one operand, zero-extend
them to 16 bits each, and add the results to two 16-bit values from another operand.
\param [in] x values added to the zero-extended to 16-bit values.
\param [in] y two 8-bit values to be extracted and zero-extended.
\return the addition of val1 and val2, where the 8-bit values in val2[7:0] and
val2[23:16] have been extracted and zero-extended prior to the addition.
\remark
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y)
{
return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) |
((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and sign extend each to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x)
{
return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) |
((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000)));
}
/**
\brief Dual extract 8-bits and zero-extend to 16-bits.
\details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
\param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended.
\return the 8-bit values sign-extended to 16-bit values.\n
sign-extended value of val[7:0] in the low halfword of the return value.\n
sign-extended value of val[23:16] in the high halfword of the return value.
\remark
res[15:0] = SignExtended(val[7:0]) \n
res[31:16] = SignExtended(val[23:16])
*/
__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
{
return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) |
(((x << 8) >> 8) & 0xFFFF0000)));
}
#endif /* _CSI_RV32_GCC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/core/csi_rv32_gcc.h | C | apache-2.0 | 106,830 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file csi_core.h
* @brief CSI Core Layer Header File
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef _CORE_H_
#define _CORE_H_
#include <stdint.h>
#if defined(__CK801__) || defined(__E801__)
#include <core/core_801.h>
#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
#include <core/core_802.h>
#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
#include <core/core_804.h>
#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
#include <core/core_803.h>
#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
#include <core/core_805.h>
#elif defined(__CK610__)
#include <core/core_ck610.h>
#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
#include <core/core_810.h>
#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
#include <core/core_807.h>
#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
#include <core/core_rv32_old.h>
#elif defined(__riscv) && (__riscv_xlen == 32)
#include <core/core_rv32.h>
#elif defined(__riscv) && (__riscv_xlen == 64)
#include <core/core_rv64.h>
#endif
#if defined(__riscv) && (__riscv_xlen == 32)
#include <core/csi_rv32_gcc.h>
#elif defined(__riscv) && (__riscv_xlen == 64)
#include <core/csi_rv64_gcc.h>
#elif defined(__csky__)
#include <core/csi_gcc.h>
#endif
#ifdef __arm__
#include <csi_core_cmsis.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CORE_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/csi_core.h | C | apache-2.0 | 1,997 |
/*
* @file csi_kernel.h
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file aos/kernel.h
* @brief header file for kernel definition
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#ifndef _CSI_KERNEL_
#define _CSI_KERNEL_
#include <stdint.h>
#include <errno.h>
#ifdef __cplusplus
extern "C"
{
#endif
/* =================================================================================== */
/* Enumerations, structures, defines */
/* =================================================================================== */
/// Status code values returned by CSI-kernel functions. 0 - success, negative represents error code ,see errno.h
typedef int32_t k_status_t;
/// Kernel scheduler state.
typedef enum {
KSCHED_ST_INACTIVE = 0, ///< Inactive: The kernel is not ready yet. csi_kernel_init needs to be executed successfully.
KSCHED_ST_READY = 1, ///< Ready: The kernel is not yet running. csi_kernel_start transfers the kernel to the running state.
KSCHED_ST_RUNNING = 2, ///< Running: The kernel is initialized and running.
KSCHED_ST_LOCKED = 3, ///< Locked: The kernel was locked with csi_kernel_sched_lock. The functions csi_kernel_sched_unlock or csi_kernel_sched_restore_lock unlocks it.
KSCHED_ST_SUSPEND = 4, ///< Suspended: The kernel was suspended using aos_kernel_sched_suspend. The function aos_kernel_sched_resume returns to normal operation
KSCHED_ST_ERROR = 5 ///< Error: An error occurred.
} k_sched_stat_t;
/// task state.
typedef enum {
KTASK_ST_INACTIVE = 0, ///< Inactive.
KTASK_ST_READY = 1, ///< Ready.
KTASK_ST_RUNNING = 2, ///< Running.
KTASK_ST_BLOCKED = 3, ///< Blocked.
KTASK_ST_TERMINATED = 4, ///< Terminated.
KTASK_ST_ERROR = 5 ///< Error: An error occurred.
} k_task_stat_t;
/// timer state.
typedef enum {
KTIMER_ST_INACTIVE = 0, ///< not running
KTIMER_ST_ACTIVE = 1, ///< running
} k_timer_stat_t;
/// Timer type.
typedef enum {
KTIMER_TYPE_ONCE = 0, ///< One-shot timer.
KTIMER_TYPE_PERIODIC = 1 ///< Repeating timer.
} k_timer_type_t;
/// event option.
typedef enum {
KEVENT_OPT_SET_ANY = 0, ///< Check any bit in flags to be 1.
KEVENT_OPT_SET_ALL = 1, ///< Check all bits in flags to be 1.
KEVENT_OPT_CLR_ANY = 2, ///< Check any bit in flags to be 0.
KEVENT_OPT_CLR_ALL = 3 ///< Check all bits in flags to be 0.
} k_event_opt_t;
/// Priority definition.
typedef enum {
KPRIO_IDLE = 0, ///< priority: idle (lowest)
KPRIO_LOW0 , ///< priority: low
KPRIO_LOW1 , ///< priority: low + 1
KPRIO_LOW2 , ///< priority: low + 2
KPRIO_LOW3 , ///< priority: low + 3
KPRIO_LOW4 , ///< priority: low + 4
KPRIO_LOW5 , ///< priority: low + 5
KPRIO_LOW6 , ///< priority: low + 6
KPRIO_LOW7 , ///< priority: low + 7
KPRIO_NORMAL_BELOW0 , ///< priority: below normal
KPRIO_NORMAL_BELOW1 , ///< priority: below normal + 1
KPRIO_NORMAL_BELOW2 , ///< priority: below normal + 2
KPRIO_NORMAL_BELOW3 , ///< priority: below normal + 3
KPRIO_NORMAL_BELOW4 , ///< priority: below normal + 4
KPRIO_NORMAL_BELOW5 , ///< priority: below normal + 5
KPRIO_NORMAL_BELOW6 , ///< priority: below normal + 6
KPRIO_NORMAL_BELOW7 , ///< priority: below normal + 7
KPRIO_NORMAL , ///< priority: normal (default)
KPRIO_NORMAL1 , ///< priority: normal + 1
KPRIO_NORMAL2 , ///< priority: normal + 2
KPRIO_NORMAL3 , ///< priority: normal + 3
KPRIO_NORMAL4 , ///< priority: normal + 4
KPRIO_NORMAL5 , ///< priority: normal + 5
KPRIO_NORMAL6 , ///< priority: normal + 6
KPRIO_NORMAL7 , ///< priority: normal + 7
KPRIO_NORMAL_ABOVE0 , ///< priority: above normal + 1
KPRIO_NORMAL_ABOVE1 , ///< priority: above normal + 2
KPRIO_NORMAL_ABOVE2 , ///< priority: above normal + 3
KPRIO_NORMAL_ABOVE3 , ///< priority: above normal + 4
KPRIO_NORMAL_ABOVE4 , ///< priority: above normal + 5
KPRIO_NORMAL_ABOVE5 , ///< priority: above normal + 6
KPRIO_NORMAL_ABOVE6 , ///< priority: above normal + 7
KPRIO_NORMAL_ABOVE7 , ///< priority: above normal + 8
KPRIO_HIGH0 , ///< priority: high
KPRIO_HIGH1 , ///< priority: high + 1
KPRIO_HIGH2 , ///< priority: high + 2
KPRIO_HIGH3 , ///< priority: high + 3
KPRIO_HIGH4 , ///< priority: high + 4
KPRIO_HIGH5 , ///< priority: high + 5
KPRIO_HIGH6 , ///< priority: high + 6
KPRIO_HIGH7 , ///< priority: high + 7
KPRIO_REALTIME0 , ///< priority: realtime + 1
KPRIO_REALTIME1 , ///< priority: realtime + 2
KPRIO_REALTIME2 , ///< priority: realtime + 3
KPRIO_REALTIME3 , ///< priority: realtime + 4
KPRIO_REALTIME4 , ///< priority: realtime + 5
KPRIO_REALTIME5 , ///< priority: realtime + 6
KPRIO_REALTIME6 , ///< priority: realtime + 7
KPRIO_REALTIME7 , ///< priority: realtime + 8
KPRIO_ISR , ///< priority: Reserved for ISR deferred thread
KPRIO_ERROR ///< Illegal priority
} k_priority_t;
/// Entry point of a task.
typedef void (*k_task_entry_t)(void *arg);
/// Entry point of a timer call back function.
typedef void (*k_timer_cb_t)(void *arg);
/// \details Task handle identifies the task.
typedef void *k_task_handle_t;
/// \details Timer handle identifies the timer.
typedef void *k_timer_handle_t;
/// \details Event Flags handle identifies the event flags.
typedef void *k_event_handle_t;
/// \details Mutex handle identifies the mutex.
typedef void *k_mutex_handle_t;
/// \details Semaphore handle identifies the semaphore.
typedef void *k_sem_handle_t;
/// \details Memory Pool handle identifies the memory pool.
typedef void *k_mpool_handle_t;
/// \details Message Queue handle identifies the message queue.
typedef void *k_msgq_handle_t;
/* =================================================================================== */
/* Kernel Management Functions */
/* =================================================================================== */
/// Initialize the Kernel. Before it is successfully executed, no RTOS function should be called
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_init(void);
/// Start the kernel .It will not return to its calling function in case of success
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_start(void);
/// Get the current kernel state.
/// \return current kernel state \ref k_sched_stat_t .
k_sched_stat_t csi_kernel_get_stat(void);
/* =================================================================================== */
/* scheduler Management Functions */
/* =================================================================================== */
/// Lock the scheduler.
/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
int32_t csi_kernel_sched_lock(void);
/// Unlock the scheduler.
/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
int32_t csi_kernel_sched_unlock(void);
/// Restore the scheduler lock state.
/// \param[in] lock lock state obtained by \ref csi_kernel_sched_lock or \ref csi_kernel_sched_unlock.
/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
int32_t csi_kernel_sched_restore_lock(int32_t lock);
/// Suspend the scheduler.
/// \return time in ticks, for how long the system can sleep or power-down.
uint32_t aos_kernel_sched_suspend(void);
/// Resume the scheduler.
/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
void aos_kernel_sched_resume(uint32_t sleep_ticks);
/* =================================================================================== */
/* Task Management Functions */
/* =================================================================================== */
/// Create a task and add it to Active Tasks.
/// \param[in] task task function.
/// \param[in] name the name of task.
/// \param[in] arg pointer that is passed to the task function as start argument.
/// \param[in] prio task priority.
/// \param[in] time_quanta the amount of time (in clock ticks) for the time quanta when round robin is enabled,if Zero, then use FIFO sched
/// \param[in] stack stack base.
/// \param[in] stack_size stack size.
/// \param[in] task_handle reference to a task handle.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_new(k_task_entry_t task, const char *name, void *arg,
k_priority_t prio, uint32_t time_quanta,
void *stack, uint32_t stack_size, k_task_handle_t *task_handle);
/// Delete a task.
/// \param[in] task_handle task handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_del(k_task_handle_t task_handle);
/// Return the task handle of the current running task.
/// \return task handle for reference by other functions or NULL in case of error.
k_task_handle_t csi_kernel_task_get_cur(void);
/// Get current task state of a task.
/// \param[in] task_handle task handle to operate.
/// \return current task state of the specified task.
k_task_stat_t csi_kernel_task_get_stat(k_task_handle_t task_handle);
/// Change priority of a task.
/// \param[in] task_handle task handle to operate.
/// \param[in] priority new priority value for the task function.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_set_prio(k_task_handle_t task_handle, k_priority_t priority);
/// Get current priority of a task.
/// \param[in] task_handle task handle to operate.
/// \return current priority value of the specified task.negative indicates error code.
k_priority_t csi_kernel_task_get_prio(k_task_handle_t task_handle);
/// Get name of a task.
/// \param[in] task_handle task handle to operate.
/// \return name of the task.
const char *csi_kernel_task_get_name(k_task_handle_t task_handle);
/// Suspend execution of a task.
/// \param[in] task_handle task handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_suspend(k_task_handle_t task_handle);
/// Resume execution of a task.
/// \param[in] task_handle task handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_resume(k_task_handle_t task_handle);
/// Terminate execution of a task.
/// \param[in] task_handle task handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_terminate(k_task_handle_t task_handle);
/// Exit from the calling task.
/// \return none
void csi_kernel_task_exit(void);
/// Pass control to next task that is in state \b READY.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_task_yield(void);
/// Get number of active tasks.
/// \return number of active tasks.
uint32_t csi_kernel_task_get_count(void);
/// Get stack size of a task.
/// \param[in] task_handle task handle to operate.
/// \return stack size in bytes.
uint32_t csi_kernel_task_get_stack_size(k_task_handle_t task_handle);
/// Get available stack space of a thread based on stack watermark recording during execution.
/// \param[in] task_handle task handle to operate.
/// \return remaining stack space in bytes.
uint32_t csi_kernel_task_get_stack_space(k_task_handle_t task_handle);
/// Enumerate active tasks.
/// \param[out] task_array pointer to array for retrieving task handles.
/// \param[in] array_items maximum number of items in array for retrieving task handles.
/// \return number of enumerated tasks.
uint32_t csi_kernel_task_list(k_task_handle_t *task_array, uint32_t array_items);
/// System enter interrupt status.
/// \return execution status code. \ref k_status_t
k_status_t aos_kernel_intrpt_enter(void);
/// System exit interrupt status.
/// \return execution status code. \ref k_status_t
k_status_t aos_kernel_intrpt_exit(void);
/* =================================================================================== */
/* Generic time Functions */
/* =================================================================================== */
/// Waits for a time period specified in kernel ticks.
/// \param[in] ticks time ticks value
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_delay(uint32_t ticks);
/// Waits until an absolute time (specified in kernel ticks) is reached.
/// \param[in] ticks absolute time in ticks
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_delay_until(uint64_t ticks);
/// Convert kernel ticks to ms.
/// \param[in] ticks ticks which will be converted to ms
/// \return the ms of the ticks.
uint64_t csi_kernel_tick2ms(uint32_t ticks);
/// Convert ms to kernel ticks.
/// \param[in] ms ms which will be converted to ticks
/// \return the ticks of the ms.
uint64_t csi_kernel_ms2tick(uint32_t ms);
/// Waits for a time period specified in ms.
/// \param[in] ms time to be delayed in ms
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_delay_ms(uint32_t ms);
/// Get kernel ticks.
/// \return kernel ticks number
uint64_t csi_kernel_get_ticks(void);
/// Get the RTOS kernel tick frequency.
/// \return frequency of the kernel tick.
uint32_t csi_kernel_get_tick_freq(void);
/// Get the RTOS kernel system timer frequency.
/// \return frequency of the system timer.
uint32_t csi_kernel_get_systimer_freq(void);
/* =================================================================================== */
/* Timer Management Functions */
/* =================================================================================== */
/// Create and Initialize a timer.
/// \param[in] func start address of a timer call back function.
/// \param[in] type time type, \ref k_timer_type_t.
/// \param[in] arg argument to the timer call back function.
/// \return timer handle for reference by other functions or NULL in case of error.
k_timer_handle_t csi_kernel_timer_new(k_timer_cb_t func, k_timer_type_t type, void *arg);
/// Delete a timer.
/// \param[in] timer_handle timer handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_timer_del(k_timer_handle_t timer_handle);
/// Start or restart a timer.
/// \param[in] timer_handle timer handle to operate.
/// \param[in] ticks time out value in ticks
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_timer_start(k_timer_handle_t timer_handle, uint32_t ticks);
/// Stop a timer.
/// \param[in] timer_handle timer handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_timer_stop(k_timer_handle_t timer_handle);
/// Check if a timer is running.
/// \param[in] timer_handle timer handle to operate.
/// \return \ref k_timer_stat_t.
k_timer_stat_t csi_kernel_timer_get_stat(k_timer_handle_t timer_handle);
/* =================================================================================== */
/* Event Management Functions */
/* =================================================================================== */
/// Create and Initialize an Event Flags object.
/// \return event flags handle for reference by other functions or NULL in case of error.
k_event_handle_t csi_kernel_event_new(void);
/// Delete an Event Flags object.
/// \param[in] ev_handle event flags handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_event_del(k_event_handle_t ev_handle);
/// Set the specified Event Flags.
/// \param[in] ev_handle event flags handle to operate.
/// \param[in] flags specifies the flags that shall be set.
/// \param[out] ret_flags The value of the event after setting.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_event_set(k_event_handle_t ev_handle, uint32_t flags, uint32_t *ret_flags);
/// Clear the specified Event Flags.
/// \param[in] ev_handle event flags handle to operate.
/// \param[in] flags specifies the flags that shall be clear.
/// \param[out] ret_flags event flags before clearing.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_event_clear(k_event_handle_t ev_handle, uint32_t flags, uint32_t *ret_flags);
/// Get the current Event Flags. This function allows the user to know “Who did it!”
/// \param[in] ev_handle event flags handle to operate.
/// \param[out] ret_flags The value of the current event.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_event_get(k_event_handle_t ev_handle, uint32_t *ret_flags);
/// Wait for one or more Event Flags to become signaled.
/// \param[in] ev_handle event flags handle to operate.
/// \param[in] flags specifies the flags to wait for.
/// \param[in] options specifies flags options, \ref k_event_opt_t.
/// \param[in] clr_on_exit 1 - event flags will be cleared before exit, otherwise event flags are not altered
/// \param[out] actl_flags The value of the event at the time either the bits being waited for became set, or the block time expired.
/// \param[in] timeout time out value in ticks if > 0, 0 in case of no time-out, negative in case of wait forever
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_event_wait(k_event_handle_t ev_handle, uint32_t flags,
k_event_opt_t options, uint8_t clr_on_exit,
uint32_t *actl_flags, int32_t timeout);
/* =================================================================================== */
/* Mutex Management Functions */
/* =================================================================================== */
/// Create and Initialize a Mutex object.
/// \return mutex handle for reference by other functions or NULL in case of error.
k_mutex_handle_t csi_kernel_mutex_new(void);
/// Delete a Mutex object.
/// \param[in] mutex_handle mutex handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_mutex_del(k_mutex_handle_t mutex_handle);
/// Acquire a Mutex or timeout if it is locked.
/// \param[in] mutex_handle mutex handle to operate.
/// \param[in] timeout time out value in ticks if > 0, 0 in case of no time-out, negative in case of wait forever
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_mutex_lock(k_mutex_handle_t mutex_handle, int32_t timeout);
/// Release a Mutex that was acquired by \ref csi_kernel_mutex_new.
/// \param[in] mutex_handle mutex handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_mutex_unlock(k_mutex_handle_t mutex_handle);
/// Get Thread which owns a Mutex object.
/// \param[in] mutex_handle mutex handle to operate.
/// \return task handle or NULL when mutex was not acquired.
k_task_handle_t csi_kernel_mutex_get_owner(k_mutex_handle_t mutex_handle);
/* =================================================================================== */
/* Semaphore Management Functions */
/* =================================================================================== */
/// Create and Initialize a Semaphore object.
/// \param[in] max_count maximum number of available tokens.
/// \param[in] initial_count initial number of available tokens.
/// \return semaphore handle for reference by other functions or NULL in case of error.
k_sem_handle_t csi_kernel_sem_new(int32_t max_count, int32_t initial_count);
/// Delete a Semaphore object.
/// \param[in] sem_handle semaphore handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_sem_del(k_sem_handle_t sem_handle);
/// Acquire a Semaphore token or timeout if no tokens are available.
/// \param[in] sem_handle semaphore handle to operate.
/// \param[in] timeout time out value in ticks if > 0, 0 in case of no time-out, negative in case of wait forever
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_sem_wait(k_sem_handle_t sem_handle, int32_t timeout);
/// Release a Semaphore token that was acquired by \ref csi_kernel_sem_wait.
/// \param[in] sem_handle semaphore handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_sem_post(k_sem_handle_t sem_handle);
/// Get current Semaphore token count.
/// \param[in] sem_handle semaphore handle to operate.
/// \return number of tokens available. negative indicates error code.
int32_t csi_kernel_sem_get_count(k_sem_handle_t sem_handle);
/* =================================================================================== */
/* Memory Pool Management Functions */
/* =================================================================================== */
/// Create and Initialize a Memory Pool object.
/// \param[in] p_addr memory block base address.
/// \param[in] block_count maximum number of memory blocks in memory pool.
/// \param[in] block_size memory block size in bytes.
/// \return memory pool handle for reference by other functions or NULL in case of error.
k_mpool_handle_t csi_kernel_mpool_new(void *p_addr, int32_t block_count, int32_t block_size);
/// Delete a Memory Pool object.
/// \param[in] mp_handle memory pool handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_mpool_del(k_mpool_handle_t mp_handle);
/// Allocate a memory block from a Memory Pool.
/// \param[in] mp_handle memory pool handle to operate.
/// \param[in] timeout time out value in ticks if > 0, 0 in case of no time-out, negative in case of wait forever
/// \return address of the allocated memory block or NULL in case of no memory is available.
void *csi_kernel_mpool_alloc(k_mpool_handle_t mp_handle, int32_t timeout);
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] mp_handle memory pool handle to operate.
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_mpool_free(k_mpool_handle_t mp_handle, void *block);
/// Get number of memory blocks used in a Memory Pool.
/// \param[in] mp_handle memory pool handle to operate.
/// \return number of memory blocks used. negative indicates error code.
int32_t csi_kernel_mpool_get_count(k_mpool_handle_t mp_handle);
/// Get maximum number of memory blocks in a Memory Pool.
/// \param[in] mp_handle memory pool handle to operate.
/// \return maximum number of memory blocks.
uint32_t csi_kernel_mpool_get_capacity(k_mpool_handle_t mp_handle);
/// Get memory block size in a Memory Pool.
/// \param[in] mp_handle memory pool handle to operate.
/// \return memory block size in bytes.
uint32_t csi_kernel_mpool_get_block_size(k_mpool_handle_t mp_handle);
/* =================================================================================== */
/* Message Queue Management Functions */
/* =================================================================================== */
/// Create and Initialize a Message Queue object.
/// \param[in] msg_count maximum number of messages in queue.
/// \param[in] msg_size maximum message size in bytes.
/// \return message queue handle for reference by other functions or NULL in case of error.
k_msgq_handle_t csi_kernel_msgq_new(int32_t msg_count, int32_t msg_size);
/// Delete a Message Queue object.
/// \param[in] mq_handle message queue handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_msgq_del(k_msgq_handle_t mq_handle);
/// Put a Message into a Queue or timeout if Queue is full.
/// \param[in] mq_handle message queue handle to operate.
/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
/// \param[in] front_or_back specify this msg to be put to front or back. 1 - front, 0 -back
/// \param[in] timeout time out value in ticks if > 0, 0 in case of no time-out, negative in case of wait forever
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_msgq_put(k_msgq_handle_t mq_handle, const void *msg_ptr, uint8_t front_or_back, int32_t timeout);
/// Get a Message from a Queue or timeout if Queue is empty.
/// \param[in] mq_handle message queue handle to operate.
/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
/// \param[in] timeout time out value in ticks if > 0, 0 in case of no time-out, negative in case of wait forever
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_msgq_get(k_msgq_handle_t mq_handle, void *msg_ptr, int32_t timeout);
/// Get number of queued messages in a message queue.
/// \param[in] mq_handle message queue handle to operate.
/// \return number of queued messages.negative indicates error code.
int32_t csi_kernel_msgq_get_count(k_msgq_handle_t mq_handle);
/// Get maximum number of messages in a message queue.
/// \param[in] mq_handle message queue handle to operate.
/// \return maximum number of messages.
uint32_t csi_kernel_msgq_get_capacity(k_msgq_handle_t mq_handle);
/// Get maximum message size in a message queue.
/// \param[in] mq_handle message queue handle to operate.
/// \return maximum message size in bytes.
uint32_t csi_kernel_msgq_get_msg_size(k_msgq_handle_t mq_handle);
/// Reset a Message Queue to initial empty state.
/// \param[in] mq_handle message queue handle to operate.
/// \return execution status code. \ref k_status_t
k_status_t csi_kernel_msgq_flush(k_msgq_handle_t mq_handle);
/* =================================================================================== */
/* Heap Management Functions */
/* =================================================================================== */
/// Allocates size bytes and returns a pointer to the allocated memory.
/// \param[in] size Allocates size bytes.
/// \param[in] caller the function who call this interface or NULL.
/// \return a pointer to the allocated memory.
void *csi_kernel_malloc(int32_t size, void *caller);
/// Frees the memory space pointed to by ptr
/// \param[in] ptr a pointer to memory block, return by csi_kernel_malloc or csi_kernel_realloc.
/// \param[in] caller the function who call this interface or NULL.
/// \return void
void csi_kernel_free(void *ptr, void *caller);
/// Changes the size of the memory block pointed to by ptr to size bytes
/// \param[in] ptr a pointer to memory block, return by csi_kernel_malloc or csi_kernel_realloc.
/// \param[in] size Allocates size bytes.
/// \param[in] caller the function who call this interface or NULL.
/// \return a pointer to the allocated memory.
void *csi_kernel_realloc(void *ptr, int32_t size, void *caller);
/// Get csi memory used info.
/// \param[out] total the total memory can be use.
/// \param[out] used the used memory by malloc.
/// \param[out] free the free memory can be use.
/// \param[out] peak the peak memory used.
/// \return execution status code. \ref k_status_t.
k_status_t csi_kernel_get_mminfo(int32_t *total, int32_t *used, int32_t *free, int32_t *peak);
/// Dump csi memory .
/// \param void
/// \return execution status code. \ref k_status_t.
k_status_t csi_kernel_mm_dump(void);
#ifdef __cplusplus
}
#endif
#endif // _CSI_KERNEL_
| YifuLiu/AliOS-Things | components/csi/csi2/include/csi_kernel.h | C | apache-2.0 | 29,910 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/adc.h
* @brief Header File for ADC Driver
* @version V1.0
* @date 08. Apr 2020
* @model adc
******************************************************************************/
#ifndef _DRV_ADC_H_
#define _DRV_ADC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** ADC Event *****/
typedef enum {
ADC_EVENT_CONVERT_COMPLETE = 0, ///< All data convert completed
ADC_EVENT_CONVERT_HALF_DONE, ///< Convert half done
ADC_EVENT_ERROR ///< All errors including but not limited to what converted data has not been read before the new conversion result is load to the data register
} csi_adc_event_t;
typedef struct csi_adc csi_adc_t;
struct csi_adc {
csi_dev_t dev; ///< Hw-device info
void (*callback)(csi_adc_t *adc, csi_adc_event_t event, void *arg); ///< User callback ,signaled by driver event
void *arg; ///< User private param ,passed to user callback
uint32_t *data; ///< Data buf
uint32_t num; ///< Data size by word
csi_dma_ch_t *dma; ///< Dma channel handle
csi_error_t (*start)(csi_adc_t *adc); ///< Start function
csi_error_t (*stop)(csi_adc_t *adc); ///< Stop function
csi_state_t state; ///< ADC current state
void *priv;
};
/**
\brief Initialize adc Interface. Initialize the resources needed for the adc interface
\param[in] adc ADC handle to operate
\param[in] idx ADC controller index
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_init(csi_adc_t *adc, uint32_t idx);
/**
\brief De-initialize adc Interface. stops operation and releases the software resources used by the interface
\param[in] handle ADC handle to operate
\return None
*/
void csi_adc_uninit(csi_adc_t *adc);
/**
\brief Set adc receive buffer
\param[in] adc ADC handle to operate
\param[in] num The receive data length by word.
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_set_buffer(csi_adc_t *adc, uint32_t *data, uint32_t num);
/**
\brief Start adc
\param[in] handle ADC handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_start(csi_adc_t *adc);
/**
\brief Enable dma or interrupt, and start adc conversion
\param[in] handle ADC handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_start_async(csi_adc_t *adc);
/**
\brief Stop adc
\param[in] handle ADC handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_stop(csi_adc_t *adc);
/**
\brief Disable dma or interrupt, and stop adc conversion
\param[in] handle ADC handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_stop_async(csi_adc_t *adc);
/**
\brief ADC channel enable
\param[in] adc ADC handle to operate
\param[in] ch_id ADC channel id
\param[in] is_enable true->enable, false->disable
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_channel_enable(csi_adc_t *adc, uint8_t ch_id, bool is_enable);
/**
\brief Set the ADC sampling time for the selected channel
\param[in] adc ADC handle to operate
\param[in] ch_id ADC channel id
\param[in] clock_num Channel sampling clock number
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_channel_sampling_time(csi_adc_t *adc, uint8_t ch_id, uint16_t clock_num);
/**
\brief Set the ADC controller sampling time
\param[in] adc ADC handle to operate
\param[in] clock_num ADC controller sampling clock number
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_sampling_time(csi_adc_t *adc, uint16_t clock_num);
/**
\brief Enable the continue mode of ADC
\param[in] adc ADC handle to operate
\param[in] is_enable true->enable, false->disable
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_continue_mode(csi_adc_t *adc, bool is_enable);
/**
\brief Set ADC frequence division
\param[in] adc ADC handle to operate
\param[in] div The division of frequence
\return The actual config frequency
*/
uint32_t csi_adc_freq_div(csi_adc_t *adc, uint32_t div);
/**
\brief Receiving data from ADC receiver
\param[in] handle ADC handle to operate
\return If read successful, this function shall return the result of convert value
otherwise, the function shall return error code
*/
int32_t csi_adc_read(csi_adc_t *adc);
/**
\brief Receiving converted voltage(unit:mV) from ADC receiver
\param[in] handle ADC handle to operate
\return If read successful, this function shall return the voltage(unit:mV)
otherwise, the function shall return error code
*/
int32_t csi_adc_read_voltage(csi_adc_t *adc);
/**
\brief Get ADC state
\param[in] adc ADC handle to operate
\param[in] state ADC state
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_get_state(csi_adc_t *adc, csi_state_t *state);
/**
\brief Get ADC range
\param[in] adc ADC handle to operate
\param[in] ch_id Channel id
\param[out] range ADC range
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_get_range(csi_adc_t *adc, uint8_t ch_id, uint32_t *range);
/**
\brief Attach the callback handler to adc
\param[in] adc Operate handle
\param[in] callback Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_attach_callback(csi_adc_t *adc, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] adc Operate handle
\return None
*/
void csi_adc_detach_callback(csi_adc_t *adc);
/**
\brief Link DMA channel to adc device
\param[in] adc ADC handle to operate
\param[in] dma The DMA channel handle for send, when it is NULL means to unlink the channel
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_link_dma(csi_adc_t *adc, csi_dma_ch_t *dma);
/**
\brief Enable adc low power mode
\param[in] adc ADC handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_adc_enable_pm(csi_adc_t *adc);
/**
\brief Disable adc low power mode
\param[in] adc ADC handle to operate
\return None
*/
void csi_adc_disable_pm(csi_adc_t *adc);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_ADC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/adc.h | C | apache-2.0 | 7,000 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/aes.h
* @brief Header File for AES Driver
* @version V1.0
* @date 9. Oct 2020
* @model aes
******************************************************************************/
#ifndef _DRV_AES_H_
#define _DRV_AES_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/*----- Encrypt & Decrypt: Config key length -----*/
typedef enum {
AES_KEY_LEN_BITS_128 = 0, ///< 128 Data bits
AES_KEY_LEN_BITS_192, ///< 192 Data bits
AES_KEY_LEN_BITS_256 ///< 256 Data bits
} csi_aes_key_bits_t;
/**
\brief AES Ctrl Block
*/
typedef struct {
csi_dev_t dev;
void *priv;
} csi_aes_t;
/**
\brief Initialize AES interface. Initializes the resources needed for the AES interface
\param[in] aes Handle to operate
\param[in] idx Device id
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_init(csi_aes_t *aes, uint32_t idx);
/**
\brief De-initialize AES interface. Stops operation and releases the software resources used by the interface
\param[in] aes Dandle to operate
\return None
*/
void csi_aes_uninit(csi_aes_t *aes);
/**
\brief Set encrypt key
\param[in] aes Handle to operate
\param[in] key Pointer to the key buf
\param[in] key_len Pointer to \ref csi_aes_key_bits_t
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_set_encrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len);
/**
\brief Set decrypt key
\param[in] aes Handle to operate
\param[in] key Pointer to the key buf
\param[in] key_len Pointer to \ref csi_aes_key_bits_t
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_set_decrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len);
/**
\brief AES ecb encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_ecb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size);
/**
\brief AES ecb decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size);
/**
\brief AES cbc encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cbc decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cbc_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb1 encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cfb1_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb1 decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cfb1_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb8 encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cfb8_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb8 decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\return Error code \ref Csi_error_t
*/
csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
/**
\brief AES cfb128 decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
/**
\brief AES cfb128 encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
/**
\brief AES ofb encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
/**
\brief AES ofb decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
/**
\brief AES ctr encrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv Init vector
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
void *in,
void *out,
uint32_t size,
uint8_t nonce_counter[16],
uint8_t stream_block[16],
void *iv,
uint32_t *num);
/**
\brief AES ctr decrypt
\param[in] aes Handle to operate
\param[in] in Pointer to the source data
\param[out] out Pointer to the result data
\param[in] size The source data size
\param[in] nonce_counter Pointer to the 128-bit nonce and counter
\param[in] stream_block Pointer to the saved stream-block for resuming
\param[in] iv Init vecotr
\param[out] num The number of the 128-bit block we have used
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,
void *in,
void *out,
uint32_t size,
uint8_t nonce_counter[16],
uint8_t stream_block[16],
void *iv,
uint32_t *num);
/**
\brief Enable AES power manage
\param[in] aes Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_aes_enable_pm(csi_aes_t *aes);
/**
\brief Disable AES power manage
\param[in] aes Handle to operate
\return None
*/
void csi_aes_disable_pm(csi_aes_t *aes);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_AES_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/aes.h | C | apache-2.0 | 9,379 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/baud_calc.h
* @brief Header File for the PWM capture uart bandrate Driver
* @version V1.0
* @date 9. Oct 2020
* @model baud_calc
******************************************************************************/
#ifndef _DRV_BAUD_CALC_H_
#define _DRV_BAUD_CALC_H_
#include <stdint.h>
#include <drv/common.h>
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Baud rate calculation(Algorithm level)
\param[in] idx PWM idx
\param[in] channel Channel num
\return Error code(-1) or Baudare value
*/
int drv_calc_baud_adjust(uint32_t idx, uint32_t channel);
/**
\brief Baud rate calculation(Capture level)
\param[in] idx PWM idx
\param[in] channel Channel num
\return Error code(-1) or Baudare value
*/
int drv_calc_baud_original(uint32_t idx, uint32_t channel);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_BAUD_CALC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/baud_calc.h | C | apache-2.0 | 1,091 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/clk.h
* @brief Header File for CLK Driver.
* @version V1.0
* @date 18. Mar 2020
******************************************************************************/
#ifndef _DRV_CLK_H_
#define _DRV_CLK_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t module;
uint16_t dev_tag;
uint8_t idx;
} csi_clkmap_t;
void csi_clk_enable(csi_dev_t *dev);
void csi_clk_disable(csi_dev_t *dev);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_CLK_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/clk.h | C | apache-2.0 | 687 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/codec.h
* @brief head file for codec
* @version V1.0
* @date 17. Mar 2020
* @model codec
******************************************************************************/
#ifndef _DRV_CODEC_H_
#define _DRV_CODEC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/dma.h>
#include "drv/ringbuffer.h"
typedef enum {
CODEC_EVENT_PERIOD_READ_COMPLETE = 0U, ///< A peroid data read completed
CODEC_EVENT_PERIOD_WRITE_COMPLETE = 1U, ///< A peroid data write completed
CODEC_EVENT_WRITE_BUFFER_EMPTY = 2U, ///< Fifo is empty
CODEC_EVENT_READ_BUFFER_FULL = 3U, ///< Fifo is full
CODEC_EVENT_ERROR_OVERFLOW = 4U, ///< Fifo overflow error
CODEC_EVENT_ERROR_UNDERFLOW = 5U, ///< Fifo underflow error
CODEC_EVENT_ERROR = 6U, ///< The device has a hardware error
} csi_codec_event_t;
struct csi_codec;
typedef struct csi_codec csi_codec_t;
typedef struct csi_codec_output csi_codec_output_t;
struct csi_codec_output {
csi_codec_t *codec;
uint32_t ch_idx; ///< Codec output channel idx
void (*callback)(csi_codec_output_t *output, csi_codec_event_t event, void *arg);
void *arg;
ringbuffer_t *ring_buf; ///< The ringbuffer used to save audio data
uint32_t period; ///< When the period data is sent, the callback function will be called
uint32_t sound_channel_num; ///< Number of sound channel
csi_dma_ch_t *dma; ///< Dma channel handle
csi_state_t state; ///< Codec output channel current state
void *priv;
struct csi_codec_output *next;
};
typedef struct csi_codec_input csi_codec_input_t;
struct csi_codec_input {
csi_codec_t *codec;
uint32_t ch_idx; ///< Codec input channel idx
void (*callback)(csi_codec_input_t *input, csi_codec_event_t event, void *arg);
void *arg;
ringbuffer_t *ring_buf; ///< The ringbuffer used to save audio data
uint32_t period; ///< When the period data is received, the callback function will be called
uint32_t sound_channel_num; ///< Number of sound channel
csi_dma_ch_t *dma; ///< Codec input channel current state
csi_state_t state; ///< Dma channel handle
void *priv;
struct csi_codec_input *next;
};
struct csi_codec {
csi_dev_t dev; ///< Codec hw-device info
csi_codec_output_t *output_chs; ///< Codec output channel operate handle
csi_codec_input_t *input_chs; ///< Codec input channel operate handle
void *priv; ///< User private param passed to user callback
};
typedef enum {
CODEC_OUTPUT_SINGLE_ENDED, ///< Single-ended output
CODEC_OUTPUT_DIFFERENCE, ///< Differential output
} csi_codec_output_mode_t;
typedef enum {
CODEC_INPUT_SINGLE_ENDED, ///< Single-ended input
CODEC_INPUT_DIFFERENCE, ///< Differential input
} csi_codec_input_mode_t;
typedef struct {
uint32_t sample_rate; ///< Input data sample rate
uint32_t bit_width; ///< Input data sample width
csi_codec_input_mode_t mode; ///< Input work mode
uint8_t *buffer; ///< The buffer used to save audio data
uint32_t buffer_size; ///< Input buffer size
uint32_t period; ///< When a peroid data is reached,the callback function is called
uint32_t sound_channel_num; ///< Number of soundtrack per channel
} csi_codec_input_config_t;
typedef struct {
uint32_t sample_rate; ///< Output data sample rate
uint32_t bit_width; ///< Onput data sample width
csi_codec_output_mode_t mode; ///< Onput work mode
uint8_t *buffer; ///< The buffer used to save audio data
uint32_t buffer_size; ///< Output buffer size
uint32_t period; ///< When a peroid data is reached,the callback function is called
uint32_t sound_channel_num; ///< Number of soundchannel per channel
} csi_codec_output_config_t;
/**
\brief Init the codec according to the specified
\param[in] codec Codec handle to operate
\param[in] idx Codec interface idx
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_init(csi_codec_t *codec, uint32_t idx);
/**
\brief Codec uninit
\param[in] codec Codec handle to operate
\return None
*/
void csi_codec_uninit(csi_codec_t *codec);
/**
\brief Open a codec output channel
\param[in] codec Codec handle to operate
\param[in] ch Codec output channel handle
\param[in] ch_idx Codec output channel idx
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_open(csi_codec_t *codec, csi_codec_output_t *ch, uint32_t ch_idx);
/**
\brief Config codec output channel
\param[in] ch Codec output channel handle
\param[in] config Codec channel param. \ref csi_codec_output_config_t
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_config(csi_codec_output_t *ch, csi_codec_output_config_t *config);
/**
\brief Attach the callback handler to codec output
\param[in] ch Codec output channel handle
\param[in] cb Callback function
\param[in] arg User private param
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_attach_callback(csi_codec_output_t *ch, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] ch Codec output channel handle
\return None
*/
void csi_codec_output_detach_callback(csi_codec_output_t *ch);
/**
\brief Close a codec output channel
\param[in] ch Codec output channel handle
\return error code \ref csi_error_t
*/
void csi_codec_output_close(csi_codec_output_t *ch);
/**
\brief Link DMA channel to codec output channel
\param[in] ch Codec output channel handle
\param[in] dma The codec output DMA channel handle, when it is NULL means to unlink the channel
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_link_dma(csi_codec_output_t *ch, csi_dma_ch_t *dma);
/**
\brief Send an amount of data to buffer in blocking mode
\param[in] ch The codec output channel
\param[in] data Pointer to send data buffer
\param[in] size Send data size
\return the num of data witch is send successful
*/
uint32_t csi_codec_output_write(csi_codec_output_t *ch, const void *data, uint32_t size);
/**
\brief Send data to the buffer with asynchronous sending
The data is first written to the buffer and then output through the codec interface
This function does not block, and the return value is the number
Of data that was successfully written to the buffer
\param[in] ch The codec output channel
\param[in] data Pointer to send data buffer
\param[in] size Send data size
\return The data size that send to buffer
*/
uint32_t csi_codec_output_write_async(csi_codec_output_t *ch, const void *data, uint32_t size);
/**
\brief Start sending data from the buffer
\param[in] ch Codec output channel handle
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_start(csi_codec_output_t *ch);
/**
\brief Stop sending data from the buffer
\param[in] ch Codec output channel handle
\return None
*/
void csi_codec_output_stop(csi_codec_output_t *ch);
/**
\brief Pause sending data from the buffer
\param[in] ch Codec output channel handle
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_pause(csi_codec_output_t *ch);
/**
\brief Resume sending data from the buffer
\param[in] ch Codec output channel handle
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_resume(csi_codec_output_t *ch);
/**
\brief Get output-buffer free space
\param[in] ch Codec output channel handle
\return Buffer free space (bytes)
*/
uint32_t csi_codec_output_buffer_avail(csi_codec_output_t *ch);
/**
\brief Get used space of output-buffer
\param[in] ch Codec output channel handle
\return Buffer free space (bytes)
*/
uint32_t csi_codec_output_buffer_remain(csi_codec_output_t *ch);
/**
\brief Reset the buf, discard all data in the buffer
\param[in] ch Codec output channel handle
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_buffer_reset(csi_codec_output_t *ch);
/**
\brief Mute codec ouput channel
\param[in] ch Codec output channel handle
\param[in] en True enable codec mute. false disable codec mute
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_mute(csi_codec_output_t *ch, bool enable);
/**
\brief Set codec ouput channel digital gain
\param[in] ch Codec output channel handle
\param[in] val Gain val
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_digital_gain(csi_codec_output_t *ch, uint32_t val);
/**
\brief Set codec ouput channel analog gain
\param[in] ch Codec output channel handle
\param[in] val Gain val
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_analog_gain(csi_codec_output_t *ch, uint32_t val);
/**
\brief Set codec ouput channel mix gain
\param[in] ch Codec output channel handle
\param[in] val Gain val
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_output_mix_gain(csi_codec_output_t *ch, uint32_t val);
/**
\brief Get codec output channel state
\param[in] ch Codec output channel handle
\param[out] state Channel state. \ref csi_state_t
\return channel state
*/
csi_error_t csi_codec_output_get_state(csi_codec_output_t *ch, csi_state_t *state);
/**
\brief Open a codec input channel
\param[in] codec Codec handle to operate
\param[in] ch Codec input channel handle
\param[in] ch_idx Codec input channel idx
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_open(csi_codec_t *codec, csi_codec_input_t *ch, uint32_t ch_idx);
/**
\brief Config codec input channel
\param[in] ch Codec input channel handle
\param[in] config Codec channel prarm. \ref csi_codec_input_config_t
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_config(csi_codec_input_t *ch, csi_codec_input_config_t *config);
/**
\brief Attach the callback handler to codec output
\param[in] ch Codec input channel handle
\param[in] cb Callback function
\param[in] arg User private param for event callback
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_attach_callback(csi_codec_input_t *ch, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] ch Codec input channel handle
\return None
*/
void csi_codec_input_detach_callback(csi_codec_input_t *ch);
/**
\brief Close a codec input channel
\param[in] ch Codec input channel handle
\return None
*/
void csi_codec_input_close(csi_codec_input_t *ch);
/**
\brief Link DMA channel to codec input channel
\param[in] ch Codec input channel handle
\param[in] dma The codec input DMA channel handle, when it is NULL means to unlink the channel
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_link_dma(csi_codec_input_t *ch, csi_dma_ch_t *dma);
/**
\brief Read an amount of data in blocking mode
\param[in] ch Codec input channel handle
\param[in] data Pointer to receive data buffer
\param[in] size Receive data size
\return The size of data read successfully
*/
uint32_t csi_codec_input_read(csi_codec_input_t *ch, void *data, uint32_t size);
/**
\brief Read data from the buffer
using asynchronous receive
this function read data from the buffer, returns the number of successful receive
and returns 0 if there is no data in the buffer
\param[in] ch Codec input channel handle
\param[in] data Pointer to receive data buffer
\param[in] size Receive data size
\return The size of data read successfully
*/
uint32_t csi_codec_input_read_async(csi_codec_input_t *ch, void *data, uint32_t size);
/**
\brief Start receive data to the buffer
\param[in] ch Codec input channel handle
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_start(csi_codec_input_t *ch);
/**
\brief Stop receive data
\param[in] ch Codec input channel handle
\return None
*/
void csi_codec_input_stop(csi_codec_input_t *ch);
/**
\brief Reset the buf, discard all data in the buffer
\param[in] ch Codec input channel handle
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_buffer_reset(csi_codec_input_t *ch);
/**
\brief Get input-buffer free space
\param[in] ch Codec input channel handle
\return Buffer free space (bytes)
*/
uint32_t csi_codec_input_buffer_avail(csi_codec_input_t *ch);
/**
\brief Get used space of input-buffer
\param[in] ch Codec input channel handle
\return Buffer free space (bytes)
*/
uint32_t csi_codec_input_buffer_remain(csi_codec_input_t *ch);
/**
\brief Mute codec input channel
\param[in] ch Codec input channel handle
\param[in] en True enable codec mute. false disable codec mute
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_mute(csi_codec_input_t *ch, bool en);
/**
\brief Set codec input channel digital gain
\param[in] ch Codec input channel handle
\param[in] val Gain val
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_digital_gain(csi_codec_input_t *ch, uint32_t val);
/**
\brief Set codec input channel analog gain
\param[in] ch Codec input channel handle
\param[in] val Gain val
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_analog_gain(csi_codec_input_t *ch, uint32_t val);
/**
\brief Set codec input channel mix gain
\param[in] ch Codec input channel handle
\param[in] val Gain val
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_input_mix_gain(csi_codec_input_t *ch, uint32_t val);
/**
\brief Get codec input channel state
\param[in] ch Codec input channel handle
\param[out] state Channel state
\return Channel state
*/
csi_error_t csi_codec_input_get_state(csi_codec_input_t *ch, csi_state_t *state);
/**
\brief Enable codec power manage
\param[in] codec Codec handle to operate
\return error code \ref csi_error_t
*/
csi_error_t csi_codec_enable_pm(csi_codec_t *codec);
/**
\brief Disable codec power manage
\param[in] codec Codec handle to operate
\return None
*/
void csi_codec_disable_pm(csi_codec_t *codec);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_CODEC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/codec.h | C | apache-2.0 | 16,036 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/common.h
* @brief Header File for Common Driver
* @version V1.0
* @date 31. March 2020
* @model common
******************************************************************************/
#ifndef _DRV_COMMON_H_
#define _DRV_COMMON_H_
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <drv/list.h>
#include <drv/dev_tag.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef CONFIG_DEBUG_MODE
#define CSI_ASSERT(expr) \
do { \
if ((long)expr == (long)NULL) { \
printf("PROGRAM ASSERT\n"); \
while(1); \
} \
} while(0);
#else
#define CSI_ASSERT(expr) ((void)0U)
#endif
#ifdef CONFIG_PARAM_NOT_CHECK
#define CSI_PARAM_CHK(para, err) \
do { \
if ((int32_t)para == (int32_t)NULL) { \
return (err); \
} \
} while (0)
#define CSI_PARAM_CHK_NORETVAL(para) \
do { \
if ((int32_t)para == (int32_t)NULL) { \
return; \
} \
} while (0)
#else
#define CSI_PARAM_CHK(para, err)
#define CSI_PARAM_CHK_NORETVAL(para)
#endif
typedef enum {
CSI_OK = 0,
CSI_ERROR = -1,
CSI_BUSY = -2,
CSI_TIMEOUT = -3,
CSI_UNSUPPORTED = -4
} csi_error_t;
typedef struct {
uint8_t readable;
uint8_t writeable;
uint8_t error;
} csi_state_t;
typedef struct csi_dev csi_dev_t;
#ifdef CONFIG_PM
typedef enum {
PM_DEV_SUSPEND,
PM_DEV_RESUME,
} csi_pm_dev_action_t;
typedef enum {
PM_MODE_RUN = 0, ///< Running mode
PM_MODE_SLEEP_1, ///< Sleep LV1 mode
PM_MODE_SLEEP_2, ///< Sleep LV2 mode
PM_MODE_DEEP_SLEEP_1, ///< Deep sleep LV1 mode
PM_MODE_DEEP_SLEEP_2, ///< Deep sleep LV2 mode
} csi_pm_mode_t;
typedef struct {
slist_t next;
csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action);
uint32_t *reten_mem;
uint32_t size;
} csi_pm_dev_t;
#include <drv/pm.h>
#endif
struct csi_dev {
unsigned long reg_base;
uint8_t irq_num;
uint8_t idx;
uint16_t dev_tag;
void (*irq_handler)(void *);
#ifdef CONFIG_PM
csi_pm_dev_t pm_dev;
#endif
};
#define HANDLE_REG_BASE(handle) (handle->dev.reg_base)
#define HANDLE_IRQ_NUM(handle) (handle->dev.irq_num)
#define HANDLE_DEV_IDX(handle) (handle->dev.idx)
#define HANDLE_IRQ_HANDLER(handle) (handle->dev.irq_handler)
typedef struct {
unsigned long reg_base;
uint8_t irq_num;
uint8_t idx;
uint16_t dev_tag;
} csi_perip_info_t;
csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev);
csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info);
void mdelay(uint32_t ms);
void udelay(uint32_t us);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_COMMON_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/common.h | C | apache-2.0 | 3,536 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file crc.h
* @brief Header File for CRC Driver
* @version V1.0
* @date 02. June 2020
* @model crc
******************************************************************************/
#ifndef _DRV_CRC_H_
#define _DRV_CRC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Compute the CRC-7 checksum of a buffer.
*
* See JESD84-A441. Used by the MMC protocol. Uses 0x09 as the
* polynomial with no reflection. The CRC is left
* justified, so bit 7 of the result is bit 6 of the CRC.
* init = 0; poly = 0x09 refin = 0 refout = 0 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
*
* \return The computed CRC7 value
*/
uint8_t csi_crc7_be(uint8_t crc, uint8_t *data, uint32_t size);
/**
* \brief Compute the CRC-8 checksum of a buffer.
* init = 0 or 0xff; poly = 0x07 refin = 0 refout = 0 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC8 value
*/
uint8_t csi_crc8(uint8_t crc, uint8_t *data, size_t size);
/**
* \brief Compute the CRC-8 checksum of a buffer.
* init = 0; poly = 0x31 refin = 1 refout = 1 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC8 value
*/
uint8_t csi_crc8_maxim(uint8_t crc, uint8_t *data, size_t size);
/**
* \brief Compute the CRC-16 checksum of a buffer.
* init = 0 or 0xffff; poly = 0x8005 refin = 1 refout = 1 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC16 without xorout
*/
uint16_t csi_crc16(uint16_t crc, uint8_t *data, uint32_t size);
/**
* \brief Compute the CRC-16 checksum of a buffer.
* init = 0; poly = 0x1021 refin = 1 refout = 1 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC16 without xorout
*/
uint16_t csi_crc16_ccitt(uint16_t crc, uint8_t *data, uint32_t size);
/**
* \brief Compute the CRC-16 checksum of a buffer.
* init = 0; poly = 0x3d65 refin = 1 refout = 1 xorout = 0xffff
* \param[in] init_value Crc init value
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC16 with xorout
*/
uint16_t csi_crc16_dnp(uint16_t init_value, uint8_t *data, uint32_t size);
/**
* \brief Compute the CRC-16 checksum of a buffer.
* init = 0; poly = 0x1021 refin = 0 refout = 0 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC16 without xorout
*/
uint16_t csi_crc16_itu(uint16_t crc, uint8_t *data, uint32_t size);
/**
* \brief Compute the CRC-32 checksum of a buffer.Little-endian by bit.
* init = 0; poly = 0xEDB88320 refin = 0 refout = 0 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC32 without xorout
*/
uint32_t csi_crc32_le(uint32_t crc, uint8_t *data, uint32_t size);
/**
* \brief Compute the CRC-32 checksum of a buffer.Big-endian by bit.
* init = 0; poly = 0x04C11DB7 refin = 0 refout = 0 xorout = 0
* \param[in] crc Crc init value or crc immediate result
* \param[in] data Data buf to be calculate
* \param[in] size Data size
* \return The computed CRC32 without xorout
*/
uint32_t csi_crc32_be(uint32_t crc, uint8_t *data, uint32_t size);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_CRC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/crc.h | C | apache-2.0 | 4,131 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/dev_tag.h
* @brief Header File for DEV TAG Driver
* @version V1.0
* @date 31. March 2020
* @model common
******************************************************************************/
#ifndef _DRV_DEV_TAG_H_
#define _DRV_DEV_TAG_H_
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdbool.h>
#include <drv/list.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
DEV_BLANK_TAG = 0U,
DEV_DW_UART_TAG,
DEV_DW_DMA_TAG,
DEV_DW_GPIO_TAG,
DEV_DW_IIC_TAG,
DEV_DW_QSPI_TAG,
DEV_DW_SDMMC_TAG,
DEV_DW_SDHCI_TAG,
DEV_DW_SPI_TAG,
DEV_DW_TIMER_TAG,
DEV_DW_WDT_TAG,
DEV_WJ_ADC_TAG,
DEV_WJ_AES_TAG,
DEV_WJ_CODEC_TAG,
DEV_WJ_CRC_TAG,
DEV_WJ_DMA_TAG,
DEV_WJ_EFLASH_TAG,
DEV_WJ_EFUSE_TAG,
DEV_WJ_ETB_TAG,
DEV_WJ_FFT_TAG,
DEV_WJ_I2S_TAG,
DEV_WJ_MBOX_TAG,
DEV_WJ_PADREG_TAG,
DEV_WJ_PDM_TAG,
DEV_WJ_PINMUX_TAG,
DEV_WJ_PMU_TAG,
DEV_WJ_PWM_TAG,
DEV_WJ_RNG_TAG,
DEV_WJ_ROM_TAG,
DEV_WJ_RSA_TAG,
DEV_WJ_RTC_TAG,
DEV_WJ_SASC_TAG,
DEV_WJ_SHA_TAG,
DEV_WJ_SPDIF_TAG,
DEV_WJ_SPIDF_TAG,
DEV_WJ_TDM_TAG,
DEV_WJ_TIPC_TAG,
DEV_WJ_USB_TAG,
DEV_WJ_USI_TAG,
DEV_WJ_VAD_TAG,
DEV_CD_QSPI_TAG,
DEV_DCD_ISO7816_TAG,
DEV_OSR_RNG_TAG,
DEV_QX_RTC_TAG,
DEV_RCHBAND_CODEC_TAG,
DEV_CMSDK_UART_TAG,
} csi_dev_tag_t;
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TAG_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/dev_tag.h | C | apache-2.0 | 1,615 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file dma.h
* @brief header file for dma driver
* @version V1.0
* @date 08. Apr 2020
* @model dma
******************************************************************************/
#ifndef _DRV_DMA_H_
#define _DRV_DMA_H_
#include <stdint.h>
#include <stdio.h>
#include <drv/common.h>
#include <drv/list.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** DMA Event *****/
typedef enum {
DMA_EVENT_TRANSFER_DONE = 0, ///< transfer complete
DMA_EVENT_TRANSFER_HALF_DONE, ///< transfer half done
DMA_EVENT_TRANSFER_ERROR, ///< transfer error
} csi_dma_event_t;
typedef enum {
DMA_ADDR_INC = 0,
DMA_ADDR_DEC,
DMA_ADDR_CONSTANT
} csi_dma_addr_inc_t;
typedef enum {
DMA_DATA_WIDTH_8_BITS = 0,
DMA_DATA_WIDTH_16_BITS,
DMA_DATA_WIDTH_32_BITS,
DMA_DATA_WIDTH_64_BITS,
DMA_DATA_WIDTH_128_BITS,
DMA_DATA_WIDTH_512_BITS
} csi_dma_data_width_t;
typedef enum {
DMA_MEM2MEM = 0,
DMA_MEM2PERH,
DMA_PERH2MEM,
} csi_dma_trans_dir_t;
typedef struct {
int8_t ctrl_idx;
int8_t ch_idx;
} csi_dma_ch_desc_t;
typedef struct {
uint16_t dev_tag;
int8_t ctrl_idx;
const csi_dma_ch_desc_t *ch_list;
} csi_dma_ch_spt_list_t;
typedef struct {
csi_dma_addr_inc_t src_inc; ///< source address increment
csi_dma_addr_inc_t dst_inc; ///< destination address increment
csi_dma_data_width_t src_tw; ///< source transfer width in byte
csi_dma_data_width_t dst_tw; ///< destination transfer width in byte
csi_dma_trans_dir_t trans_dir; ///< transfer direction
uint16_t handshake; ///< handshake id
uint16_t group_len; ///< group transaction length (unit: bytes)
uint8_t src_reload_en; ///< 1:dma enable src addr auto reload, 0:disable
uint8_t dst_reload_en; ///< 1:dma enable dst addr auto reload, 0:disable
uint8_t half_int_en; ///< 1:dma enable half interrupt, 0: disable
uint8_t lli_src_en; ///< 1:dma enable llp, 0 disable
uint8_t lli_dst_en; ///< 1:dma enable llp, 0 disable
} csi_dma_ch_config_t;
#ifndef DMA_LLI_SIZE
#define DMA_LLI_SIZE 28
#endif
#define DEFINE_DESC_BUF(buf_name, num) uint8_t buf_name[num * DMA_LLI_SIZE]
typedef struct csi_dma_ch csi_dma_ch_t;
struct csi_dma_ch {
void *parent;
int8_t ctrl_id;
int8_t ch_id;
void (*callback)(csi_dma_ch_t *dma_ch, csi_dma_event_t event, void *arg);
void *arg;
uint32_t lli_num; //lli buffer len
uint32_t lli_count; //lli data count
int32_t lli_w_p; //write position
int32_t lli_r_p; //read position
void *lli; //lli buffer
uint32_t lli_loop_buf0; //lli loop data
uint32_t lli_loop_buf1; //lli loop data
uint8_t lli_loop[DMA_LLI_SIZE]; //lli loop handle
int16_t etb_ch_id;
slist_t next;
};
typedef struct {
csi_dev_t dev;
slist_t head;
uint32_t alloc_status;
uint32_t ch_num;
void *priv;
} csi_dma_t;
/**
\brief Init dma controller
\param[in] dma the dma controller operate handle
\param[in] ctrl_id the dma controller id
\return csi error code
*/
csi_error_t csi_dma_init(csi_dma_t *dma, int8_t ctrl_id);
/**
\brief Uninit dma controller
\param[in] dma the dma controller operate handle
\return none
*/
void csi_dma_uninit(csi_dma_t *dma);
/**
\brief Alloc a dma channel
\param[in] dma_ch the dma channel operate handle
\param[in] ch_id the channel id of dma; when set -1, means auto alloc
\param[in] ctrl_id the dma controller id; when set -1, means auto alloc
\return csi error code
*/
csi_error_t csi_dma_ch_alloc(csi_dma_ch_t *dma_ch, int8_t ch_id, int8_t ctrl_id);
/**
\brief Free a dma channel
\param[in] dma_ch the dma channel operate handle
\return none
*/
void csi_dma_ch_free(csi_dma_ch_t *dma_ch);
/**
\brief Config a dma channel
\param[in] dma_ch the dma channel operate handle
\param[in] config the config structure for dma channel
\return csi error code
*/
csi_error_t csi_dma_ch_config(csi_dma_ch_t *dma_ch, csi_dma_ch_config_t *config);
/**
\brief Start a dma channel
\param[in] dma_ch the dma channel operate handle
\param[in] psrcaddr transfer source address
\param[in] pdstaddr transfer destination address
\param[in] length transfer length (unit: bytes), if set data_width is 16, the length should be the multiple of 2, and
if set data_width is 32, the length should be the multiple of 4
\return none
*/
void csi_dma_ch_start(csi_dma_ch_t *dma_ch, void *srcaddr, void *dstaddr, uint32_t length);
/**
\brief Stop a dma channel
\param[in] dma_ch the dma channel operate handle
\return none
*/
void csi_dma_ch_stop(csi_dma_ch_t *dma_ch);
/**
\brief Attach the callback handler to DMA channel
\param[in] dma_ch operate handle.
\param[in] callback callback function
\param[in] arg user can define it by himself as callback's param
\return error code
*/
csi_error_t csi_dma_ch_attach_callback(csi_dma_ch_t *dma_ch, void *callback, void *arg);
/**
\brief detach the callback handler
\param[in] uart operate handle.
*/
void csi_dma_ch_detach_callback(csi_dma_ch_t *dma_ch);
/**
\brief enable dma power manage
\param[in] dma dma handle to operate.
\return error code
*/
csi_error_t csi_dma_enable_pm(csi_dma_t *dma);
/**
\brief disable dma power manage
\param[in] dma dma handle to operate.
*/
void csi_dma_disable_pm(csi_dma_t *dma);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_DMA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/dma.h | C | apache-2.0 | 6,401 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_fft.h
* @brief header file for gpio driver
* @version V1.0
* @date 11. Nov 2017
* @model fft
******************************************************************************/
#ifndef _CSI_FFT_H_
#define _CSI_FFT_H_
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
//#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
// 512-point FFT
CSKY_MCA_FFT_LEN_512 = 0x1,
// 256-point FFT
CSKY_MCA_FFT_LEN_256 = 0x2,
// 128-point FFT
CSKY_MCA_FFT_LEN_128 = 0x4,
// 64-point FFT
CSKY_MCA_FFT_LEN_64 = 0x8,
// 32-point FFT
CSKY_MCA_FFT_LEN_32 = 0x10,
// 16-point FFT
CSKY_MCA_FFT_LEN_16 = 0x20,
} csky_mca_fft_len_t;
/* 8-bit fixed-point numeric type in user-defined format */
typedef int8_t fxp8_t;
/* 16-bit fixed-point numeric type in user-defined format */
typedef int16_t fxp16_t;
/* 24-bit fixed-point numeric type in user-defined format */
typedef int32_t fxp24_t;
/* 32-bit fixed-point numeric type in user-defined format */
typedef int32_t fxp32_t;
/* 64-bit fixed-point numeric type in user-defined format */
typedef int64_t fxp64_t;
/* 8-bit fixed-point numeric type in 1.0.7 format */
typedef fxp8_t q7_t;
/* 16-bit fixed-point numeric type in 1.0.15 format */
typedef fxp16_t q15_t;
/* 32-bit fixed-point numeric type in 1.15.16 format */
typedef fxp32_t q16_t;
void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output);
void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_FFT_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/drv_fft.h | C | apache-2.0 | 2,111 |
/*
* @file eflash.h
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file eflash.h
* @brief header file for eflash driver
* @version V1.0
* @date 02. June 2017
* @model eflash
******************************************************************************/
#ifndef _DRV_EFLASH_H_
#define _DRV_EFLASH_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Flash information
*/
typedef struct {
uint32_t flash_size; ///< Chip End address (start+size-1)
uint32_t sector_size; ///< Uniform sector size in bytes
uint32_t erased_value; ///< erased value
} csi_eflash_info_t;
/**
\brief Flash Status
*/
typedef struct {
uint32_t busy : 1; ///< Flash busy flag
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
} eflash_status_t;
/// definition for eflash handle.
typedef struct {
csi_dev_t dev;
void *arg;
csi_eflash_info_t eflashinfo;
uint16_t prog;
uint16_t erase;
void *priv;
} csi_eflash_t;
// Function documentation
/**
\brief Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function
\param[in] eflash eflash handle to operate.
\param[in] idx device id
\param[in] arg User can define it by himself as callback's param
\return error code
*/
csi_error_t csi_eflash_init(csi_eflash_t *eflash, int32_t idx, void *arg);
/**
\brief De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface
\param[in] eflash eflash handle to operate.
\return error code
*/
csi_error_t csi_eflash_uninit(csi_eflash_t *eflash);
/**
\brief Read data from Flash.
\param[in] eflash eflash handle to operate.
\param[in] offset Data address.
\param[out] data Pointer to a buffer storing the data read from Flash.
\param[in] size Number of data items to read.
\return error code
*/
csi_error_t csi_eflash_read(csi_eflash_t *eflash, uint32_t offset, void *data, uint32_t size);
/**
\brief Program data to Flash.
\param[in] eflash eflash handle to operate.
\param[in] offset Data address.
\param[in] data Pointer to a buffer containing the data to be programmed to Flash.
\param[in] size Number of data items to program.
\return error code
*/
csi_error_t csi_eflash_program(csi_eflash_t *eflash, uint32_t offset, const void *data, uint32_t size);
/**
\brief Erase Flash Sector.
\param[in] eflash eflash handle to operate.
\param[in] offset flash address, flash address need sector size aligned
\param[in] size erase size
\return error code
*/
csi_error_t csi_eflash_erase(csi_eflash_t *eflash, uint32_t offset,uint32_t size);
/**
\brief Erase whole flash
\param[in] eflash eflash handle to operate.
\return error code
*/
csi_error_t csi_eflash_erase_chip(csi_eflash_t *eflash);
/**
\brief Get Flash information.
\param[in] eflash eflash handle to operate.
*/
void csi_eflash_dev_info(csi_eflash_t *eflash,csi_eflash_info_t *eflash_info);
/**
\brief enable eflash power manage
\param[in] eflash eflash handle to operate.
\return error code
*/
csi_error_t csi_eflash_enable_pm(csi_eflash_t *eflash);
/**
\brief disable eflash power manage
\param[in] eflash eflash handle to operate.
*/
void csi_eflash_disable_pm(csi_eflash_t *eflash);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_EFLASH_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/eflash.h | C | apache-2.0 | 3,839 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/efuse.h
* @brief Header File for EFUSE Driver
* @version V1.0
* @date 22. Mar 2020
* @model efuse
******************************************************************************/
#ifndef _DEV_EFUSEC_H_
#define _DEV_EFUSEC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t start; ///< Efuse start address
uint32_t end; ///< Efuse end address
} csi_efuse_info_t;
typedef struct {
csi_dev_t dev;
csi_efuse_info_t info;
} csi_efuse_t;
/**
\brief Initialize EFUSEC Interface. 1. Initializes the resources needed for the EFUSEC interface
\param[in] idx Device id
\return Error code
*/
csi_error_t drv_efuse_init(csi_efuse_t *efuse, int32_t idx);
/**
\brief De-initialize EFUSEC Interface. stops operation and releases the software resources used by the interface
\param[in] efuse Efuse efuse to operate.
\return None
*/
void drv_efuse_uninit(csi_efuse_t *efuse);
/**
\brief Read data from Efuse.
\param[in] efuse Efuse handle to operate.
\param[in] addr Data address.
\param[out] data Pointer to a buffer storing the data read from Efuse.
\param[in] size Number of data items to read.
\return Number of data items read or error code
*/
int32_t drv_efuse_read(csi_efuse_t *efuse, uint32_t addr, void *data, uint32_t size);
/**
\brief Program data to Efuse.
\param[in] efuse Efuse handle to operate.
\param[in] addr Data address.
\param[in] data Pointer to a buffer containing the data to be programmed to Efuse.
\param[in] cnt Number of data items to program.
\return number of data items programmed or error code
*/
int32_t drv_efuse_program(csi_efuse_t *efuse, uint32_t addr, const void *data, uint32_t size);
/**
\brief Get Efuse information.
\param[in] efuse Efuse handle to operate.
\param[out] info Efuse info \refs csi_efuse_info_t.
\return Error code
*/
csi_error_t drv_efuse_get_info(csi_efuse_t *efuse, csi_efuse_info_t *info);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_EFUSEC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/efuse.h | C | apache-2.0 | 2,349 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_etb.h
* @brief header file for event trigger driver
* @version V1.0
* @date 27. octorber 2017
* @model etb
******************************************************************************/
#ifndef _DRV_ETB_H_
#define _DRV_ETB_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ETB_HARDWARE_TRIG = 0, ///< etb channel inout is hardware trigger.
ETB_SOFTWARE_TRIG ///< etb channel inout is software trigger.
} csi_etb_trig_mode_t;
typedef enum {
ETB_CH_ONE_TRIGGER_ONE = 0, ///< one device trig one deivce
ETB_CH_ONE_TRIGGER_MORE, ///< one device trig two for more device
ETB_CH_MORE_TRIGGER_ONE ///< two or more device trig one deivce
} csi_etb_ch_type_t;
typedef struct {
uint8_t src_ip; ///< a specific number represent a location in an source trigger location map to trigger other ip(s).
uint8_t dst_ip; ///< a specific number represent an location in an dest trigger map to wait signal(s) from source ip(s) or location(s).
csi_etb_trig_mode_t trig_mode; ///< the input source is hardware trigger or software trigger.
csi_etb_ch_type_t ch_type; ///< channel type
} csi_etb_config_t;
/**
\brief Init the etb device
\return error code
*/
csi_error_t csi_etb_init(void);
/**
\brief Uninit the etb device
\return none
*/
void csi_etb_uninit(void);
/**
\brief alloc an etb channel
\param[in] ch_mode etb channel work mode
\return channel id or CSI_ERROR
*/
int32_t csi_etb_ch_alloc(csi_etb_ch_type_t ch_type);
/**
\brief free an etb channel
\param[in] ch_id etb channel work mode
\return none
*/
void csi_etb_ch_free(int32_t ch_id);
/**
\brief config etb channel
\param[in] ch_id etb channel id
\param[in] config the config structure for etb channel
\return csi error code
*/
csi_error_t csi_etb_ch_config(int32_t ch_id, csi_etb_config_t *config);
/**
\brief start an etb channel
\param[in] ch_id etb channel id
\return none
*/
void csi_etb_ch_start(int32_t ch_id);
/**
\brief stop an etb channel
\param[in] etb etb channel id
\return none
*/
void csi_etb_ch_stop(int32_t ch_id);
#endif /* _CSI_ETB_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/etb.h | C | apache-2.0 | 2,553 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/fft.h
* @brief Header File for FFT Driver
* @version V1.0
* @date 11. Nov 2020
* @model fft
******************************************************************************/
#ifndef _DRV_FFT_H_
#define _DRV_FFT_H_
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
///< 512-point FFT
CSKY_MCA_FFT_LEN_512 = 0x1,
///< 256-point FFT
CSKY_MCA_FFT_LEN_256 = 0x2,
///< 128-point FFT
CSKY_MCA_FFT_LEN_128 = 0x4,
///< 64-point FFT
CSKY_MCA_FFT_LEN_64 = 0x8,
///< 32-point FFT
CSKY_MCA_FFT_LEN_32 = 0x10,
///< 16-point FFT
CSKY_MCA_FFT_LEN_16 = 0x20,
} csky_mca_fft_len_t;
/* 8-bit fixed-point numeric type in user-defined format */
typedef int8_t fxp8_t;
/* 16-bit fixed-point numeric type in user-defined format */
typedef int16_t fxp16_t;
/* 24-bit fixed-point numeric type in user-defined format */
typedef int32_t fxp24_t;
/* 32-bit fixed-point numeric type in user-defined format */
typedef int32_t fxp32_t;
/* 64-bit fixed-point numeric type in user-defined format */
typedef int64_t fxp64_t;
/* 8-bit fixed-point numeric type in 1.0.7 format */
typedef fxp8_t q7_t;
/* 16-bit fixed-point numeric type in 1.0.15 format */
typedef fxp16_t q15_t;
/* 32-bit fixed-point numeric type in 1.15.16 format */
typedef fxp32_t q16_t;
void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output);
void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_FFT_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/fft.h | C | apache-2.0 | 2,094 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/gpio.h
* @brief Header File for GPIO Driver
* @version V1.0
* @date 8. Apr 2020
* @model gpio
******************************************************************************/
#ifndef _DRV_GPIO_H_
#define _DRV_GPIO_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \enum csi_gpio_dir_t
* \brief GPIO dir define
*/
typedef enum {
GPIO_DIRECTION_INPUT = 0, ///< GPIO as input
GPIO_DIRECTION_OUTPUT, ///< GPIO as output
} csi_gpio_dir_t;
/**
* \enum csi_gpio_pin_state_t
* \brief GPIO pin state define
*/
typedef enum {
GPIO_PIN_LOW = 0, ///< GPIO low level
GPIO_PIN_HIGH, ///< GPIO high level
} csi_gpio_pin_state_t;
/**
* \enum csi_gpio_mode_t
* \brief GPIO mode define
*/
typedef enum {
GPIO_MODE_PULLNONE = 0, ///< Pull none for input
GPIO_MODE_PULLUP, ///< Pull up for input
GPIO_MODE_PULLDOWN, ///< Pull down for input
GPIO_MODE_OPEN_DRAIN, ///< Open drain mode for output
GPIO_MODE_PUSH_PULL, ///< Push-pull mode for output
} csi_gpio_mode_t;
/**
* \enum csi_gpio_irq_mode_t
* \brief GPIO irq triger type
*/
typedef enum {
GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge
GPIO_IRQ_MODE_FALLING_EDGE, ///< Interrupt mode for falling edge
GPIO_IRQ_MODE_BOTH_EDGE, ///< Interrupt mode for both edge
GPIO_IRQ_MODE_LOW_LEVEL, ///< Interrupt mode for low level
GPIO_IRQ_MODE_HIGH_LEVEL, ///< Interrupt mode for high level
} csi_gpio_irq_mode_t;
/**
* \struct csi_gpio_t
* \brief GPIO control block
*/
typedef struct csi_gpio csi_gpio_t;
struct csi_gpio {
csi_dev_t dev; ///< Hw-dev info
void (*callback)(csi_gpio_t *gpio, uint32_t pins, void *arg); ///< Call-back of gpio port
void *arg; ///< User param passed to callback
void *priv; ///< User private param
};
/**
\brief Initialize GPIO Port handle
\param[in] gpio GPIO port handle
\param[in] port_idx GPIO port index
\return Error code
*/
csi_error_t csi_gpio_init(csi_gpio_t *gpio, uint32_t port_idx);
/**
\brief De-initialize GPIO pin.stops operation
releases the software resources used by the gpio-pin
\param[in] gpio GPIO port handle
\return None
*/
void csi_gpio_uninit(csi_gpio_t *gpio);
/**
\brief Config pin direction
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\param[in] dir \ref csi_gpio_dir_t
\return Error code
*/
csi_error_t csi_gpio_dir(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_dir_t dir);
/**
\brief Config pin mode
If one of pins config error, then the rest of pins will not config, and function return CSI_ERROR
If one or more pin unsupport, function will return CSI_UNSUPPORT, but the other pin still configured
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\param[in] mode \ref csi_gpio_mode_t
\return Error code
*/
csi_error_t csi_gpio_mode(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_mode_t mode);
/**
\brief Config gpio irq params
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\param[in] mode Interrupt trigger mode \ref csi_gpio_irq_mode_t
\return Error code
*/
csi_error_t csi_gpio_irq_mode(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_irq_mode_t mode);
/**
\brief Enable or disable gpio pin interrupt
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\param[in] enable 0:disable 1:enable
\return Error code
*/
csi_error_t csi_gpio_irq_enable(csi_gpio_t *gpio, uint32_t pin_mask, bool enable);
/**
\brief Set debonce of gpio when gpio configed as input
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\param[in] enbale 0: disable 1:enable
\return Error code
*/
csi_error_t csi_gpio_debonce(csi_gpio_t *gpio, uint32_t pin_mask, bool enable);
/**
\brief Set one or zero to the selected pin mask
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\param[in] value Value to be set \ref csi_gpio_pin_state_t
\return None
*/
void csi_gpio_write(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_pin_state_t value);
/**
\brief Toggle output gpio value,ex.if previous value is 1, then output 0
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\return None
*/
void csi_gpio_toggle(csi_gpio_t *gpio, uint32_t pin_mask);
/**
\brief Get the value of selected GPIO pin mask
\param[in] gpio GPIO port handle
\param[in] pin_mask Pin mask need to be set
\return According to the bit mask, the corresponding pin status is obtained
*/
uint32_t csi_gpio_read(csi_gpio_t *gpio, uint32_t pin_mask);
/**
\brief Attach the interrupt callback to the port
\param[in] gpio GPIO port handle
\param[in] callback Callback function
\param[in] arg User param passed to callback
\return Error code
*/
csi_error_t csi_gpio_attach_callback(csi_gpio_t *gpio, void *callback, void *arg);
/**
\brief Detach the interrupt callback to the port
\param[in] gpio GPIO port handle
\return None
*/
void csi_gpio_detach_callback(csi_gpio_t *gpio);
/**
\brief Enable gpio power manage
\param[in] gpio GPIO handle to operate
\return Error code
*/
csi_error_t csi_gpio_enable_pm(csi_gpio_t *gpio);
/**
\brief Disable gpio power manage
\param[in] gpio GPIO handle to operate
\return None
*/
void csi_gpio_disable_pm(csi_gpio_t *gpio);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_GPIO_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/gpio.h | C | apache-2.0 | 6,317 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/gpio_pin.h
* @brief Header File for GPIO PIN Driver
* @version v1.0
* @date 2020-06-28
* @note Only one of gpio or gpio_pin interface can be selected
******************************************************************************/
#ifndef _DRV_GPIO_PIN_H_
#define _DRV_GPIO_PIN_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/gpio.h>
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \struct csi_gpio_pin_t
* \brief GPIO PIN control block
*/
typedef struct csi_gpio_pin csi_gpio_pin_t;
struct csi_gpio_pin {
csi_gpio_t *gpio;
uint32_t pin_idx;
void (*callback)(csi_gpio_pin_t *pin, void *arg);
void *arg;
};
/**
\brief Initialize GPIO pin handle
\param[in] pin GPIO pin handle
\param[in] pin_name GPIO pin name
\return Error code
*/
csi_error_t csi_gpio_pin_init(csi_gpio_pin_t *pin, pin_name_t pin_name);
/**
\brief De-initialize GPIO pin
\param[in] pin GPIO pin handle
\return None
*/
void csi_gpio_pin_uninit(csi_gpio_pin_t *pin);
/**
\brief Attach the interrupt callback to the GPIO pin
\param[in] pin GPIO pin handle
\param[in] callback Callback function
\param[in] arg User param passed to callback
\return Error code
*/
csi_error_t csi_gpio_pin_attach_callback(csi_gpio_pin_t *pin, void *callback, void *arg);
/**
\brief Config pin direction
\param[in] pin GPIO pin handle
\param[in] dir \ref csi_gpio_dir_t
\return Error code
*/
csi_error_t csi_gpio_pin_dir(csi_gpio_pin_t *pin, csi_gpio_dir_t dir);
/**
\brief Config pin mode
\param[in] pin GPIO pin handle
\param[in] mode \ref csi_gpio_mode_t
\return Error code
*/
csi_error_t csi_gpio_pin_mode(csi_gpio_pin_t *pin, csi_gpio_mode_t mode);
/**
\brief Config pin irq params
\param[in] pin GPIO pin handle
\param[in] mode Interrupt trigger mode \ref csi_gpio_irq_mode_t
\return Error code
*/
csi_error_t csi_gpio_pin_irq_mode(csi_gpio_pin_t *pin, csi_gpio_irq_mode_t mode);
/**
\brief Enable or disable gpio pin interrupt
\param[in] pin GPIO pin handle
\param[in] enable 0:disable 1:enable
\return Error code
*/
csi_error_t csi_gpio_pin_irq_enable(csi_gpio_pin_t *pin, bool enable);
/**
\brief Set debonce of pin when pin configed as input
\param[in] pin GPIO pin handle
\param[in] enbale 0: disable 1:enable
\return Error code
*/
csi_error_t csi_gpio_pin_debonce(csi_gpio_pin_t *pin, bool enable);
/**
\brief Set one or zero to specified pin
\param[in] pin GPIO pin handle
\param[in] value Value to be set \ref csi_gpio_pin_state_t
\return None
*/
void csi_gpio_pin_write(csi_gpio_pin_t *pin, csi_gpio_pin_state_t value);
/**
\brief Toggle output pin value,ex.if previous value is 1, then output 0
\param[in] pin GPIO pin handle
\return None
*/
void csi_gpio_pin_toggle(csi_gpio_pin_t *pin);
/**
\brief Get the value of specified GPIO pin
\param[in] pin GPIO port handle
\return gpio pin state, \ref csi_gpio_pin_state_t
*/
csi_gpio_pin_state_t csi_gpio_pin_read(csi_gpio_pin_t *pin);
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_PIN_H_*/
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/gpio_pin.h | C | apache-2.0 | 3,567 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/i2s.h
* @brief header file for i2s driver
* @version V1.0
* @date 16. Mar 2020
* @model i2s
******************************************************************************/
#ifndef _DRV_I2S_H_
#define _DRV_I2S_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/dma.h>
#include "drv/ringbuffer.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
I2S_MODE_MASTER, ///< I2s transmitter master mode
I2S_MODE_SLAVE, ///< I2s transmitter slave mode
} csi_i2s_mode_t;
typedef enum {
I2S_PROTOCOL_I2S, ///< I2S protocol
I2S_PROTOCOL_MSB_JUSTIFIED, ///< MSB (left) justified protocol
I2S_PROTOCOL_LSB_JUSTIFIED, ///< LSB (right) justified protocol
I2S_PROTOCOL_PCM, ///< PCM protocol
} csi_i2s_protocol_t;
typedef enum {
I2S_LEFT_POLARITY_LOW, ///< Low level represents the left channel
I2S_LEFT_POLARITY_HIGH, ///< High level represents the left channel
} csi_i2s_ws_left_polarity_t;
typedef enum {
I2S_SAMPLE_RATE_8000 = 8000U, ///< I2S sample rate is 8000
I2S_SAMPLE_RATE_11025 = 11025U,
I2S_SAMPLE_RATE_12000 = 12000U,
I2S_SAMPLE_RATE_16000 = 16000U,
I2S_SAMPLE_RATE_22050 = 22050U,
I2S_SAMPLE_RATE_24000 = 24000U,
I2S_SAMPLE_RATE_32000 = 32000U,
I2S_SAMPLE_RATE_44100 = 44100U,
I2S_SAMPLE_RATE_48000 = 48000U,
I2S_SAMPLE_RATE_96000 = 96000U,
I2S_SAMPLE_RATE_192000 = 192000U,
I2S_SAMPLE_RATE_256000 = 256000U,
} csi_i2s_sample_rate_t;
typedef enum {
I2S_SAMPLE_WIDTH_16BIT = 16U, ///< I2S sample width is 16bit
I2S_SAMPLE_WIDTH_24BIT = 24U,
I2S_SAMPLE_WIDTH_32BIT = 32U,
} csi_i2s_sample_width_t;
typedef enum {
I2S_SCLK_16FS = 16U, ///< SCLK frequency is 16 times that of I2S sample rate
I2S_SCLK_32FS = 32U,
I2S_SCLK_48FS = 48U,
I2S_SCLK_64FS = 64U,
} csi_i2s_sclk_freq_t;
typedef enum {
I2S_MCLK_256FS = 256U, ///< MCLK frequency is 256 times that of I2S sample rate
I2S_MCLK_384FS = 384U,
} csi_i2s_mclk_freq_t;
typedef struct {
csi_i2s_mode_t mode; ///< I2S work mode
csi_i2s_protocol_t protocol; ///< Protocols used by I2S
csi_i2s_ws_left_polarity_t polarity; ///< left channel polarity
csi_i2s_sample_rate_t rate; ///< I2S sample rate
csi_i2s_sample_width_t width; ///< I2S sample width
csi_i2s_sclk_freq_t sclk_nfs; ///< SCLK frequency is N times that of I2S sample rate
csi_i2s_mclk_freq_t mclk_nfs; ///< MCLK frequency is N times that of I2S sample rate
} csi_i2s_format_t;
typedef enum {
I2S_LEFT_CHANNEL,
I2S_RIGHT_CHANNEL,
I2S_LEFT_RIGHT_CHANNEL,
} csi_i2s_sound_channel_t;
typedef enum {
I2S_EVENT_SEND_COMPLETE,
I2S_EVENT_RECEIVE_COMPLETE,
I2S_EVENT_TX_BUFFER_EMPTY,
I2S_EVENT_RX_BUFFER_FULL,
I2S_EVENT_ERROR_OVERFLOW,
I2S_EVENT_ERROR_UNDERFLOW,
I2S_EVENT_ERROR,
} csi_i2s_event_t;
typedef struct csi_i2s csi_i2s_t;
struct csi_i2s {
csi_dev_t dev; ///< I2S hw-device info
void (*callback)(csi_i2s_t *i2s, csi_i2s_event_t event, void *arg); ///< I2S event callback for user
void *arg; ///< user private param passed to user callback
ringbuffer_t *tx_buf; ///< I2S send buffer
ringbuffer_t *rx_buf; ///< I2S receive buffer
csi_dma_ch_t *tx_dma; ///< send dma channel handle
csi_dma_ch_t *rx_dma; ///< receive dma channel handle
uint32_t tx_period; ///< I2S send period num data will callback
uint32_t rx_period; ///< I2S receive period num data will callback
csi_state_t state; ///< I2S communication state
void *priv;
};
/**
\brief Init i2s
\param[in] i2s I2s handle to operate
\param[in] idx I2s interface idx
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_init(csi_i2s_t *i2s, uint32_t idx);
/**
\brief Uninit i2s
\param[in] i2s I2s handle to operate
\return none
*/
void csi_i2s_uninit(csi_i2s_t *i2s);
/**
\brief Enable i2s
\param[in] i2s I2s handle to operate
\param[in] en True enable, False disable
\return None
*/
void csi_i2s_enable(csi_i2s_t *i2s, bool enable);
/**
\brief I2s config format
\param[in] i2s I2s handle to operate
\param[in] format I2s config param \ref csi_i2s_format_t
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_format(csi_i2s_t *i2s, csi_i2s_format_t *format);
/**
\brief Set the i2s tx mono
\param[in] i2s I2s handle to operate
\param[in] ch Mono channel selection
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_tx_select_sound_channel(csi_i2s_t *i2s, csi_i2s_sound_channel_t ch);
/**
\brief Set the i2s rx mono
\param[in] i2s I2s handle to operate
\param[in] ch Mono channel selection
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_rx_select_sound_channel(csi_i2s_t *i2s, csi_i2s_sound_channel_t ch);
/**
\brief Link DMA channel to i2s device
\param[in] i2s I2s handle to operate
\param[in] rx_dma The DMA channel for receive, when it is NULL means to unused dma
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_rx_link_dma(csi_i2s_t *i2s, csi_dma_ch_t *rx_dma);
/**
\brief Link DMA channel to i2s device
\param[in] i2s I2s handle to operate
\param[in] tx_dma The DMA channel for send, when it is NULL means to unused dma
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_tx_link_dma(csi_i2s_t *i2s, csi_dma_ch_t *tx_dma);
/**
\brief I2s rx buffer config
\param[in] i2s I2s handle to operate
\param[in] buffer I2s rx buffer
\return None
*/
void csi_i2s_rx_set_buffer(csi_i2s_t *i2s, ringbuffer_t *buffer);
/**
\brief I2s tx buffer config
\param[in] i2s I2s handle to operate
\param[in] buffer I2s tx buffer
\return None
*/
void csi_i2s_tx_set_buffer(csi_i2s_t *i2s, ringbuffer_t *buffer);
/**
\brief I2s rx set period.The value of period is to report a receive completion event
after each period value data is received
\param[in] i2s I2s handle to operate
\param[in] period I2s rx period
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_rx_set_period(csi_i2s_t *i2s, uint32_t period);
/**
\brief I2s tx set period.The value of period is to report a receive completion event
after each period value data is send
\param[in] i2s I2s handle to operate
\param[in] period I2s tx period
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_tx_set_period(csi_i2s_t *i2s, uint32_t period);
/**
\brief Get rx ringbuffer buffer free space
\param[in] i2s I2s handle to operate
\return Buffer free space (bytes)
*/
uint32_t csi_i2s_rx_buffer_avail(csi_i2s_t *i2s);
/**
\brief Get rx ringbuffer buffer used space
\param[in] i2s I2s handle to operate
\return Buffer used space (bytes)
*/
uint32_t csi_i2s_rx_buffer_remain(csi_i2s_t *i2s);
/**
\brief Reset the rx ringbuffer, discard all data in the buffer
\param[in] i2s I2s handle to operate
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_rx_buffer_reset(csi_i2s_t *i2s);
/**
\brief Get tx ringbuffer buffer free space
\param[in] i2s I2s handle to operate
\return Buffer free space (bytes)
*/
uint32_t csi_i2s_tx_buffer_avail(csi_i2s_t *i2s);
/**
\brief Get tx ringbuffer buffer used space
\param[in] i2s I2s handle to operate
\return Buffer used space (bytes)
*/
uint32_t csi_i2s_tx_buffer_remain(csi_i2s_t *i2s);
/**
\brief Reset the tx ringbuffer, discard all data in the buffer
\param[in] i2s Handle to operate
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_tx_buffer_reset(csi_i2s_t *i2s);
/**
\brief Send an amount of data to buffer in blocking mode
\param[in] i2s Operate handle
\param[in] data Pointer to send data buffer
\param[in] size Send data size
\return The num of data witch is send successful
*/
int32_t csi_i2s_send(csi_i2s_t *i2s, const void *data, uint32_t size);
/**
\brief Receive an amount of data to buffer in blocking mode
\param[in] i2s Operate handle
\param[out] data Pointer to receive data buffer
\param[in] size Receive data size
\return The size of data receive successfully
*/
int32_t csi_i2s_receive(csi_i2s_t *i2s, const void *data, uint32_t size);
/**
\brief Write data to the buffer
With asynchronous sending
The data is first written to the buffer and then output through the i2s interface
Return value is the number of data that was successfully written to the buffer
\param[in] i2s Operate handle
\param[in] data Pointer to send data buffer
\param[in] size Send data size
\return The data size that write to buffer
*/
uint32_t csi_i2s_send_async(csi_i2s_t *i2s, const void *data, uint32_t size);
/**
\brief Read data from the buffer
Using asynchronous receive, i2s writes the received data to the buffer
This function reads data from the buffer, returns the number of successful reads
Returns 0 if there is no data in the buffer
\param[in] i2s Operate handle
\param[out] data Pointer to receive data buffer
\param[in] size Receive data size
\return The size of data read successfully
*/
uint32_t csi_i2s_receive_async(csi_i2s_t *i2s, const void *data, uint32_t size);
/**
\brief Start i2s pause asynchronous send
\param[in] i2s Operate handle
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_send_pause(csi_i2s_t *i2s);
/**
\brief Start i2s resume asynchronous send
\param[in] i2s Operate handle
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_send_resume(csi_i2s_t *i2s);
/**
\brief Start i2s asynchronous send
\param[in] i2s Operate handle
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_send_start(csi_i2s_t *i2s);
/**
\brief Start i2s asynchronous receive
\param[in] i2s Operate handle
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_receive_start(csi_i2s_t *i2s);
/**
\brief Stop i2s asynchronous send
\param[in] i2s Operate handle
\return None
*/
void csi_i2s_send_stop(csi_i2s_t *i2s);
/**
\brief Stop i2s asynchronous receive
\param[in] i2s Operate handle
\return None
*/
void csi_i2s_receive_stop(csi_i2s_t *i2s);
/**
\brief Attach the callback handler to i2s
\param[in] i2s Operate handle
\param[in] cb Callback function
\param[in] arg User private param
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_attach_callback(csi_i2s_t *i2s, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] i2s Operate handle
\return None
*/
void csi_i2s_detach_callback(csi_i2s_t *i2s);
/**
\brief Get i2s status
\param[in] i2s I2s handle to operate
\param[out] state I2s state
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_get_state(csi_i2s_t *i2s, csi_state_t *state);
/**
\brief Enable i2s power manage
\param[in] i2s I2s handle to operate
\return error code \ref csi_error_t
*/
csi_error_t csi_i2s_enable_pm(csi_i2s_t *i2s);
/**
\brief Disable i2s power manage
\param[in] i2s I2s handle to operate
\return None
*/
void csi_i2s_disable_pm(csi_i2s_t *i2s);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_I2S_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/i2s.h | C | apache-2.0 | 12,748 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file iic.h
* @brief header file for iic driver
* @version V1.0
* @date 08. Apr 2020
* @model iic
******************************************************************************/
#ifndef _DRV_IIC_H_
#define _DRV_IIC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\enum csi_iic_mode_t
\brief iic work in master/slave mode
*/
typedef enum {
IIC_MODE_MASTER = 0U, ///< IIC master
IIC_MODE_SLAVE ///< IIC slave
} csi_iic_mode_t;
/**
\enum csi_iic_speed_t
\brief iic speed mode
*/
typedef enum {
IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed (<=100kHz)
IIC_BUS_SPEED_FAST, ///< Fast Speed (<=400kHz)
IIC_BUS_SPEED_FAST_PLUS, ///< Fast plus Speed (<= 1MHz)
IIC_BUS_SPEED_HIGH ///< High Speed (<=3.4MHz)
} csi_iic_speed_t;
/**
\enum csi_iic_address_mode_t
\brief iic address mode
*/
typedef enum {
IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode
IIC_ADDRESS_10BIT ///< 10-bit address mode
} csi_iic_addr_mode_t;
/**
\enum csi_iic_mem_addr_size_t
\brief iic memory address size
*/
typedef enum {
IIC_MEM_ADDR_SIZE_8BIT = 0U, ///< IIC e2prom 8bit address mode
IIC_MEM_ADDR_SIZE_16BIT ///< IIC e2prom 16bit address mode
} csi_iic_mem_addr_size_t;
/**
\enum csi_iic_event_t
\brief iic event signaled by iic driver
*/
typedef enum {
IIC_EVENT_SEND_COMPLETE = 0U, ///< Master/slave Send finished
IIC_EVENT_RECEIVE_COMPLETE, ///< Master/slave Receive finished
IIC_EVENT_ERROR_OVERFLOW, ///< Master/slave fifo overflow error
IIC_EVENT_ERROR_UNDERFLOW, ///< Master/slave fifo underflow error
IIC_EVENT_ERROR ///< The receive buffer was completely filled to FIFO and more data arrived. That data is lost
} csi_iic_event_t;
/**
\struct csi_iic_t
\brief iic ctrl block
*/
typedef struct csi_iic csi_iic_t;
struct csi_iic {
csi_dev_t dev; ///< IIC hw-device info
void (*callback)(csi_iic_t *iic, csi_iic_event_t event, void *arg); ///< IIC event callback for user
void *arg; ///< User private param passed to user callback
uint8_t *data; ///< IIC transfer-data buffer
uint32_t size; ///< IIC transfer-data size
csi_iic_mode_t mode; ///< IIC mode
csi_dma_ch_t *tx_dma; ///< Send dma channel handle
csi_dma_ch_t *rx_dma; ///< Receive dma channel handle
void *send; ///< Send function pointer asynchronously
void *receive; ///< Receive function pointer asynchronously
csi_state_t state; ///< IIC current state
void *priv;
};
typedef void (*csi_iic_master_send_async_t)(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size);
typedef void (*csi_iic_master_receive_async_t)(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size);
typedef void (*csi_iic_slave_send_async_t)(csi_iic_t *iic, const void *data, uint32_t size);
typedef void (*csi_iic_slave_receive_async_t)(csi_iic_t *iic, void *data, uint32_t size);
/**
\brief Init iic ctrl block
Initializes the resources needed for the iic instance
\param[in] iic Handle of iic instance
\param[in] idx Index of instance
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_init(csi_iic_t *iic, uint32_t idx);
/**
\brief Uninit iic ctrl block
Stops operation and releases the software resources used by the instance
\param[in] iic Handle of iic instance
\return None
*/
void csi_iic_uninit(csi_iic_t *iic);
/**
\brief Config iic master or slave mode
\param[in] iic Handle of iic instance
\param[in] mode iic mode \ref csi_iic_mode_t
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode);
/**
\brief Config iic addr mode
\param[in] iic Handle of iic instance
\param[in] addr_mode iic addr mode \ref csi_iic_addr_mode_t
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode);
/**
\brief Config iic speed
\param[in] iic Handle of iic instance
\param[in] speed iic speed mode \ref csi_iic_speed_t
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed);
/**
\brief Config iic own addr
\param[in] iic Handle of iic instance
\param[in] own_addr iic set own addr at slave mode
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_own_addr(csi_iic_t *iic, uint32_t own_addr);
/**
\brief Start sending data as iic master
This function is blocking
\param[in] iic Handle of iic instance
\param[in] devaddr Addrress of slave device
\param[in] data Pointer to send data buffer
\param[in] size Size of data items to send
\param[in] timout Unit of time delay(ms)
\return The amount of real data sent or error code
*/
int32_t csi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data as iic master
This function is blocking
\param[in] iic Handle to operate
\param[in] devaddr iic addrress of slave device
\param[out] data Pointer to buffer for data to receive from iic receiver
\param[in] size Size of data items to receive
\param[in] timeout Unit of time delay(ms)
\return The amount of real data received or error code
*/
int32_t csi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data as iic master
This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens
\param[in] iic Handle to operate
\param[in] devaddr iic addrress of slave device
\param[in] data Pointer to send data buffer
\param[in] size Size of data items to send
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_master_send_async(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size);
/**
\brief Start receiving data as iic master.
This function is non-blocking.\ref csi_iic_event_t is signaled when transfer completes or error happens
\param[in] iic Handle to operate
\param[in] devaddr iic addrress of slave device
\param[out] data Pointer to buffer for data to receive from iic receiver
\param[in] size Size of data items to receive
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_master_receive_async(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size);
/**
\brief Start sending data as iic master
This function is blocking
\param[in] iic Handle of iic instance
\param[in] devaddr Addrress of slave device
\param[in] memaddr Internal addr of device
\param[in] memaddr_size Internal addr mode of device
\param[in] data Pointer to send data buffer
\param[in] size Size of data items to send
\param[in] timout Unit of time delay(ms)
\return The amount of real data sent or error code
*/
int32_t csi_iic_mem_send(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data as iic master
This function is blocking
\param[in] iic Handle to operate
\param[in] devaddr iic addrress of slave device
\param[in] memaddr Internal addr of device
\param[in] memaddr_mode Internal addr mode of device
\param[out] data Pointer to buffer for data to receive from eeprom device
\param[in] size Size of data items to receive
\param[in] timeout Unit of time delay(ms)
\return The amount of real data received or error code
*/
int32_t csi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data as iic slave
This function is blocking
\param[in] iic Handle to operate
\param[in] data Pointer to buffer with data to send to iic master
\param[in] size Size of data items to send
\param[in] timeout Unit of time delay(ms)
\return The amount of real data sent or error code
*/
int32_t csi_iic_slave_send(csi_iic_t *iic, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data as iic slave
This function is blocking
\param[in] iic Handle to operate
\param[out] data Pointer to buffer for data to receive from iic master
\param[in] size Size of data items to receive
\param[in] timeout Unit of time delay(ms)
\return The amount of real data received or error code
*/
int32_t csi_iic_slave_receive(csi_iic_t *iic, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data as iic slave
This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens
\param[in] iic Handle to operate
\param[in] data Pointer to buffer with data to send to iic master
\param[in] size Size of data items to send
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t size);
/**
\brief Start receiving data as iic slave
This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens
\param[in] handle iic handle to operate
\param[out] data Pointer to buffer for data to receive from iic master
\param[in] size Size of data items to receive
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t size);
/**
\brief Attach callback to the iic
\param[in] iic iic handle to operate
\param[in] cb Event callback function \ref csi_iic_callback_t
\param[in] arg User private param for event callback
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_attach_callback(csi_iic_t *iic, void *callback, void *arg);
/**
\brief Detach callback from the iic
\param[in] iic iic handle to operate
\return None
*/
void csi_iic_detach_callback(csi_iic_t *iic);
/**
\brief Config iic stop to generate
\param[in] iic iic handle to operate
\param[in] enable Transfer operation is pending - stop condition will not be generated
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_xfer_pending(csi_iic_t *iic, bool enable);
/**
\brief Link DMA channel to iic device
\param[in] iic Handle to operate
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_link_dma(csi_iic_t *iic, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get iic state
\param[in] iic Handle to operate
\param[out] state iic state \ref csi_state_t
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_get_state(csi_iic_t *iic, csi_state_t *state);
/**
\brief Enable iic power manage
\param[in] iic iic handle to operate
\return error code \ref csi_error_t
*/
csi_error_t csi_iic_enable_pm(csi_iic_t *iic);
/**
\brief Disable iic power manage
\param[in] iic iic handle to operate
\return None
*/
void csi_iic_disable_pm(csi_iic_t *iic);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_IIC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/iic.h | C | apache-2.0 | 12,818 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/intc.h
* @brief Header File for INTC Driver
* @version V1.0
* @date 02. June 2020
* @model intc
******************************************************************************/
#ifndef _DRV_INTC_H_
#define _DRV_INTC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum int_trigger_mode_t {
INT_MODE_LOW_LEVEL,
INT_MODE_HIGH_LEVEL,
INT_MODE_RISING_EDGE,
INT_MODE_FALLING_EDGE,
INT_MODE_DOUBLE_EDGE,
} int_trigger_mode_t;
/**
\brief Initialize the INTC interrupt controller
*/
void csi_intc_init(void);
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the INTC interrupt controller.
\param[in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_enable_irq(int32_t IRQn);
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the INTC interrupt controller.
\param[in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_disable_irq(int32_t IRQn);
/**
\brief Get Pending Interrupt
\details Reads the pending register in the INTC and returns the pending bit for the specified interrupt.
\param[in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
uint32_t csi_intc_get_pending_irq(int32_t IRQn);
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param[in] IRQn Interrupt number. Value cannot be negative.
*/
void csi_intc_set_pending_irq(int32_t IRQn);
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param[in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_clear_pending_irq(int32_t IRQn);
/**
\brief Get Wake up Interrupt
\details Reads the wake up register in the INTC and returns the pending bit for the specified interrupt.
\param[in] IRQn Interrupt number.
\return 0 Interrupt is not set as wake up interrupt.
\return 1 Interrupt is set as wake up interrupt.
*/
uint32_t csi_intc_get_wakeup_irq(int32_t IRQn);
/**
\brief Set Wake up Interrupt
\details Sets the wake up bit of an external interrupt.
\param[in] IRQn Interrupt number. Value cannot be negative.
*/
void csi_intc_set_wakeup_irq(int32_t IRQn);
/**
\brief Clear Wake up Interrupt
\details Clears the wake up bit of an external interrupt.
\param[in] IRQn External interrupt number. Value cannot be negative.
*/
void csi_intc_clear_wakeup_irq(int32_t IRQn);
/**
\brief Get Active Interrupt
\details Reads the active register in the INTC and returns the active bit for the device specific interrupt.
\param[in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
uint32_t csi_intc_get_active(int32_t IRQn);
/**
\brief Set Threshold register
\details set the threshold register in the INTC.
\param[in] VectThreshold specific vecter threshold.
\param[in] PrioThreshold specific priority threshold.
*/
void csi_intc_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold);
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param[in] IRQn Interrupt number.
\param[in] priority Priority to set.
*/
void csi_intc_set_prio(int32_t IRQn, uint32_t priority);
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param[in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
uint32_t csi_intc_get_prio(int32_t IRQn);
/**
\brief funciton is acknowledge the IRQ. this interface is internally used by irq system
\param[in] irq irq number to operate
\return 0 on success; -1 on failure
*/
int csi_intc_ack_irq(int32_t IRQn);
/**
\brief This function is set the attributes of an IRQ.
\param[in] irq irq number to operate
\param[in] priority interrupt priority
\param[in] trigger_mode interrupt trigger_mode
\return 0 on success; -1 on failure
*/
int csi_intc_set_attribute(int32_t IRQn, uint32_t priority, int_trigger_mode_t trigger_mode);
/**
\brief Set interrupt handler
\details Set the interrupt handler according to the interrupt num, the handler will be filled in g_irqvector[].
\param[in] IRQn Interrupt number.
\param[in] handler Interrupt handler.
*/
void csi_intc_set_vector(int32_t IRQn, uint32_t handler);
/**
\brief Get interrupt handler
\details Get the address of interrupt handler function.
\param[in] IRQn Interrupt number.
*/
uint32_t csi_intc_get_vector(int32_t IRQn);
#endif /* _DRV_INTC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/intc.h | C | apache-2.0 | 5,503 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/io.h
* @brief Header File for register bits operation
* @version V1.0
* @date 9. Oct 2020
* @model io
******************************************************************************/
#ifndef _DRV_IO_H_
#define _DRV_IO_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Bit field operate*/
#define REG64(addr) (*(volatile uint64_t *)(addr))
#define REG32(addr) (*(volatile uint32_t *)(addr))
#define REG16(addr) (*(volatile uint16_t *)(addr))
#define REG8(addr) (*(volatile uint8_t *)(addr))
/* Insert value to some field in reg, other field is set to 0(the field make macro) */
#define HAL_FMK(PER_REG_FIELD, val) \
(((val) << PER_REG_FIELD##_SHIFT) & PER_REG_FIELD##_MASK)
/* Get value of some field in reg(the field extract macro) */
#define HAL_FEXT(reg, PER_REG_FIELD) \
(((reg) & PER_REG_FIELD##_MASK) >> PER_REG_FIELD##_SHIFT)
/* Insert value to some field in reg, other field don't change(the field insert macro) */
#define HAL_FINS(reg, PER_REG_FIELD, val) \
((reg) = ((reg) & ~PER_REG_FIELD##_MASK) \
| HAL_FMK(PER_REG_FIELD, val))
/* Bit operate */
/* Set one value to 1, other bit don't change*/
#define HAL_BIT_SET(reg, bit) ((reg) = ((reg) | (1U << (bit))))
/* Set one value to 0, other bit don't change*/
#define HAL_BIT_CLR(reg, bit) ((reg) = ((reg) & (~(1U << (bit)))))
/* Get value of one bit(0/1) */
#define HAL_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1U)
/* Judge one bit is 1 or not */
#define HAL_IS_BIT_SET(reg, pos) (((reg) & (1U << (pos))) != 0x0U)
/* Judge one bit is 0 or not */
#define HAL_IS_BIT_CLR(reg, pos) (((reg) & (1U << (pos))) == 0x0U)
/* Set one value to bit, other bit don't change*/
#define HAL_BIT_INSR(reg, bit, val) \
((reg) = (((reg) & (~(1U << (bit)))) | (((val) & 1U) << (bit))))
static inline uint8_t getreg8(volatile void *addr)
{
return *(volatile uint8_t *)addr;
}
static inline void putreg8(uint8_t val, volatile void *addr)
{
*(volatile uint8_t *)addr = val;
}
static inline uint16_t getreg16(volatile void *addr)
{
return *(volatile uint16_t *)addr;
}
static inline void putreg16(uint16_t val, volatile void *addr)
{
*(volatile uint16_t *)addr = val;
}
static inline uint32_t getreg32(volatile void *addr)
{
return *(volatile uint32_t *)addr;
}
static inline void putreg32(uint32_t val, volatile void *addr)
{
*(volatile uint32_t *)addr = val;
}
static inline uint64_t getreg64(volatile void *addr)
{
return *(volatile uint64_t *)addr;
}
static inline void putreg64(uint32_t val, volatile void *addr)
{
*(volatile uint64_t *)addr = val;
}
static inline uint32_t inl(void *addr)
{
return *(volatile uint32_t *)addr;
}
static inline void outl(uint32_t val, void *addr)
{
*(volatile uint32_t *)addr = val;
}
#ifdef __cplusplus
}
#endif
#endif /* _DRV_IO_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/io.h | C | apache-2.0 | 3,218 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/irq.h
* @brief header File for IRQ Driver
* @version V1.0
* @date 16. Mar 2020
* @model irq
******************************************************************************/
#ifndef _DRV_IRQ_H_
#define _DRV_IRQ_H_
#include <stdint.h>
#include <drv/common.h>
#include <soc.h>
#include <csi_core.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Enable irq.
\param[in] irq_num Number of IRQ.
\return None.
*/
__ALWAYS_STATIC_INLINE void csi_irq_enable(uint32_t irq_num)
{
extern void soc_irq_enable(uint32_t irq_num);
soc_irq_enable(irq_num);
}
/**
\brief Disable irq.
\param[in] irq_num Number of IRQ.
\return None.
*/
__ALWAYS_STATIC_INLINE void csi_irq_disable(uint32_t irq_num)
{
extern void soc_irq_disable(uint32_t irq_num);
soc_irq_disable(irq_num);
}
/**
\brief Attach irq handler.
\param[in] irq_num Number of IRQ.
\param[in] irq_handler IRQ Handler.
\param[in] dev The dev to operate
\return None.
*/
void csi_irq_attach(uint32_t irq_num, void *irq_handler, csi_dev_t *dev);
/**
\brief detach irq handler.
\param[in] irq_num Number of IRQ.
\param[in] irq_handler IRQ Handler.
\return None.
*/
void csi_irq_detach(uint32_t irq_num);
/**
\brief Set irq priority
\param[in] irq_num Number of IRQ.
\param[in] priority IRQ Priority.
\return None.
*/
__ALWAYS_STATIC_INLINE void csi_irq_priority(uint32_t irq_num, uint32_t priority)
{
extern void soc_irq_priority(uint32_t irq_num, uint32_t priority);
soc_irq_priority(irq_num, priority);
}
/**
\brief Gets whether the interrupt is enabled
\param[in] irq_num Number of IRQ.
\return true or false.
*/
static inline bool csi_irq_is_enabled(uint32_t irq_num)
{
extern bool soc_irq_is_enabled(uint32_t irq_num);
return soc_irq_is_enabled(irq_num);
}
/**
\brief Enable the interrupt wakeup attribution
\param[in] irq_num Number of IRQ.
\return None.
*/
__ALWAYS_STATIC_INLINE void csi_irq_enable_wakeup(uint32_t irq_num)
{
extern void soc_irq_enable_wakeup(uint32_t irq_num);
soc_irq_enable_wakeup(irq_num);
}
/**
\brief Disable the interrupt wakeup attribution
\param[in] irq_num Number of IRQ.
\return None.
*/
__ALWAYS_STATIC_INLINE void csi_irq_disable_wakeup(uint32_t irq_num)
{
extern void soc_irq_disable_wakeup(uint32_t irq_num);
soc_irq_disable_wakeup(irq_num);
}
/**
\brief Gets whether in irq context
\return true or false.
*/
bool csi_irq_context(void);
/**
\brief Dispatching irq handlers
\return None.
*/
void do_irq(void);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_IRQ_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/irq.h | C | apache-2.0 | 2,890 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/iso7816.h
* @brief Header File for ISO7816 Driver
* @version V1.0
* @date 9. Oct 2020
* @model iso7816
******************************************************************************/
#ifndef _DRV_ISO7816_H_
#define _DRV_ISO7816_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
A_5V,
B_3_3V,
C_1_8V,
} dcd_vclass_t;
typedef enum {
T0,
T1,
} iso7816_tprotocol_t;
typedef enum {
ISO7816_EVENT_CARD_DETECTED,
ISO7816_EVENT_READ_COMPLETE,
ISO7816_EVENT_WRITE_COMPLETE,
ISO7816_EVENT_READ_ERROR,
ISO7816_EVENT_WRITE_ERROR,
ISO7816_EVENT_ACTIVATE_SUCCESS,
ISO7816_EVENT_ACTIVATE_FAILED,
ISO7816_EVENT_CARD_ERROR_DEACTIVATE,
ISO7816_EVENT_CARD_SESSION_CLOSED,
ISO7816_EVENT_RX_FULL,
ISO7816_EVENT_CWT_TIME_OUT,
ISO7816_EVENT_RX_OVER,
ISO7816_EVENT_CRC_ERR,
ISO7816_EVENT_PARITY_ERR,
ISO7816_EVENT_SLAVE_ATR_DETECTED,
ISO7816_EVENT_SLAVE_ATR_DONE,
} iso7816_event_t;
typedef void (*iso7816_event_cb_t)(iso7816_event_t event, void *arg);
typedef enum {
ISO7816_SLAVE,
ISO7816_MASTER,
} iso7816_mode_t;
typedef struct {
uint8_t clk_div;
dcd_vclass_t vclass;
iso7816_mode_t mode;
int32_t card_detected_en;
} iso7816_config_t;
typedef enum {
ISO7816_A_ONLY = 1U,
ISO7816_B_ONLY,
ISO7816_C_ONLY,
ISO7816_AB,
ISO7816_AC,
ISO7816_BC,
ISO7816_ABC,
} iso7816_voltage_class_t;
typedef struct {
iso7816_voltage_class_t support_voltage_class;
int32_t proto_t;
int32_t clk_stop_is_support;
int32_t history_byte_num;
uint8_t history_data[15];
} iso7816_atr_info_t;
typedef enum {
EVEN_PARITY,
ODD_PARITY,
} iso7816_parity_type_t;
typedef enum {
ISO7816_DRIECT,
ISO7816_INVERSE,
} iso7816_convention_t;
typedef enum {
INVCTIVE,
ACTIVATEING,
PSS_TRF,
PSS_RECV,
ACTIVATE,
} iso7816_card_sta_t;
/**
\brief Initialize ISO7816 master interface
\param[in] idx Master index
\param[in] cb_event Pointer to \ref iso7816_event_cb_t
\param[in] cb_arg Event callback arg
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_init(int idx, iso7816_event_cb_t cb_event, void *cb_arg);
/**
\brief Uninit ISO7816 master interface
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_uninit(int idx);
/**
\brief Config ISO7816 master attributes
\param[in] idx Master index
\param[in] config master config \ref iso7816_config_t
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_config(int idx, iso7816_config_t *config);
/**
\brief Receiving data from ISO7816 master receiver, used polling mode
\param[in] idx Master index
\param[in] buf Pointer to buffer for data to receive from i2s receiver
\param[in] len Size of receiver data
\param[in] time_out Receive time out value
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_receive(int idx, uint8_t *buf, uint32_t len, uint32_t time_out);
/**
\brief Receiving data from ISO7816 master receiver, used interrupt mode
\param[in] idx Master index
\param[in] buf Pointer to buffer for data to receive from i2s receiver
\param[in] len Size of receiver data
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_receive_it(int idx, uint8_t *buf, uint32_t len);
/**
\brief Sending data to ISO7816 master transmitter, used polling mode
\param[in] idx Master index
\param[in] buf Pointer to buffer for data to send
\param[in] len Size of tranmitter data
\param[in] time_out Send time out value
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_send(int idx, uint8_t *buf, uint32_t len, uint32_t time_out);
/**
\brief Sending data to ISO7816 master transmitter, used interrupt mode
\param[in] idx Master index
\param[in] buf Pointer to buffer for data to send
\param[in] len Size of tranmitter data
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_send_it(int idx, uint8_t *buf, uint32_t len);
/**
\brief ISO7816 master performs the activation smart card process, this process
is non-blocking,should monitor callback event or read card status to check card is activate
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_card_activate(int idx);
/**
\brief ISO7816 master performs the deactivation smart card process, this process
is non-blocking,should monitor callback event or read card status to check card is activate
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_card_deactivate(int idx);
/**
\brief The smard card session status
\param[in] idx Master index
\return smart card status.
*/
iso7816_card_sta_t csi_iso7816_master_card_status(int idx);
/**
\brief ISO7816 master performs the warm reset smart card process
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_card_warm_reset(int idx);
/**
\brief ISO7816 master performs clock stop
\param[in] idx Master index
\param[in] en The clk last state when power down
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_card_clk_stop_enable(int idx, int en);
/**
\brief ISO7816 master performs pwoer down
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_power_down(int idx);
/**
\brief Get atr analytical results
\param[in] idx Master index
\param[out] info The result of atr information
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_master_atr_info(int idx, iso7816_atr_info_t *info);
/**
\brief Initialize ISO7816 slave interface
\param[in] idx Slave index
\param[in] cb Pointer to \ref iso7816_event_cb_t
\param[in] cb_arg Event callback arg
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_init(int idx, iso7816_event_cb_t cb, void *cb_arg);
/**
\brief Uninit ISO7816 slave interface
\param[in] idx Slave index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_uninit(int idx);
/**
\brief Enable ISO7816 slave interface
\param[in] idx Slave index
\param[in] en Slave enable
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_enable(int idx, int en);
/**
\brief Enable ISO7816 slave receive parity
\param[in] idx Slave index
\param[in] en Enable receive parity
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_receive_parity_enable(int idx, int en);
/**
\brief Set ISO7816 slave receive parity attributes
\param[in] idx Slave index
\param[in] type Set receiver parity type
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_receive_parity(int idx, iso7816_parity_type_t type);
/**
\brief Enable ISO7816 slave send parity
\param[in] idx Slave index
\param[in] en Enable send parity
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_send_parity_enable(int idx, int en);
/**
\brief Set ISO7816 slave send parity attributes
\param[in] idx Slave index
\param[in] type Set send parity attributes
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_send_parity(int idx, iso7816_parity_type_t type);
/**
\brief Set the number of ISO7816 slave receive retry
\param[in] idx Slave index
\param[in] val Set the number retry
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_receive_retry(int idx, uint8_t val);
/**
\brief Set the number of ISO7816 send send retry
\param[in] idx Slave index
\param[in] val Set the number retry
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_send_retry(int idx, uint8_t val);
/**
\brief Set the ISO7816 slave GT
\param[in] idx Slave index
\param[in] val Set the slave GT
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_gt(int idx, uint8_t val);
/**
\brief Set the ISO7816 slave WT
\param[in] idx Slave index
\param[in] val Set the slave WT
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_wt(int idx, uint16_t val);
/**
\brief Set the ISO7816 slave baud, baud = F/D
\param[in] idx Slave index
\param[in] val Set the slave baud
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_baud(int idx, uint16_t val);
/**
\brief Set the ISO7816 slave convention
\param[in] idx Slave index
\param[in] convention Set the slave convention \ref iso7816_convention_t
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_convention(int idx, iso7816_convention_t convention);
/**
\brief Set the ISO7816 slave art response time, val range is 400~40000
\param[in] idx Slave index
\param[in] val Set the slave art response time
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_set_atr_ack_time(int idx, int val);
/**
\brief Set the ISO7816 slave send atr data
\param[in] idx Slave index
\param[in] buf Pointer to buffer for data to send
\param[in] len Size of tranmitter data
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_send_atr(int idx, uint8_t *buf, int len);
/**
\brief Receiving data from ISO7816 slave receiver, used polling mode
\param[in] idx Master index
\param[in] buf Pointer to buffer for data to receive from i2s receiver
\param[in] len Size of receiver data
\param[in] timer_out receive time out value
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_receive(int idx, uint8_t *buf, uint32_t len, uint32_t time_out);
/**
\brief Flushed the ISO7816 slave receive fifo
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_flushed_receive_fifo(int idx);
/**
\brief Receiving data from ISO7816 slave receiver, used interrupt mode
\param[in] idx Master index
\param[in] buf Pointer to buffer for data to receive from i2s receiver
\param[in] len Size of receiver data
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_receive_it(int idx, uint8_t *buf, uint32_t len);
/**
\brief Sending data to ISO7816 slave transmitter, used polling mode
\param[in] idx Slave index
\param[in] buf Pointer to buffer for data to send
\param[in] len Size of tranmitter data
\param[in] timer_out Send time out value
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_send(int idx, uint8_t *buf, uint32_t len, uint32_t time_out);
/**
\brief Flushed the ISO7816 slave send fifo.
\param[in] idx Master index
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_flushed_send_fifo(int idx);
/**
\brief Sending data to ISO7816 slave transmitter, used interrupt mode
\param[in] idx Slave index
\param[in] buf Pointer to buffer for data to send
\param[in] len Size of tranmitter data
\return 0 for success, negative for error code
*/
int32_t csi_iso7816_slave_send_it(int idx, uint8_t *buf, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_ISO7816_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/iso7816.h | C | apache-2.0 | 12,505 |
/*
* Copyright (C) 2015-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/list.h
* @brief Header File for LIST Driver
* @version V1.0
* @date 10. Oct 2020
* @model list
******************************************************************************/
#ifndef AOS_LIST_H
#define AOS_LIST_H
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Get offset of a member variable
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the variable within the struct
\return None
*/
#define aos_offsetof(type, member) ((size_t)&(((type *)0)->member))
/**
\brief Get the struct for this entry
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the variable within the struct
\return None
*/
#define aos_container_of(ptr, type, member) \
((type *) ((char *) (ptr) - aos_offsetof(type, member)))
/* For double link list */
typedef struct dlist_s {
struct dlist_s *prev;
struct dlist_s *next;
} dlist_t;
static inline void __dlist_add(dlist_t *node, dlist_t *prev, dlist_t *next)
{
node->next = next;
node->prev = prev;
prev->next = node;
next->prev = node;
}
/**
\brief Get the struct for this entry
\param[in] addr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_entry(addr, type, member) \
((type *)((long)addr - aos_offsetof(type, member)))
static inline void dlist_add(dlist_t *node, dlist_t *queue)
{
__dlist_add(node, queue, queue->next);
}
static inline void dlist_add_tail(dlist_t *node, dlist_t *queue)
{
__dlist_add(node, queue->prev, queue);
}
static inline void dlist_del(dlist_t *node)
{
dlist_t *prev = node->prev;
dlist_t *next = node->next;
prev->next = next;
next->prev = prev;
}
static inline void dlist_init(dlist_t *node)
{
node->next = (node->prev = node);
}
static inline void INIT_AOS_DLIST_HEAD(dlist_t *list)
{
list->next = list;
list->prev = list;
}
static inline int dlist_empty(const dlist_t *head)
{
return head->next == head;
}
/**
\brief Initialise the list
\param[in] list The list to be inited
\return None
*/
#define AOS_DLIST_INIT(list) {&(list), &(list)}
/**
\brief Get the first element from a list
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_first_entry(ptr, type, member) \
dlist_entry((ptr)->next, type, member)
/**
\brief Iterate over a list
\param[in] pos The &struct dlist_t to use as a loop cursor
\param[in] head The head for your list
\return None
*/
#define dlist_for_each(pos, head) \
for (pos = (head)->next; pos != (head); pos = pos->next)
/**
\brief Iterate over a list safe against removal of list entry
\param[in] pos The &struct dlist_t to use as a loop cursor
\param[in] n Another &struct dlist_t to use as temporary storage
\param[in] head The head for your list
\return None
*/
#define dlist_for_each_safe(pos, n, head) \
for (pos = (head)->next, n = pos->next; pos != (head); \
pos = n, n = pos->next)
/**
\brief Iterate over list of given type
\param[in] queue The head for your list
\param[in] node The &struct dlist_t to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_for_each_entry(queue, node, type, member) \
for (node = aos_container_of((queue)->next, type, member); \
&node->member != (queue); \
node = aos_container_of(node->member.next, type, member))
/**
\brief Iterate over list of given type safe against removal of list entry
\param[in] queue The head for your list
\param[in] n The type * to use as a temp
\param[in] node The type * to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the dlist_t within the struct
\return None
*/
#define dlist_for_each_entry_safe(queue, n, node, type, member) \
for (node = aos_container_of((queue)->next, type, member), \
n = (queue)->next ? (queue)->next->next : NULL; \
&node->member != (queue); \
node = aos_container_of(n, type, member), n = n ? n->next : NULL)
/**
\brief Get the struct for this entry
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the variable within the struct
\return None
*/
#define list_entry(ptr, type, member) \
aos_container_of(ptr, type, member)
/**
\brief Iterate backwards over list of given type
\param[in] pos The type * to use as a loop cursor
\param[in] head The head for your list
\param[in] member The name of the dlist_t within the struct
\param[in] type The type of the struct this is embedded in
\return None
*/
#define dlist_for_each_entry_reverse(pos, head, member, type) \
for (pos = list_entry((head)->prev, type, member); \
&pos->member != (head); \
pos = list_entry(pos->member.prev, type, member))
/**
\brief Get the list length
\param[in] queue The head for your list
\return None
*/
int dlist_entry_number(dlist_t *queue);
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_DLIST_HEAD_INIT(name) { &(name), &(name) }
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_DLIST_HEAD(name) \
dlist_t name = AOS_DLIST_HEAD_INIT(name)
/* For single link list */
typedef struct slist_s {
struct slist_s *next;
} slist_t;
static inline void slist_add(slist_t *node, slist_t *head)
{
node->next = head->next;
head->next = node;
}
void slist_add_tail(slist_t *node, slist_t *head);
static inline void slist_del(slist_t *node, slist_t *head)
{
while (head->next) {
if (head->next == node) {
head->next = node->next;
break;
}
head = head->next;
}
}
static inline int slist_empty(const slist_t *head)
{
return !head->next;
}
static inline void slist_init(slist_t *head)
{
head->next = 0;
}
static inline slist_t *slist_remove(slist_t *l, slist_t *n)
{
/* Remove slist head */
struct slist_s *node = l;
while (node->next && (node->next != n)) {
node = node->next;
}
/* Remove node */
if (node->next != (slist_t *)0) {
node->next = node->next->next;
}
return l;
}
static inline slist_t *slist_first(slist_t *l)
{
return l->next;
}
static inline slist_t *slist_tail(slist_t *l)
{
while (l->next) {
l = l->next;
}
return l;
}
static inline slist_t *slist_next(slist_t *n)
{
return n->next;
}
/**
\brief Iterate over list of given type
\param[in] node The type * to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\param[in] queue The head for your list
\return None
*/
#define slist_for_each_entry(queue, node, type, member) \
for (node = aos_container_of((queue)->next, type, member); \
(uintptr_t)node + aos_offsetof(type, member) != 0; \
node = aos_container_of(node->member.next, type, member))
/**
\brief Iterate over list of given type safe against removal of list entry
\param[in] queue The head for your list
\param[in] tmp The type * to use as a temp
\param[in] node The type * to use as a loop cursor
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\return None
*/
#define slist_for_each_entry_safe(queue, tmp, node, type, member) \
for (node = aos_container_of((queue)->next, type, member), \
tmp = (queue)->next ? (queue)->next->next : NULL; \
(uintptr_t)node + aos_offsetof(type, member) != 0; \
node = aos_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp)
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_SLIST_HEAD_INIT(name) {0}
/**
\brief Initialise the list
\param[in] name The list to be initialized
\return None
*/
#define AOS_SLIST_HEAD(name) \
slist_t name = AOS_SLIST_HEAD_INIT(name)
/**
\brief Get the struct for this entry
\param[in] addr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\return None
*/
#define slist_entry(addr, type, member) ( \
addr ? (type *)((long)addr - aos_offsetof(type, member)) : (type *)addr \
)
/**
\brief Get the first element from a list
\param[in] ptr The list head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_t within the struct
\return None
*/
#define slist_first_entry(ptr, type, member) \
slist_entry((ptr)->next, type, member)
/**
\brief Slist_tail_entry - get the tail element from a slist
\param[in] ptr The slist head to take the element from
\param[in] type The type of the struct this is embedded in
\param[in] member The name of the slist_struct within the struct
\return None
\note That slist is expected to be not empty
*/
#define slist_tail_entry(ptr, type, member) \
slist_entry(slist_tail(ptr), type, member)
/**
\brief Get the list length
\param[in] queue The head for your list
\return None
*/
int slist_entry_number(slist_t *queue);
#ifdef __cplusplus
}
#endif
#endif /* AOS_LIST_H */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/list.h | C | apache-2.0 | 10,697 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/mbox.h
* @brief Header File for MBOX Driver
* @version V1.0
* @date 5. Apr 2020
* @model mbox
******************************************************************************/
#ifndef _DRV_MBOX_H_
#define _DRV_MBOX_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
MBOX_EVENT_SEND_COMPLETE = 0U, ///< Send completed; however mbox may still transmit data
MBOX_EVENT_RECEIVED = 1U, ///< Data Received, only in mbox buf, call memcpy() get the data
MBOX_EVENT_ERROR = 2U, ///< Mbox transmit error occurred
} csi_mbox_event_t;
typedef struct csi_mbox csi_mbox_t;
struct csi_mbox {
csi_dev_t dev;
void (*callback)(csi_mbox_t *mbox, csi_mbox_event_t event, uint32_t channel_id, uint32_t received_len, void *arg);
void *arg;
void *priv;
};
/**
\brief Initialize mbox Interface.
Initializes the resources needed for the mbox interface.
\param[in] mbox Operate handle.
\param[in] idx The device idx.
\return Error code \ref csi_error_t.
*/
csi_error_t csi_mbox_init(csi_mbox_t *mbox, uint32_t idx);
/**
\brief Uninitialize mbox interface. stops operation and releases the software resources used by the interface.
\param[in] mbox Operate handle.
*/
void csi_mbox_uninit(csi_mbox_t *mbox);
/**
\brief Start sending data to mbox transmitter.
\param[in] mbox Operate handle.
\param[in] channel_id Index of channel.
\param[in] data Pointer to buffer with data to send to mbox transmitter.
\param[in] size Number of data items to send.
\return sent Number of data or error code.
*/
int32_t csi_mbox_send(csi_mbox_t *mbox, uint32_t channel_id, const void *data, uint32_t size);
/**
\brief Start receiving data from mbox receiver.
\param[in] mbox Operate handle.
\param[in] channel_id Index of channel.
\param[out] data Pointer to buffer with data to receive from mailbox.
\param[in] size Number of data items to receive.
\return received Number or error code.
*/
int32_t csi_mbox_receive(csi_mbox_t *mbox, uint32_t channel_id, void *data, uint32_t size);
/**
\brief Attach callback to the mbox.
\param[in] mbox Operate handle.
\param[in] cb Event callback function.
\param[in] arg User private param for event callback.
\return Error code \ref csi_error_t.
*/
csi_error_t csi_mbox_attach_callback(csi_mbox_t *mbox, void *callback, void *arg);
/**
\brief Detach callback from the mbox
\param[in] mbox Operate handle.
*/
void csi_mbox_detach_callback(csi_mbox_t *mbox);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_MBOX_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/mbox.h | C | apache-2.0 | 2,886 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file soc.h
* @brief For pin
* @version V1.0
* @date 11. Mar 2020
******************************************************************************/
#ifndef _DRV_PIN_H_
#define _DRV_PIN_H_
#include <drv/common.h>
#include <drv/gpio.h>
#include <soc.h>
typedef csi_gpio_mode_t csi_pin_mode_t;
typedef enum {
PIN_SPEED_LV0 = 0U,
PIN_SPEED_LV1,
PIN_SPEED_LV2,
PIN_SPEED_LV3
} csi_pin_speed_t;
typedef enum {
PIN_DRIVE_LV0 = 0U,
PIN_DRIVE_LV1,
PIN_DRIVE_LV2,
PIN_DRIVE_LV3
} csi_pin_drive_t;
typedef enum{
PIN_UART_TX = 0U,
PIN_UART_RX,
PIN_UART_CTS,
PIN_UART_RTS
}csi_pin_uart_t;
typedef enum{
PIN_IIC_SCL = 0U,
PIN_IIC_SDA
}csi_pin_iic_t;
typedef enum{
PIN_SPI_MISO = 0U,
PIN_SPI_MOSI,
PIN_SPI_SCK,
PIN_SPI_CS
}csi_pin_spi_t;
typedef enum{
PIN_I2S_MCLK = 0U,
PIN_I2S_SCLK,
PIN_I2S_WSCLK,
PIN_I2S_SDA,
PIN_I2S_SDI,
PIN_I2S_SDO
}csi_pin_i2s_t;
typedef struct {
pin_name_t pin_name;
uint8_t idx; ///< ctrl idx. e.g: ADC0 channel 1, idx = 0, channel = 1
uint8_t channel; ///< channel idx. e.g: same as the previous line
pin_func_t pin_func;
} csi_pinmap_t;
extern uint32_t target_pin_to_devidx(pin_name_t pin_name, const csi_pinmap_t *pinmap);
extern uint32_t target_pin_to_channel(pin_name_t pin_name,const csi_pinmap_t *pinmap);
extern pin_name_t target_gpio_to_pin(uint8_t gpio_idx, uint8_t channel,const csi_pinmap_t *pinmap);
/**
\brief Set pin mux function
\param[in] pin_name Pin name, defined in soc.h
\param[in] pin_func Pin function, defined in soc.h
\return \ref csi_error_t
*/
csi_error_t csi_pin_set_mux(pin_name_t pin_name, pin_func_t pin_func);
/**
\brief Get pin function
\param[in] pin_name Pin name, defined in soc.h
\return pin function
*/
pin_func_t csi_pin_get_mux(pin_name_t pin_name);
/**
\brief Set pin mode
\param[in] pin_name Pin name, defined in soc.h
\param[in] mode Push/pull mode
\return \ref csi_error_t
*/
csi_error_t csi_pin_mode(pin_name_t pin_name, csi_pin_mode_t mode);
/**
\brief Set pin speed
\param[in] pin_name Pin name, defined in soc.h
\param[in] speed Io speed
\return \ref csi_error_t
*/
csi_error_t csi_pin_speed(pin_name_t pin_name, csi_pin_speed_t speed);
/**
\brief Set pin drive
\param[in] pin_name Pin name, defined in soc.h
\param[in] drive Io drive
\return \ref csi_error_t
*/
csi_error_t csi_pin_drive(pin_name_t pin_name, csi_pin_drive_t drive);
/**
\brief Get ctrl idx by pin
\param[in] pin_name Pin name, defined in soc.h
\return idx
*/
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_gpio_devidx(pin_name_t pin_name)
{
extern const csi_pinmap_t gpio_pinmap[];
return target_pin_to_devidx(pin_name, gpio_pinmap);
}
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_uart_devidx(pin_name_t pin_name)
{
extern const csi_pinmap_t uart_pinmap[];
return target_pin_to_devidx(pin_name, uart_pinmap);
}
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_iic_devidx(pin_name_t pin_name)
{
extern const csi_pinmap_t iic_pinmap[];
return target_pin_to_devidx(pin_name, iic_pinmap);
}
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_spi_devidx(pin_name_t pin_name)
{
extern const csi_pinmap_t spi_pinmap[];
return target_pin_to_devidx(pin_name, spi_pinmap);
}
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_i2s_devidx(pin_name_t pin_name)
{
extern const csi_pinmap_t i2s_pinmap[];
return target_pin_to_devidx(pin_name, i2s_pinmap);
}
/**
\brief Get channel by pin
\param[in] pin_name Pin name, defined in soc.h
\return channel
*/
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_adc_channel(pin_name_t pin_name)
{
extern const csi_pinmap_t adc_pinmap[];
return target_pin_to_channel(pin_name, adc_pinmap);
}
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_pwm_channel(pin_name_t pin_name)
{
extern const csi_pinmap_t pwm_pinmap[];
return target_pin_to_channel(pin_name, pwm_pinmap);
}
__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_gpio_channel(pin_name_t pin_name)
{
extern const csi_pinmap_t gpio_pinmap[];
return target_pin_to_channel(pin_name, gpio_pinmap);
}
/**
\brief Get pin name by gpio ctrl idx and channel
\param[in] gpio_idx Idx, defined in soc.h
\param[in] channel Channel, defined in soc.h
\return pin name
*/
__ALWAYS_STATIC_INLINE pin_name_t csi_pin_get_pinname_by_gpio(uint8_t gpio_idx, uint8_t channel)
{
extern const csi_pinmap_t gpio_pinmap[];
return target_gpio_to_pin(gpio_idx,channel,gpio_pinmap);
}
#endif /* _DRV_PIN_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/pin.h | C | apache-2.0 | 4,872 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/pm.h
* @brief Header File for PM Driver
* @version V1.0
* @date 10. Oct 2020
* @model pm
******************************************************************************/
#ifndef _DRV_PM_H_
#define _DRV_PM_H_
#include <stdint.h>
#include <drv/common.h>
#include <soc.h>
#include <csi_core.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Initialize PM module
\return Error code \ref csi_error_t
*/
csi_error_t csi_pm_init(void);
/**
\brief De-initialize PM module
\return None
*/
void csi_pm_uninit(void);
/**
\brief Set the retention memory used to save registers
\param[in] mem Retention memory(word align)
\param[in] num Number of memory(1: 1 word)
\return Error code \ref csi_error_t
*/
csi_error_t csi_pm_set_reten_mem(uint32_t *mem, uint32_t num);
/**
\brief Config the wakeup source
\param[in] wakeup_num Wakeup source num
\param[in] enable Flag control the wakeup source is enable or not
\return Error code \ref csi_error_t
*/
csi_error_t csi_pm_config_wakeup_source(uint32_t wakeup_num, bool enable);
/**
\brief System enter low-power mode
\param[in] mode Low-power mode, \ref csi_pm_mode_t
\return Error code \ref csi_error_t
*/
csi_error_t csi_pm_enter_sleep(csi_pm_mode_t mode);
/**
\brief Register device to the PM list
\param[in] dev Csi dev
\param[in] pm_action PM action function
\param[in] mem_size Size of memory for saving registers
\param[in] priority PM dev priority(0-3), The smaller the value,
the last execution before entering low power consumption,
the first execution after exiting low power consumption
\return Error code \ref csi_error_t
*/
csi_error_t csi_pm_dev_register(csi_dev_t *dev, void *pm_action, uint32_t mem_size, uint8_t priority);
/**
\brief Deregister device to the PM list
\param[in] dev Csi dev
\return None
*/
void csi_pm_dev_unregister(csi_dev_t *dev);
/**
\brief Save registers to memory
\param[in] mem Mem to store registers
\param[in] addr Registers address
\param[in] num Number of memory(1: 1 word)
\return None
*/
void csi_pm_dev_save_regs(uint32_t *mem, uint32_t *addr, uint32_t num);
/**
\brief Save registers to memory
\param[in] mem Mem to store registers
\param[in] addr Registers address
\param[in] num Number of memory(1: 1 word)
\return None
*/
void csi_pm_dev_restore_regs(uint32_t *mem, uint32_t *addr, uint32_t num);
/**
\brief Notify devices enter low-power states
\param[in] action Device low-power action
\return Error code \ref csi_error_t
*/
csi_error_t csi_pm_dev_notify(csi_pm_dev_action_t action);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_PM_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/pm.h | C | apache-2.0 | 3,058 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file drv_pmu.h
* @brief header file for pmu driver
* @version V1.0
* @date 02. June 2017
* @model pmu
******************************************************************************/
#ifndef _DRV_PMU_H_
#define _DRV_PMU_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/// definition for pmu handle.
typedef void *pmu_handle_t;
/****** PMU specific error codes *****/
typedef enum {
EDRV_PMU_MODE = (1), ///< Specified Mode not supported
} pmu_error_e;
/*----- PMU Control Codes: Mode -----*/
typedef enum {
PMU_MODE_RUN = 0, ///< Running mode
PMU_MODE_SLEEP, ///< Sleep mode
PMU_MODE_DOZE, ///< Doze mode
PMU_MODE_DORMANT, ///< Dormant mode
PMU_MODE_STANDBY, ///< Standby mode
PMU_MODE_SHUTDOWN ///< Shutdown mode
} pmu_mode_e;
/*----- PMU Control Codes: Wakeup type -----*/
typedef enum {
PMU_WAKEUP_TYPE_PULSE = 0, ///< Pulse interrupt
PMU_WAKEUP_TYPE_LEVEL ///< Level interrupt
} pmu_wakeup_type_e;
/*----- PMU Control Codes: Wakeup polarity -----*/
typedef enum {
PMU_WAKEUP_POL_LOW = 0, ///< Low or negedge
PMU_WAKEUP_POL_HIGH ///< High or posedge
} pmu_wakeup_pol_e;
/****** PMU Event *****/
typedef enum {
PMU_EVENT_SLEEP_DONE = 0, ///< Send completed; however PMU may still transmit data
PMU_EVENT_PREPARE_SLEEP = 1
} pmu_event_e;
typedef void (*pmu_event_cb_t)(int32_t idx, pmu_event_e event, pmu_mode_e mode); ///< Pointer to \ref pmu_event_cb_t : PMU Event call back.
/**
\brief Initialize PMU Interface. 1. Initializes the resources needed for the PMU interface 2.registers event callback function
\param[in] idx the id of the pmu
\param[in] cb_event Pointer to \ref pmu_event_cb_t
\return return pmu handle if success
*/
pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event);
/**
\brief De-initialize PMU Interface. stops operation and releases the software resources used by the interface
\param[in] handle pmu handle to operate.
\return error code
*/
int32_t csi_pmu_uninitialize(pmu_handle_t handle);
/**
\brief choose the pmu mode to enter
\param[in] handle pmu handle to operate.
\param[in] mode \ref pmu_mode_e
\return error code
*/
int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode);
/**
\brief control pmu power.
\param[in] handle pmu handle to operate.
\param[in] state power state.\ref csi_power_stat_e.
\return error code
*/
/**
\brief Config the wakeup source.
\param[in] handle pmu handle to operate
\param[in] wakeup_num wakeup source num
\param[in] type \ref pmu_wakeup_type
\param[in] pol \ref pmu_wakeup_pol
\param[in] enable flag control the wakeup source is enable or not
\return error code
*/
int32_t csi_pmu_config_wakeup_source(pmu_handle_t handle, uint32_t wakeup_num, pmu_wakeup_type_e type, pmu_wakeup_pol_e pol, uint8_t enable);
#ifdef __cplusplus
}
#endif
#endif /* _CSI_PMU_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/pmu.h | C | apache-2.0 | 3,366 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/porting.h
* @brief Header File for SOC Porting
* @version V1.0
* @date 8. Apr 2020
* @model porting
******************************************************************************/
#ifndef _DRV_PORTING_H_
#define _DRV_PORTING_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
/**
\brief Soc get device frequence.
\param[in] idx Device index
\return frequence
*/
uint32_t soc_get_apb_freq(uint32_t idx);
uint32_t soc_get_ahb_freq(uint32_t idx);
uint32_t soc_get_cpu_freq(uint32_t idx);
uint32_t soc_get_uart_freq(uint32_t idx);
uint32_t soc_get_spi_freq(uint32_t idx);
uint32_t soc_get_iic_freq(uint32_t idx);
uint32_t soc_get_i2s_freq(uint32_t idx);
uint32_t soc_get_pwm_freq(uint32_t idx);
uint32_t soc_get_adc_freq(uint32_t idx);
uint32_t soc_get_qspi_freq(uint32_t idx);
uint32_t soc_get_usi_freq(uint32_t idx);
uint32_t soc_get_timer_freq(uint32_t idx);
uint32_t soc_get_rtc_freq(uint32_t idx);
uint32_t soc_get_wdt_freq(uint32_t idx);
uint32_t soc_get_sdio_freq(uint32_t idx);
uint32_t soc_get_coretim_freq(void);
uint32_t soc_get_cur_cpu_freq(void);
/**
\brief Soc get device frequence.
\param[in] freq CPU frequence
\return none
*/
void soc_set_sys_freq(uint32_t freq);
/*
\brief Soc enable device clock
\param[in] module Clock module, defined in sys_clk.h, \ref clk_module_t
\return none
*/
void soc_clk_enable(int32_t module);
/*
\brief Soc disable device clock
\param[in] module Clock module, defined in sys_clk.h, \ref clk_module_t
\return none
*/
void soc_clk_disable(int32_t module);
/*
\brief Get CPU ID
\return CPU ID, the val is 0, 1, 2...
*/
uint32_t soc_get_cpu_id(void);
/**
\brief SOC Dcache clean & invalid by range.
\return None
*/
void soc_dcache_clean_invalid_range(unsigned long addr, uint32_t size);
/**
\brief SOC Dcache clean & invalid all.
\return None
*/
void soc_dcache_clean_invalid_all(void);
/**
\brief SOC Dcache invalid by range.
\return None
*/
void soc_dcache_invalid_range(unsigned long addr, uint32_t size);
/**
\brief SOC Dcache clean all.
\return None
*/
void soc_dcache_clean(void);
/**
\brief SOC Icache invalid all.
\return None
*/
void soc_icache_invalid(void);
/**
\brief SOC dma address remap.
\return Remaped address
*/
extern unsigned long soc_dma_address_remap(unsigned long addr);
#ifdef CONFIG_PM
/**
\brief SoC enter low-power mode, each chip's implementation is different
called by csi_pm_enter_sleep
\param[in] mode low-power mode
\return Error code
*/
csi_error_t soc_pm_enter_sleep(csi_pm_mode_t mode);
/**
\brief SoC the wakeup source.
\param[in] wakeup_num Wakeup source num
\param[in] enable Flag control the wakeup source is enable or not
\return Error code
*/
csi_error_t soc_pm_config_wakeup_source(uint32_t wakeup_num, bool enable);
#endif
#endif /* _DRV_PORTING_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/porting.h | C | apache-2.0 | 3,210 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/pwm.h
* @brief Header File for PWM Driver
* @version V1.0
* @date 9. Oct 2020
* @model pwm
******************************************************************************/
#ifndef _DRV_PWM_H_
#define _DRV_PWM_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PWM_POLARITY_HIGH = 0U, ///< High level
PWM_POLARITY_LOW ///< Low level
} csi_pwm_polarity_t;
typedef enum {
PWM_CAPTURE_POLARITY_POSEDGE = 0U, ///< Posedge Edge
PWM_CAPTURE_POLARITY_NEGEDGE, ///< Negedge Edge
PWM_CAPTURE_POLARITY_BOTHEDGE ///< Both Edge
} csi_pwm_capture_polarity_t;
typedef enum {
PWM_EVENT_CAPTURE_POSEDGE = 0U, ///< Capture Posedge Event
PWM_EVENT_CAPTURE_NEGEDGE, ///< Capture Negedge Event
PWM_EVENT_CAPTURE_BOTHEDGE, ///< Capture Bothedge Event
PWM_EVENT_ERROR, ///< Error
} csi_pwm_event_t;
typedef struct csi_pwm csi_pwm_t;
struct csi_pwm {
csi_dev_t dev;
void (*callback)(csi_pwm_t *pwm, csi_pwm_event_t event, uint32_t ch, uint32_t time_us, void *arg);
void *arg;
void *priv;
};
/**
\brief Initialize PWM interface. Initializes the resources needed for the PWM interface
\param[in] pwm Handle to operate
\param[in] idx PWM idx
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_init(csi_pwm_t *pwm, uint32_t idx);
/**
\brief De-initialize PWM interface. Stops operation and releases the software resources used by the interface
\param[in] pwm Handle to operate
\return None
*/
void csi_pwm_uninit(csi_pwm_t *pwm);
/**
\brief Config PWM out mode
\param[in] pwm Handle to operate
\param[in] channel Channel num
\param[in] period_us The PWM period in us
\param[in] pulse_width_us The PMW pulse width in us
\param[in] polarity The PWM polarity \ref csi_pwm_polarity_t
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_out_config(csi_pwm_t *pwm,
uint32_t channel,
uint32_t period_us,
uint32_t pulse_width_us,
csi_pwm_polarity_t polarity);
/**
\brief Start generate PWM signal
\param[in] pwm Handle to operate
\param[in] channel Channel num
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_out_start(csi_pwm_t *pwm, uint32_t channel);
/**
\brief Stop generate PWM signal
\param[in] pwm Handle to operate
\param[in] channel Channel num
\return None
*/
void csi_pwm_out_stop(csi_pwm_t *pwm, uint32_t channel);
/**
\brief Config PWM capture mode
\param[in] pwm Handle to operate
\param[in] channel Channel num
\param[in] polarity PWM capture polarity \ref csi_pwm_capture_polarity_t
\param[in] count PWM capture polarity count
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_capture_config(csi_pwm_t *pwm,
uint32_t channel,
csi_pwm_capture_polarity_t polarity,
uint32_t count);
/**
\brief Start PWM capture
\param[in] pwm Handle to operate
\param[in] channel Channel num
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_capture_start(csi_pwm_t *pwm, uint32_t channel);
/**
\brief Stop PWM capture
\param[in] pwm Handle to operate
\param[in] channel Channel num
\return None
*/
void csi_pwm_capture_stop(csi_pwm_t *pwm, uint32_t channel);
/**
\brief Attach PWM callback
\param[in] pwm Handle to operate
\param[in] callback Callback func
\param[in] arg Callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_attach_callback(csi_pwm_t *pwm, void *callback, void *arg);
/**
\brief Detach PWM callback
\param[in] pwm Handle to operate
\return None
*/
void csi_pwm_detach_callback(csi_pwm_t *pwm);
/**
\brief Enable PWM power manage
\param[in] pwm Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_pwm_enable_pm(csi_pwm_t *pwm);
/**
\brief Disable PWM power manage
\param[in] pwm Handle to operate
\return None
*/
void csi_pwm_disable_pm(csi_pwm_t *pwm);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_PWM_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/pwm.h | C | apache-2.0 | 4,845 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/qspi.h
* @brief Header File for QSPI Driver
* @version V1.0
* @date 8. Apr 2020
* @model qspi
******************************************************************************/
#ifndef _DRV_QSPI_H_
#define _DRV_QSPI_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \enum csi_qspi_clock_mode_t
* \brief QSPI clock mode
*/
typedef enum {
QSPI_CLOCK_MODE_0 = 0, ///< Clock Polarity 0, Clock Phase 0
QSPI_CLOCK_MODE_1, ///< Clock Polarity 0, Clock Phase 1
QSPI_CLOCK_MODE_2, ///< Clock Polarity 1, Clock Phase 0
QSPI_CLOCK_MODE_3, ///< Clock Polarity 1, Clock Phase 1
} csi_qspi_mode_t;
/**
* \enum csi_qspi_bus_width_t
* \brief QSPI bus width
*/
typedef enum {
QSPI_CFG_BUS_SINGLE = 0, ///< Single line
QSPI_CFG_BUS_DUAL, ///< Two line
QSPI_CFG_BUS_QUAD, ///< Four line
} csi_qspi_bus_width_t;
/**
* \enum csi_qspi_address_size_t
* \brief Address size in bits
*/
typedef enum {
QSPI_ADDRESS_8_BITS = 0,
QSPI_ADDRESS_16_BITS,
QSPI_ADDRESS_24_BITS,
QSPI_ADDRESS_32_BITS,
} csi_qspi_address_size_t;
/**
* \enum csi_qspi_alternate_bytes_size_t
* rief QSPI alternate bytes
*/
typedef enum {
QSPI_ALTERNATE_8_BITS = 0,
QSPI_ALTERNATE_16_BITS,
QSPI_ALTERNATE_24_BITS,
QSPI_ALTERNATE_32_BITS,
} csi_qspi_alt_size_t;
/** QSPI command
*
* Defines a frame format. It consists of instruction, address, alternative, dummy count and data
*/
typedef struct {
struct {
csi_qspi_bus_width_t bus_width; ///< Bus width for the instruction
uint8_t value; ///< Instruction value
bool disabled; ///< Instruction phase skipped if disabled is set to true
} instruction;
struct {
csi_qspi_bus_width_t bus_width; ///< Bus width for the address
csi_qspi_address_size_t size; ///< Address size
uint32_t value; ///< Address value
bool disabled; ///< Address phase skipped if disabled is set to true
} address;
struct {
csi_qspi_bus_width_t bus_width; ///< Bus width for alternative
csi_qspi_alt_size_t size; ///< Alternative size
uint32_t value; ///< Alternative value
bool disabled; ///< Alternative phase skipped if disabled is set to true
} alt;
uint8_t dummy_count; ///< Dummy cycles count
struct {
csi_qspi_bus_width_t bus_width; ///< Bus width for data
} data;
uint8_t ddr_enable;
} csi_qspi_command_t;
/**
* \enum csi_qspi_event_t
* \brief QSPI event
*/
typedef enum {
QSPI_EVENT_COMMAND_COMPLETE = 0, ///< Command completed
QSPI_EVENT_ERROR, ///< An error has occurred
} csi_qspi_event_t;
/**
* \struct csi_qspi_t
* \brief QSPI Handle Structure definition
*/
typedef struct csi_qspi csi_qspi_t;
struct csi_qspi {
csi_dev_t dev; ///< QSPI hw-device info
void (*callback)(csi_qspi_t *qspi, csi_qspi_event_t event, void *arg); ///< User callback function
void *arg; ///< QSPI custom designed param passed to evt_cb
uint8_t *tx_data; ///< Pointer to QSPI Tx transfer Buffer
uint32_t tx_size; ///< QSPI Tx Transfer size
uint8_t *rx_data; ///< Pointer to QSPI Rx transfer Buffer
uint32_t rx_size; ///< QSPI Rx Transfer size
void *send; ///< The send_async func
void *receive; ///< The receive_async func
void *send_receive; ///< The send_receive_async func
csi_state_t state; ///< Peripheral state
csi_dma_ch_t *tx_dma;
csi_dma_ch_t *rx_dma;
void *priv;
};
/**
\brief Init QSPI ctrl block
1. Initializes the QSPI mode according to the specified parameters in the csi_qspi_init_t
2. Registers event callback function and user param for the callback
\param[in] qspi Handle of QSPI instance
\param[in] idx Index of instance
\return Error code
*/
csi_error_t csi_qspi_init(csi_qspi_t *qspi, uint32_t idx);
/**
\brief De-initialize QSPI Instance
stops operation and releases the software resources used by the Instance
\param[in] qspi Handle of QSPI instance
*/
void csi_qspi_uninit(csi_qspi_t *qspi);
/**
\brief Attach the callback handler to QSPI
\param[in] qspi Operate handle
\param[in] callback Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code
*/
csi_error_t csi_qspi_attach_callback(csi_qspi_t *qspi, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] qspi Operate handle
\return None
*/
void csi_qspi_detach_callback(csi_qspi_t *qspi);
/**
\brief Config qspi frequence
\param[in] qspi Handle of qspi instance
\param[in] hz QSPI frequence
\return The actual config frequency
*/
uint32_t csi_qspi_frequence(csi_qspi_t *qspi, uint32_t hz);
/**
\brief Config qspi mode
\param[in] qspi Handle of qspi instance
\param[in] mode QSPI mode
\return Error code
*/
csi_error_t csi_qspi_mode(csi_qspi_t *qspi, csi_qspi_mode_t mode);
/**
\brief Send an amount of data in blocking mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\param[in] data Pointer to data buffer
\param[in] size Size of data to send
\param[in] timeout Time out duration
\return If send successful, this function shall return the num of data witch is sent successful
otherwise, the function shall return error code
*/
int32_t csi_qspi_send(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Receive an amount of data in blocking mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\param[out] data Pointer to data buffer
\param[in] size Size of data items to receive
\param[in] timeout Time out duration
\return If receive successful, this function shall return the num of data witch is received successfulful
otherwise, the function shall return error code
*/
int32_t csi_qspi_receive(csi_qspi_t *qspi, csi_qspi_command_t *cmd, void *data, uint32_t size, uint32_t timeout);
/**
\brief Transfer an amount of data in blocking mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\param[in] tx_data Pointer to send data buffer
\param[out] rx_data Pointer to receive data buffer
\param[in] size Size of data to transfer
\param[in] timeout Time out duration
\return If transfer successful, this function shall return the num of data witch is transfer successfulful
otherwise, the function shall return error code
*/
int32_t csi_qspi_send_receive(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *tx_data, void *rx_data, uint32_t size, uint32_t timeout);
/**
\brief Send an amount of data in async mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\param[in] data Pointer to data buffer
\param[in] size Size of data to send
\return Data number send
*/
csi_error_t csi_qspi_send_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *data, uint32_t size);
/**
\brief Receive an amount of data in async mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\param[out] data Pointer to data buffer
\param[in] size Size of data items to receive
\return Data number received
*/
csi_error_t csi_qspi_receive_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, void *data, uint32_t size);
/**
\brief Transfer an amount of data in async mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\param[in] tx_data Pointer to send data buffer
\param[out] rx_data Pointer to receive data buffer
\param[in] size Size of data to transfer
\return Data number transfered
*/
csi_error_t csi_qspi_send_receive_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *tx_data, void *rx_data, uint32_t size);
/**
\brief Link DMA channel to qspi device
\param[in] qspi QSPI handle to operate
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel
\return Error code
*/
csi_error_t csi_qspi_link_dma(csi_qspi_t *qspi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get the state of qspi device
\param[in] qspi QSPI handle
\param[in] state QSPI state \ref csi_state_t
\return Error code
*/
csi_error_t csi_qspi_get_state(csi_qspi_t *qspi, csi_state_t *state);
/**
\brief Comfigure the memory mapped mode
\param[in] qspi QSPI handle
\param[in] cmd Structure that contains the command configuration information
\return Error code
*/
csi_error_t csi_qspi_memory_mapped(csi_qspi_t *qspi, csi_qspi_command_t *cmd);
/**
\brief Enable qspi power manage
\param[in] qspi QSPI handle to operate
\return Error code
*/
csi_error_t csi_qspi_enable_pm(csi_qspi_t *qspi);
/**
\brief Disable qspi power manage
\param[in] qspi QSPI handle to operate
\return None
*/
void csi_qspi_disable_pm(csi_qspi_t *qspi);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_QSPI_H_*/
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/qspi.h | C | apache-2.0 | 10,347 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/ringbuffer.h
* @brief Header File for RINGBUFFER Driver
* @version V1.0
* @date August 15. 2020
******************************************************************************/
#ifndef _DRV_RINGBUFFER_H_
#define _DRV_RINGBUFFER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "stdint.h"
#include <stdbool.h>
typedef struct ringbuffer {
uint8_t *buffer;
uint32_t size;
uint32_t write;
uint32_t read;
uint32_t data_len;
} ringbuffer_t;
void ringbuffer_reset(ringbuffer_t *fifo);
uint32_t ringbuffer_len(ringbuffer_t *fifo);
uint32_t ringbuffer_avail(ringbuffer_t *fifo);
bool ringbuffer_is_empty(ringbuffer_t *fifo);
bool ringbuffer_is_full(ringbuffer_t *fifo);
/*write to ringbuffer*/
uint32_t ringbuffer_in(ringbuffer_t *fifo, const void *in, uint32_t len);
/*read to ringbuffer*/
uint32_t ringbuffer_out(ringbuffer_t *fifo, void *out, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_RINGBUFFER_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/ringbuffer.h | C | apache-2.0 | 1,110 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/tng.h
* @brief Header File for RNG Driver
* @version V1.0
* @date 22. Apr 2020
* @model tng
******************************************************************************/
#ifndef _DRV_TNG_H_
#define _DRV_TNG_H_
#include "drv/common.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Get data from the TNG engine
\param[out] Data Pointer to buffer with data get from TNG
\param[in] Num Number of data items,uinit in uint32
\return Error code \ref csi_error_t
*/
csi_error_t csi_rng_get_multi_word(uint32_t *data, uint32_t num);
/**
\brief Get data from the TNG engine
\return Error code \ref csi_error_t
*/
csi_error_t csi_rng_get_single_word(uint32_t* data);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TNG_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/rng.h | C | apache-2.0 | 959 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/rsa.h
* @brief Header File for RSA Driver
* @version V1.0
* @date 02. June 2020
* @model rsa
******************************************************************************/
#ifndef _DRV_RSA_H_
#define _DRV_RSA_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <drv/common.h>
/*----- RSA Control Codes: Mode Parameters: Key Bits -----*/
typedef enum {
RSA_KEY_BITS_192 = 0, ///< 192 Key bits
RSA_KEY_BITS_256, ///< 256 Key bits
RSA_KEY_BITS_512, ///< 512 Key bits
RSA_KEY_BITS_1024, ///< 1024 Key bits
RSA_KEY_BITS_2048, ///< 2048 Key bits
RSA_KEY_BITS_3072, ///< 3072 Key bits
RSA_KEY_BITS_4096 ///< 4096 Key bits
} csi_rsa_key_bits_t;
typedef enum {
RSA_PADDING_MODE_NO = 0, ///< RSA NO Padding Mode
RSA_PADDING_MODE_PKCS1, ///< RSA PKCS1 Padding Mode
RSA_PADDING_MODE_PKCS1_OAEP, ///< RSA PKCS1 OAEP Padding Mode
RSA_PADDING_MODE_SSLV23, ///< RSA SSLV23 Padding Mode
RSA_PADDING_MODE_X931, ///< RSA X931 Padding Mode
RSA_PADDING_MODE_PSS ///< RSA PSS Padding Mode
} csi_rsa_padding_type_t;
typedef enum {
RSA_HASH_TYPE_MD5 = 0,
RSA_HASH_TYPE_SHA1,
RSA_HASH_TYPE_SHA224,
RSA_HASH_TYPE_SHA256,
RSA_HASH_TYPE_SHA384,
RSA_HASH_TYPE_SHA512
} csi_rsa_hash_type_t;
typedef struct {
void *n; ///< Pointer to the public modulus
void *e; ///< Pointer to the public exponent
void *d; ///< Pointer to the private exponent
csi_rsa_key_bits_t key_bits; ///< RSA KEY BITS
csi_rsa_padding_type_t padding_type; ///< RSA PADDING TYPE
} csi_rsa_context_t;
/**
\brief RSA State
*/
typedef struct {
uint8_t busy : 1; ///< Calculate busy flag
uint8_t error : 1; ///< Calculate error flag
} csi_rsa_state_t;
typedef struct {
csi_dev_t dev;
void *cb;
void *arg;
csi_rsa_state_t state;
void *prim;
} csi_rsa_t;
typedef struct {
uint32_t pout[64];
uint8_t *pouts;
uint32_t *pout_size;
uint32_t u32keywords;
uint8_t *pdst;
uint32_t u32padding;
uint32_t u32dst_words;
uint32_t u32type;
uint32_t rsa_state;
}rsa_middle_t;
/****** RSA Event *****/
typedef enum {
RSA_EVENT_COMPLETE = 0, ///< rsa event completed
RSA_EVENT_VERIFY_SUCCESS,
RSA_EVENT_VERIFY_FAILED,
RSA_EVENT_ERROR, ///< error event
} csi_rsa_event_t;
typedef void (*csi_rsa_callback_t)(csi_rsa_t *rsa, csi_rsa_event_t event, void *arg); ///< Pointer to \ref csi_rsa_callback_t : RSA Event call back.
/**
\brief Initialize RSA Interface. 1. Initializes the resources needed for the RSA interface 2.registers event callback function
\param[in] rsa RSA handle to operate.
\param[in] idx Device id
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_init(csi_rsa_t *rsa, uint32_t idx);
/**
\brief De-initialize RSA Interface. stops operation and releases the software resources used by the interface
\param[in] rsa RSA handle to operate.
\return none
*/
void csi_rsa_uninit(csi_rsa_t *rsa);
/**
\brief Attach the callback handler to RSA
\param[in] rsa Operate handle.
\param[in] cb Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_attach_callback(csi_rsa_t *rsa, csi_rsa_callback_t cb, void *arg);
/**
\brief Detach the callback handler
\param[in] rsa Operate handle.
*/
void csi_rsa_detach_callback(csi_rsa_t *rsa);
/**
\brief Generate rsa key pair.
\param[in] rsa RSA handle to operate.
\param[out] context Pointer to the rsa context
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_gen_key(csi_rsa_t *rsa, csi_rsa_context_t *context);
/**
\brief Encrypt
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[out] out Pointer to the result buffer
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_encrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out);
/**
\brief decrypt
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[out] out Pointer to the result buffer
\param[out] out_size The result size
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_decrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out, uint32_t *out_size);
/**
\brief RSA sign
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[out] signature Pointer to the signature
\param[in] hash_type The source data hash type
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_sign(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, csi_rsa_hash_type_t hash_type);
/**
\brief RSA verify
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[in] signature Pointer to the signature
\param[in] sig_size The signature size
\param[in] hash_type The source data hash type
\return Verify result
*/
bool csi_rsa_verify(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, uint32_t sig_size, csi_rsa_hash_type_t hash_type);
/**
\brief encrypt(async mode)
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[out] out Pointer to the result buffer
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_encrypt_async(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out);
/**
\brief decrypt(async mode)
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[out] out Pointer to the result buffer
\param[out] out_size The result size
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_decrypt_async(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out, uint32_t *out_size);
/**
\brief RSA sign(async mode)
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[out] signature Pointer to the signature
\param[in] hash_type The source data hash type
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_sign_async(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, csi_rsa_hash_type_t hash_type);
/**
\brief RSA verify(async mode)
\param[in] rsa RSA handle to operate.
\param[in] context Pointer to the rsa context
\param[in] src Pointer to the source data.
\param[in] src_size The source data len
\param[in] signature Pointer to the signature
\param[in] sig_size The signature size
\param[in] hash_type The source data hash type
\return Verify result
*/
csi_error_t csi_rsa_verify_async(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, uint32_t sig_size, csi_rsa_hash_type_t hash_type);
/**
\brief Get RSA state.
\param[in] rsa RSA handle to operate.
\param[out] state RSA state \ref csi_rsa_state_t.
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_get_state(csi_rsa_t *rsa, csi_rsa_state_t *state);
/**
\brief Get big prime data
\param[in] rsa RSA handle to operate.
\param[in] p Pointer to the prime
\param[in] bit_length Pointer to the prime bit length
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_get_prime(csi_rsa_t *rsa, void *p, uint32_t bit_length);
/**
\brief Enable rsa power manage
\param[in] rsa RSA handle to operate.
\return Error code \ref csi_error_t
*/
csi_error_t csi_rsa_enable_pm(csi_rsa_t *rsa);
/**
\brief Disable rsa power manage
\param[in] rsa RSA handle to operate.
*/
void csi_rsa_disable_pm(csi_rsa_t *rsa);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_RSA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/rsa.h | C | apache-2.0 | 9,368 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/rtc.h
* @brief Header File for RTC Driver
* @version V1.0
* @date 9. Oct 2020
* @model rtc
******************************************************************************/
#ifndef _DRV_RTC_H_
#define _DRV_RTC_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** RTC time ******/
typedef struct {
int tm_sec; ///< Second. [0-59]
int tm_min; ///< Minute. [0-59]
int tm_hour; ///< Hour. [0-23]
int tm_mday; ///< Day. [1-31]
int tm_mon; ///< Month. [0-11]
int tm_year; ///< Year-1900. [70- ] !NOTE:Set 100 mean 2000
int tm_wday; ///< Day of week. [0-6 ] !NOTE:Set 0 mean Sunday
int tm_yday; ///< Days in year.[0-365] !NOTE:Set 0 mean January 1st
} csi_rtc_time_t;
/****** definition for RTC ******/
typedef struct csi_rtc csi_rtc_t;
struct csi_rtc {
csi_dev_t dev;
void (*callback)(csi_rtc_t *rtc, void *arg);
void *arg;
void *priv;
};
/**
\brief Initialize RTC interface. Initializes the resources needed for the RTC interface
\param[in] rtc Handle to operate
\param[in] idx RTC index
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_init(csi_rtc_t *rtc, uint32_t idx);
/**
\brief De-initialize RTC interface. Stops operation and releases the software resources used by the interface
\param[in] rtc Handle to operate
\return None
*/
void csi_rtc_uninit(csi_rtc_t *rtc);
/**
\brief Set system date and wait for synchro
\param[in] rtc Handle to operate
\param[in] rtctime Pointer to RTC time
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_set_time(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime);
/**
\brief Set system date but no wait
\param[in] rtc Handle to operate
\param[in] rtctime Pointer to RTC time
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_set_time_no_wait(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime);
/**
\brief Get system date
\param[in] rtc Handle to operate
\param[out] rtctime Pointer to RTC time
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_get_time(csi_rtc_t *rtc, csi_rtc_time_t *rtctime);
/**
\brief Get alarm remaining time
\param[in] rtc Handle to operate
\return The remaining time(s)
*/
uint32_t csi_rtc_get_alarm_remaining_time(csi_rtc_t *rtc);
/**
\brief Config RTC alarm timer
\param[in] rtc Handle to operate
\param[in] rtctime Time to wake up
\param[in] callback Callback function
\param[in] arg Callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_set_alarm(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime, void *callback, void *arg);
/**
\brief Cancel the RTC alarm
\param[in] rtc Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_cancel_alarm(csi_rtc_t *rtc);
/**
\brief Judge RTC is running
\param[in] rtc Handle to operate
\return
true - RTC is running
false - RTC is not running
*/
bool csi_rtc_is_running(csi_rtc_t *rtc);
/**
\brief Enable RTC power manage
\param[in] rtc Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_rtc_enable_pm(csi_rtc_t *rtc);
/**
\brief Disable RTC power manage
\param[in] rtc Handle to operate
\return None
*/
void csi_rtc_disable_pm(csi_rtc_t *rtc);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_RTC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/rtc.h | C | apache-2.0 | 3,878 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/sasc.h
* @brief Header File for SASC driver
* @version V1.0
* @date 02. June 2020
* @model sasc
******************************************************************************/
#ifndef _DRV_SASC_H_
#define _DRV_SASC_H_
#include <stdint.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SASC_RW = 0,
SASC_RO = 1,
SASC_WO = 2,
SASC_AP_DENY = 3
} csi_sasc_ap_t;
typedef enum {
SASC_DI = 0,
SASC_DO = 1,
SASC_IO = 2,
SASC_DI_DENY = 3
} csi_sasc_di_t;
typedef enum {
SASC_RAM_4B = 5,
SASC_RAM_8B = 6,
SASC_RAM_16B = 7,
SASC_RAM_32B = 8,
SASC_RAM_64B = 9,
SASC_RAM_128B = 10,
SASC_RAM_256B = 11,
SASC_RAM_512B = 12,
SASC_RAM_1KB = 13,
SASC_RAM_2KB = 14,
SASC_RAM_4KB = 15,
SASC_RAM_8KB = 16,
SASC_RAM_16KB = 17,
SASC_RAM_32KB = 18,
SASC_RAM_64KB = 19,
SASC_RAM_128KB = 20,
} csi_sasc_ram_size_t;
typedef enum {
SASC_FLASH_1S = 0,
SASC_FLASH_2S,
SASC_FLASH_4S,
SASC_FLASH_8S,
SASC_FLASH_16S,
SASC_FLASH_32S,
SASC_FLASH_64S,
SASC_FLASH_128S,
SASC_FLASH_256S,
SASC_FLASH_512S,
SASC_FLASH_1024S,
SASC_FLASH_2048S
} csi_sasc_flash_size_t;
typedef struct {
csi_sasc_ap_t super_ap;
csi_sasc_ap_t user_ap;
csi_sasc_di_t super_di;
csi_sasc_di_t user_di;
bool is_secure;
} csi_sasc_attr_t;
/**
\brief Config the sasc ram region attribute.
\param[in] region_id Config region index
\param[in] base_addr Config region base address.
\param[in] size config region size.
\param[in] attr Region attr.
\return Error code
*/
csi_error_t csi_sasc_ram_config(uint8_t region_id, uint32_t base_addr, csi_sasc_ram_size_t size, csi_sasc_attr_t attr);
/**
\brief Config the sasc flash region attribute.
\param[in] region_id Config region index
\param[in] base_addr Config region base address.
\param[in] size Config region size.
\param[in] attr Region attr.
\return Error code
*/
csi_error_t csi_sasc_flash_config(uint8_t region_id, uint32_t base_addr, csi_sasc_flash_size_t size, csi_sasc_attr_t attr);
/**
\brief Enable sasc ram config.
\param[in] region_id Region index
\return error code
*/
csi_error_t csi_sasc_ram_enable(uint8_t region_id);
/**
\brief Enable sasc flash config
\param[in] region_id Config region index
\return error code
*/
csi_error_t csi_sasc_flash_enable(uint8_t region_id);
/**
\brief Disable sasc ram config.
\param[in] region_id Region index
\return error code
*/
csi_error_t csi_sasc_ram_disable(uint8_t region_id);
/**
\brief Disable sasc flash config
\param[in] region_id Region index
\return error code
*/
csi_error_t csi_sasc_flash_disable(uint8_t region_id);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SASC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/sasc.h | C | apache-2.0 | 3,071 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/sdif.h
* @brief Header File for SDIF Driver
* @version V1.0
* @date 28. June 2020
* @model sdif
******************************************************************************/
#ifndef _DRV_SDIF_H_
#define _DRV_SDIF_H_
#include <stdbool.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef void *sdif_handle_t;
/*! @brief Construct a status code value from a group and code number. */
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
/*! @brief Status group numbers. */
enum _status_groups {
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
};
/*! @brief Generic status return codes. */
enum _generic_status {
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*! Macro to change a value to a given size aligned value */
#define SDK_SIZEALIGN(var, alignbytes) \
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
///< #define assert(__e) ((void)0)
/*! @name Min/max macros */
#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
#define SDK_ALIGN(var, alignbytes) var
static inline uint32_t cpu_to_dma(uint32_t addr)
{
return addr;
}
static inline uint32_t *ptr_cpu_to_dma(uint32_t *addr)
{
return (uint32_t *)cpu_to_dma((uint32_t)addr);
}
typedef enum {
SDIF_ERROR_CMD_CRC_FAIL = (1), ///< Command response received (but CRC check failed)
SDIF_ERROR_DATA_CRC_FAIL, ///< Data block sent/received (CRC check failed)
SDIF_ERROR_CMD_RSP_TIMEOUT, ///< Command response timeout
SDIF_ERROR_DATA_TIMEOUT, ///< Data timeout
SDIF_ERROR_TX_UNDERRUN, ///< Transmit FIFO underrun
SDIF_ERROR_RX_OVERRUN, ///< Receive FIFO overrun
SDIF_ERROR_ADDR_MISALIGNED, ///< Misaligned address
SDIF_ERROR_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
SDIF_ERROR_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs
SDIF_ERROR_BAD_ERASE_PARAM, ///< An invalid selection for erase groups
SDIF_ERROR_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block
SDIF_ERROR_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
SDIF_ERROR_COM_CRC_FAILED, ///< CRC check of the previous command failed
SDIF_ERROR_ILLEGAL_CMD, ///< Command is not legal for the card state
SDIF_ERROR_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data
SDIF_ERROR_CC_ERR, ///< Internal card controller error
SDIF_ERROR_GENERAL_UNKNOWN_ERR, ///< General or unknown error
SDIF_ERROR_STREAM_READ_UNDERRUN, ///< The card could not sustain data reading in stream rmode
SDIF_ERROR_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode
SDIF_ERROR_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error
SDIF_ERROR_WP_ERASE_SKIP, ///< Only partial address space was erased
SDIF_ERROR_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC
SDIF_ERROR_ERASE_RESET, ///< Erase sequence was cleared before executing because an out
SDIF_ERROR_AKE_SEQ_ERR, ///< Error in sequence of authentication
SDIF_ERROR_INVALID_VOLTRANGE, ///< Error in case of invalid voltage range
SDIF_ERROR_ADDR_OUT_OF_RANGE, ///< Error when addressed block is out of range
SDIF_ERROR_REQUEST_NOT_APPLICABLE, ///< Error when command request is not applicable
SDIF_ERROR_UNSUPPORTED_FEATURE, ///< Error when feature is not insupported
} sdif_error_e;
/* Host controller capabilities flag mask */
typedef enum {
SDIF_SUPPORT_HIGH_SPEED = 0x1U, ///< Support high-speed
SDIF_SUPPORT_DMA_SPEED = 0x2U, ///< Support DMA
SDIF_SUPPORT_USPEND_RESUME = 0x4U, ///< Support suspend/resume
SDIF_SUPPORT_V330 = 0x8U, ///< Support voltage 3.3V
SDIF_SUPPORT_4BIT = 0x10U, ///< Support 4 bit mode
SDIF_SUPPORT_8BIT = 0x20U, ///< Support 8 bit mode
} sdif_capability_flag_e;
/* \brief define the internal DMA mode */
typedef enum {
SDIF_CHAIN_DMA_MODE = 0x01U, ///< one descriptor with one buffer,but one descriptor point to another
SDIF_DUAL_DMA_MODE = 0x02U, ///< dual mode is one descriptor with two buffer
} sdif_dma_mode_e;
/* The command type */
typedef enum {
SDIF_CARD_COMMAND_NORMAL = 0U, ///< Normal command
SDIF_CARD_COMMAND_SUSPEND = 1U, ///< Suspend command
SDIF_CARD_COMMAND_RESUME = 2U, ///< Resume command
SDIF_CARD_COMMAND_ABORT = 3U, ///< Abort command
} sdif_card_command_type_e;
/* The command response type */
typedef enum {
SDIF_CARD_RESPONSE_NONE = 0U, ///< Response type: none
SDIF_CARD_RESPONSE_R1 = 1U, ///< Response type: R1
SDIF_CARD_RESPONSE_R1b = 2U, ///< Response type: R1b
SDIF_CARD_RESPONSE_R2 = 3U, ///< Response type: R2
SDIF_CARD_RESPONSE_R3 = 4U, ///< Response type: R3
SDIF_CARD_RESPONSE_R4 = 5U, ///< Response type: R4
SDIF_CARD_RESPONSE_R5 = 6U, ///< Response type: R5
SDIF_CARD_RESPONSE_R5b = 7U, ///< Response type: R5b
SDIF_CARD_RESPONSE_R6 = 8U, ///< Response type: R6
SDIF_CARD_RESPONSE_R7 = 9U, ///< Response type: R7
} sdif_card_response_type_e;
/* \brief define the card bus width type */
typedef enum {
SDIF_BUS_1BIT_WIDTH = 0U, ///< 1bit bus width, 1bit mode and 4bit mode share one register bit
SDIF_BUS_4BIT_WIDTH = 1U, ///< 4bit mode mask
SDIF_BUS_8BIT_WIDTH = 2U, ///< support 8 bit mode
} sdif_bus_width_e;
/* \brief Defines the internal DMA configure structure. */
typedef struct {
bool enable_fix_burst_len; ///< fix burst len enable/disable flag,When set, the AHB will
///< use only SINGLE, INCR4, INCR8 or INCR16 during start of
///< normal burst transfers. When reset, the AHB will use SINGLE
///< and INCR burst transfer operations
sdif_dma_mode_e mode; ///< define the DMA mode */
uint32_t *dma_des_buffer_start_addr; ///< internal DMA descriptor start address
uint32_t dma_des_buffer_len; ///< internal DMA buffer descriptor buffer len ,user need to pay attention to the
///< dma descriptor buffer length if it is bigger enough for your transfer
uint8_t dma_dws_skip_len; ///< define the descriptor skip length ,the length between two descriptor
///< this field is special for dual DMA mode
} sdif_dma_config_t;
/* \brief sdif callback functions. */
typedef struct {
void (*card_inserted)(uint32_t idx, void *user_data); ///< card insert call back
void (*card_removed)(uint32_t idx, void *user_data); ///< card remove call back
void (*sdif_interrupt)(uint32_t idx, void *user_data); ///< SDIF card interrupt occurs
void (*dma_des_unavailable)(uint32_t idx, void *user_data);///< DMA descriptor unavailable
void (*command_reload)(uint32_t idx, void *user_data); ///< command buffer full,need re-load
void (*transfer_complete)(uint32_t idx,
void *state,
int32_t status,
void *user_data); ///<Transfer complete callback
} sdif_callback_t;
/* Card data descriptor */
typedef struct {
bool stream_transfer; ///< indicate this is a stream data transfer command
bool enable_auto_command12; ///< indicate if auto stop will send when data transfer over
bool enable_ignore_error; ///< indicate if enable ignore error when transfer data
uint32_t block_size; ///< Block size, take care when configure this parameter
uint32_t block_count; ///< Block count
uint32_t *rx_date_buffer; ///< data buffer to receive
const uint32_t *tx_data_buffer; ///< data buffer to transfer
} sdif_data_t;
/* Card command descriptor */
typedef struct {
uint32_t index; ///< Command index
uint32_t argument; ///< Command argument
uint32_t response[4U]; ///< Response for this command
uint32_t type; ///< define the command type
uint32_t response_type; ///< Command response type
uint32_t flags; ///< Cmd flags
uint32_t resopnse_error_flags; ///< response error flags, need to check the flags when receive the cmd response
} sdif_command_t;
/* Transfer state */
typedef struct {
sdif_data_t *data; ///< Data to transfer
sdif_command_t *command; ///< Command to send
} sdif_transfer_t;
/* Data structure to initialize the sdif */
typedef struct {
uint8_t response_timeout; ///< command response timeout value
uint32_t card_det_debounce_clock; ///< define the debounce clock count which will used in
/// card detect logic,typical value is 5-25ms
uint32_t endian_mode; ///< define endian mode ,this field is not used in this
/// module actually, keep for compatible with middleware
uint32_t data_timeout; ///< data timeout value
} sdif_config_t;
/*
* \brief SDIF capability information.
* Defines a structure to get the capability information of SDIF.
*/
typedef struct {
uint32_t sd_version; ///< support SD card/SDIF version
uint32_t mmc_version; ///< support emmc card version
uint32_t max_block_length; ///< Maximum block length united as byte
uint32_t max_block_count; ///< Maximum byte count can be transfered
uint32_t flags; ///< Capability flags to indicate the support information
} sdif_capability_t;
/**
\brief Initializes the SDIF according to the specified
\param[in] idx SDIF index
\param[in] callback Callback Structure pointer to contain all callback functions.
\param[in] user_data User_data Callback function parameter.
\return sdif Handle if success
*/
sdif_handle_t drv_sdif_initialize(uint32_t idx, sdif_callback_t *callback, void *user_data);
/**
\brief De-initialize SD Interface. stops operation and releases the software resources used by the interface
\param[in] handle SDIF handle to operate.
*/
void drv_sdif_uninitialize(uint32_t idx, sdif_handle_t handle);
/**
\brief Initializes the SDIF config
\param[in] idx SDIF index
\param[in] config SDIF config descriptor \ref sdif_config_t
*/
void drv_sdif_config(sdif_handle_t handle, sdif_config_t *config);
/**
\brief Get driver capabilities.
\param[in] handle SDIF handle to operate.
\param[out] capability SDIF capability information \ref sdif_capabilities_t
*/
void drv_sdif_get_capabilities(sdif_handle_t handle, sdif_capability_t *capability);
/**
\brief send command to the card
\param[in] handle SDIF handle to operate.
\param[in] cmd command configuration collection
\param[in] retries total number of tries
\return Error code
*/
int32_t drv_sdif_send_command(sdif_handle_t handle, sdif_command_t *cmd, uint32_t retries);
/**
\brief SDIF transfer function data/cmd in a non-blocking way
this API should be use in interrupt mode, when use this API user
must call drv_sdif_create_state first, all status check through
interrupt
\param[in] handle SDIF handle to operate.
\param[in] dma_config DMA config structure \ref sdif_dma_config_t
This parameter can be config as:
1. NULL
In this condition, polling transfer mode is selected
2. avaliable DMA config
In this condition, DMA transfer mode is selected
\param[in] transfer SDIF transfer configuration collection. \ref sdif_transfer_t
\return Error code
*/
int32_t drv_sdif_transfer(sdif_handle_t handle, sdif_dma_config_t *dma_config, sdif_transfer_t *transfer);
/**
\brief Poll-wait for the response to the last command to be ready. This
function should be called even after sending commands that have no
response (such as CMD0) to make sure that the hardware is ready to
receive the next command.
\param[in] handle SDIF handle to operate.
\param[in] cmd : The command that was sent. See 32-bit command definitions above.
*/
void drv_sdif_transfer_abort(sdif_handle_t handle);
/**
\brief Called after change in Bus width has been selected (via ACMD6). Most
controllers will need to perform some special operations to work
correctly in the new bus mode.
\param[in] handle SDIF handle to operate.
\param[in] bus_width Wide bus mode \ref sdif_bus_width_e.
*/
void drv_sdif_bus_width(sdif_handle_t handle, sdif_bus_width_e bus_width);
/**
\brief Set SDIF clocking
\param[in] Handle SDIF handle to operate.
\param[in] Target_hz card bus clock frequency united in Hz.
\return Error code
*/
uint32_t drv_sdif_set_clock(sdif_handle_t handle, uint32_t target_hz);
/**
\brief Get sdif handle
\param[in] Idx sdif index
\return SDIF handle
*/
sdif_handle_t drv_sdif_get_handle(uint32_t idx);
/**
\brief Get sdif index
\param[out] Handle SDIF handle to operate.
\return SDIF index
*/
uint32_t drv_sdif_get_idx(sdif_handle_t handle);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SDIF_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/sdif.h | C | apache-2.0 | 15,306 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file sensor.h
* @brief Header File for SENSOR Driver
* @version V1.0
* @date 15. June 2020
* @model sensor
******************************************************************************/
#ifndef _DRV_SENSOR_H_
#define _DRV_SENSOR_H_
#include <drv/common.h>
#include <soc.h>
typedef enum {
SENSOR_VDS_3V3_3V3 = 1,
SENSOR_VDS_2V5_3V3,
SENSOR_VDS_1V8_1V8,
SENSOR_VDS_1V5_1V8,
SENSOR_VDS_1V2_1V2,
SENSOR_VDS_1V1_1V2
}drv_sensor_vds_t;
typedef enum {
SENSOR_VHS_RANGE_15 = 0,
SENSOR_VHS_RANGE_12,
SENSOR_VHS_RANGE_9,
SENSOR_VHS_RANGE_6,
}drv_sensor_vhs_t;
typedef enum {
SENSOR_VLS_RANGE_6 = 0,
SENSOR_VLS_RANGE_9,
SENSOR_VLS_RANGE_12,
SENSOR_VLS_RANGE_15,
}drv_sensor_vls_t;
typedef enum {
SENSOR_TDHS_NEG_55 = 0, ///< -55
SENSOR_TDHS_NEG_50,
SENSOR_TDHS_NEG_45,
SENSOR_TDHS_NEG_40,
SENSOR_TDHS_NEG_35,
SENSOR_TDHS_NEG_30,
SENSOR_TDHS_NEG_25,
SENSOR_TDHS_NEG_20,
SENSOR_TDHS_NEG_15,
SENSOR_TDHS_NEG_10,
SENSOR_TDHS_NEG_5,
SENSOR_TDHS_NEG_0,
SENSOR_TDHS_POS_5, ///< +5
SENSOR_TDHS_POS_10,
SENSOR_TDHS_POS_15,
SENSOR_TDHS_POS_20,
SENSOR_TDHS_POS_25,
SENSOR_TDHS_POS_30,
SENSOR_TDHS_POS_35,
SENSOR_TDHS_POS_40,
SENSOR_TDHS_POS_45,
SENSOR_TDHS_POS_50,
SENSOR_TDHS_POS_55,
SENSOR_TDHS_POS_60,
SENSOR_TDHS_POS_65,
SENSOR_TDHS_POS_70,
SENSOR_TDHS_POS_75,
SENSOR_TDHS_POS_80,
SENSOR_TDHS_POS_85,
SENSOR_TDHS_POS_90,
SENSOR_TDHS_POS_95,
SENSOR_TDHS_POS_100,
SENSOR_TDHS_POS_105,
SENSOR_TDHS_POS_110,
SENSOR_TDHS_POS_115,
SENSOR_TDHS_POS_120,
SENSOR_TDHS_POS_125
}drv_sensor_tdhs_t;
typedef enum {
SENSOR_TDLS_NEG_55 = 0, ///< -55
SENSOR_TDLS_NEG_50,
SENSOR_TDLS_NEG_45,
SENSOR_TDLS_NEG_40,
SENSOR_TDLS_NEG_35,
SENSOR_TDLS_NEG_30,
SENSOR_TDLS_NEG_25,
SENSOR_TDLS_NEG_20,
SENSOR_TDLS_NEG_15,
SENSOR_TDLS_NEG_10,
SENSOR_TDLS_NEG_5,
SENSOR_TDLS_NEG_0,
SENSOR_TDLS_POS_5, ///< +5
SENSOR_TDLS_POS_10,
SENSOR_TDLS_POS_15,
SENSOR_TDLS_POS_20,
}drv_sensor_tdls_t;
typedef enum {
SENSOR_FHS_RANGE_50 = 0,
SENSOR_FHS_RANGE_30,
SENSOR_FHS_RANGE_10,
SENSOR_FHS_RANGE_5,
}drv_sensor_fhs_t;
typedef enum {
SENSOR_FLS_RANGE_50 = 0,
SENSOR_FLS_RANGE_30,
SENSOR_FLS_RANGE_10,
SENSOR_FLS_RANGE_5,
}drv_sensor_fls_t;
typedef enum {
SENSOR_FHS_FREQ_33M = 0,
SENSOR_FHS_FREQ_66M,
SENSOR_FHS_FREQ_24M,
SENSOR_FHS_FREQ_12M,
SENSOR_FHS_FREQ_99M,
SENSOR_FHS_FREQ_198M,
SENSOR_FHS_FREQ_72M,
SENSOR_FHS_FREQ_36M,
}drv_sensor_freq_t;
typedef enum {
SENSOR_WARN_H = 0,
SENSOR_WARN_L,
SENSOR_WARN_RST,
}drv_sensor_warn_t;
/**
\brief Initialize Sensor VD
\param[in] vds Voltage range
\param[in] vhs Voltage high threshold
\param[in] vls Voltage low threshold
\param[in] vtm Used to modify the threshold value of the voltage detection point
\return Error code
*/
csi_error_t drv_sensor_vd_init(drv_sensor_vds_t vds,drv_sensor_vhs_t vhs,drv_sensor_vls_t vls,uint8_t vtm);
/**
\brief Get vd warn
\param[in] warn Vd warn select
\return Vd warn code
*/
uint32_t drv_sensor_vd_get_warn(drv_sensor_warn_t warn);
/**
\brief Initialize Sensor td
\param[in] hs Temp high threshold
\param[in] ls Temp low threshold
\return Error code
*/
csi_error_t drv_sensor_td_init(drv_sensor_tdhs_t hs,drv_sensor_tdls_t ls);
/**
\brief Get td warn
\param[in] warn Td warn select
\return Td warn code
*/
uint32_t drv_sensor_td_get_warn(drv_sensor_warn_t warn);
/**
\brief Initialize Sensor FD
\param[in] hs Temp high threshold
\param[in] ls Temp low threshold
\return Error code
*/
csi_error_t drv_sensor_fd_init(drv_sensor_freq_t freq,drv_sensor_fhs_t fhs,drv_sensor_fls_t fls);
/**
\brief Get fd warn
\param[in] warn Fd warn select
\return FD warn code
*/
uint32_t drv_sensor_fd_get_warn(drv_sensor_warn_t warn);
#endif /* _DRV_SENSOR_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/sensor.h | C | apache-2.0 | 4,286 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/sha.h
* @brief Header File for SHA Driver
* @version V1.0
* @date 9. Oct 2020
* @model sha
******************************************************************************/
#ifndef _DRV_SHA_H_
#define _DRV_SHA_H_
#include <drv/common.h>
#include <drv/dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** SHA mode ******/
typedef enum {
SHA_MODE_1 = 1U, ///< SHA_1 mode
SHA_MODE_256, ///< SHA_256 mode
SHA_MODE_224, ///< SHA_224 mode
SHA_MODE_512, ///< SHA_512 mode
SHA_MODE_384, ///< SHA_384 mode
SHA_MODE_512_256, ///< SHA_512_256 mode
SHA_MODE_512_224 ///< SHA_512_224 mode
} csi_sha_mode_t;
/****** SHA State ******/
typedef struct {
uint32_t busy : 1; ///< Calculate busy flag
uint32_t error : 1; ///< Calculate error flag
} csi_sha_state_t;
typedef struct {
csi_sha_mode_t mode; ///< SHA mode
uint32_t total[2]; ///< Number of bytes processed
uint32_t state[16]; ///< Intermediate digest state
uint8_t buffer[128]; ///< Data block being processed
} csi_sha_context_t;
/****** SHA Event ******/
typedef enum {
SHA_EVENT_COMPLETE = 0U, ///< Calculate completed
SHA_EVENT_ERROR ///< Calculate error
} csi_sha_event_t;
typedef struct csi_sha csi_sha_t;
struct csi_sha {
csi_dev_t dev; ///< SHA hw-device info
void (*callback)(csi_sha_t *sha, csi_sha_event_t event, void *arg); ///< SHA event callback for user
void *arg; ///< SHA custom designed param passed to evt_cb
csi_dma_ch_t *dma_in; ///< SHA in dma handle param
csi_sha_state_t state; ///< SHA state
void *priv;
};
/**
\brief Initialize SHA Interface. Initializes the resources needed for the SHA interface
\param[in] sha Operate handle
\param[in] idx Index of SHA
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_init(csi_sha_t *sha, uint32_t idx);
/**
\brief De-initialize SHA Interface. Stops operation and releases the software resources used by the interface
\param[in] sha SHA handle to operate
\return None
*/
void csi_sha_uninit(csi_sha_t *sha);
/**
\brief Attach the callback handler to SHA
\param[in] sha Handle to operate
\param[in] callback Callback function
\param[in] arg Callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_attach_callback(csi_sha_t *sha, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] sha Handle to operate
\return None
*/
void csi_sha_detach_callback(csi_sha_t *sha);
/**
\brief Start the engine
\param[in] sha Handle to operate
\param[in] context Pointer to the SHA context \ref csi_sha_context_t
\param[in] mode SHA mode \ref csi_sha_mode_t
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_start(csi_sha_t *sha, csi_sha_context_t *context, csi_sha_mode_t mode);
/**
\brief Update the engine
\param[in] sha Handle to operate
\param[in] context Pointer to the SHA context \ref csi_sha_context_t
\param[in] input Pointer to the Source data
\param[in] size The data size
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_update(csi_sha_t *sha, csi_sha_context_t *context, const void *input, uint32_t size);
/**
\brief Accumulate the engine (async mode)
\param[in] sha Handle to operate
\param[in] context Pointer to the SHA context \ref csi_sha_context_t
\param[in] input Pointer to the Source data
\param[in] size The data size
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_update_async(csi_sha_t *sha, csi_sha_context_t *context, const void *input, uint32_t size);
/**
\brief Finish the engine
\param[in] sha Handle to operate
\param[in] context Pointer to the SHA context \ref csi_sha_context_t
\param[out] output Pointer to the result data
\param[out] out_size Pointer to the result data size(bytes)
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_finish(csi_sha_t *sha, csi_sha_context_t *context, void *output, uint32_t *out_size);
/**
\brief Get SHA state
\param[in] sha Handle to operate
\param[out] state SHA state \ref csi_sha_state_t
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_get_state(csi_sha_t *sha, csi_sha_state_t *state);
/**
\brief Enable SHA power manage
\param[in] sha Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_sha_enable_pm(csi_sha_t *sha);
/**
\brief Disable SHA power manage
\param[in] sha Handle to operate
\return None
*/
void csi_sha_disable_pm(csi_sha_t *sha);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SHA_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/sha.h | C | apache-2.0 | 5,500 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/spi.h
* @brief Header File for SPI Driver
* @version V1.0
* @date 08. Apr 2020
* @model spi
******************************************************************************/
#ifndef _DRV_SPI_H_
#define _DRV_SPI_H_
#include <stdint.h>
#include <drv/common.h>
#include <drv/gpio.h>
#include <drv/dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \enum csi_spi_mode_t
* \brief Function mode of spi
*/
typedef enum {
SPI_MASTER, ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
SPI_SLAVE, ///< SPI Slave (Output on MISO, Input on MOSI)
} csi_spi_mode_t;
/**
* \enum csi_spi_frame_len_t
* \brief SPI data width (4bit ~ 16bit)
*/
typedef enum {
SPI_FRAME_LEN_4 = 4,
SPI_FRAME_LEN_5,
SPI_FRAME_LEN_6,
SPI_FRAME_LEN_7,
SPI_FRAME_LEN_8,
SPI_FRAME_LEN_9,
SPI_FRAME_LEN_10,
SPI_FRAME_LEN_11,
SPI_FRAME_LEN_12,
SPI_FRAME_LEN_13,
SPI_FRAME_LEN_14,
SPI_FRAME_LEN_15,
SPI_FRAME_LEN_16
} csi_spi_frame_len_t;
/**
* \enum csi_spi_format_t
* \brief Timing format of spi
*/
typedef enum {
SPI_FORMAT_CPOL0_CPHA0 = 0, ///< Clock Polarity 0, Clock Phase 0
SPI_FORMAT_CPOL0_CPHA1, ///< Clock Polarity 0, Clock Phase 1
SPI_FORMAT_CPOL1_CPHA0, ///< Clock Polarity 1, Clock Phase 0
SPI_FORMAT_CPOL1_CPHA1, ///< Clock Polarity 1, Clock Phase 1
} csi_spi_cp_format_t;
/**
* \enum csi_spi_event_t
* \brief Signaled event for user by driver
*/
typedef enum {
SPI_EVENT_SEND_COMPLETE, ///< Data Send completed. Occurs after call to csi_spi_send_async to indicate that all the data has been send over
SPI_EVENT_RECEIVE_COMPLETE, ///< Data Receive completed. Occurs after call to csi_spi_receive_async to indicate that all the data has been received
SPI_EVENT_SEND_RECEIVE_COMPLETE, ///< Data Send_receive completed. Occurs after call to csi_spi_send_receive_async to indicate that all the data has been send_received
SPI_EVENT_ERROR_OVERFLOW, ///< Data overflow: Receive overflow
SPI_EVENT_ERROR_UNDERFLOW, ///< Data underflow: Transmit underflow
SPI_EVENT_ERROR ///< Master Mode Fault (SS deactivated when Master).Occurs in master mode when Slave Select is deactivated and indicates Master Mode Fault
} csi_spi_event_t;
/**
* \struct csi_spi_t
* \brief Ctrl block of spi instance
*/
typedef struct csi_spi csi_spi_t;
struct csi_spi {
csi_dev_t dev; ///< Hw-device info
void (*callback)(csi_spi_t *spi, csi_spi_event_t event, void *arg); ///< User callback ,signaled by driver event
void *arg; ///< User private param ,passed to user callback
uint8_t *tx_data; ///< Output data buf
uint32_t tx_size; ///< Output data size specified by user
uint8_t *rx_data; ///< Input data buf
uint32_t rx_size; ///< Input data size specified by user
csi_error_t (*send)(csi_spi_t *spi, const void *data, uint32_t size); ///< The send_async func
csi_error_t (*receive)(csi_spi_t *spi, void *data, uint32_t size); ///< The receive_async func
csi_error_t (*send_receive)(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); ///< The send_receive_async func
csi_state_t state; ///< Peripheral state
csi_dma_ch_t *tx_dma;
csi_dma_ch_t *rx_dma;
void *priv;
};
/**
\brief Initialize SPI Interface
Initialize the resources needed for the SPI instance
\param[in] spi SPI handle
\param[in] idx SPI instance index
\return Error code
*/
csi_error_t csi_spi_init(csi_spi_t *spi, uint32_t idx);
/**
\brief De-initialize SPI Interface
stops Operation and releases the software resources used by the spi instance
\param[in] spi Handle
\return None
*/
void csi_spi_uninit(csi_spi_t *spi);
/**
\brief Attach the callback handler to SPI
\param[in] spi Operate handle
\param[in] callback Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code
*/
csi_error_t csi_spi_attach_callback(csi_spi_t *spi, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] spi Operate handle
\return None
*/
void csi_spi_detach_callback(csi_spi_t *spi);
/**
\brief Config spi mode (master or slave)
\param[in] spi SPI handle
\param[in] mode The mode of spi (master or slave)
\return Error code
*/
csi_error_t csi_spi_mode(csi_spi_t *spi, csi_spi_mode_t mode);
/**
\brief Config spi cp format
\param[in] spi SPI handle
\param[in] format SPI cp format
\return Error code
*/
csi_error_t csi_spi_cp_format(csi_spi_t *spi, csi_spi_cp_format_t format);
/**
\brief Config spi frame len
\param[in] spi SPI handle
\param[in] length SPI frame len
\return Error code
*/
csi_error_t csi_spi_frame_len(csi_spi_t *spi, csi_spi_frame_len_t length);
/**
\brief Config spi work frequence
\param[in] spi SPI handle
\param[in] baud SPI work baud
\return the actual config frequency
*/
uint32_t csi_spi_baud(csi_spi_t *spi, uint32_t baud);
/**
\brief Sending data to SPI transmitter,(received data is ignored)
blocking mode ,return unti all data has been sent or err happened
\param[in] spi Handle to operate
\param[in] data Pointer to buffer with data to send to SPI transmitter
\param[in] size Number of data to send(byte)
\param[in] timeout Unit in mini-second
\return If send successful, this function shall return the num of data witch is sent successful
otherwise, the function shall return Error code
*/
int32_t csi_spi_send(csi_spi_t *spi, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Sending data to SPI transmitter,(received data is ignored)
non-blocking mode,transfer done event will be signaled by driver
\param[in] spi Handle to operate
\param[in] data Pointer to buffer with data to send to SPI transmitter
\param[in] size Number of data items to send(byte)
\return Error code
*/
csi_error_t csi_spi_send_async(csi_spi_t *spi, const void *data, uint32_t size);
/**
\brief Receiving data from SPI receiver
blocking mode, return untill curtain data items are readed
\param[in] spi Handle to operate
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] size Number of data items to receive(byte)
\param[in] timeout Unit in mini-second
\return If receive successful, this function shall return the num of data witch is received successful
otherwise, the function shall return Error code
*/
int32_t csi_spi_receive(csi_spi_t *spi, void *data, uint32_t size, uint32_t timeout);
/**
\brief Receiving data from SPI receiver
not-blocking mode, event will be signaled when receive done or err happend
\param[in] spi Handle to operate
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] size Number of data items to receive(byte)
\return Error code
*/
csi_error_t csi_spi_receive_async(csi_spi_t *spi, void *data, uint32_t size);
/**
\brief Dulplex,sending and receiving data at the same time
\ref csi_spi_event_t is signaled when operation completes or error happens
\ref csi_spi_get_state can get operation status
blocking mode, this function returns after operation completes or error happens
\param[in] spi SPI handle to operate
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] size Data size(byte)
\return If transfer successful, this function shall return the num of data witch is transfer successful,
otherwise, the function shall return Error code
*/
int32_t csi_spi_send_receive(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size, uint32_t timeout);
/**
\brief Transmit first then receive ,receive will begin after transmit is done
if non-blocking mode, this function only starts the transfer,
\ref csi_spi_event_t is signaled when operation completes or error happens
\ref csi_spi_get_state can get operation status
\param[in] spi SPI handle to operate
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] size Data size(byte)
\return Error code
*/
csi_error_t csi_spi_send_receive_async(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size);
/*
\brief Set slave select num. Only valid for master
\param[in] handle SPI handle to operate
\param[in] slave_num SPI slave num
\return None
*/
void csi_spi_select_slave(csi_spi_t *spi, uint32_t slave_num);
/**
\brief Link DMA channel to spi device
\param[in] spi SPI handle to operate
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel
\return Error code
*/
csi_error_t csi_spi_link_dma(csi_spi_t *spi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get the state of spi device
\param[in] spi SPI handle to operate
\param[out] state The state of spi device
\return Error code
*/
csi_error_t csi_spi_get_state(csi_spi_t *spi, csi_state_t *state);
/**
\brief Enable spi power manage
\param[in] spi SPI handle to operate
\return Error code
*/
csi_error_t csi_spi_enable_pm(csi_spi_t *spi);
/**
\brief Disable spi power manage
\param[in] spi SPI handle to operate
\return Error code
*/
void csi_spi_disable_pm(csi_spi_t *spi);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SPI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/spi.h | C | apache-2.0 | 10,605 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/spiflash.h
* @brief Header File for SPIFLASH Driver
* @version V1.0
* @date 02. June 2020
* @model spiflash
******************************************************************************/
#ifndef _DRV_SPIFLASH_H_
#define _DRV_SPIFLASH_H_
#include <stdint.h>
#include <drv/gpio.h>
#include <drv/spi.h>
#include <drv/qspi.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Build a flash ID
* \param [in] vendor_id Vendor id(8bit)
* \param [in] device_id Flash device id (ID15~ID0) 16bit
* \return 24bit flash id
*/
#define FLASH_ID_BUILD(VENDOR_ID,DEVICE_ID)
/**
* \struct csi_spiflash_lock_info_t
* \ flash use status register 1 to protect data in memory array
* \ different flash vendor support different protect region (top/bottom/none)
* also support different protect number
* status1 register bif field show as follow
* 7 |6 |5 |4 |3 |2 |1 |0
* ---------------------------------------------------------------------
* vensor def | vendor def | vendor def | BP2 | BP1 | BP0 | WEL | BUSY
* \ Protect type
* \ Protect block size : Vendor define ,user should check flash datasheet of vendor
* : Use w25q64fw as example , min protect block size is 128 KB
* \ TOP : Protect address from flash top address
* \ BOTTOM : Protect address from flash bottom address
* \ SEC : Protect addres base on sector unit and protect region only must not exceed one block
* \ BPx : Protect start addres base on TOP/BOTTOM feature,and BPx value denote protect number
* \ BP[x..0]'s value : 2^(n-1) protect block unit, ex, BP[x..0] = 5, protect block number = 2^(5-1) = 16
* \ If BP[x..0] = 0 denote protect none
* \ If BP[x..0]'s all bis is 1 ,denote protect all flash
* \
* \ NOTE:
* \ only support SEC = 0
* \ only support CMP = 0
* \
*
* Sample table portion for 8MB flash (Winbond w25q64fw):
*
* SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
* --------------------------------------------------------------------------
* X | X | 0 | 0 | 0 | NONE | NONE
* 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
* 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
* 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
* 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
* 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
* 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
* X | X | 1 | 1 | 1 | 8 MB | ALL
* ------|-------|-------|-------|-------|---------------|-------------------
* 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
* 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
* 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
* 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
* 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
* 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
*
*/
typedef enum {
LOCK_TP_NONE,
LOCK_TP_TOP,
LOCK_TP_BOTTOM,
LOCK_TP_DUAL
} csi_spiflash_lock_region_t;
typedef enum {
SPIFLASH_DATA_1_LINE = 1,
SPIFLASH_DATA_2_LINES = 2,
SPIFLASH_DATA_4_LINES = 4
} csi_spiflash_data_line_t;
typedef union {
csi_spi_t spi;
csi_qspi_t qspi;
} csi_spi_qspi_t;
/**
\brief Flash information
*/
typedef struct {
char *flash_name; ///< Name string of spiflash
uint32_t flash_id; ///< JEDEC ID = manufature ID <<16 | device ID (ID15~ID0)
uint32_t flash_size; ///< Flash chip size
uint32_t xip_addr; ///< If use qspi controler to access flash ,code can be ececuted on flash ,the addr is xip addr
uint32_t sector_size; ///< Sector size
uint32_t page_size; ///< Page size for read or program
} csi_spiflash_info_t;
typedef struct{
struct{
uint8_t buswidth; ///< cmd buswidth
}cmd;
struct {
uint8_t buswidth; ///< addr buswidth
}addr;
struct {
uint8_t nbytes; ///< dummy bytes
}dummy;
struct {
uint8_t buswidth; ///< data buswidth
}data;
} csi_spiflash_cmd_t;
/**
\brief Flash control block
*/
typedef struct {
csi_spi_qspi_t spi_qspi; ///< Spi/qspi handle
void (*spi_cs_callback)(csi_gpio_pin_state_t value);
void *flash_prv_info; ///< Point to vendor private feature struct
int32_t (*spi_send)(void *spi, uint8_t cmd, uint32_t addr, uint32_t addr_size, const void *data, uint32_t size);
int32_t (*spi_receive)(void *spi, uint8_t cmd, uint32_t addr, uint32_t addr_size, void *data, uint32_t size);
csi_error_t (*set_cmd)(void *spi, csi_spiflash_cmd_t *cmd);
void *priv; ///< User private param
} csi_spiflash_t;
/**
\brief Initialize SPIFLASH with spi controler and probe flash device
\param[in] spiflash SPIFLASH handle
\param[in] spi_idx SPI controler index
\param[in] spi_cs GPIO info for chip select,if NULL, not use gpio cs
\return Error code
*/
csi_error_t csi_spiflash_spi_init(csi_spiflash_t *spiflash, uint32_t spi_idx, void *spi_cs_callback);
/**
\brief Initialize SPIFLASH with qspi controler and probe flash device
\param[in] spiflash SPIFLASH handle
\param[in] qspi_idx QSPI controler index
\return Error code
*/
csi_error_t csi_spiflash_qspi_init(csi_spiflash_t *spiflash, uint32_t qspi_idx, void *qspi_cs_callback);
/**
\brief De-initialize SPIFLASH Interface based on spi controler. stops operation and releases the software resources used by the interface
\param[in] spiflash SPIFLASH handle to operate
\return Error code
*/
void csi_spiflash_spi_uninit(csi_spiflash_t *spiflash);
/**
\brief De-initialize SPIFLASH Interface based on qspi controler. stops operation and releases the software resources used by the interface
\param[in] spiflash SPIFLASH handle to operate
\return Error code
*/
void csi_spiflash_qspi_uninit(csi_spiflash_t *spiflash);
/**
\brief Get flash device infomation
\param[in] spiflash SPIFLASH handle to operate
\param[in] flash_info User storage to get flash vendor info after flash init
\return spiflash_info_t
*/
csi_error_t csi_spiflash_get_flash_info(csi_spiflash_t *spiflash, csi_spiflash_info_t *flash_info);
/**
\brief Read data from Flash
\param[in] spiflash SPIFLASH handle to operate
\param[in] offset Data address, offset address relative to zero
\param[out] data Pointer to a buffer storing the data read from Flash
\param[in] size Number of data items to read
\return If receive successful, this function shall return the num of data witch is received successful
otherwise, the function shall return Error code
*/
int32_t csi_spiflash_read(csi_spiflash_t *spiflash, uint32_t offset, void *data, uint32_t size);
/**
\brief Program data to Flash
\param[in] spiflash SPIFLASH handle to operate
\param[in] offset Data address, offset address relative to zero
\param[in] data Pointer to a buffer containing the data to be programmed to Flash.
\param[in] size Number of data items to program
\return If program successful, this function shall return the num of data witch is program successful,
otherwise, the function shall return Error code
*/
int32_t csi_spiflash_program(csi_spiflash_t *spiflash, uint32_t offset, const void *data, uint32_t size);
/**
\brief Erase Flash Sector
\param[in] spiflash SPIFLASH handle to operate
\param[in] offset Data address, offset address relative to zero
\param[in] size Length to be erased
\return Error code
*/
csi_error_t csi_spiflash_erase(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size);
/**
\brief Read flash status register
\param[in] spiflash SPIFLASH handle to operate
\param[in] cmd_code Cmd code
\param[out] data Data buf to save flash status register
\param[in] size Register length in byte
\return Error code
*/
csi_error_t csi_spiflash_read_reg(csi_spiflash_t *spiflash, uint8_t cmd_code, uint8_t *data, uint32_t size);
/**
\brief Write status register
\param[in] spiflash SPIFLASH handle to operate
\param[in] cmd Cmd code
\param[out] data Data buf to save flash status register
\param[in] size Register length in byte
\return Error code
*/
csi_error_t csi_spiflash_write_reg(csi_spiflash_t *spiflash, uint8_t cmd_code, uint8_t *data, uint32_t size);
/**
\brief Enable spiflash write protection
\param[in] spiflash SPIFLASH handle to operate
\param[in] offset Protect flash offset,offset need protect block size aligned
\param[in] size Lock size(byte)
\return Error code
*/
csi_error_t csi_spiflash_lock(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size);
/**
\brief Enable spiflash write protection
\param[in] spiflash SPIFLASH handle to operate
\param[in] offset Protect flash offset,offset need protect block size aligned
\param[in] size Unlock size(byte)
\return Error code
*/
csi_error_t csi_spiflash_unlock(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size);
/**
\brief check flash is locked(write protect)
\param[in] spiflash SPIFLASH handle to operate
\param[in] offset Protect flash offset,offset need protect block size aligned
\param[in] size Locked size(byte)
\return 0:unlocked if query region overlay with locked region 1: locked if query reigon is fully in locked region
*/
int csi_spiflash_is_locked(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size);
/**
\brief Set QSPI data line
\param[in] spiflash SPIFLASH handle to operate
\param[in] line SPIFLASH data line mode
\return Error code
*/
csi_error_t csi_spiflash_config_data_line(csi_spiflash_t *spiflash, csi_spiflash_data_line_t line);
/**
\brief Set QSPI frequence
\param[in] spiflash SPIFLASH handle to operate
\param[in] hz SPIFLASH frequence
\return The actual config frequency
*/
uint32_t csi_spiflash_frequence(csi_spiflash_t *spiflash, uint32_t hz);
/**
\brief Flash power down.
\param[in] spiflash SPIFLASH handle to operate.
\return error code
*/
csi_error_t csi_spiflash_release_power_down(csi_spiflash_t *spiflash);
/**
\brief Flash power release.
\param[in] spiflash SPIFLASH handle to operate.
\return none
*/
void csi_spiflash_power_down(csi_spiflash_t *spiflash);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SPIFLASH_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/spiflash.h | C | apache-2.0 | 11,246 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/tee.h
* @brief Header File for TEE Driver
* @version V1.0
* @date 12 Sep 2020
* @model tee
******************************************************************************/
#ifndef _DRV_TEE_H_
#define _DRV_TEE_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/****** TEE AES mode *****/
typedef enum {
TEE_AES_MODE_ECB = 0, ///< TEE AES ECB mode
TEE_AES_MODE_CBC = 1, ///< TEE AES CBC mode
TEE_AES_MODE_MAX, ///< invaild mode
}
tee_aes_mode_e;
/**
\brief TEE AES encrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to ciphertext buffer
\param[in] mode \ref tee_aes_mode_e
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_aes_encrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t iv[16],
uint8_t *out,
tee_aes_mode_e mode);
/**
\brief TEE AES decrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\param[in] mode \ref tee_aes_mode_e
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_aes_decrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t iv[16],
uint8_t *out,
uint32_t mode);
/**
\brief TEE AES ECB encrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to ciphertext buffer
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_aes_encrypt_ecb(in, in_len, key, key_len, out) \
csi_tee_aes_encrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB)
/**
\brief TEE AES ECB decrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_aes_decrypt_ecb(in, in_len, key, key_len, out) \
csi_tee_aes_decrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB)
/**
\brief TEE AES CBC encrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_aes_encrypt_cbc(in, in_len, key, key_len, iv, out) \
csi_tee_aes_encrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC)
/**
\brief TEE AES CBC decrypt
\note Length should be a multiple of the block size (16 bytes)
After calling this function, the content of iv is updated.
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to secret key
\param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256
\param[out] out Pointer to plaintext buffer
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_aes_decrypt_cbc(in, in_len, key, key_len, iv, out) \
csi_tee_aes_decrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC)
/**
\brief TEE BASE64 encode/decode
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len Output data buffer length
\param[in] is_encode 1 encode 0 decode
\param[in] wsafe Base64 websafe feature,set 1, replace "+/" with "-_"
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_base64(const uint8_t *in, uint32_t in_len,
uint8_t *out, uint32_t *out_len,
uint32_t is_encode,
uint32_t wsafe);
/**
\brief TEE BASE64 encode
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len Output data buffer length
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_base64_encode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,1,0)
/**
\brief TEE BASE64 decode
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len Output data buffer length
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_base64_decode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,0,0)
/**
\brief TEE BASE64 web safe encode
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len Output data buffer length
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_base64_websafe_encode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,1,1)
/**
\brief TEE BASE64 web safe decode
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output data buffer
\param[out] out_len Output data buffer length
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_base64_websafe_decode(in,in_len,out,out_len) \
csi_tee_base64(in,in_len,out,out_len,0,1)
/**
\brief TEE obtain CID from Key Provisioning
\param[out] out Pointer to cid buffer
\param[out] out_len CID buffer length,if cid obtain successfully,
out_len is updated to actual cid sizes
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_get_cid(uint8_t *out, uint32_t *out_len);
/****** lpm mode *****/
typedef enum {
TEE_LPM_MODE_WAIT = 0, ///< lpm wait
TEE_LPM_MODE_DOZE = 1, ///< lpm doze
TEE_LPM_MODE_STOP = 2, ///< lpm stop
TEE_LPM_MODE_STANDBY = 3, ///< lpm standby
TEE_LPM_MODE_CLOCK = 4, ///< lpm clock gate
TEE_LPM_MODE_MAX,
} tee_lpm_mode_e;
/**
\brief TEE set low power mode
\param[in] gate Not use for now
\param[in] irqid Not use for now
\param[in] mode \ref tee_lpm_mode_e
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_enter_lpm(uint32_t gate, uint32_t irqid, tee_lpm_mode_e mode);
/**
\brief TEE obtain manifest info from manifest table
\note call csi_tee_get_sys_img_info, csi_tee_get_sys_os_version or csi_tee_get_sys_partition is better
\param[out] out Pointer to info buffer
\param[out] out_len Info buffer length,if info obtain successfully,
out_len is updated to actual sizes
\param[in] name info name
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_get_manifest_info(uint8_t *out, uint32_t *out_len, char *name);
/**
\brief TEE obtain image buffer from manifest table
\param[out] out Pointer to image buffer
\param[out] out_len Image buffer length,if info obtain successfully,
out_len is updated to actual image buffer sizes
\param[in] img_name Image name
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_get_sys_img_info(out,out_len,img_name) \
csi_tee_get_manifest_info(out,out_len,img_name)
/**
\brief TEE obtain os version from manifest table
\param[out] out Pointer to os version buffer
\param[out] out_len OS version buffer length,if info obtain successfully,
out_len is updated to actual os version buffer sizes
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_get_sys_os_version(out,out_len) \
csi_tee_get_manifest_info(out,out_len,"os_v")
/**
\brief TEE obtain partition buffer from manifest table
\param[out] out Pointer to partition buffer
\param[out] out_len Partition buffer length,if info obtain successfully,
out_len is updated to actual partition buffer sizes
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_get_sys_partition(out,out_len) \
csi_tee_get_manifest_info(out,out_len,"sys_p")
/**
\brief TEE set random seed
\param[in] Seed random sedd
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_rand_seed(uint32_t seed);
/**
\brief TEE ramdom date generation
\param[out] out Pointer to random data buffer
\param[in] out_len Data buffer length
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_rand_generate(uint8_t *out, uint32_t out_len);
/****** TEE RSA sign type *****/
typedef enum {
TEE_RSA_MD5 = 0, ///< MD5
TEE_RSA_SHA1 = 1, ///< SHA1
TEE_RSA_SHA256 = 3, ///< SHA256
TEE_RSA_SIGN_TYPE_MAX, ///< invailed type
} tee_rsa_sign_type_e;
/**
\brief TEE RSA sign with private key
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] key Pointer to private key,key contains n, e, d
\param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048
\param[out] sign Pointer to sign buffer
\param[out] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_rsa_sign(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *sign, uint32_t *sign_len,
tee_rsa_sign_type_e type);
/**
\brief TEE RSA verify with public key
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] key Pointer to public key,key contains n, e
\param[in] key_len Public key size,must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048
\param[in] sign Pointer to sign buffer
\param[in] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return Return 0 if verify successful,otherwise error code
*/
int32_t csi_tee_rsa_verify(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *sign, uint32_t sign_len,
tee_rsa_sign_type_e type);
/****** TEE RSA padding mode *****/
typedef enum {
TEE_RSA_PKCS1_PADDING = 0x01, ///< RSA PKCS padding mode
TEE_RSA_NO_PADDING = 0x02, ///< RSA no padding mode
} tee_rsa_padding_mode_e;
/**
\brief TEE RSA encrypt with public key
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] key Pointer to public key,key contains n, e
\param[in] key_len Public key size, must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048
\param[in] out Pointer to ciphertext buffer
\param[in] out_len Ciphertext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_rsa_encrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *out, uint32_t *out_len,
tee_rsa_padding_mode_e padding);
/**
\brief TEE RSA decrypt with private key
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to private key,key contains n, e, d
\param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048
\param[in] out Pointer to plaintext buffer
\param[in] out_len Plaintext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_rsa_decrypt(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *out, uint32_t *out_len,
tee_rsa_padding_mode_e padding);
/**
\brief TEE RSA sign with internal private key
\note Only use if key provisioning exist
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[out] sign Pointer to sign buffer
\param[out] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_cid_rsa_sign(in,in_len,sign,sign_len,type) \
csi_tee_rsa_sign(in,in_len,NULL,0,sign,sign_len,type)
/**
\brief TEE RSA verify with internal public key
\note Only use if key provisioning exist
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] sign Pointer to sign buffer
\param[in] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return Return 0 if verify successful,otherwise error code
*/
#define csi_tee_cid_rsa_verify(in,in_len,sign,sign_len,type) \
csi_tee_rsa_verify(in,in_len,NULL,0,sign,sign_len,type)
/**
\brief TEE RSA encrypt with internal public key
\note Only use if key provisioning exist
\param[in] in Pointer to plaintext buffer
\param[in] in_len Plaintext buffer length
\param[in] out Pointer to ciphertext buffer
\param[in] out_len Ciphertext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_cid_rsa_encrypt(in,in_len,out,out_len,padding) \
csi_tee_rsa_encrypt(in,in_len,NULL,0,out,out_len,padding)
/**
\brief TEE RSA decrypt with internal private key
\note Only use if key provisioning exist
\param[in] in Pointer to ciphertext buffer
\param[in] in_len Ciphertext buffer length
\param[in] key Pointer to private key,key contains n, e, d
\param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048
\param[in] out Pointer to plaintext buffer
\param[in] out_len Plaintext buffer length
\param[in] padding \ref tee_rsa_padding_mode_e
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_cid_rsa_decrypt(in,in_len,out,out_len,padding) \
csi_tee_rsa_decrypt(in,in_len,NULL,0,out,out_len,padding)
/**
\brief verify boot image with boot public key
\note Only use if key provisioning exist
\param[in] in Pointer to digest buffer
\param[in] in_len Digest buffer length
\param[in] sign Pointer to sign buffer
\param[in] sign_len Sign buffer length
\param[in] type \ref tee_rsa_sign_type_e
\return Return 0 if verify successful,otherwise error code
*/
int32_t csi_tee_img_rsa_verify(const uint8_t *in, uint32_t in_len,
uint8_t *sign, uint32_t sign_len,
tee_rsa_sign_type_e type);
/****** TEE HASH operation mode *****/
typedef enum {
TEE_HASH_OP_NONE = 0, ///< No operation
TEE_HASH_OP_START = 1, ///< HASH init
TEE_HASH_OP_UPDATA = 2, ///< HASH update
TEE_HASH_OP_FINISH = 3, ///< HASH finish
TEE_HASH_OP_MAX, ///< invailed operation
} tee_hash_op_e;
/****** TEE HMAC type *****/
typedef enum {
TEE_HMAC_SHA1 = 1, ///< HMAC with SHA1
} tee_hmac_type_e;
/**
\brief TEE HAMC
\note Call csi_tee_hmac_digest is better
out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[in] key Pointer to key buffer
\param[in] key_len Key buffer size
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_hmac_type_e
\param[in] hash_op \ref tee_hash_op_e
\param[in] ctx Pointer to context of hmac
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_hmac(const uint8_t *in, uint32_t in_len,
const uint8_t *key, uint32_t key_len,
uint8_t *out,
tee_hmac_type_e type,
tee_hash_op_e hash_op,
uint32_t *ctx);
/**
\brief TEE HAMC digest
\note out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[in] key Pointer to key buffer
\param[in] key_len Key buffer size
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_hmac_type_e
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_hmac_digest(in,in_len,key,key_len,out,type) \
csi_tee_hmac(in,in_len,key,key_len,out,type,TEE_HASH_OP_NONE,NULL)
/****** TEE SHA type *****/
typedef enum {
TEE_SHA1 = 0, ///< SHA1
TEE_SHA256 = 1, ///< SHA256
TEE_SHA224 = 2, ///< SHA224
TEE_SHA384 = 3, ///< SHA384
TEE_SHA512 = 4, ///< SHA512
TEE_SHA_MAX, ///< invaild sha type
} tee_sha_type_t;
/**
\brief TEE SHA
\note Call csi_tee_sha_digest, csi_tee_sha_start, csi_tee_sha_update or csi_tee_sha_finish is better
out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_sha_type_t
\param[in] hash_op \ref tee_hash_op_e
\param[in] ctx Pointer to context of sha
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_sha(const uint8_t *in, uint32_t in_len,
uint8_t *out,
tee_sha_type_t type,
tee_hash_op_e hash_op,
void *ctx);
/**
\brief TEE SHA digest
\note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[out] out Pointer to output date buffer
\param[in] type \ref tee_sha_type_t
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_sha_digest(in,in_len,out,type) \
csi_tee_sha(in,in_len,out,type,TEE_HASH_OP_NONE,NULL);
/**
\brief TEE SHA start, initial sha
\param[in] type \ref tee_sha_type_t
\param[in] ctx Pointer to context of sha
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_sha_start(type,ctx) \
csi_tee_sha(NULL,0,NULL,type,TEE_HASH_OP_START,ctx);
/**
\brief TEE SHA update, update data
\param[in] in Pointer to input data buffer
\param[in] in_len Input data buffer length
\param[in] ctx Pointer to context of sha
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_sha_update(in,in_len,ctx) \
csi_tee_sha(in,in_len,NULL,0,TEE_HASH_OP_UPDATA,ctx);
/**
\brief TEE SHA digest, get sha digest
\note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256
\param[out] out Pointer to output date buffer
\param[in] ctx Pointer to context of sha
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_sha_finish(out,ctx) \
csi_tee_sha(NULL,0,out,0,TEE_HASH_OP_FINISH,ctx);
/**
\brief TEE get device name and product key
\param[in] name_encrypted Pointer to device name ciphertext
\param[in] name_encrypted_len device name ciphertext length
\param[in] product_key_encrypted Pointer to device product key ciphertext
\param[in] product_key_encrypted_len Device product key ciphertext length
\param[out] name Pointer to device name
\param[out] name_len Device name length
\param[out] product_key Pointer to device product key
\param[out] product_key_len Device product key length
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_dev_info_get(const uint8_t *name_encrypted, uint32_t name_encrypted_len,
const uint8_t *product_key_encrypted, uint32_t product_key_encrypted_len,
const uint8_t *name, uint32_t *name_len,
const uint8_t *product_key, uint32_t *product_key_len);
/**
\brief TEE device info sign
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] device_secret Pointer to device secret ciphertext
\param[in] device_secret_len Device secret ciphertext length
\param[out] sign Pointer to signed buffer
\param[out] sign_len Signed buffer length
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_dev_info_sign(const uint8_t *in, uint32_t in_len,
const uint8_t *device_secret, uint32_t device_secret_len,
const uint8_t *sign, uint32_t *sign_len);
/**
\brief TEE device info encrypt/decrypt
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] out Pointer to output date buffer
\param[in] out_len Onput data buffer length
\param[in] is_enc 1 incrypt 0 decrypt
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_dev_info_crypt(const uint8_t *in, uint32_t in_len,
uint8_t *out, uint32_t *out_len,
uint8_t is_enc);
/**
\brief TEE device info encrypt
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] out Pointer to output date buffer
\param[in] out_len Onput data buffer length
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_dev_info_encrypt(in, in_len, out, out_len) \
csi_tee_dev_info_crypt(in, in_len, out, out_len, 1)
/**
\brief TEE device info decrypt
\param[in] in Pointer to input date buffer
\param[in] in_len Input data buffer length
\param[in] out Pointer to output date buffer
\param[in] out_len Onput data buffer length
\return Return 0 if successful,otherwise error code
*/
#define csi_tee_dev_info_decrypt(in, in_len, out, out_len) \
csi_tee_dev_info_crypt(in, in_len, out, out_len, 0)
/**
\brief Set system frequence
\param[in] clk_src Indicate clock source type
\param[in] clk_val System freqence to be set
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_set_sys_freq(uint32_t clk_src, uint32_t clk_val);
/**
\brief Get system frequence
\param[in] clk_val Value address to store system freqence
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_get_sys_freq(uint32_t *clk_val);
/**
\brief Read system register
\param[in] addr Indicate register address
\param[out] val Value to read from the address
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_read_reg(uint32_t addr, uint32_t *val);
/**
\brief Wrte system register
\param[in] addr Indicate register address
\param[in] val Value to be written into the address
\return Return 0 if successful,otherwise error code
*/
int32_t csi_tee_write_reg(uint32_t addr, uint32_t val);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TEE_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/tee.h | C | apache-2.0 | 26,284 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file tick.h
* @brief Header File for TICK Driver
* @version V1.0
* @date 28. Sep 2020
******************************************************************************/
#ifndef _DRV_TICK_H_
#define _DRV_TICK_H_
#include <stdint.h>
#include <stdint.h>
#include <drv/common.h>
#ifndef CONFIG_SYSTICK_HZ
#define CONFIG_SYSTICK_HZ 100U
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Initializes the resources needed for the TICK interface
\return error code \ref csi_error_t
*/
csi_error_t csi_tick_init(void);
/**
\brief De-initialize TICK Interface
*/
void csi_tick_uninit(void);
/**
\brief Get the sys-tick, one tick == (1000 / CONFIG_SYSTICK_HZ) ms
\return the sys-tick
*/
uint32_t csi_tick_get(void);
/**
\brief Get the time which start from csi_tick_init
\return The time which start from csi_tick_init (ms)
*/
uint32_t csi_tick_get_ms(void);
/**
\brief Get the time which start from csi_tick_init
\return The time which start from csi_tick_init (us)
*/
uint64_t csi_tick_get_us(void);
/**
\brief Increase the sys-tick
*/
void csi_tick_increase(void);
#ifdef __cplusplus
}
#endif
#endif /*_DRV_TICK_H_*/
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/tick.h | C | apache-2.0 | 1,367 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/timer.h
* @brief Header File for TIMER Driver
* @version V1.0
* @date 9. Oct 2020
* @model timer
******************************************************************************/
#ifndef _DRV_TIMER_H_
#define _DRV_TIMER_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct csi_timer csi_timer_t;
struct csi_timer {
csi_dev_t dev;
void (*callback)(csi_timer_t *timer, void *arg);
void *arg;
void *priv;
};
/**
\brief Initialize TIMER interface. initializes the resources needed for the TIMER interface
\param[in] timer Handle to operate
\param[in] idx TIMER index
\return Error code \ref csi_error_t
*/
csi_error_t csi_timer_init(csi_timer_t *timer, uint32_t idx);
/**
\brief De-initialize TIMER interface. stops operation and releases the software resources used by the interface
\param[in] timer Handle to operate
\return None
*/
void csi_timer_uninit(csi_timer_t *timer);
/**
\brief Start TIMER
\param[in] timer Handle to operate
\param[in] timeout_us The timeout for TIMER
\return Error code \ref csi_error_t
*/
csi_error_t csi_timer_start(csi_timer_t *timer, uint32_t timeout_us);
/**
\brief Stop TIMER
\param[in] timer Handle to operate
\return None
*/
void csi_timer_stop(csi_timer_t *timer);
/**
\brief Get TIMER remaining value
\param[in] timer Handle to operate
\return remaining value
*/
uint32_t csi_timer_get_remaining_value(csi_timer_t *timer);
/**
\brief Get TIMER load value
\param[in] timer Handle to operate
\return Load value
*/
uint32_t csi_timer_get_load_value(csi_timer_t *timer);
/**
\brief Check TIMER is running
\param[in] timer Handle to operate
\return
true - TIMER is running
false - TIMER is stopped
*/
bool csi_timer_is_running(csi_timer_t *timer);
/**
\brief Attach the callback handler to TIMER
\param[in] timer Operate handle
\param[in] callback Callback function
\param[in] arg Callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_timer_attach_callback(csi_timer_t *timer, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] timer Operate handle
\return None
*/
void csi_timer_detach_callback(csi_timer_t *timer);
/**
\brief Enable TIMER power manage
\param[in] timer Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_timer_enable_pm(csi_timer_t *timer);
/**
\brief Disable TIMER power manage
\param[in] timer Handle to operate
\return None
*/
void csi_timer_disable_pm(csi_timer_t *timer);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TIMER_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/timer.h | C | apache-2.0 | 3,035 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/tipc.h
* @brief Header File for TIPC Driver
* @version V1.0
* @date 08. Mar 2020
* @model tipc
******************************************************************************/
#ifndef _DRV_TIPC_H_
#define _DRV_TIPC_H_
#include <stdint.h>
#include <stdbool.h>
#include <csi_core.h>
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t ip;
uint16_t dev_tag;
uint8_t idx;
} csi_tipcmap_t;
/**
\brief Config the tipc module properity
\param[in] dev Dev handle \ref csi_dev_t
\param[in] is_secure is secure or not
*/
csi_error_t csi_dev_secure_config(csi_dev_t *dev, bool is_secure);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_TIPC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/tipc.h | C | apache-2.0 | 882 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/uart.h
* @brief Header File for UART Driver
* @version V1.0
* @date 08. Apr 2020
* @model uart
******************************************************************************/
#ifndef _DRV_UART_H_
#define _DRV_UART_H_
#include <drv/common.h>
#include <drv/dma.h>
#ifdef __cplusplus
extern "C" {
#endif
/*----- UART Control Codes: Mode Parameters: Data Bits -----*/
typedef enum {
UART_DATA_BITS_5 = 0, ///< 5 Data bits
UART_DATA_BITS_6, ///< 6 Data bit
UART_DATA_BITS_7, ///< 7 Data bits
UART_DATA_BITS_8, ///< 8 Data bits (default)
UART_DATA_BITS_9 ///< 9 Data bits
} csi_uart_data_bits_t;
/*----- UART Control Codes: Mode Parameters: Parity -----*/
typedef enum {
UART_PARITY_NONE = 0, ///< No Parity (default)
UART_PARITY_EVEN, ///< Even Parity
UART_PARITY_ODD, ///< Odd Parity
} csi_uart_parity_t;
/*----- UART Control Codes: Mode Parameters: Stop Bits -----*/
typedef enum {
UART_STOP_BITS_1 = 0, ///< 1 Stop bit (default)
UART_STOP_BITS_2, ///< 2 Stop bits
UART_STOP_BITS_1_5, ///< 1.5 Stop bits
} csi_uart_stop_bits_t;
/*----- UART Control Codes: Mode Parameters: Flow Control -----*/
typedef enum {
UART_FLOWCTRL_NONE = 0, ///< none flowctrl
UART_FLOWCTRL_RTS, ///< RTS
UART_FLOWCTRL_CTS, ///< CTS
UART_FLOWCTRL_RTS_CTS ///< RTS & CTS
} csi_uart_flowctrl_t;
/****** UART Event *****/
typedef enum {
UART_EVENT_SEND_COMPLETE = 0, ///< Send data completed.
UART_EVENT_RECEIVE_COMPLETE, ///< Receive data completed.
UART_EVENT_RECEIVE_FIFO_READABLE, ///< Data in uart fifo, call csi_uart_receive() get the data.
UART_ENENT_BREAK_INTR, ///< the serial input,sin, is held in a logic '0' state for longer than the sum of start time+data bits+parity+stop bits.
UART_EVENT_ERROR_OVERFLOW, ///< A new data character was received before the previous data was read.
UART_EVENT_ERROR_PARITY, ///< Occur parity error in the receiver.
UART_EVENT_ERROR_FRAMING ///< the receiver does not detect a valid STOP bit in the received data.
} csi_uart_event_t;
///< definition for uart.
typedef struct csi_uart csi_uart_t;
struct csi_uart {
csi_dev_t dev;
void (*callback)(csi_uart_t *uart, csi_uart_event_t event, void *arg);
void *arg;
uint8_t *tx_data;
uint32_t tx_size;
uint8_t *rx_data;
uint32_t rx_size;
csi_dma_ch_t *tx_dma;
csi_dma_ch_t *rx_dma;
csi_error_t (*send)(csi_uart_t *uart, const void *data, uint32_t size);
csi_error_t (*receive)(csi_uart_t *uart, void *data, uint32_t size);
csi_state_t state;
void *priv;
};
/**
\brief Initializes the resources needed for the UART interface.
\param[in] uart Operate handle.
\param[in] idx The device idx.
\return Error code.
*/
csi_error_t csi_uart_init(csi_uart_t *uart, uint32_t idx);
/**
\brief De-initialize UART Interface. stops operation and releases the software resources used by the interface.
\param[in] uart Operate handle.
\return Error code.
*/
void csi_uart_uninit(csi_uart_t *uart);
/**
\brief Attach the callback handler to UART.
\param[in] uart Operate handle.
\param[in] callback Callback function.
\param[in] arg User can define it by himself as callback's param.
\return Error code.
*/
csi_error_t csi_uart_attach_callback(csi_uart_t *uart, void *callback, void *arg);
/**
\brief Detach the callback handler.
\param[in] uart Operate handle.
*/
void csi_uart_detach_callback(csi_uart_t *uart);
/**
\brief Config the baudrate.
\param[in] uart UART handle to operate.
\param[in] baud UART baudrate.
\return Error code.
*/
csi_error_t csi_uart_baud(csi_uart_t *uart, uint32_t baud);
/**
\brief Config the uart format.
\param[in] uart UART handle to operate.
\param[in] data_bit UART data bits.
\param[in] parity UART data parity.
\param[in] stop_bit UART stop bits.
\return Error code.
*/
csi_error_t csi_uart_format(csi_uart_t *uart, csi_uart_data_bits_t data_bits,
csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits);
/**
\brief Config the uart flow control.
\param[in] uart UART handle to operate.
\param[in] flowctrl UART flow control.
\return Error code.
*/
csi_error_t csi_uart_flowctrl(csi_uart_t *uart, csi_uart_flowctrl_t flowctrl);
/**
\brief Start send data to UART transmitter, this function is blocking.
\param[in] uart UART handle to operate.
\param[in] data Pointer to buffer with data to send to UART transmitter.
\param[in] size Number of data to send (byte).
\param[in] timeout The timeout between bytes(ms).
\return the num of data which is sent successfully or CSI_ERROR.
*/
int32_t csi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start send data to UART transmitter, this function is non-blocking.
\param[in] uart UART handle to operate.
\param[in] data Pointer to buffer with data to send to UART transmitter.
\param[in] size Number of data to send (byte).
\return Error code.
*/
csi_error_t csi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size);
/**
\brief Query data from UART receiver FIFO, this function is blocking.
\param[in] uart UART handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver.
\param[in] size Number of data to receive.
\param[in] timeout The timeout between bytes(ms).
\return the num of data witch is received successfully or CSI_ERROR.
*/
int32_t csi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data from UART receiver, this function is non-blocking.
\param[in] uart UART handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver.
\param[in] size Number of data to receive (byte).
\return Error code.
*/
csi_error_t csi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size);
/**
\brief Get character in query mode.
\param[in] uart UART handle to operate.
\return the character to get.
*/
uint8_t csi_uart_getc(csi_uart_t *uart);
/**
\brief Send character in query mode.
\param[in] uart UART handle to operate.
\param[in] ch The character to be send.
*/
void csi_uart_putc(csi_uart_t *uart, uint8_t ch);
/**
\brief Link DMA channel to uart device.
\param[in] uart UART handle to operate.
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel.
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel.
\return Error code.
*/
csi_error_t csi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get the state of uart device.
\param[in] uart UART handle to operate.
\param[out] state The state of uart device.
\return Error code.
*/
csi_error_t csi_uart_get_state(csi_uart_t *uart, csi_state_t *state);
/**
\brief Enable uart power manage.
\param[in] uart UART handle to operate.
\return Error code.
*/
csi_error_t csi_uart_enable_pm(csi_uart_t *uart);
/**
\brief Disable uart power manage.
\param[in] uart UART handle to operate.
*/
void csi_uart_disable_pm(csi_uart_t *uart);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_UART_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/uart.h | C | apache-2.0 | 8,315 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/usi.h
* @brief Header File for USI Driver
* @version V1.0
* @date 02. June 2020
* @model usi
******************************************************************************/
#ifndef _DRV_USI_H_
#define _DRV_USI_H_
#include <drv/usi_iic.h>
#include <drv/usi_spi.h>
#include <drv/usi_usart.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _DRV_USI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/usi.h | C | apache-2.0 | 565 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/drv_usi_iic.h
* @brief Header File for IIC driver
* @version V1.0
* @date 02. June 2020
* @model usi_iic
******************************************************************************/
#ifndef _DRV_USI_IIC_H_
#define _DRV_USI_IIC_H_
#include <stdint.h>
#include <stdbool.h>
#include <drv/common.h>
#include <drv/iic.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Init iic ctrl block.
Initializes the resources needed for the iic instance.
\param[in] iic Handle of iic instance.
\param[in] idx Index of instance.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_init(csi_iic_t *iic, uint32_t idx);
/**
\brief Uninit iic ctrl block.
Stops operation and releases the software resources used by the instance.
\param[in] iic Handle of iic instance.
*/
void csi_usi_iic_uninit(csi_iic_t *iic);
/**
\brief Config iic master or slave mode.
\param[in] iic Handle of iic instance.
\param[in] mode IIC mode \ref csi_iic_mode_t.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode);
/**
\brief Config iic addr mode.
\param[in] iic Handle of iic instance.
\param[in] addr_mode IIC addr mode \ref csi_iic_addr_mode_t.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode);
/**
\brief Config iic speed.
\param[in] iic Handle of iic instance.
\param[in] speed iic speed mode \ref csi_iic_speed_t.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed);
/**
\brief Config iic own addr.
\param[in] iic Handle of iic instance.
\param[in] own_addr IIC set own addr at slave mode.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_own_addr(csi_iic_t *iic, uint32_t own_addr);
/**
\brief Start sending data as iic master.
This function is blocking.
\param[in] iic Handle of iic instance.
\param[in] devaddr Addrress of slave device.
\param[in] data Pointer to send data buffer.
\param[in] size Size of data items to send.
\param[in] timout Unit of time delay(ms).
\return The amount of real data sent.
*/
int32_t csi_usi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data as iic master.
This function is blocking.
\param[in] iic Handle to operate.
\param[in] devaddr IIC addrress of slave device.
\param[out] data Pointer to buffer for data to receive from iic receiver.
\param[in] size Size of data items to receive.
\param[in] timeout Unit of time delay(ms).
\return The amount of real data received.
*/
int32_t csi_usi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data as iic master.
This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens.
\param[in] iic Handle to operate.
\param[in] devaddr IIC addrress of slave device.
\param[in] data Pointer to send data buffer.
\param[in] size Size of data items to send.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_master_send_async(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size);
/**
\brief Start receiving data as iic master.
This function is non-blocking.\ref csi_usi_iic_event_t is signaled when transfer completes or error happens.
\param[in] iic Handle to operate.
\param[in] devaddr IIC addrress of slave device.
\param[out] data Pointer to buffer for data to receive from iic receiver.
\param[in] size Size of data items to receive.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_master_receive_async(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size);
/**
\brief Start sending data as iic master.
This function is blocking.
\param[in] iic Handle of iic instance.
\param[in] devaddr Addrress of slave device.
\param[in] memaddr Internal addr of device.
\param[in] memaddr_size Internal addr mode of device.
\param[in] data Pointer to send data buffer.
\param[in] size Size of data items to send.
\param[in] timout Unit of time delay(ms).
\return The amount of real data sent.
*/
int32_t csi_usi_iic_mem_send(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data as iic master.
This function is blocking.
\param[in] iic Handle to operate.
\param[in] devaddr IIC addrress of slave device.
\param[in] memaddr Internal addr of device.
\param[in] memaddr_mode Internal addr mode of device.
\param[out] data Pointer to buffer for data to receive from eeprom device.
\param[in] size Size of data items to receive.
\param[in] timeout Unit of time delay(ms).
\return The amount of real data received.
*/
int32_t csi_usi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data as iic slave.
This function is blocking.
\param[in] iic Handle to operate.
\param[in] data Pointer to buffer with data to send to iic master.
\param[in] size Size of data items to send.
\param[in] timeout Unit of time delay(ms).
\return The amount of real data sent.
*/
int32_t csi_usi_iic_slave_send(csi_iic_t *iic, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start receiving data as iic slave.
This function is blocking.
\param[in] iic Handle to operate.
\param[out] data Pointer to buffer for data to receive from iic master.
\param[in] size Size of data items to receive.
\param[in] timeout Unit of time delay(ms).
\return The amount of real data received.
*/
int32_t csi_usi_iic_slave_receive(csi_iic_t *iic, void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data as iic slave.
This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens.
\param[in] iic Handle to operate.
\param[in] data Pointer to buffer with data to send to iic master.
\param[in] size size of data items to send.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t size);
/**
\brief Start receiving data as iic slave.
This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens.
\param[in] handle IIC handle to operate.
\param[out] data Pointer to buffer for data to receive from iic master.
\param[in] size Size of data items to receive.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t size);
/**
\brief Attach callback to the iic.
\param[in] iic IIC handle to operate.
\param[in] cb Event callback function \ref csi_usi_iic_callback_t.
\param[in] arg User private param for event callback.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_attach_callback(csi_iic_t *iic, void *callback, void *arg);
/**
\brief Detach callback from the iic.
\param[in] iic IIC handle to operate.
\return \ref csi_error_t.
*/
void csi_usi_iic_detach_callback(csi_iic_t *iic);
/**
\brief Config iic stop to generate.
\param[in] iic IIC handle to operate.
\param[in] enable Transfer operation is pending - stop condition will not be generated.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_xfer_pending(csi_iic_t *iic, bool enable);
/**
\brief Link DMA channel to iic device.
\param[in] iic Handle to operate.
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel.
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_link_dma(csi_iic_t *iic, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get iic state.
\param[in] iic Handle to operate.
\param[out] state IIC state \ref csi_state_t.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_get_state(csi_iic_t *iic, csi_state_t *state);
/**
\brief Enable iic power manage.
\param[in] iic IIC handle to operate.
\return \ref csi_error_t.
*/
csi_error_t csi_usi_iic_enable_pm(csi_iic_t *iic);
/**
\brief Disable iic power manage.
\param[in] iic IIC handle to operate.
*/
void csi_usi_iic_disable_pm(csi_iic_t *iic);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_USI_IIC_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/usi_iic.h | C | apache-2.0 | 9,222 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/usi_spi.h
* @brief Header File for SPI Driver
* @version V1.0
* @date 02. June 2020
* @model usi_spi
******************************************************************************/
#ifndef _DRV_SPI_USI_H_
#define _DRV_SPI_USI_H_
#include <stdint.h>
#include <drv/common.h>
#include <drv/spi.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Initialize SPI Interface.
Initializes the resources needed for the SPI instance
\param[in] spi SPI handle
\param[in] idx SPI instance index
\return Error code
*/
csi_error_t csi_usi_spi_init(csi_spi_t *spi, uint32_t idx);
/**
\brief De-initialize SPI Interface
Stops operation and releases the software resources used by the spi instance
\param[in] spi SPI handle
\return None
*/
void csi_usi_spi_uninit(csi_spi_t *spi);
/**
\brief Attach the callback handler to SPI
\param[in] spi Operate handle.
\param[in] callback Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code
*/
csi_error_t csi_usi_spi_attach_callback(csi_spi_t *spi, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] spi Operate handle.
\return None
*/
void csi_usi_spi_detach_callback(csi_spi_t *spi);
/**
\brief Config spi mode (master or slave).
\param[in] spi SPI handle
\param[in] mode The mode of spi (master or slave)
\return Error code
*/
csi_error_t csi_usi_spi_mode(csi_spi_t *spi, csi_spi_mode_t mode);
/**
\brief Config spi cp format.
\param[in] spi SPI handle
\param[in] format SPI cp format
\return Error code
*/
csi_error_t csi_usi_spi_cp_format(csi_spi_t *spi, csi_spi_cp_format_t format);
/**
\brief Config spi frame len.
\param[in] spi SPI handle
\param[in] length spi frame len
\return error code
*/
csi_error_t csi_usi_spi_frame_len(csi_spi_t *spi, csi_spi_frame_len_t length);
/**
\brief Config spi work frequence.
\param[in] spi SPI handle
\param[in] baud SPI work baud
\return The actual config frequency
*/
uint32_t csi_usi_spi_baud(csi_spi_t *spi, uint32_t baud);
/**
\brief Config spi mode.
\param[in] Handle spi handle to operate.
\param[in] baud SPI baud rate. If negative, then this attribute not changed
\param[in] mode \ref spi_mode_e . If negative, then this attribute not changed
\param[in] format \ref spi_format_e . If negative, then this attribute not changed
\param[in] order \ref spi_bit_order_e . If negative, then this attribute not changed
\param[in] ss_mode \ref spi_ss_mode_t . If negative, then this attribute not changed
\param[in] bit_width SPI data bitwidth: (1 ~ SPI_DATAWIDTH_MAX) . If negative, then this attribute not changed
\return Error code
*/
csi_error_t drv_usi_spi_config(csi_spi_t *spi, csi_spi_mode_t mode, csi_spi_frame_len_t width, csi_spi_cp_format_t format);
/**
\brief Sending data to SPI transmitter,(received data is ignored).
Blocking mode ,return unti all data has been sent or err happened
\param[in] spi Handle to operate.
\param[in] data Pointer to buffer with data to send to SPI transmitter.
\param[in] size Number of data to send(byte)
\param[in] timeout Unit in mini-second
\return If send success, this function shall return the num of data witch is sent successful
otherwise, the function shall return error code
*/
int32_t csi_usi_spi_send(csi_spi_t *spi, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Sending data to SPI transmitter,(received data is ignored).
non-blocking mode,transfer done event will be signaled by driver
\param[in] spi Handle to operate.
\param[in] data Pointer to buffer with data to send to SPI transmitter.
\param[in] size Number of data items to send(byte)
\return Error code
*/
csi_error_t csi_usi_spi_send_async(csi_spi_t *spi, const void *data, uint32_t size);
/**
\brief Receiving data from SPI receiver.
Blocking mode, return untill curtain data items are readed
\param[in] spi Handle to operate.
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] size Number of data items to receive(byte)
\param[in] timeout Unit in mini-second
\return If receive success, this function shall return the num of data witch is received successful
Otherwise, the function shall return error code
*/
int32_t csi_usi_spi_receive(csi_spi_t *spi, void *data, uint32_t size, uint32_t timeout);
/**
\brief Receiving data from SPI receiver.
Not-blocking mode, event will be signaled when receive done or err happend
\param[in] spi Handle to operate.
\param[out] data Pointer to buffer for data to receive from SPI receiver
\param[in] size Number of data items to receive(byte)
\return Error code
*/
csi_error_t csi_usi_spi_receive_async(csi_spi_t *spi, void *data, uint32_t size);
/**
\brief Dulplex,sending and receiving data at the same time
\ref csi_spi_event_t is signaled when operation completes or error happens.
\ref csi_spi_get_state can get operation status.
Blocking mode, this function returns after operation completes or error happens.
\param[in] Handle spi handle to operate.
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] size Data size(byte)
\return If transfer success, this function shall return the num of data witch is transfer successful
otherwise, the function shall return error code
*/
int32_t csi_usi_spi_send_receive(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size, uint32_t timeout);
/**
\brief Transmit first then receive ,receive will begin after transmit is done
if non-blocking mode, this function only starts the transfer,
\ref csi_spi_event_t is signaled when operation completes or error happens.
\ref csi_spi_get_state can get operation status.
\param[in] handle spi Handle to operate.
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
\param[in] size Data size(byte)
\return Error code
*/
csi_error_t csi_usi_spi_send_receive_async(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size);
/*
\brief Set slave select num. Only valid for master
\param[in] Handle spi handle to operate.
\param[in] slave_num SPI slave num.
\return None
*/
void csi_usi_spi_select_slave(csi_spi_t *spi, uint32_t slave_num);
/**
\brief Link DMA channel to spi device
\param[in] spi SPI handle to operate.
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel
\return Error code
*/
csi_error_t csi_usi_spi_link_dma(csi_spi_t *spi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get the state of spi device
\param[in] spi SPI handle to operate.
\param[out] state The state of spi device
\return Error code
*/
csi_error_t csi_usi_spi_get_state(csi_spi_t *spi, csi_state_t *state);
/**
\brief Enable spi power manage
\param[in] spi SPI handle to operate.
\return Error code
*/
csi_error_t csi_usi_spi_enable_pm(csi_spi_t *spi);
/**
\brief Disable spi power manage
\param[in] spi SPI handle to operate.
\return Error code
*/
void csi_spi_disable_pm(csi_spi_t *spi);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_SPI_USI_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/usi_spi.h | C | apache-2.0 | 8,199 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/usi_usart.h
* @brief Header File for USART Driver
* @version V1.0
* @date 02. June 2020
* @model usi_usart
******************************************************************************/
#ifndef _DRV_USI_USART_H_
#define _DRV_USI_USART_H_
#include <drv/common.h>
#include <drv/uart.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Initialize UART Interface. 1. Initializes the resources needed for the UART interface 2.registers event callback function
\param[in] uart Operate handle.
\param[in] idx The device idx
\param[in] cb_event Event call back function \ref uart_event_cb_t
\param[in] arg User can define it by himself
\return error code
*/
csi_error_t csi_usi_uart_init(csi_uart_t *uart, uint32_t idx);
/**
\brief De-initialize UART Interface. stops operation and releases the software resources used by the interface
\param[in] uart Operate handle.
\return Error code
*/
void csi_usi_uart_uninit(csi_uart_t *uart);
/**
\brief Attach the callback handler to UART
\param[in] uart Operate handle.
\param[in] cb Callback function
\param[in] arg User can define it by himself as callback's param
\return Error code
*/
csi_error_t csi_usi_uart_attach_callback(csi_uart_t *uart, void * cb, void *arg);
/**
\brief Detach the callback handler
\param[in] uart Operate handle.
*/
void csi_usi_uart_detach_callback(csi_uart_t *uart);
/**
\brief Config the baudrate.
\param[in] uart UART handle to operate.
\param[in] baud UART baudrate
\return Error code
*/
csi_error_t csi_usi_uart_baud(csi_uart_t *uart, uint32_t baud);
/**
\brief Config the uart format.
\param[in] uart UART handle to operate.
\param[in] data_bit UART data bits
\param[in] parity UART data parity
\param[in] stop_bit UART stop bits
\return Error code
*/
csi_error_t csi_usi_uart_format(csi_uart_t *uart, csi_uart_data_bits_t data_bits,
csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits);
/**
\brief Config the uart flow control.
\param[in] uart UART handle to operate.
\param[in] flowctrl UART flow control
\return Error code
*/
csi_error_t csi_usi_uart_flowctrl(csi_uart_t *uart, csi_uart_flowctrl_t flowctrl);
/**
\brief Start sending data to UART transmitter.
\param[in] uart UART handle to operate.
\param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to send (byte)
\param[in] Timeout is the number of queries, not time
\return The num of data witch is send successful
*/
int32_t csi_usi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout);
/**
\brief Start sending data to UART transmitter (interrupt mode).
\param[in] uart UART handle to operate.
\param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to send
\return The status of send func
*/
csi_error_t csi_usi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size);
/**
\brief Get the num of data in RX_FIFO.
\param[in] uart UART handle to operate.
\return The num of data in RX_FIFO
*/
uint32_t csi_usi_uart_get_recvfifo_waiting_num(csi_uart_t *uart);
/**
\brief Start receiving data from UART receiver. \n
This function is non-blocking,\ref uart_event_e is signaled when operation completes or error happens.
\ref csi_uart_get_status can get operation status.
\param[in] uart UART handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
\param[in] num Number of data items to receive
\return Error code
*/
csi_error_t csi_usi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size);
/**
\brief Query data from UART receiver FIFO.
\param[in] uart UART handle to operate.
\param[out] data Pointer to buffer for data to receive from UART receiver
\param[in] num Number of data items to receive
\param[in] Timeout is the number of queries, not time
\return FIFO data num to receive
*/
int32_t csi_usi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout);
/**
\brief Get character in query mode.
\param[in] uart UART handle to operate.
\param[out] ch The pointer to the received character.
\return Error code
*/
uint8_t csi_usi_uart_getchar(csi_uart_t *uart);
/**
\brief Transmit character in query mode.
\param[in] uart UART handle to operate.
\param[in] ch The input character
\return Error code
*/
void csi_usi_uart_putchar(csi_uart_t *uart, uint8_t ch);
/**
\brief Link DMA channel to uart device
\param[in] uart UART handle to operate.
\param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel
\param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel
\return Error code
*/
csi_error_t csi_usi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
/**
\brief Get the state of uart device.
\param[in] uart UART handle to operate.
\param[out] state The state of uart device.
\return Error code.
*/
csi_error_t csi_usi_uart_get_state(csi_uart_t *uart, csi_state_t *state);
/**
\brief Enable uart power manage.
\param[in] uart UART handle to operate.
\return Error code.
*/
csi_error_t csi_usi_uart_enable_pm(csi_uart_t *uart);
/**
\brief Disable uart power manage.
\param[in] uart UART handle to operate.
*/
void csi_usi_uart_disable_pm(csi_uart_t *uart);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_USI_USART_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/usi_usart.h | C | apache-2.0 | 6,252 |
/*
* Copyright (C) 2017-2020 Alibaba Group Holding Limited
*/
/******************************************************************************
* @file drv/wdt.h
* @brief Header File for WDT Driver
* @version V1.0
* @date 9. Oct 2020
* @model wdt
******************************************************************************/
#ifndef _DRV_WDT_H_
#define _DRV_WDT_H_
#include <drv/common.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct csi_wdt csi_wdt_t;
struct csi_wdt {
csi_dev_t dev;
void (*callback)(csi_wdt_t *wdt, void *arg);
void *arg;
void *priv;
};
/**
\brief Initialize WDT interface. Initializes the resources needed for the WDT interface
\param[in] wdt Handle to operate
\param[in] idx WDT index
\return Error code \ref csi_error_t
*/
csi_error_t csi_wdt_init(csi_wdt_t *wdt, uint32_t idx);
/**
\brief De-initialize WDT interface. Stops operation and releases the software resources used by the interface
\param[in] wdt Handle to operate
\return None
*/
void csi_wdt_uninit(csi_wdt_t *wdt);
/**
\brief Set the WDT value
\param[in] wdt Handle to operate
\param[in] ms The timeout value(ms)
\return Error code \ref csi_error_t
*/
csi_error_t csi_wdt_set_timeout(csi_wdt_t *wdt, uint32_t ms);
/**
\brief Start the WDT
\param[in] wdt Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_wdt_start(csi_wdt_t *wdt);
/**
\brief Stop the WDT
\param[in] wdt Handle to operate
\return None
*/
void csi_wdt_stop(csi_wdt_t *wdt);
/**
\brief Feed the WDT
\param[in] wdt Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_wdt_feed(csi_wdt_t *wdt);
/**
\brief Get the remaining time to timeout
\param[in] wdt Handle to operate
\return The remaining time of WDT(ms)
*/
uint32_t csi_wdt_get_remaining_time(csi_wdt_t *wdt);
/**
\brief Check WDT is running
\param[in] wdt Handle to operate
\return
true - WDT is running
false - WDT is stopped
*/
bool csi_wdt_is_running(csi_wdt_t *wdt);
/**
\brief Attach the callback handler to WDT
\param[in] wdt Handle to operate
\param[in] callback Callback function
\param[in] arg Callback's param
\return Error code \ref csi_error_t
*/
csi_error_t csi_wdt_attach_callback(csi_wdt_t *wdt, void *callback, void *arg);
/**
\brief Detach the callback handler
\param[in] wdt Handle to operate
\return None
*/
void csi_wdt_detach_callback(csi_wdt_t *wdt);
/**
\brief Enable WDT power manage
\param[in] wdt Handle to operate
\return Error code \ref csi_error_t
*/
csi_error_t csi_wdt_enable_pm(csi_wdt_t *wdt);
/**
\brief Disable WDT power manage
\param[in] wdt Handle to operate
\return None
*/
void csi_wdt_disable_pm(csi_wdt_t *wdt);
#ifdef __cplusplus
}
#endif
#endif /* _DRV_WDT_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/drv/wdt.h | C | apache-2.0 | 3,091 |
/*
* Copyright (C) 2017-2019 Alibaba Group Holding Limited
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
* @file syslog.h
* @brief Defines syslog APIs and usage
* @version V1.1
* @date 14. February 2019
* @usage Add 3 lines codes below at head of source code file
* // 0: Err; 1: Err&Warn; 2: Err&Warn&Info; 3: Err&Warn&Info&Debug
* #define LOG_LEVEL 3
* #include <syslog.h>
******************************************************************************/
#include <stdio.h>
#ifndef _SYSLOG_H_
#define _SYSLOG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef LOG_LEVEL
#if (LOG_LEVEL >= 3) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG)
#define LOG_ENABLE_D
#endif
#if (LOG_LEVEL >= 2) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG || \
defined CONFIG_SYSLOG_LEVEL_INFO)
#define LOG_ENABLE_I
#endif
#if (LOG_LEVEL >= 1) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG || \
defined CONFIG_SYSLOG_LEVEL_INFO || \
defined CONFIG_SYSLOG_LEVEL_WARN)
#define LOG_ENABLE_W
#endif
#if (LOG_LEVEL >= 0) && \
(defined CONFIG_SYSLOG_LEVEL_DEBUG || \
defined CONFIG_SYSLOG_LEVEL_INFO || \
defined CONFIG_SYSLOG_LEVEL_WARN || \
defined CONFIG_SYSLOG_LEVEL_ERROR)
#define LOG_ENABLE_E
#endif
#endif /* #ifdef LOG_LEVEL */
/* [LogLevel:FileName:Function:Line] */
extern const char *PFORMAT_D;
extern const char *PFORMAT_I;
extern const char *PFORMAT_W;
extern const char *PFORMAT_E;
#define LOG_E_BASE_ARGS __FUNCTION__, __LINE__
#define LOG_W_BASE_ARGS __FUNCTION__, __LINE__
#define LOG_I_BASE_ARGS __FUNCTION__, __LINE__
#define LOG_D_BASE_ARGS __FUNCTION__, __LINE__
/* Log in freely format without prefix */
#define LOG_F(fmt, args...) printf(fmt,##args)
/* Log debug */
#ifdef LOG_ENABLE_D
#define LOG_D(fmt, args...) \
do {printf(PFORMAT_D,LOG_D_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_D(fmt, args...)
#endif
/* Log information */
#ifdef LOG_ENABLE_I
#define LOG_I(fmt, args...) \
do {printf(PFORMAT_I ,LOG_I_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_I(fmt, args...)
#endif
/* Log warning */
#ifdef LOG_ENABLE_W
#define LOG_W(fmt, args...) \
do {printf(PFORMAT_W,LOG_W_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_W(fmt, args...)
#endif
/* Log error */
#ifdef LOG_ENABLE_E
#define LOG_E(fmt, args...) \
do {printf(PFORMAT_E,LOG_E_BASE_ARGS); printf(fmt,##args);} while(0)
#else
#define LOG_E(fmt, args...)
#endif
#define ENTER() LOG_D("Enter\n")
#define EXIT_VOID() do { LOG_D("Exit\n"); return;} while(0)
#define EXIT_INT(val) do { LOG_D("Exit, return val=%d\n", (int)val); return val;} while(0)
#define EXIT_PTR(ptr) do { LOG_D("Exit, return ptr=%p\n", (void*)ptr); return ptr;} while(0)
#ifdef __cplusplus
}
#endif
#endif /* _SYSLOG_H_ */
| YifuLiu/AliOS-Things | components/csi/csi2/include/syslog.h | C | apache-2.0 | 2,898 |
/* ----------------------------------------------------------------------
* Title: csky_dsp2_nnfunctions.h
* Description: Public header file for CSI NN Library
*
* -------------------------------------------------------------------- */
#ifndef _CSKY_DSP2_NNFUNCTIONS_H
#define _CSKY_DSP2_NNFUNCTIONS_H
#ifdef __cplusplus
extern "C"
{
#endif
#include"csky_math.h"
/**
* @brief Struct for specifying activation function types
*
*/
typedef enum
{
CSKY_SIGMOID = 0, /**< Sigmoid activation function */
CSKY_TANH = 1, /**< Tanh activation function */
} csky_dsp2_nn_activation_type;
/**
* @brief Basic Q7 convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
*/
void csky_dsp2_convolve_HWC_q7_basic(const q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Basic Q15 convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
*/
void csky_dsp2_convolve_HWC_q15_basic(const q15_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q15_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q15_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q15_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Fast Q7 convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 4
* ch_im_out is multiple of 2
*/
void csky_dsp2_convolve_HWC_q7_fast(const q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Fast Q7 convolution function (non-sqaure shape)
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in_x input tensor dimention x
* @param[in] dim_im_in_y input tensor dimention y
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel_x filter kernel size x
* @param[in] dim_kernel_y filter kernel size y
* @param[in] padding_x padding size x
* @param[in] padding_y padding size y
* @param[in] stride_x convolution stride x
* @param[in] stride_y convolution stride y
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out_x output tensor dimension x
* @param[in] dim_im_out_y output tensor dimension y
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 4
* ch_im_out is multiple of 2
*/
void csky_dsp2_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in,
const uint16_t dim_im_in_x,
const uint16_t dim_im_in_y,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel_x,
const uint16_t dim_kernel_y,
const uint16_t padding_x,
const uint16_t padding_y,
const uint16_t stride_x,
const uint16_t stride_y,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out_x,
const uint16_t dim_im_out_y,
q15_t * bufferA);
/**
* @brief Fast Q7 version of 1x1 convolution (non-sqaure shape)
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in_x input tensor dimention x
* @param[in] dim_im_in_y input tensor dimention y
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel_x filter kernel size x
* @param[in] dim_kernel_y filter kernel size y
* @param[in] padding_x padding size x
* @param[in] padding_y padding size y
* @param[in] stride_x convolution stride x
* @param[in] stride_y convolution stride y
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out_x output tensor dimension x
* @param[in] dim_im_out_y output tensor dimension y
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1
* and dim_kernel_y=1). It can be used for
* second half of MobileNets after depthwise separable convolution.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 4
* ch_im_out is multiple of 2
*/
void csky_dsp2_convolve_1x1_HWC_q7_fast(const q7_t * Im_in,
const uint16_t dim_im_in_x,
const uint16_t dim_im_in_y,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out_x,
const uint16_t dim_im_out_y,
q15_t * bufferA);
/**
* @brief Q7 version of convolution for RGB image
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This kernel is written exclusively for convolution with ch_im_in
* equals 3. This applies on the first layer of CNNs which has input
* image with RGB format.
*/
void csky_dsp2_convolve_HWC_q7_RGB(const q7_t * Im_in,
const uint16_t dim_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Fast Q15 convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 2
* ch_im_out is multiple of 2
*/
void csky_dsp2_convolve_HWC_q15_fast(const q15_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q15_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q15_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q15_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Q7 depthwise separable convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 2
* ch_im_out is multiple of 2
*/
void csky_dsp2_depthwise_separable_conv_HWC_q7(const q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Q7 depthwise separable convolution function (non-square shape)
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in_x input tensor dimention x
* @param[in] dim_im_in_y input tensor dimention y
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel_x filter kernel size x
* @param[in] dim_kernel_y filter kernel size y
* @param[in] padding_x padding sizes x
* @param[in] padding_y padding sizes y
* @param[in] stride_x convolution stride x
* @param[in] stride_y convolution stride y
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out_x output tensor dimension x
* @param[in] dim_im_out_y output tensor dimension y
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 2
* ch_im_out is multiple of 2
*/
void csky_dsp2_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in,
const uint16_t dim_im_in_x,
const uint16_t dim_im_in_y,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel_x,
const uint16_t dim_kernel_y,
const uint16_t padding_x,
const uint16_t padding_y,
const uint16_t stride_x,
const uint16_t stride_y,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out_x,
const uint16_t dim_im_out_y,
q15_t * bufferA);
/**
* @brief Q7 basic fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*/
void csky_dsp2_fully_connected_q7(const q7_t * pV,
const q7_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q7_t * pOut);
/**
* @brief Q7 opt fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @param[in,out] vec_buffer pointer to buffer space for input
* @return none.
*
*/
void csky_dsp2_fully_connected_q7_opt(const q7_t * pV,
const q7_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q7_t * pOut,
q15_t * vec_buffer);
/**
* @brief Q15 basic fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*
*/
void csky_dsp2_fully_connected_q15(const q15_t * pV,
const q15_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q15_t * bias,
q15_t * pOut);
/**
* @brief Q15 opt fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*
*/
void csky_dsp2_fully_connected_q15_opt(const q15_t * pV,
const q15_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q15_t * bias,
q15_t * pOut);
/**
* @brief Mixed Q15-Q7 fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*
*/
void csky_dsp2_fully_connected_mat_q7_vec_q15(const q15_t * pV,
const q7_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q15_t * pOut);
/**
* @brief Mixed Q15-Q7 opt fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*
*/
void csky_dsp2_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV,
const q7_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q15_t * pOut);
/**
* @brief Matrix-Multiplication Kernels for Convolution
*
* These functions are used within convolution layer functions for
* matrix multiplication.
*
* The implementation is similar to CSI-DSP csky_dsp2_mat_mult functions
* with one Q7 and one Q15 operands. The Q15 operand is the im2col
* output which is always with 2 columns.
*
*/
/**
* @brief Matrix-multiplication function for convolution
* @param[in] pA pointer to operand A
* @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors
* @param[in] ch_im_out numRow of A
* @param[in] numCol_A numCol of A
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias the bias
* @param[in,out] pOut pointer to output
* @return The function returns the incremented output pointer
*/
q7_t *csky_dsp2_nn_mat_mult_kernel_q7_q15(const q7_t * pA,
const q15_t * pInBuffer,
const uint16_t ch_im_out,
const uint16_t numCol_A,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q7_t * pOut);
/**
* @brief Matrix-multiplication function for convolution with reordered columns
* @param[in] pA pointer to operand A
* @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors
* @param[in] ch_im_out numRow of A
* @param[in] numCol_A numCol of A
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias the bias
* @param[in,out] pOut pointer to output
* @return The function returns the incremented output pointer
*/
q7_t *csky_dsp2_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA,
const q15_t * pInBuffer,
const uint16_t ch_im_out,
const uint16_t numCol_A,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q7_t * pOut);
#ifdef __cplusplus
}
#endif
/*
* Other functions
* These layers are typically not timing critical
* Basic implementation is supported here
*/
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief Q7 RELU function
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @return none.
*/
void csky_dsp2_relu_q7(q7_t * data, uint16_t size);
/**
* @brief Q15 RELU function
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @return none.
*/
void csky_dsp2_relu_q15(q15_t * data, uint16_t size);
/**
* @brief Q7 neural network activation function using direct table look-up
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @param[in] int_width bit-width of the integer part, assume to be smaller than 3
* @param[in] type type of activation functions
* @return none.
*/
void csky_dsp2_nn_activations_direct_q7(q7_t * data, uint16_t size,
uint16_t int_width,
csky_dsp2_nn_activation_type type);
/**
* @brief Q15 neural network activation function using direct table look-up
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @param[in] int_width bit-width of the integer part, assume to be smaller than 3
* @param[in] type type of activation functions
* @return none.
*/
void csky_dsp2_nn_activations_direct_q15(q15_t * data, uint16_t size,
uint16_t int_width,
csky_dsp2_nn_activation_type type);
/**
* @brief Q7 max pooling function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @param[in,out] Im_out pointer to output tensor
* @return none.
*
*/
void csky_dsp2_maxpool_q7_HWC(q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const uint16_t dim_im_out,
q7_t * bufferA,
q7_t * Im_out);
/**
* @brief Q7 average pooling function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @param[in,out] Im_out pointer to output tensor
* @return none.
*
*/
void csky_dsp2_avepool_q7_HWC(q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const uint16_t dim_im_out,
q7_t * bufferA,
q7_t * Im_out);
/**
* @brief Q7 softmax function
* @param[in] vec_in pointer to input vector
* @param[in] dim_vec input vector dimention
* @param[out] p_out pointer to output vector
* @return none.
*
*/
void csky_dsp2_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out);
/**
* @brief Q15 softmax function
* @param[in] vec_in pointer to input vector
* @param[in] dim_vec input vector dimention
* @param[out] p_out pointer to output vector
* @return none.
*
*/
void csky_dsp2_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec,
q15_t *p_out);
#ifdef __cplusplus
}
#endif
#endif
| YifuLiu/AliOS-Things | components/csi/csi2/nn/include/csky_dsp2_nnfunctions.h | C | apache-2.0 | 34,083 |
/* ----------------------------------------------------------------------
* Title: csky_vdsp2_nnfunctions.h
* Description: Public header file for CSI NN Library
*
* -------------------------------------------------------------------- */
#ifndef _CSKY_VDSP2_NNFUNCTIONS_H
#define _CSKY_VDSP2_NNFUNCTIONS_H
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef CSKY_VDSP2_MATH_DSP
#include "csky_vdsp2_math.h"
#include "csky_vdsp2_nnsupportfunctions.h"
#endif
/**
* @brief Struct for specifying activation function types
*
*/
typedef enum
{
CSKY_SIGMOID = 0, /**< Sigmoid activation function */
CSKY_TANH = 1, /**< Tanh activation function */
} csky_vdsp2_nn_activation_type;
/**
* @brief Basic Q7 convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
*/
void csky_vdsp2_convolve_HWC_q7_basic(const q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Basic Q15 convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
*/
void csky_vdsp2_convolve_HWC_q15_basic(const q15_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q15_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q15_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q15_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Fast Q7 convolution function (non-sqaure shape)
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in_x input tensor dimention x
* @param[in] dim_im_in_y input tensor dimention y
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel_x filter kernel size x
* @param[in] dim_kernel_y filter kernel size y
* @param[in] padding_x padding size x
* @param[in] padding_y padding size y
* @param[in] stride_x convolution stride x
* @param[in] stride_y convolution stride y
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out_x output tensor dimension x
* @param[in] dim_im_out_y output tensor dimension y
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 4
* ch_im_out is multiple of 2
*/
void csky_vdsp2_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in,
const uint16_t dim_im_in_x,
const uint16_t dim_im_in_y,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel_x,
const uint16_t dim_kernel_y,
const uint16_t padding_x,
const uint16_t padding_y,
const uint16_t stride_x,
const uint16_t stride_y,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out_x,
const uint16_t dim_im_out_y,
q15_t * bufferA);
/**
* @brief Fast Q7 version of 1x1 convolution (non-sqaure shape)
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in_x input tensor dimention x
* @param[in] dim_im_in_y input tensor dimention y
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel_x filter kernel size x
* @param[in] dim_kernel_y filter kernel size y
* @param[in] padding_x padding size x
* @param[in] padding_y padding size y
* @param[in] stride_x convolution stride x
* @param[in] stride_y convolution stride y
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out_x output tensor dimension x
* @param[in] dim_im_out_y output tensor dimension y
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1
* and dim_kernel_y=1). It can be used for
* second half of MobileNets after depthwise separable convolution.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 4
* ch_im_out is multiple of 2
*/
void csky_vdsp2_convolve_1x1_HWC_q7_fast(const q7_t * Im_in,
const uint16_t dim_im_in_x,
const uint16_t dim_im_in_y,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out_x,
const uint16_t dim_im_out_y,
q15_t * bufferA);
/**
* @brief Q7 version of convolution for RGB image
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This kernel is written exclusively for convolution with ch_im_in
* equals 3. This applies on the first layer of CNNs which has input
* image with RGB format.
*/
void csky_vdsp2_convolve_HWC_q7_RGB(const q7_t * Im_in,
const uint16_t dim_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Q7 depthwise separable convolution function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 2
* ch_im_out is multiple of 2
*/
void csky_vdsp2_depthwise_separable_conv_HWC_q7(const q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out,
q15_t * bufferA);
/**
* @brief Q7 depthwise separable convolution function (non-square shape)
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in_x input tensor dimention x
* @param[in] dim_im_in_y input tensor dimention y
* @param[in] ch_im_in number of input tensor channels
* @param[in] wt pointer to kernel weights
* @param[in] ch_im_out number of filters, i.e., output tensor channels
* @param[in] dim_kernel_x filter kernel size x
* @param[in] dim_kernel_y filter kernel size y
* @param[in] padding_x padding sizes x
* @param[in] padding_y padding sizes y
* @param[in] stride_x convolution stride x
* @param[in] stride_y convolution stride y
* @param[in] bias pointer to bias
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in,out] Im_out pointer to output tensor
* @param[in] dim_im_out_x output tensor dimension x
* @param[in] dim_im_out_y output tensor dimension y
* @param[in,out] bufferA pointer to buffer space for input
* @return none.
*
* This function is the version with full list of optimization tricks, but with
* some contraints:
* ch_im_in is multiple of 2
* ch_im_out is multiple of 2
*/
void csky_vdsp2_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in,
const uint16_t dim_im_in_x,
const uint16_t dim_im_in_y,
const uint16_t ch_im_in,
const q7_t * wt,
const uint16_t ch_im_out,
const uint16_t dim_kernel_x,
const uint16_t dim_kernel_y,
const uint16_t padding_x,
const uint16_t padding_y,
const uint16_t stride_x,
const uint16_t stride_y,
const q7_t * bias,
const uint16_t bias_shift,
const uint16_t out_shift,
q7_t * Im_out,
const uint16_t dim_im_out_x,
const uint16_t dim_im_out_y,
q15_t * bufferA);
/**
* @brief Q7 basic fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*/
void csky_vdsp2_fully_connected_q7(const q7_t * pV,
const q7_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q7_t * pOut);
/**
* @brief Q15 basic fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*
*/
void csky_vdsp2_fully_connected_q15(const q15_t * pV,
const q15_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q15_t * bias,
q15_t * pOut);
/**
* @brief Mixed Q15-Q7 fully-connected layer function
* @param[in] pV pointer to input vector
* @param[in] pM pointer to matrix weights
* @param[in] dim_vec length of the vector
* @param[in] num_of_rows number of rows in weight matrix
* @param[in] bias_shift amount of left-shift for bias
* @param[in] out_shift amount of right-shift for output
* @param[in] bias pointer to bias
* @param[in,out] pOut pointer to output vector
* @return none.
*
*/
void csky_vdsp2_fully_connected_mat_q7_vec_q15(const q15_t * pV,
const q7_t * pM,
const uint16_t dim_vec,
const uint16_t num_of_rows,
const uint16_t bias_shift,
const uint16_t out_shift,
const q7_t * bias,
q15_t * pOut);
/**
* @brief Q7 RELU function
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @return none.
*/
void csky_vdsp2_relu_q7(q7_t * data, uint16_t size);
/**
* @brief Q15 RELU function
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @return none.
*/
void csky_vdsp2_relu_q15(q15_t * data, uint16_t size);
/**
* @brief Q7 neural network activation function using direct table look-up
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @param[in] int_width bit-width of the integer part, assume to be smaller than 3
* @param[in] type type of activation functions
* @return none.
*/
void csky_vdsp2_nn_activations_direct_q7(q7_t * data, uint16_t size,
uint16_t int_width,
csky_vdsp2_nn_activation_type type);
/**
* @brief Q15 neural network activation function using direct table look-up
* @param[in,out] data pointer to input
* @param[in] size number of elements
* @param[in] int_width bit-width of the integer part, assume to be smaller than 3
* @param[in] type type of activation functions
* @return none.
*/
void csky_vdsp2_nn_activations_direct_q15(q15_t * data, uint16_t size,
uint16_t int_width,
csky_vdsp2_nn_activation_type type);
/**
* @brief Q7 max pooling function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @param[in,out] Im_out pointer to output tensor
* @return none.
*
*/
void csky_vdsp2_maxpool_q7_HWC(q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const uint16_t dim_im_out,
q7_t * bufferA,
q7_t * Im_out);
/**
* @brief Q7 average pooling function
* @param[in] Im_in pointer to input tensor
* @param[in] dim_im_in input tensor dimention
* @param[in] ch_im_in number of input tensor channels
* @param[in] dim_kernel filter kernel size
* @param[in] padding padding sizes
* @param[in] stride convolution stride
* @param[in] dim_im_out output tensor dimension
* @param[in,out] bufferA pointer to buffer space for input
* @param[in,out] Im_out pointer to output tensor
* @return none.
*
*/
void csky_vdsp2_avepool_q7_HWC(q7_t * Im_in,
const uint16_t dim_im_in,
const uint16_t ch_im_in,
const uint16_t dim_kernel,
const uint16_t padding,
const uint16_t stride,
const uint16_t dim_im_out,
q7_t * bufferA,
q7_t * Im_out);
/**
* @brief Q7 softmax function
* @param[in] vec_in pointer to input vector
* @param[in] dim_vec input vector dimention
* @param[out] p_out pointer to output vector
* @return none.
*
*/
void csky_vdsp2_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out);
/**
* @brief Q15 softmax function
* @param[in] vec_in pointer to input vector
* @param[in] dim_vec input vector dimention
* @param[out] p_out pointer to output vector
* @return none.
*
*/
void csky_vdsp2_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec,
q15_t *p_out);
#ifdef __cplusplus
}
#endif
#endif
| YifuLiu/AliOS-Things | components/csi/csi2/nn/include/csky_vdsp2_nnfunctions.h | C | apache-2.0 | 24,045 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2020, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/* <DESC>
* Set working URL with CURLU *.
* </DESC>
*/
#include <stdio.h>
#include <curl/curl.h>
#if AOS_COMP_CLI
#include "aos/cli.h"
#endif
#if !CURL_AT_LEAST_VERSION(7, 62, 0)
#error "this example requires curl 7.62.0 or later"
#endif
static int main(void)
{
CURL *curl;
CURLcode res;
CURLU *urlp;
CURLUcode uc;
/* get a curl handle */
curl = curl_easy_init();
/* init Curl URL */
urlp = curl_url();
uc = curl_url_set(urlp, CURLUPART_URL,
"http://example.com/path/index.html", 0);
if(uc) {
fprintf(stderr, "curl_url_set() failed: %in", uc);
goto cleanup;
}
if(curl) {
/* set urlp to use as working URL */
curl_easy_setopt(curl, CURLOPT_CURLU, urlp);
curl_easy_setopt(curl, CURLOPT_VERBOSE, 1L);
res = curl_easy_perform(curl);
/* Check for errors */
if(res != CURLE_OK)
fprintf(stderr, "curl_easy_perform() failed: %s\n",
curl_easy_strerror(res));
goto cleanup;
}
cleanup:
curl_url_cleanup(urlp);
curl_easy_cleanup(curl);
return 0;
}
void curl_urlapi_example(int argc, char **argv)
{
main();
}
#if AOS_COMP_CLI
/* reg args: fun, cmd, description*/
ALIOS_CLI_CMD_REGISTER(curl_urlapi_example, curl_urlapi_example, curl component base example)
#endif
| YifuLiu/AliOS-Things | components/curl/example/urlapi.c | C | apache-2.0 | 2,301 |
#ifndef __CURL_CURL_H
#define __CURL_CURL_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/*
* If you have libcurl problems, all docs and details are found here:
* https://curl.haxx.se/libcurl/
*
* curl-library mailing list subscription and unsubscription web interface:
* https://cool.haxx.se/mailman/listinfo/curl-library/
*/
#ifdef CURL_NO_OLDIES
#define CURL_STRICTER
#endif
#include "curlver.h" /* libcurl version defines */
#include "system.h" /* determine things run-time */
/*
* Define WIN32 when build target is Win32 API
*/
#if (defined(_WIN32) || defined(__WIN32__)) && \
!defined(WIN32) && !defined(__SYMBIAN32__)
#define WIN32
#endif
#include <stdio.h>
#include <limits.h>
#if defined(__FreeBSD__) && (__FreeBSD__ >= 2)
/* Needed for __FreeBSD_version symbol definition */
#include <osreldate.h>
#endif
/* The include stuff here below is mainly for time_t! */
#include <sys/types.h>
#include <time.h>
#if defined(WIN32) && !defined(_WIN32_WCE) && !defined(__CYGWIN__)
#if !(defined(_WINSOCKAPI_) || defined(_WINSOCK_H) || \
defined(__LWIP_OPT_H__) || defined(LWIP_HDR_OPT_H))
/* The check above prevents the winsock2 inclusion if winsock.h already was
included, since they can't co-exist without problems */
#include <winsock2.h>
#include <ws2tcpip.h>
#endif
#endif
/* HP-UX systems version 9, 10 and 11 lack sys/select.h and so does oldish
libc5-based Linux systems. Only include it on systems that are known to
require it! */
#if defined(_AIX) || defined(__NOVELL_LIBC__) || defined(__NetBSD__) || \
defined(__minix) || defined(__SYMBIAN32__) || defined(__INTEGRITY) || \
defined(ANDROID) || defined(__ANDROID__) || defined(__OpenBSD__) || \
defined(__CYGWIN__) || \
(defined(__FreeBSD_version) && (__FreeBSD_version < 800000))
#include <sys/select.h>
#endif
#if !defined(WIN32) && !defined(_WIN32_WCE)
#ifdef USE_LWIPSOCK
#include <lwip/sockets.h>
#else
#include <sys/socket.h>
#endif
#endif
#if !defined(WIN32) && !defined(__WATCOMC__) && !defined(__VXWORKS__)
#include <sys/time.h>
#endif
#ifdef __BEOS__
#include <support/SupportDefs.h>
#endif
/* Compatibility for non-Clang compilers */
#ifndef __has_declspec_attribute
# define __has_declspec_attribute(x) 0
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BUILDING_LIBCURL) || defined(CURL_STRICTER)
typedef struct Curl_easy CURL;
typedef struct Curl_share CURLSH;
#else
typedef void CURL;
typedef void CURLSH;
#endif
/*
* libcurl external API function linkage decorations.
*/
#ifdef CURL_STATICLIB
# define CURL_EXTERN
#elif defined(WIN32) || defined(__SYMBIAN32__) || \
(__has_declspec_attribute(dllexport) && \
__has_declspec_attribute(dllimport))
# if defined(BUILDING_LIBCURL)
# define CURL_EXTERN __declspec(dllexport)
# else
# define CURL_EXTERN __declspec(dllimport)
# endif
#elif defined(BUILDING_LIBCURL) && defined(CURL_HIDDEN_SYMBOLS)
# define CURL_EXTERN CURL_EXTERN_SYMBOL
#else
# define CURL_EXTERN
#endif
#ifndef curl_socket_typedef
/* socket typedef */
#if defined(WIN32) && !defined(__LWIP_OPT_H__) && !defined(LWIP_HDR_OPT_H)
typedef SOCKET curl_socket_t;
#define CURL_SOCKET_BAD INVALID_SOCKET
#else
typedef int curl_socket_t;
#define CURL_SOCKET_BAD -1
#endif
#define curl_socket_typedef
#endif /* curl_socket_typedef */
/* enum for the different supported SSL backends */
typedef enum {
CURLSSLBACKEND_NONE = 0,
CURLSSLBACKEND_OPENSSL = 1,
CURLSSLBACKEND_GNUTLS = 2,
CURLSSLBACKEND_NSS = 3,
CURLSSLBACKEND_OBSOLETE4 = 4, /* Was QSOSSL. */
CURLSSLBACKEND_GSKIT = 5,
CURLSSLBACKEND_POLARSSL = 6,
CURLSSLBACKEND_WOLFSSL = 7,
CURLSSLBACKEND_SCHANNEL = 8,
CURLSSLBACKEND_SECURETRANSPORT = 9,
CURLSSLBACKEND_AXTLS = 10, /* never used since 7.63.0 */
CURLSSLBACKEND_MBEDTLS = 11,
CURLSSLBACKEND_MESALINK = 12
} curl_sslbackend;
/* aliases for library clones and renames */
#define CURLSSLBACKEND_LIBRESSL CURLSSLBACKEND_OPENSSL
#define CURLSSLBACKEND_BORINGSSL CURLSSLBACKEND_OPENSSL
/* deprecated names: */
#define CURLSSLBACKEND_CYASSL CURLSSLBACKEND_WOLFSSL
#define CURLSSLBACKEND_DARWINSSL CURLSSLBACKEND_SECURETRANSPORT
struct curl_httppost {
struct curl_httppost *next; /* next entry in the list */
char *name; /* pointer to allocated name */
long namelength; /* length of name length */
char *contents; /* pointer to allocated data contents */
long contentslength; /* length of contents field, see also
CURL_HTTPPOST_LARGE */
char *buffer; /* pointer to allocated buffer contents */
long bufferlength; /* length of buffer field */
char *contenttype; /* Content-Type */
struct curl_slist *contentheader; /* list of extra headers for this form */
struct curl_httppost *more; /* if one field name has more than one
file, this link should link to following
files */
long flags; /* as defined below */
/* specified content is a file name */
#define CURL_HTTPPOST_FILENAME (1<<0)
/* specified content is a file name */
#define CURL_HTTPPOST_READFILE (1<<1)
/* name is only stored pointer do not free in formfree */
#define CURL_HTTPPOST_PTRNAME (1<<2)
/* contents is only stored pointer do not free in formfree */
#define CURL_HTTPPOST_PTRCONTENTS (1<<3)
/* upload file from buffer */
#define CURL_HTTPPOST_BUFFER (1<<4)
/* upload file from pointer contents */
#define CURL_HTTPPOST_PTRBUFFER (1<<5)
/* upload file contents by using the regular read callback to get the data and
pass the given pointer as custom pointer */
#define CURL_HTTPPOST_CALLBACK (1<<6)
/* use size in 'contentlen', added in 7.46.0 */
#define CURL_HTTPPOST_LARGE (1<<7)
char *showfilename; /* The file name to show. If not set, the
actual file name will be used (if this
is a file part) */
void *userp; /* custom pointer used for
HTTPPOST_CALLBACK posts */
curl_off_t contentlen; /* alternative length of contents
field. Used if CURL_HTTPPOST_LARGE is
set. Added in 7.46.0 */
};
/* This is the CURLOPT_PROGRESSFUNCTION callback proto. It is now considered
deprecated but was the only choice up until 7.31.0 */
typedef int (*curl_progress_callback)(void *clientp,
double dltotal,
double dlnow,
double ultotal,
double ulnow);
/* This is the CURLOPT_XFERINFOFUNCTION callback proto. It was introduced in
7.32.0, it avoids floating point and provides more detailed information. */
typedef int (*curl_xferinfo_callback)(void *clientp,
curl_off_t dltotal,
curl_off_t dlnow,
curl_off_t ultotal,
curl_off_t ulnow);
#ifndef CURL_MAX_READ_SIZE
/* The maximum receive buffer size configurable via CURLOPT_BUFFERSIZE. */
#define CURL_MAX_READ_SIZE 524288
#endif
#ifndef CURL_MAX_WRITE_SIZE
/* Tests have proven that 20K is a very bad buffer size for uploads on
Windows, while 16K for some odd reason performed a lot better.
We do the ifndef check to allow this value to easier be changed at build
time for those who feel adventurous. The practical minimum is about
400 bytes since libcurl uses a buffer of this size as a scratch area
(unrelated to network send operations). */
#define CURL_MAX_WRITE_SIZE 16384
#endif
#ifndef CURL_MAX_HTTP_HEADER
/* The only reason to have a max limit for this is to avoid the risk of a bad
server feeding libcurl with a never-ending header that will cause reallocs
infinitely */
#define CURL_MAX_HTTP_HEADER (100*1024)
#endif
/* This is a magic return code for the write callback that, when returned,
will signal libcurl to pause receiving on the current transfer. */
#define CURL_WRITEFUNC_PAUSE 0x10000001
typedef size_t (*curl_write_callback)(char *buffer,
size_t size,
size_t nitems,
void *outstream);
/* This callback will be called when a new resolver request is made */
typedef int (*curl_resolver_start_callback)(void *resolver_state,
void *reserved, void *userdata);
/* enumeration of file types */
typedef enum {
CURLFILETYPE_FILE = 0,
CURLFILETYPE_DIRECTORY,
CURLFILETYPE_SYMLINK,
CURLFILETYPE_DEVICE_BLOCK,
CURLFILETYPE_DEVICE_CHAR,
CURLFILETYPE_NAMEDPIPE,
CURLFILETYPE_SOCKET,
CURLFILETYPE_DOOR, /* is possible only on Sun Solaris now */
CURLFILETYPE_UNKNOWN /* should never occur */
} curlfiletype;
#define CURLFINFOFLAG_KNOWN_FILENAME (1<<0)
#define CURLFINFOFLAG_KNOWN_FILETYPE (1<<1)
#define CURLFINFOFLAG_KNOWN_TIME (1<<2)
#define CURLFINFOFLAG_KNOWN_PERM (1<<3)
#define CURLFINFOFLAG_KNOWN_UID (1<<4)
#define CURLFINFOFLAG_KNOWN_GID (1<<5)
#define CURLFINFOFLAG_KNOWN_SIZE (1<<6)
#define CURLFINFOFLAG_KNOWN_HLINKCOUNT (1<<7)
/* Content of this structure depends on information which is known and is
achievable (e.g. by FTP LIST parsing). Please see the url_easy_setopt(3) man
page for callbacks returning this structure -- some fields are mandatory,
some others are optional. The FLAG field has special meaning. */
struct curl_fileinfo {
char *filename;
curlfiletype filetype;
time_t time; /* always zero! */
unsigned int perm;
int uid;
int gid;
curl_off_t size;
long int hardlinks;
struct {
/* If some of these fields is not NULL, it is a pointer to b_data. */
char *time;
char *perm;
char *user;
char *group;
char *target; /* pointer to the target filename of a symlink */
} strings;
unsigned int flags;
/* used internally */
char *b_data;
size_t b_size;
size_t b_used;
};
/* return codes for CURLOPT_CHUNK_BGN_FUNCTION */
#define CURL_CHUNK_BGN_FUNC_OK 0
#define CURL_CHUNK_BGN_FUNC_FAIL 1 /* tell the lib to end the task */
#define CURL_CHUNK_BGN_FUNC_SKIP 2 /* skip this chunk over */
/* if splitting of data transfer is enabled, this callback is called before
download of an individual chunk started. Note that parameter "remains" works
only for FTP wildcard downloading (for now), otherwise is not used */
typedef long (*curl_chunk_bgn_callback)(const void *transfer_info,
void *ptr,
int remains);
/* return codes for CURLOPT_CHUNK_END_FUNCTION */
#define CURL_CHUNK_END_FUNC_OK 0
#define CURL_CHUNK_END_FUNC_FAIL 1 /* tell the lib to end the task */
/* If splitting of data transfer is enabled this callback is called after
download of an individual chunk finished.
Note! After this callback was set then it have to be called FOR ALL chunks.
Even if downloading of this chunk was skipped in CHUNK_BGN_FUNC.
This is the reason why we don't need "transfer_info" parameter in this
callback and we are not interested in "remains" parameter too. */
typedef long (*curl_chunk_end_callback)(void *ptr);
/* return codes for FNMATCHFUNCTION */
#define CURL_FNMATCHFUNC_MATCH 0 /* string corresponds to the pattern */
#define CURL_FNMATCHFUNC_NOMATCH 1 /* pattern doesn't match the string */
#define CURL_FNMATCHFUNC_FAIL 2 /* an error occurred */
/* callback type for wildcard downloading pattern matching. If the
string matches the pattern, return CURL_FNMATCHFUNC_MATCH value, etc. */
typedef int (*curl_fnmatch_callback)(void *ptr,
const char *pattern,
const char *string);
/* These are the return codes for the seek callbacks */
#define CURL_SEEKFUNC_OK 0
#define CURL_SEEKFUNC_FAIL 1 /* fail the entire transfer */
#define CURL_SEEKFUNC_CANTSEEK 2 /* tell libcurl seeking can't be done, so
libcurl might try other means instead */
typedef int (*curl_seek_callback)(void *instream,
curl_off_t offset,
int origin); /* 'whence' */
/* This is a return code for the read callback that, when returned, will
signal libcurl to immediately abort the current transfer. */
#define CURL_READFUNC_ABORT 0x10000000
/* This is a return code for the read callback that, when returned, will
signal libcurl to pause sending data on the current transfer. */
#define CURL_READFUNC_PAUSE 0x10000001
/* Return code for when the trailing headers' callback has terminated
without any errors*/
#define CURL_TRAILERFUNC_OK 0
/* Return code for when was an error in the trailing header's list and we
want to abort the request */
#define CURL_TRAILERFUNC_ABORT 1
typedef size_t (*curl_read_callback)(char *buffer,
size_t size,
size_t nitems,
void *instream);
typedef int (*curl_trailer_callback)(struct curl_slist **list,
void *userdata);
typedef enum {
CURLSOCKTYPE_IPCXN, /* socket created for a specific IP connection */
CURLSOCKTYPE_ACCEPT, /* socket created by accept() call */
CURLSOCKTYPE_LAST /* never use */
} curlsocktype;
/* The return code from the sockopt_callback can signal information back
to libcurl: */
#define CURL_SOCKOPT_OK 0
#define CURL_SOCKOPT_ERROR 1 /* causes libcurl to abort and return
CURLE_ABORTED_BY_CALLBACK */
#define CURL_SOCKOPT_ALREADY_CONNECTED 2
typedef int (*curl_sockopt_callback)(void *clientp,
curl_socket_t curlfd,
curlsocktype purpose);
struct curl_sockaddr {
int family;
int socktype;
int protocol;
unsigned int addrlen; /* addrlen was a socklen_t type before 7.18.0 but it
turned really ugly and painful on the systems that
lack this type */
struct sockaddr addr;
};
typedef curl_socket_t
(*curl_opensocket_callback)(void *clientp,
curlsocktype purpose,
struct curl_sockaddr *address);
typedef int
(*curl_closesocket_callback)(void *clientp, curl_socket_t item);
typedef enum {
CURLIOE_OK, /* I/O operation successful */
CURLIOE_UNKNOWNCMD, /* command was unknown to callback */
CURLIOE_FAILRESTART, /* failed to restart the read */
CURLIOE_LAST /* never use */
} curlioerr;
typedef enum {
CURLIOCMD_NOP, /* no operation */
CURLIOCMD_RESTARTREAD, /* restart the read stream from start */
CURLIOCMD_LAST /* never use */
} curliocmd;
typedef curlioerr (*curl_ioctl_callback)(CURL *handle,
int cmd,
void *clientp);
#ifndef CURL_DID_MEMORY_FUNC_TYPEDEFS
/*
* The following typedef's are signatures of malloc, free, realloc, strdup and
* calloc respectively. Function pointers of these types can be passed to the
* curl_global_init_mem() function to set user defined memory management
* callback routines.
*/
typedef void *(*curl_malloc_callback)(size_t size);
typedef void (*curl_free_callback)(void *ptr);
typedef void *(*curl_realloc_callback)(void *ptr, size_t size);
typedef char *(*curl_strdup_callback)(const char *str);
typedef void *(*curl_calloc_callback)(size_t nmemb, size_t size);
#define CURL_DID_MEMORY_FUNC_TYPEDEFS
#endif
/* the kind of data that is passed to information_callback*/
typedef enum {
CURLINFO_TEXT = 0,
CURLINFO_HEADER_IN, /* 1 */
CURLINFO_HEADER_OUT, /* 2 */
CURLINFO_DATA_IN, /* 3 */
CURLINFO_DATA_OUT, /* 4 */
CURLINFO_SSL_DATA_IN, /* 5 */
CURLINFO_SSL_DATA_OUT, /* 6 */
CURLINFO_END
} curl_infotype;
typedef int (*curl_debug_callback)
(CURL *handle, /* the handle/transfer this concerns */
curl_infotype type, /* what kind of data */
char *data, /* points to the data */
size_t size, /* size of the data pointed to */
void *userptr); /* whatever the user please */
/* All possible error codes from all sorts of curl functions. Future versions
may return other values, stay prepared.
Always add new return codes last. Never *EVER* remove any. The return
codes must remain the same!
*/
typedef enum {
CURLE_OK = 0,
CURLE_UNSUPPORTED_PROTOCOL, /* 1 */
CURLE_FAILED_INIT, /* 2 */
CURLE_URL_MALFORMAT, /* 3 */
CURLE_NOT_BUILT_IN, /* 4 - [was obsoleted in August 2007 for
7.17.0, reused in April 2011 for 7.21.5] */
CURLE_COULDNT_RESOLVE_PROXY, /* 5 */
CURLE_COULDNT_RESOLVE_HOST, /* 6 */
CURLE_COULDNT_CONNECT, /* 7 */
CURLE_WEIRD_SERVER_REPLY, /* 8 */
CURLE_REMOTE_ACCESS_DENIED, /* 9 a service was denied by the server
due to lack of access - when login fails
this is not returned. */
CURLE_FTP_ACCEPT_FAILED, /* 10 - [was obsoleted in April 2006 for
7.15.4, reused in Dec 2011 for 7.24.0]*/
CURLE_FTP_WEIRD_PASS_REPLY, /* 11 */
CURLE_FTP_ACCEPT_TIMEOUT, /* 12 - timeout occurred accepting server
[was obsoleted in August 2007 for 7.17.0,
reused in Dec 2011 for 7.24.0]*/
CURLE_FTP_WEIRD_PASV_REPLY, /* 13 */
CURLE_FTP_WEIRD_227_FORMAT, /* 14 */
CURLE_FTP_CANT_GET_HOST, /* 15 */
CURLE_HTTP2, /* 16 - A problem in the http2 framing layer.
[was obsoleted in August 2007 for 7.17.0,
reused in July 2014 for 7.38.0] */
CURLE_FTP_COULDNT_SET_TYPE, /* 17 */
CURLE_PARTIAL_FILE, /* 18 */
CURLE_FTP_COULDNT_RETR_FILE, /* 19 */
CURLE_OBSOLETE20, /* 20 - NOT USED */
CURLE_QUOTE_ERROR, /* 21 - quote command failure */
CURLE_HTTP_RETURNED_ERROR, /* 22 */
CURLE_WRITE_ERROR, /* 23 */
CURLE_OBSOLETE24, /* 24 - NOT USED */
CURLE_UPLOAD_FAILED, /* 25 - failed upload "command" */
CURLE_READ_ERROR, /* 26 - couldn't open/read from file */
CURLE_OUT_OF_MEMORY, /* 27 */
/* Note: CURLE_OUT_OF_MEMORY may sometimes indicate a conversion error
instead of a memory allocation error if CURL_DOES_CONVERSIONS
is defined
*/
CURLE_OPERATION_TIMEDOUT, /* 28 - the timeout time was reached */
CURLE_OBSOLETE29, /* 29 - NOT USED */
CURLE_FTP_PORT_FAILED, /* 30 - FTP PORT operation failed */
CURLE_FTP_COULDNT_USE_REST, /* 31 - the REST command failed */
CURLE_OBSOLETE32, /* 32 - NOT USED */
CURLE_RANGE_ERROR, /* 33 - RANGE "command" didn't work */
CURLE_HTTP_POST_ERROR, /* 34 */
CURLE_SSL_CONNECT_ERROR, /* 35 - wrong when connecting with SSL */
CURLE_BAD_DOWNLOAD_RESUME, /* 36 - couldn't resume download */
CURLE_FILE_COULDNT_READ_FILE, /* 37 */
CURLE_LDAP_CANNOT_BIND, /* 38 */
CURLE_LDAP_SEARCH_FAILED, /* 39 */
CURLE_OBSOLETE40, /* 40 - NOT USED */
CURLE_FUNCTION_NOT_FOUND, /* 41 - NOT USED starting with 7.53.0 */
CURLE_ABORTED_BY_CALLBACK, /* 42 */
CURLE_BAD_FUNCTION_ARGUMENT, /* 43 */
CURLE_OBSOLETE44, /* 44 - NOT USED */
CURLE_INTERFACE_FAILED, /* 45 - CURLOPT_INTERFACE failed */
CURLE_OBSOLETE46, /* 46 - NOT USED */
CURLE_TOO_MANY_REDIRECTS, /* 47 - catch endless re-direct loops */
CURLE_UNKNOWN_OPTION, /* 48 - User specified an unknown option */
CURLE_TELNET_OPTION_SYNTAX, /* 49 - Malformed telnet option */
CURLE_OBSOLETE50, /* 50 - NOT USED */
CURLE_OBSOLETE51, /* 51 - NOT USED */
CURLE_GOT_NOTHING, /* 52 - when this is a specific error */
CURLE_SSL_ENGINE_NOTFOUND, /* 53 - SSL crypto engine not found */
CURLE_SSL_ENGINE_SETFAILED, /* 54 - can not set SSL crypto engine as
default */
CURLE_SEND_ERROR, /* 55 - failed sending network data */
CURLE_RECV_ERROR, /* 56 - failure in receiving network data */
CURLE_OBSOLETE57, /* 57 - NOT IN USE */
CURLE_SSL_CERTPROBLEM, /* 58 - problem with the local certificate */
CURLE_SSL_CIPHER, /* 59 - couldn't use specified cipher */
CURLE_PEER_FAILED_VERIFICATION, /* 60 - peer's certificate or fingerprint
wasn't verified fine */
CURLE_BAD_CONTENT_ENCODING, /* 61 - Unrecognized/bad encoding */
CURLE_LDAP_INVALID_URL, /* 62 - Invalid LDAP URL */
CURLE_FILESIZE_EXCEEDED, /* 63 - Maximum file size exceeded */
CURLE_USE_SSL_FAILED, /* 64 - Requested FTP SSL level failed */
CURLE_SEND_FAIL_REWIND, /* 65 - Sending the data requires a rewind
that failed */
CURLE_SSL_ENGINE_INITFAILED, /* 66 - failed to initialise ENGINE */
CURLE_LOGIN_DENIED, /* 67 - user, password or similar was not
accepted and we failed to login */
CURLE_TFTP_NOTFOUND, /* 68 - file not found on server */
CURLE_TFTP_PERM, /* 69 - permission problem on server */
CURLE_REMOTE_DISK_FULL, /* 70 - out of disk space on server */
CURLE_TFTP_ILLEGAL, /* 71 - Illegal TFTP operation */
CURLE_TFTP_UNKNOWNID, /* 72 - Unknown transfer ID */
CURLE_REMOTE_FILE_EXISTS, /* 73 - File already exists */
CURLE_TFTP_NOSUCHUSER, /* 74 - No such user */
CURLE_CONV_FAILED, /* 75 - conversion failed */
CURLE_CONV_REQD, /* 76 - caller must register conversion
callbacks using curl_easy_setopt options
CURLOPT_CONV_FROM_NETWORK_FUNCTION,
CURLOPT_CONV_TO_NETWORK_FUNCTION, and
CURLOPT_CONV_FROM_UTF8_FUNCTION */
CURLE_SSL_CACERT_BADFILE, /* 77 - could not load CACERT file, missing
or wrong format */
CURLE_REMOTE_FILE_NOT_FOUND, /* 78 - remote file not found */
CURLE_SSH, /* 79 - error from the SSH layer, somewhat
generic so the error message will be of
interest when this has happened */
CURLE_SSL_SHUTDOWN_FAILED, /* 80 - Failed to shut down the SSL
connection */
CURLE_AGAIN, /* 81 - socket is not ready for send/recv,
wait till it's ready and try again (Added
in 7.18.2) */
CURLE_SSL_CRL_BADFILE, /* 82 - could not load CRL file, missing or
wrong format (Added in 7.19.0) */
CURLE_SSL_ISSUER_ERROR, /* 83 - Issuer check failed. (Added in
7.19.0) */
CURLE_FTP_PRET_FAILED, /* 84 - a PRET command failed */
CURLE_RTSP_CSEQ_ERROR, /* 85 - mismatch of RTSP CSeq numbers */
CURLE_RTSP_SESSION_ERROR, /* 86 - mismatch of RTSP Session Ids */
CURLE_FTP_BAD_FILE_LIST, /* 87 - unable to parse FTP file list */
CURLE_CHUNK_FAILED, /* 88 - chunk callback reported error */
CURLE_NO_CONNECTION_AVAILABLE, /* 89 - No connection available, the
session will be queued */
CURLE_SSL_PINNEDPUBKEYNOTMATCH, /* 90 - specified pinned public key did not
match */
CURLE_SSL_INVALIDCERTSTATUS, /* 91 - invalid certificate status */
CURLE_HTTP2_STREAM, /* 92 - stream error in HTTP/2 framing layer
*/
CURLE_RECURSIVE_API_CALL, /* 93 - an api function was called from
inside a callback */
CURL_LAST /* never use! */
} CURLcode;
#ifndef CURL_NO_OLDIES /* define this to test if your app builds with all
the obsolete stuff removed! */
/* Previously obsolete error code re-used in 7.38.0 */
#define CURLE_OBSOLETE16 CURLE_HTTP2
/* Previously obsolete error codes re-used in 7.24.0 */
#define CURLE_OBSOLETE10 CURLE_FTP_ACCEPT_FAILED
#define CURLE_OBSOLETE12 CURLE_FTP_ACCEPT_TIMEOUT
/* compatibility with older names */
#define CURLOPT_ENCODING CURLOPT_ACCEPT_ENCODING
#define CURLE_FTP_WEIRD_SERVER_REPLY CURLE_WEIRD_SERVER_REPLY
/* The following were added in 7.62.0 */
#define CURLE_SSL_CACERT CURLE_PEER_FAILED_VERIFICATION
/* The following were added in 7.21.5, April 2011 */
#define CURLE_UNKNOWN_TELNET_OPTION CURLE_UNKNOWN_OPTION
/* The following were added in 7.17.1 */
/* These are scheduled to disappear by 2009 */
#define CURLE_SSL_PEER_CERTIFICATE CURLE_PEER_FAILED_VERIFICATION
/* The following were added in 7.17.0 */
/* These are scheduled to disappear by 2009 */
#define CURLE_OBSOLETE CURLE_OBSOLETE50 /* no one should be using this! */
#define CURLE_BAD_PASSWORD_ENTERED CURLE_OBSOLETE46
#define CURLE_BAD_CALLING_ORDER CURLE_OBSOLETE44
#define CURLE_FTP_USER_PASSWORD_INCORRECT CURLE_OBSOLETE10
#define CURLE_FTP_CANT_RECONNECT CURLE_OBSOLETE16
#define CURLE_FTP_COULDNT_GET_SIZE CURLE_OBSOLETE32
#define CURLE_FTP_COULDNT_SET_ASCII CURLE_OBSOLETE29
#define CURLE_FTP_WEIRD_USER_REPLY CURLE_OBSOLETE12
#define CURLE_FTP_WRITE_ERROR CURLE_OBSOLETE20
#define CURLE_LIBRARY_NOT_FOUND CURLE_OBSOLETE40
#define CURLE_MALFORMAT_USER CURLE_OBSOLETE24
#define CURLE_SHARE_IN_USE CURLE_OBSOLETE57
#define CURLE_URL_MALFORMAT_USER CURLE_NOT_BUILT_IN
#define CURLE_FTP_ACCESS_DENIED CURLE_REMOTE_ACCESS_DENIED
#define CURLE_FTP_COULDNT_SET_BINARY CURLE_FTP_COULDNT_SET_TYPE
#define CURLE_FTP_QUOTE_ERROR CURLE_QUOTE_ERROR
#define CURLE_TFTP_DISKFULL CURLE_REMOTE_DISK_FULL
#define CURLE_TFTP_EXISTS CURLE_REMOTE_FILE_EXISTS
#define CURLE_HTTP_RANGE_ERROR CURLE_RANGE_ERROR
#define CURLE_FTP_SSL_FAILED CURLE_USE_SSL_FAILED
/* The following were added earlier */
#define CURLE_OPERATION_TIMEOUTED CURLE_OPERATION_TIMEDOUT
#define CURLE_HTTP_NOT_FOUND CURLE_HTTP_RETURNED_ERROR
#define CURLE_HTTP_PORT_FAILED CURLE_INTERFACE_FAILED
#define CURLE_FTP_COULDNT_STOR_FILE CURLE_UPLOAD_FAILED
#define CURLE_FTP_PARTIAL_FILE CURLE_PARTIAL_FILE
#define CURLE_FTP_BAD_DOWNLOAD_RESUME CURLE_BAD_DOWNLOAD_RESUME
/* This was the error code 50 in 7.7.3 and a few earlier versions, this
is no longer used by libcurl but is instead #defined here only to not
make programs break */
#define CURLE_ALREADY_COMPLETE 99999
/* Provide defines for really old option names */
#define CURLOPT_FILE CURLOPT_WRITEDATA /* name changed in 7.9.7 */
#define CURLOPT_INFILE CURLOPT_READDATA /* name changed in 7.9.7 */
#define CURLOPT_WRITEHEADER CURLOPT_HEADERDATA
/* Since long deprecated options with no code in the lib that does anything
with them. */
#define CURLOPT_WRITEINFO CURLOPT_OBSOLETE40
#define CURLOPT_CLOSEPOLICY CURLOPT_OBSOLETE72
#endif /*!CURL_NO_OLDIES*/
/* This prototype applies to all conversion callbacks */
typedef CURLcode (*curl_conv_callback)(char *buffer, size_t length);
typedef CURLcode (*curl_ssl_ctx_callback)(CURL *curl, /* easy handle */
void *ssl_ctx, /* actually an
OpenSSL SSL_CTX */
void *userptr);
typedef enum {
CURLPROXY_HTTP = 0, /* added in 7.10, new in 7.19.4 default is to use
CONNECT HTTP/1.1 */
CURLPROXY_HTTP_1_0 = 1, /* added in 7.19.4, force to use CONNECT
HTTP/1.0 */
CURLPROXY_HTTPS = 2, /* added in 7.52.0 */
CURLPROXY_SOCKS4 = 4, /* support added in 7.15.2, enum existed already
in 7.10 */
CURLPROXY_SOCKS5 = 5, /* added in 7.10 */
CURLPROXY_SOCKS4A = 6, /* added in 7.18.0 */
CURLPROXY_SOCKS5_HOSTNAME = 7 /* Use the SOCKS5 protocol but pass along the
host name rather than the IP address. added
in 7.18.0 */
} curl_proxytype; /* this enum was added in 7.10 */
/*
* Bitmasks for CURLOPT_HTTPAUTH and CURLOPT_PROXYAUTH options:
*
* CURLAUTH_NONE - No HTTP authentication
* CURLAUTH_BASIC - HTTP Basic authentication (default)
* CURLAUTH_DIGEST - HTTP Digest authentication
* CURLAUTH_NEGOTIATE - HTTP Negotiate (SPNEGO) authentication
* CURLAUTH_GSSNEGOTIATE - Alias for CURLAUTH_NEGOTIATE (deprecated)
* CURLAUTH_NTLM - HTTP NTLM authentication
* CURLAUTH_DIGEST_IE - HTTP Digest authentication with IE flavour
* CURLAUTH_NTLM_WB - HTTP NTLM authentication delegated to winbind helper
* CURLAUTH_BEARER - HTTP Bearer token authentication
* CURLAUTH_ONLY - Use together with a single other type to force no
* authentication or just that single type
* CURLAUTH_ANY - All fine types set
* CURLAUTH_ANYSAFE - All fine types except Basic
*/
#define CURLAUTH_NONE ((unsigned long)0)
#define CURLAUTH_BASIC (((unsigned long)1)<<0)
#define CURLAUTH_DIGEST (((unsigned long)1)<<1)
#define CURLAUTH_NEGOTIATE (((unsigned long)1)<<2)
/* Deprecated since the advent of CURLAUTH_NEGOTIATE */
#define CURLAUTH_GSSNEGOTIATE CURLAUTH_NEGOTIATE
/* Used for CURLOPT_SOCKS5_AUTH to stay terminologically correct */
#define CURLAUTH_GSSAPI CURLAUTH_NEGOTIATE
#define CURLAUTH_NTLM (((unsigned long)1)<<3)
#define CURLAUTH_DIGEST_IE (((unsigned long)1)<<4)
#define CURLAUTH_NTLM_WB (((unsigned long)1)<<5)
#define CURLAUTH_BEARER (((unsigned long)1)<<6)
#define CURLAUTH_ONLY (((unsigned long)1)<<31)
#define CURLAUTH_ANY (~CURLAUTH_DIGEST_IE)
#define CURLAUTH_ANYSAFE (~(CURLAUTH_BASIC|CURLAUTH_DIGEST_IE))
#define CURLSSH_AUTH_ANY ~0 /* all types supported by the server */
#define CURLSSH_AUTH_NONE 0 /* none allowed, silly but complete */
#define CURLSSH_AUTH_PUBLICKEY (1<<0) /* public/private key files */
#define CURLSSH_AUTH_PASSWORD (1<<1) /* password */
#define CURLSSH_AUTH_HOST (1<<2) /* host key files */
#define CURLSSH_AUTH_KEYBOARD (1<<3) /* keyboard interactive */
#define CURLSSH_AUTH_AGENT (1<<4) /* agent (ssh-agent, pageant...) */
#define CURLSSH_AUTH_GSSAPI (1<<5) /* gssapi (kerberos, ...) */
#define CURLSSH_AUTH_DEFAULT CURLSSH_AUTH_ANY
#define CURLGSSAPI_DELEGATION_NONE 0 /* no delegation (default) */
#define CURLGSSAPI_DELEGATION_POLICY_FLAG (1<<0) /* if permitted by policy */
#define CURLGSSAPI_DELEGATION_FLAG (1<<1) /* delegate always */
#define CURL_ERROR_SIZE 256
enum curl_khtype {
CURLKHTYPE_UNKNOWN,
CURLKHTYPE_RSA1,
CURLKHTYPE_RSA,
CURLKHTYPE_DSS,
CURLKHTYPE_ECDSA,
CURLKHTYPE_ED25519
};
struct curl_khkey {
const char *key; /* points to a zero-terminated string encoded with base64
if len is zero, otherwise to the "raw" data */
size_t len;
enum curl_khtype keytype;
};
/* this is the set of return values expected from the curl_sshkeycallback
callback */
enum curl_khstat {
CURLKHSTAT_FINE_ADD_TO_FILE,
CURLKHSTAT_FINE,
CURLKHSTAT_REJECT, /* reject the connection, return an error */
CURLKHSTAT_DEFER, /* do not accept it, but we can't answer right now so
this causes a CURLE_DEFER error but otherwise the
connection will be left intact etc */
CURLKHSTAT_LAST /* not for use, only a marker for last-in-list */
};
/* this is the set of status codes pass in to the callback */
enum curl_khmatch {
CURLKHMATCH_OK, /* match */
CURLKHMATCH_MISMATCH, /* host found, key mismatch! */
CURLKHMATCH_MISSING, /* no matching host/key found */
CURLKHMATCH_LAST /* not for use, only a marker for last-in-list */
};
typedef int
(*curl_sshkeycallback) (CURL *easy, /* easy handle */
const struct curl_khkey *knownkey, /* known */
const struct curl_khkey *foundkey, /* found */
enum curl_khmatch, /* libcurl's view on the keys */
void *clientp); /* custom pointer passed from app */
/* parameter for the CURLOPT_USE_SSL option */
typedef enum {
CURLUSESSL_NONE, /* do not attempt to use SSL */
CURLUSESSL_TRY, /* try using SSL, proceed anyway otherwise */
CURLUSESSL_CONTROL, /* SSL for the control connection or fail */
CURLUSESSL_ALL, /* SSL for all communication or fail */
CURLUSESSL_LAST /* not an option, never use */
} curl_usessl;
/* Definition of bits for the CURLOPT_SSL_OPTIONS argument: */
/* - ALLOW_BEAST tells libcurl to allow the BEAST SSL vulnerability in the
name of improving interoperability with older servers. Some SSL libraries
have introduced work-arounds for this flaw but those work-arounds sometimes
make the SSL communication fail. To regain functionality with those broken
servers, a user can this way allow the vulnerability back. */
#define CURLSSLOPT_ALLOW_BEAST (1<<0)
/* - NO_REVOKE tells libcurl to disable certificate revocation checks for those
SSL backends where such behavior is present. */
#define CURLSSLOPT_NO_REVOKE (1<<1)
/* The default connection attempt delay in milliseconds for happy eyeballs.
CURLOPT_HAPPY_EYEBALLS_TIMEOUT_MS.3 and happy-eyeballs-timeout-ms.d document
this value, keep them in sync. */
#define CURL_HET_DEFAULT 200L
/* The default connection upkeep interval in milliseconds. */
#define CURL_UPKEEP_INTERVAL_DEFAULT 60000L
#ifndef CURL_NO_OLDIES /* define this to test if your app builds with all
the obsolete stuff removed! */
/* Backwards compatibility with older names */
/* These are scheduled to disappear by 2009 */
#define CURLFTPSSL_NONE CURLUSESSL_NONE
#define CURLFTPSSL_TRY CURLUSESSL_TRY
#define CURLFTPSSL_CONTROL CURLUSESSL_CONTROL
#define CURLFTPSSL_ALL CURLUSESSL_ALL
#define CURLFTPSSL_LAST CURLUSESSL_LAST
#define curl_ftpssl curl_usessl
#endif /*!CURL_NO_OLDIES*/
/* parameter for the CURLOPT_FTP_SSL_CCC option */
typedef enum {
CURLFTPSSL_CCC_NONE, /* do not send CCC */
CURLFTPSSL_CCC_PASSIVE, /* Let the server initiate the shutdown */
CURLFTPSSL_CCC_ACTIVE, /* Initiate the shutdown */
CURLFTPSSL_CCC_LAST /* not an option, never use */
} curl_ftpccc;
/* parameter for the CURLOPT_FTPSSLAUTH option */
typedef enum {
CURLFTPAUTH_DEFAULT, /* let libcurl decide */
CURLFTPAUTH_SSL, /* use "AUTH SSL" */
CURLFTPAUTH_TLS, /* use "AUTH TLS" */
CURLFTPAUTH_LAST /* not an option, never use */
} curl_ftpauth;
/* parameter for the CURLOPT_FTP_CREATE_MISSING_DIRS option */
typedef enum {
CURLFTP_CREATE_DIR_NONE, /* do NOT create missing dirs! */
CURLFTP_CREATE_DIR, /* (FTP/SFTP) if CWD fails, try MKD and then CWD
again if MKD succeeded, for SFTP this does
similar magic */
CURLFTP_CREATE_DIR_RETRY, /* (FTP only) if CWD fails, try MKD and then CWD
again even if MKD failed! */
CURLFTP_CREATE_DIR_LAST /* not an option, never use */
} curl_ftpcreatedir;
/* parameter for the CURLOPT_FTP_FILEMETHOD option */
typedef enum {
CURLFTPMETHOD_DEFAULT, /* let libcurl pick */
CURLFTPMETHOD_MULTICWD, /* single CWD operation for each path part */
CURLFTPMETHOD_NOCWD, /* no CWD at all */
CURLFTPMETHOD_SINGLECWD, /* one CWD to full dir, then work on file */
CURLFTPMETHOD_LAST /* not an option, never use */
} curl_ftpmethod;
/* bitmask defines for CURLOPT_HEADEROPT */
#define CURLHEADER_UNIFIED 0
#define CURLHEADER_SEPARATE (1<<0)
/* CURLALTSVC_* are bits for the CURLOPT_ALTSVC_CTRL option */
#define CURLALTSVC_IMMEDIATELY (1<<0)
#define CURLALTSVC_ALTUSED (1<<1)
#define CURLALTSVC_READONLYFILE (1<<2)
#define CURLALTSVC_H1 (1<<3)
#define CURLALTSVC_H2 (1<<4)
#define CURLALTSVC_H3 (1<<5)
/* CURLPROTO_ defines are for the CURLOPT_*PROTOCOLS options */
#define CURLPROTO_HTTP (1<<0)
#define CURLPROTO_HTTPS (1<<1)
#define CURLPROTO_FTP (1<<2)
#define CURLPROTO_FTPS (1<<3)
#define CURLPROTO_SCP (1<<4)
#define CURLPROTO_SFTP (1<<5)
#define CURLPROTO_TELNET (1<<6)
#define CURLPROTO_LDAP (1<<7)
#define CURLPROTO_LDAPS (1<<8)
#define CURLPROTO_DICT (1<<9)
#define CURLPROTO_FILE (1<<10)
#define CURLPROTO_TFTP (1<<11)
#define CURLPROTO_IMAP (1<<12)
#define CURLPROTO_IMAPS (1<<13)
#define CURLPROTO_POP3 (1<<14)
#define CURLPROTO_POP3S (1<<15)
#define CURLPROTO_SMTP (1<<16)
#define CURLPROTO_SMTPS (1<<17)
#define CURLPROTO_RTSP (1<<18)
#define CURLPROTO_RTMP (1<<19)
#define CURLPROTO_RTMPT (1<<20)
#define CURLPROTO_RTMPE (1<<21)
#define CURLPROTO_RTMPTE (1<<22)
#define CURLPROTO_RTMPS (1<<23)
#define CURLPROTO_RTMPTS (1<<24)
#define CURLPROTO_GOPHER (1<<25)
#define CURLPROTO_SMB (1<<26)
#define CURLPROTO_SMBS (1<<27)
#define CURLPROTO_ALL (~0) /* enable everything */
/* long may be 32 or 64 bits, but we should never depend on anything else
but 32 */
#define CURLOPTTYPE_LONG 0
#define CURLOPTTYPE_OBJECTPOINT 10000
#define CURLOPTTYPE_STRINGPOINT 10000
#define CURLOPTTYPE_FUNCTIONPOINT 20000
#define CURLOPTTYPE_OFF_T 30000
/* *STRINGPOINT is an alias for OBJECTPOINT to allow tools to extract the
string options from the header file */
/* name is uppercase CURLOPT_<name>,
type is one of the defined CURLOPTTYPE_<type>
number is unique identifier */
#ifdef CINIT
#undef CINIT
#endif
#ifdef CURL_ISOCPP
#define CINIT(na,t,nu) CURLOPT_ ## na = CURLOPTTYPE_ ## t + nu
#else
/* The macro "##" is ISO C, we assume pre-ISO C doesn't support it. */
#define LONG CURLOPTTYPE_LONG
#define OBJECTPOINT CURLOPTTYPE_OBJECTPOINT
#define STRINGPOINT CURLOPTTYPE_OBJECTPOINT
#define FUNCTIONPOINT CURLOPTTYPE_FUNCTIONPOINT
#define OFF_T CURLOPTTYPE_OFF_T
#define CINIT(name,type,number) CURLOPT_/**/name = type + number
#endif
/*
* This macro-mania below setups the CURLOPT_[what] enum, to be used with
* curl_easy_setopt(). The first argument in the CINIT() macro is the [what]
* word.
*/
typedef enum {
/* This is the FILE * or void * the regular output should be written to. */
CINIT(WRITEDATA, OBJECTPOINT, 1),
/* The full URL to get/put */
CINIT(URL, STRINGPOINT, 2),
/* Port number to connect to, if other than default. */
CINIT(PORT, LONG, 3),
/* Name of proxy to use. */
CINIT(PROXY, STRINGPOINT, 4),
/* "user:password;options" to use when fetching. */
CINIT(USERPWD, STRINGPOINT, 5),
/* "user:password" to use with proxy. */
CINIT(PROXYUSERPWD, STRINGPOINT, 6),
/* Range to get, specified as an ASCII string. */
CINIT(RANGE, STRINGPOINT, 7),
/* not used */
/* Specified file stream to upload from (use as input): */
CINIT(READDATA, OBJECTPOINT, 9),
/* Buffer to receive error messages in, must be at least CURL_ERROR_SIZE
* bytes big. */
CINIT(ERRORBUFFER, OBJECTPOINT, 10),
/* Function that will be called to store the output (instead of fwrite). The
* parameters will use fwrite() syntax, make sure to follow them. */
CINIT(WRITEFUNCTION, FUNCTIONPOINT, 11),
/* Function that will be called to read the input (instead of fread). The
* parameters will use fread() syntax, make sure to follow them. */
CINIT(READFUNCTION, FUNCTIONPOINT, 12),
/* Time-out the read operation after this amount of seconds */
CINIT(TIMEOUT, LONG, 13),
/* If the CURLOPT_INFILE is used, this can be used to inform libcurl about
* how large the file being sent really is. That allows better error
* checking and better verifies that the upload was successful. -1 means
* unknown size.
*
* For large file support, there is also a _LARGE version of the key
* which takes an off_t type, allowing platforms with larger off_t
* sizes to handle larger files. See below for INFILESIZE_LARGE.
*/
CINIT(INFILESIZE, LONG, 14),
/* POST static input fields. */
CINIT(POSTFIELDS, OBJECTPOINT, 15),
/* Set the referrer page (needed by some CGIs) */
CINIT(REFERER, STRINGPOINT, 16),
/* Set the FTP PORT string (interface name, named or numerical IP address)
Use i.e '-' to use default address. */
CINIT(FTPPORT, STRINGPOINT, 17),
/* Set the User-Agent string (examined by some CGIs) */
CINIT(USERAGENT, STRINGPOINT, 18),
/* If the download receives less than "low speed limit" bytes/second
* during "low speed time" seconds, the operations is aborted.
* You could i.e if you have a pretty high speed connection, abort if
* it is less than 2000 bytes/sec during 20 seconds.
*/
/* Set the "low speed limit" */
CINIT(LOW_SPEED_LIMIT, LONG, 19),
/* Set the "low speed time" */
CINIT(LOW_SPEED_TIME, LONG, 20),
/* Set the continuation offset.
*
* Note there is also a _LARGE version of this key which uses
* off_t types, allowing for large file offsets on platforms which
* use larger-than-32-bit off_t's. Look below for RESUME_FROM_LARGE.
*/
CINIT(RESUME_FROM, LONG, 21),
/* Set cookie in request: */
CINIT(COOKIE, STRINGPOINT, 22),
/* This points to a linked list of headers, struct curl_slist kind. This
list is also used for RTSP (in spite of its name) */
CINIT(HTTPHEADER, OBJECTPOINT, 23),
/* This points to a linked list of post entries, struct curl_httppost */
CINIT(HTTPPOST, OBJECTPOINT, 24),
/* name of the file keeping your private SSL-certificate */
CINIT(SSLCERT, STRINGPOINT, 25),
/* password for the SSL or SSH private key */
CINIT(KEYPASSWD, STRINGPOINT, 26),
/* send TYPE parameter? */
CINIT(CRLF, LONG, 27),
/* send linked-list of QUOTE commands */
CINIT(QUOTE, OBJECTPOINT, 28),
/* send FILE * or void * to store headers to, if you use a callback it
is simply passed to the callback unmodified */
CINIT(HEADERDATA, OBJECTPOINT, 29),
/* point to a file to read the initial cookies from, also enables
"cookie awareness" */
CINIT(COOKIEFILE, STRINGPOINT, 31),
/* What version to specifically try to use.
See CURL_SSLVERSION defines below. */
CINIT(SSLVERSION, LONG, 32),
/* What kind of HTTP time condition to use, see defines */
CINIT(TIMECONDITION, LONG, 33),
/* Time to use with the above condition. Specified in number of seconds
since 1 Jan 1970 */
CINIT(TIMEVALUE, LONG, 34),
/* 35 = OBSOLETE */
/* Custom request, for customizing the get command like
HTTP: DELETE, TRACE and others
FTP: to use a different list command
*/
CINIT(CUSTOMREQUEST, STRINGPOINT, 36),
/* FILE handle to use instead of stderr */
CINIT(STDERR, OBJECTPOINT, 37),
/* 38 is not used */
/* send linked-list of post-transfer QUOTE commands */
CINIT(POSTQUOTE, OBJECTPOINT, 39),
CINIT(OBSOLETE40, OBJECTPOINT, 40), /* OBSOLETE, do not use! */
CINIT(VERBOSE, LONG, 41), /* talk a lot */
CINIT(HEADER, LONG, 42), /* throw the header out too */
CINIT(NOPROGRESS, LONG, 43), /* shut off the progress meter */
CINIT(NOBODY, LONG, 44), /* use HEAD to get http document */
CINIT(FAILONERROR, LONG, 45), /* no output on http error codes >= 400 */
CINIT(UPLOAD, LONG, 46), /* this is an upload */
CINIT(POST, LONG, 47), /* HTTP POST method */
CINIT(DIRLISTONLY, LONG, 48), /* bare names when listing directories */
CINIT(APPEND, LONG, 50), /* Append instead of overwrite on upload! */
/* Specify whether to read the user+password from the .netrc or the URL.
* This must be one of the CURL_NETRC_* enums below. */
CINIT(NETRC, LONG, 51),
CINIT(FOLLOWLOCATION, LONG, 52), /* use Location: Luke! */
CINIT(TRANSFERTEXT, LONG, 53), /* transfer data in text/ASCII format */
CINIT(PUT, LONG, 54), /* HTTP PUT */
/* 55 = OBSOLETE */
/* DEPRECATED
* Function that will be called instead of the internal progress display
* function. This function should be defined as the curl_progress_callback
* prototype defines. */
CINIT(PROGRESSFUNCTION, FUNCTIONPOINT, 56),
/* Data passed to the CURLOPT_PROGRESSFUNCTION and CURLOPT_XFERINFOFUNCTION
callbacks */
CINIT(PROGRESSDATA, OBJECTPOINT, 57),
#define CURLOPT_XFERINFODATA CURLOPT_PROGRESSDATA
/* We want the referrer field set automatically when following locations */
CINIT(AUTOREFERER, LONG, 58),
/* Port of the proxy, can be set in the proxy string as well with:
"[host]:[port]" */
CINIT(PROXYPORT, LONG, 59),
/* size of the POST input data, if strlen() is not good to use */
CINIT(POSTFIELDSIZE, LONG, 60),
/* tunnel non-http operations through a HTTP proxy */
CINIT(HTTPPROXYTUNNEL, LONG, 61),
/* Set the interface string to use as outgoing network interface */
CINIT(INTERFACE, STRINGPOINT, 62),
/* Set the krb4/5 security level, this also enables krb4/5 awareness. This
* is a string, 'clear', 'safe', 'confidential' or 'private'. If the string
* is set but doesn't match one of these, 'private' will be used. */
CINIT(KRBLEVEL, STRINGPOINT, 63),
/* Set if we should verify the peer in ssl handshake, set 1 to verify. */
CINIT(SSL_VERIFYPEER, LONG, 64),
/* The CApath or CAfile used to validate the peer certificate
this option is used only if SSL_VERIFYPEER is true */
CINIT(CAINFO, STRINGPOINT, 65),
/* 66 = OBSOLETE */
/* 67 = OBSOLETE */
/* Maximum number of http redirects to follow */
CINIT(MAXREDIRS, LONG, 68),
/* Pass a long set to 1 to get the date of the requested document (if
possible)! Pass a zero to shut it off. */
CINIT(FILETIME, LONG, 69),
/* This points to a linked list of telnet options */
CINIT(TELNETOPTIONS, OBJECTPOINT, 70),
/* Max amount of cached alive connections */
CINIT(MAXCONNECTS, LONG, 71),
CINIT(OBSOLETE72, LONG, 72), /* OBSOLETE, do not use! */
/* 73 = OBSOLETE */
/* Set to explicitly use a new connection for the upcoming transfer.
Do not use this unless you're absolutely sure of this, as it makes the
operation slower and is less friendly for the network. */
CINIT(FRESH_CONNECT, LONG, 74),
/* Set to explicitly forbid the upcoming transfer's connection to be re-used
when done. Do not use this unless you're absolutely sure of this, as it
makes the operation slower and is less friendly for the network. */
CINIT(FORBID_REUSE, LONG, 75),
/* Set to a file name that contains random data for libcurl to use to
seed the random engine when doing SSL connects. */
CINIT(RANDOM_FILE, STRINGPOINT, 76),
/* Set to the Entropy Gathering Daemon socket pathname */
CINIT(EGDSOCKET, STRINGPOINT, 77),
/* Time-out connect operations after this amount of seconds, if connects are
OK within this time, then fine... This only aborts the connect phase. */
CINIT(CONNECTTIMEOUT, LONG, 78),
/* Function that will be called to store headers (instead of fwrite). The
* parameters will use fwrite() syntax, make sure to follow them. */
CINIT(HEADERFUNCTION, FUNCTIONPOINT, 79),
/* Set this to force the HTTP request to get back to GET. Only really usable
if POST, PUT or a custom request have been used first.
*/
CINIT(HTTPGET, LONG, 80),
/* Set if we should verify the Common name from the peer certificate in ssl
* handshake, set 1 to check existence, 2 to ensure that it matches the
* provided hostname. */
CINIT(SSL_VERIFYHOST, LONG, 81),
/* Specify which file name to write all known cookies in after completed
operation. Set file name to "-" (dash) to make it go to stdout. */
CINIT(COOKIEJAR, STRINGPOINT, 82),
/* Specify which SSL ciphers to use */
CINIT(SSL_CIPHER_LIST, STRINGPOINT, 83),
/* Specify which HTTP version to use! This must be set to one of the
CURL_HTTP_VERSION* enums set below. */
CINIT(HTTP_VERSION, LONG, 84),
/* Specifically switch on or off the FTP engine's use of the EPSV command. By
default, that one will always be attempted before the more traditional
PASV command. */
CINIT(FTP_USE_EPSV, LONG, 85),
/* type of the file keeping your SSL-certificate ("DER", "PEM", "ENG") */
CINIT(SSLCERTTYPE, STRINGPOINT, 86),
/* name of the file keeping your private SSL-key */
CINIT(SSLKEY, STRINGPOINT, 87),
/* type of the file keeping your private SSL-key ("DER", "PEM", "ENG") */
CINIT(SSLKEYTYPE, STRINGPOINT, 88),
/* crypto engine for the SSL-sub system */
CINIT(SSLENGINE, STRINGPOINT, 89),
/* set the crypto engine for the SSL-sub system as default
the param has no meaning...
*/
CINIT(SSLENGINE_DEFAULT, LONG, 90),
/* Non-zero value means to use the global dns cache */
CINIT(DNS_USE_GLOBAL_CACHE, LONG, 91), /* DEPRECATED, do not use! */
/* DNS cache timeout */
CINIT(DNS_CACHE_TIMEOUT, LONG, 92),
/* send linked-list of pre-transfer QUOTE commands */
CINIT(PREQUOTE, OBJECTPOINT, 93),
/* set the debug function */
CINIT(DEBUGFUNCTION, FUNCTIONPOINT, 94),
/* set the data for the debug function */
CINIT(DEBUGDATA, OBJECTPOINT, 95),
/* mark this as start of a cookie session */
CINIT(COOKIESESSION, LONG, 96),
/* The CApath directory used to validate the peer certificate
this option is used only if SSL_VERIFYPEER is true */
CINIT(CAPATH, STRINGPOINT, 97),
/* Instruct libcurl to use a smaller receive buffer */
CINIT(BUFFERSIZE, LONG, 98),
/* Instruct libcurl to not use any signal/alarm handlers, even when using
timeouts. This option is useful for multi-threaded applications.
See libcurl-the-guide for more background information. */
CINIT(NOSIGNAL, LONG, 99),
/* Provide a CURLShare for mutexing non-ts data */
CINIT(SHARE, OBJECTPOINT, 100),
/* indicates type of proxy. accepted values are CURLPROXY_HTTP (default),
CURLPROXY_HTTPS, CURLPROXY_SOCKS4, CURLPROXY_SOCKS4A and
CURLPROXY_SOCKS5. */
CINIT(PROXYTYPE, LONG, 101),
/* Set the Accept-Encoding string. Use this to tell a server you would like
the response to be compressed. Before 7.21.6, this was known as
CURLOPT_ENCODING */
CINIT(ACCEPT_ENCODING, STRINGPOINT, 102),
/* Set pointer to private data */
CINIT(PRIVATE, OBJECTPOINT, 103),
/* Set aliases for HTTP 200 in the HTTP Response header */
CINIT(HTTP200ALIASES, OBJECTPOINT, 104),
/* Continue to send authentication (user+password) when following locations,
even when hostname changed. This can potentially send off the name
and password to whatever host the server decides. */
CINIT(UNRESTRICTED_AUTH, LONG, 105),
/* Specifically switch on or off the FTP engine's use of the EPRT command (
it also disables the LPRT attempt). By default, those ones will always be
attempted before the good old traditional PORT command. */
CINIT(FTP_USE_EPRT, LONG, 106),
/* Set this to a bitmask value to enable the particular authentications
methods you like. Use this in combination with CURLOPT_USERPWD.
Note that setting multiple bits may cause extra network round-trips. */
CINIT(HTTPAUTH, LONG, 107),
/* Set the ssl context callback function, currently only for OpenSSL ssl_ctx
in second argument. The function must be matching the
curl_ssl_ctx_callback proto. */
CINIT(SSL_CTX_FUNCTION, FUNCTIONPOINT, 108),
/* Set the userdata for the ssl context callback function's third
argument */
CINIT(SSL_CTX_DATA, OBJECTPOINT, 109),
/* FTP Option that causes missing dirs to be created on the remote server.
In 7.19.4 we introduced the convenience enums for this option using the
CURLFTP_CREATE_DIR prefix.
*/
CINIT(FTP_CREATE_MISSING_DIRS, LONG, 110),
/* Set this to a bitmask value to enable the particular authentications
methods you like. Use this in combination with CURLOPT_PROXYUSERPWD.
Note that setting multiple bits may cause extra network round-trips. */
CINIT(PROXYAUTH, LONG, 111),
/* FTP option that changes the timeout, in seconds, associated with
getting a response. This is different from transfer timeout time and
essentially places a demand on the FTP server to acknowledge commands
in a timely manner. */
CINIT(FTP_RESPONSE_TIMEOUT, LONG, 112),
#define CURLOPT_SERVER_RESPONSE_TIMEOUT CURLOPT_FTP_RESPONSE_TIMEOUT
/* Set this option to one of the CURL_IPRESOLVE_* defines (see below) to
tell libcurl to resolve names to those IP versions only. This only has
affect on systems with support for more than one, i.e IPv4 _and_ IPv6. */
CINIT(IPRESOLVE, LONG, 113),
/* Set this option to limit the size of a file that will be downloaded from
an HTTP or FTP server.
Note there is also _LARGE version which adds large file support for
platforms which have larger off_t sizes. See MAXFILESIZE_LARGE below. */
CINIT(MAXFILESIZE, LONG, 114),
/* See the comment for INFILESIZE above, but in short, specifies
* the size of the file being uploaded. -1 means unknown.
*/
CINIT(INFILESIZE_LARGE, OFF_T, 115),
/* Sets the continuation offset. There is also a LONG version of this;
* look above for RESUME_FROM.
*/
CINIT(RESUME_FROM_LARGE, OFF_T, 116),
/* Sets the maximum size of data that will be downloaded from
* an HTTP or FTP server. See MAXFILESIZE above for the LONG version.
*/
CINIT(MAXFILESIZE_LARGE, OFF_T, 117),
/* Set this option to the file name of your .netrc file you want libcurl
to parse (using the CURLOPT_NETRC option). If not set, libcurl will do
a poor attempt to find the user's home directory and check for a .netrc
file in there. */
CINIT(NETRC_FILE, STRINGPOINT, 118),
/* Enable SSL/TLS for FTP, pick one of:
CURLUSESSL_TRY - try using SSL, proceed anyway otherwise
CURLUSESSL_CONTROL - SSL for the control connection or fail
CURLUSESSL_ALL - SSL for all communication or fail
*/
CINIT(USE_SSL, LONG, 119),
/* The _LARGE version of the standard POSTFIELDSIZE option */
CINIT(POSTFIELDSIZE_LARGE, OFF_T, 120),
/* Enable/disable the TCP Nagle algorithm */
CINIT(TCP_NODELAY, LONG, 121),
/* 122 OBSOLETE, used in 7.12.3. Gone in 7.13.0 */
/* 123 OBSOLETE. Gone in 7.16.0 */
/* 124 OBSOLETE, used in 7.12.3. Gone in 7.13.0 */
/* 125 OBSOLETE, used in 7.12.3. Gone in 7.13.0 */
/* 126 OBSOLETE, used in 7.12.3. Gone in 7.13.0 */
/* 127 OBSOLETE. Gone in 7.16.0 */
/* 128 OBSOLETE. Gone in 7.16.0 */
/* When FTP over SSL/TLS is selected (with CURLOPT_USE_SSL), this option
can be used to change libcurl's default action which is to first try
"AUTH SSL" and then "AUTH TLS" in this order, and proceed when a OK
response has been received.
Available parameters are:
CURLFTPAUTH_DEFAULT - let libcurl decide
CURLFTPAUTH_SSL - try "AUTH SSL" first, then TLS
CURLFTPAUTH_TLS - try "AUTH TLS" first, then SSL
*/
CINIT(FTPSSLAUTH, LONG, 129),
CINIT(IOCTLFUNCTION, FUNCTIONPOINT, 130),
CINIT(IOCTLDATA, OBJECTPOINT, 131),
/* 132 OBSOLETE. Gone in 7.16.0 */
/* 133 OBSOLETE. Gone in 7.16.0 */
/* zero terminated string for pass on to the FTP server when asked for
"account" info */
CINIT(FTP_ACCOUNT, STRINGPOINT, 134),
/* feed cookie into cookie engine */
CINIT(COOKIELIST, STRINGPOINT, 135),
/* ignore Content-Length */
CINIT(IGNORE_CONTENT_LENGTH, LONG, 136),
/* Set to non-zero to skip the IP address received in a 227 PASV FTP server
response. Typically used for FTP-SSL purposes but is not restricted to
that. libcurl will then instead use the same IP address it used for the
control connection. */
CINIT(FTP_SKIP_PASV_IP, LONG, 137),
/* Select "file method" to use when doing FTP, see the curl_ftpmethod
above. */
CINIT(FTP_FILEMETHOD, LONG, 138),
/* Local port number to bind the socket to */
CINIT(LOCALPORT, LONG, 139),
/* Number of ports to try, including the first one set with LOCALPORT.
Thus, setting it to 1 will make no additional attempts but the first.
*/
CINIT(LOCALPORTRANGE, LONG, 140),
/* no transfer, set up connection and let application use the socket by
extracting it with CURLINFO_LASTSOCKET */
CINIT(CONNECT_ONLY, LONG, 141),
/* Function that will be called to convert from the
network encoding (instead of using the iconv calls in libcurl) */
CINIT(CONV_FROM_NETWORK_FUNCTION, FUNCTIONPOINT, 142),
/* Function that will be called to convert to the
network encoding (instead of using the iconv calls in libcurl) */
CINIT(CONV_TO_NETWORK_FUNCTION, FUNCTIONPOINT, 143),
/* Function that will be called to convert from UTF8
(instead of using the iconv calls in libcurl)
Note that this is used only for SSL certificate processing */
CINIT(CONV_FROM_UTF8_FUNCTION, FUNCTIONPOINT, 144),
/* if the connection proceeds too quickly then need to slow it down */
/* limit-rate: maximum number of bytes per second to send or receive */
CINIT(MAX_SEND_SPEED_LARGE, OFF_T, 145),
CINIT(MAX_RECV_SPEED_LARGE, OFF_T, 146),
/* Pointer to command string to send if USER/PASS fails. */
CINIT(FTP_ALTERNATIVE_TO_USER, STRINGPOINT, 147),
/* callback function for setting socket options */
CINIT(SOCKOPTFUNCTION, FUNCTIONPOINT, 148),
CINIT(SOCKOPTDATA, OBJECTPOINT, 149),
/* set to 0 to disable session ID re-use for this transfer, default is
enabled (== 1) */
CINIT(SSL_SESSIONID_CACHE, LONG, 150),
/* allowed SSH authentication methods */
CINIT(SSH_AUTH_TYPES, LONG, 151),
/* Used by scp/sftp to do public/private key authentication */
CINIT(SSH_PUBLIC_KEYFILE, STRINGPOINT, 152),
CINIT(SSH_PRIVATE_KEYFILE, STRINGPOINT, 153),
/* Send CCC (Clear Command Channel) after authentication */
CINIT(FTP_SSL_CCC, LONG, 154),
/* Same as TIMEOUT and CONNECTTIMEOUT, but with ms resolution */
CINIT(TIMEOUT_MS, LONG, 155),
CINIT(CONNECTTIMEOUT_MS, LONG, 156),
/* set to zero to disable the libcurl's decoding and thus pass the raw body
data to the application even when it is encoded/compressed */
CINIT(HTTP_TRANSFER_DECODING, LONG, 157),
CINIT(HTTP_CONTENT_DECODING, LONG, 158),
/* Permission used when creating new files and directories on the remote
server for protocols that support it, SFTP/SCP/FILE */
CINIT(NEW_FILE_PERMS, LONG, 159),
CINIT(NEW_DIRECTORY_PERMS, LONG, 160),
/* Set the behaviour of POST when redirecting. Values must be set to one
of CURL_REDIR* defines below. This used to be called CURLOPT_POST301 */
CINIT(POSTREDIR, LONG, 161),
/* used by scp/sftp to verify the host's public key */
CINIT(SSH_HOST_PUBLIC_KEY_MD5, STRINGPOINT, 162),
/* Callback function for opening socket (instead of socket(2)). Optionally,
callback is able change the address or refuse to connect returning
CURL_SOCKET_BAD. The callback should have type
curl_opensocket_callback */
CINIT(OPENSOCKETFUNCTION, FUNCTIONPOINT, 163),
CINIT(OPENSOCKETDATA, OBJECTPOINT, 164),
/* POST volatile input fields. */
CINIT(COPYPOSTFIELDS, OBJECTPOINT, 165),
/* set transfer mode (;type=<a|i>) when doing FTP via an HTTP proxy */
CINIT(PROXY_TRANSFER_MODE, LONG, 166),
/* Callback function for seeking in the input stream */
CINIT(SEEKFUNCTION, FUNCTIONPOINT, 167),
CINIT(SEEKDATA, OBJECTPOINT, 168),
/* CRL file */
CINIT(CRLFILE, STRINGPOINT, 169),
/* Issuer certificate */
CINIT(ISSUERCERT, STRINGPOINT, 170),
/* (IPv6) Address scope */
CINIT(ADDRESS_SCOPE, LONG, 171),
/* Collect certificate chain info and allow it to get retrievable with
CURLINFO_CERTINFO after the transfer is complete. */
CINIT(CERTINFO, LONG, 172),
/* "name" and "pwd" to use when fetching. */
CINIT(USERNAME, STRINGPOINT, 173),
CINIT(PASSWORD, STRINGPOINT, 174),
/* "name" and "pwd" to use with Proxy when fetching. */
CINIT(PROXYUSERNAME, STRINGPOINT, 175),
CINIT(PROXYPASSWORD, STRINGPOINT, 176),
/* Comma separated list of hostnames defining no-proxy zones. These should
match both hostnames directly, and hostnames within a domain. For
example, local.com will match local.com and www.local.com, but NOT
notlocal.com or www.notlocal.com. For compatibility with other
implementations of this, .local.com will be considered to be the same as
local.com. A single * is the only valid wildcard, and effectively
disables the use of proxy. */
CINIT(NOPROXY, STRINGPOINT, 177),
/* block size for TFTP transfers */
CINIT(TFTP_BLKSIZE, LONG, 178),
/* Socks Service */
CINIT(SOCKS5_GSSAPI_SERVICE, STRINGPOINT, 179), /* DEPRECATED, do not use! */
/* Socks Service */
CINIT(SOCKS5_GSSAPI_NEC, LONG, 180),
/* set the bitmask for the protocols that are allowed to be used for the
transfer, which thus helps the app which takes URLs from users or other
external inputs and want to restrict what protocol(s) to deal
with. Defaults to CURLPROTO_ALL. */
CINIT(PROTOCOLS, LONG, 181),
/* set the bitmask for the protocols that libcurl is allowed to follow to,
as a subset of the CURLOPT_PROTOCOLS ones. That means the protocol needs
to be set in both bitmasks to be allowed to get redirected to. Defaults
to all protocols except FILE and SCP. */
CINIT(REDIR_PROTOCOLS, LONG, 182),
/* set the SSH knownhost file name to use */
CINIT(SSH_KNOWNHOSTS, STRINGPOINT, 183),
/* set the SSH host key callback, must point to a curl_sshkeycallback
function */
CINIT(SSH_KEYFUNCTION, FUNCTIONPOINT, 184),
/* set the SSH host key callback custom pointer */
CINIT(SSH_KEYDATA, OBJECTPOINT, 185),
/* set the SMTP mail originator */
CINIT(MAIL_FROM, STRINGPOINT, 186),
/* set the list of SMTP mail receiver(s) */
CINIT(MAIL_RCPT, OBJECTPOINT, 187),
/* FTP: send PRET before PASV */
CINIT(FTP_USE_PRET, LONG, 188),
/* RTSP request method (OPTIONS, SETUP, PLAY, etc...) */
CINIT(RTSP_REQUEST, LONG, 189),
/* The RTSP session identifier */
CINIT(RTSP_SESSION_ID, STRINGPOINT, 190),
/* The RTSP stream URI */
CINIT(RTSP_STREAM_URI, STRINGPOINT, 191),
/* The Transport: header to use in RTSP requests */
CINIT(RTSP_TRANSPORT, STRINGPOINT, 192),
/* Manually initialize the client RTSP CSeq for this handle */
CINIT(RTSP_CLIENT_CSEQ, LONG, 193),
/* Manually initialize the server RTSP CSeq for this handle */
CINIT(RTSP_SERVER_CSEQ, LONG, 194),
/* The stream to pass to INTERLEAVEFUNCTION. */
CINIT(INTERLEAVEDATA, OBJECTPOINT, 195),
/* Let the application define a custom write method for RTP data */
CINIT(INTERLEAVEFUNCTION, FUNCTIONPOINT, 196),
/* Turn on wildcard matching */
CINIT(WILDCARDMATCH, LONG, 197),
/* Directory matching callback called before downloading of an
individual file (chunk) started */
CINIT(CHUNK_BGN_FUNCTION, FUNCTIONPOINT, 198),
/* Directory matching callback called after the file (chunk)
was downloaded, or skipped */
CINIT(CHUNK_END_FUNCTION, FUNCTIONPOINT, 199),
/* Change match (fnmatch-like) callback for wildcard matching */
CINIT(FNMATCH_FUNCTION, FUNCTIONPOINT, 200),
/* Let the application define custom chunk data pointer */
CINIT(CHUNK_DATA, OBJECTPOINT, 201),
/* FNMATCH_FUNCTION user pointer */
CINIT(FNMATCH_DATA, OBJECTPOINT, 202),
/* send linked-list of name:port:address sets */
CINIT(RESOLVE, OBJECTPOINT, 203),
/* Set a username for authenticated TLS */
CINIT(TLSAUTH_USERNAME, STRINGPOINT, 204),
/* Set a password for authenticated TLS */
CINIT(TLSAUTH_PASSWORD, STRINGPOINT, 205),
/* Set authentication type for authenticated TLS */
CINIT(TLSAUTH_TYPE, STRINGPOINT, 206),
/* Set to 1 to enable the "TE:" header in HTTP requests to ask for
compressed transfer-encoded responses. Set to 0 to disable the use of TE:
in outgoing requests. The current default is 0, but it might change in a
future libcurl release.
libcurl will ask for the compressed methods it knows of, and if that
isn't any, it will not ask for transfer-encoding at all even if this
option is set to 1.
*/
CINIT(TRANSFER_ENCODING, LONG, 207),
/* Callback function for closing socket (instead of close(2)). The callback
should have type curl_closesocket_callback */
CINIT(CLOSESOCKETFUNCTION, FUNCTIONPOINT, 208),
CINIT(CLOSESOCKETDATA, OBJECTPOINT, 209),
/* allow GSSAPI credential delegation */
CINIT(GSSAPI_DELEGATION, LONG, 210),
/* Set the name servers to use for DNS resolution */
CINIT(DNS_SERVERS, STRINGPOINT, 211),
/* Time-out accept operations (currently for FTP only) after this amount
of milliseconds. */
CINIT(ACCEPTTIMEOUT_MS, LONG, 212),
/* Set TCP keepalive */
CINIT(TCP_KEEPALIVE, LONG, 213),
/* non-universal keepalive knobs (Linux, AIX, HP-UX, more) */
CINIT(TCP_KEEPIDLE, LONG, 214),
CINIT(TCP_KEEPINTVL, LONG, 215),
/* Enable/disable specific SSL features with a bitmask, see CURLSSLOPT_* */
CINIT(SSL_OPTIONS, LONG, 216),
/* Set the SMTP auth originator */
CINIT(MAIL_AUTH, STRINGPOINT, 217),
/* Enable/disable SASL initial response */
CINIT(SASL_IR, LONG, 218),
/* Function that will be called instead of the internal progress display
* function. This function should be defined as the curl_xferinfo_callback
* prototype defines. (Deprecates CURLOPT_PROGRESSFUNCTION) */
CINIT(XFERINFOFUNCTION, FUNCTIONPOINT, 219),
/* The XOAUTH2 bearer token */
CINIT(XOAUTH2_BEARER, STRINGPOINT, 220),
/* Set the interface string to use as outgoing network
* interface for DNS requests.
* Only supported by the c-ares DNS backend */
CINIT(DNS_INTERFACE, STRINGPOINT, 221),
/* Set the local IPv4 address to use for outgoing DNS requests.
* Only supported by the c-ares DNS backend */
CINIT(DNS_LOCAL_IP4, STRINGPOINT, 222),
/* Set the local IPv6 address to use for outgoing DNS requests.
* Only supported by the c-ares DNS backend */
CINIT(DNS_LOCAL_IP6, STRINGPOINT, 223),
/* Set authentication options directly */
CINIT(LOGIN_OPTIONS, STRINGPOINT, 224),
/* Enable/disable TLS NPN extension (http2 over ssl might fail without) */
CINIT(SSL_ENABLE_NPN, LONG, 225),
/* Enable/disable TLS ALPN extension (http2 over ssl might fail without) */
CINIT(SSL_ENABLE_ALPN, LONG, 226),
/* Time to wait for a response to a HTTP request containing an
* Expect: 100-continue header before sending the data anyway. */
CINIT(EXPECT_100_TIMEOUT_MS, LONG, 227),
/* This points to a linked list of headers used for proxy requests only,
struct curl_slist kind */
CINIT(PROXYHEADER, OBJECTPOINT, 228),
/* Pass in a bitmask of "header options" */
CINIT(HEADEROPT, LONG, 229),
/* The public key in DER form used to validate the peer public key
this option is used only if SSL_VERIFYPEER is true */
CINIT(PINNEDPUBLICKEY, STRINGPOINT, 230),
/* Path to Unix domain socket */
CINIT(UNIX_SOCKET_PATH, STRINGPOINT, 231),
/* Set if we should verify the certificate status. */
CINIT(SSL_VERIFYSTATUS, LONG, 232),
/* Set if we should enable TLS false start. */
CINIT(SSL_FALSESTART, LONG, 233),
/* Do not squash dot-dot sequences */
CINIT(PATH_AS_IS, LONG, 234),
/* Proxy Service Name */
CINIT(PROXY_SERVICE_NAME, STRINGPOINT, 235),
/* Service Name */
CINIT(SERVICE_NAME, STRINGPOINT, 236),
/* Wait/don't wait for pipe/mutex to clarify */
CINIT(PIPEWAIT, LONG, 237),
/* Set the protocol used when curl is given a URL without a protocol */
CINIT(DEFAULT_PROTOCOL, STRINGPOINT, 238),
/* Set stream weight, 1 - 256 (default is 16) */
CINIT(STREAM_WEIGHT, LONG, 239),
/* Set stream dependency on another CURL handle */
CINIT(STREAM_DEPENDS, OBJECTPOINT, 240),
/* Set E-xclusive stream dependency on another CURL handle */
CINIT(STREAM_DEPENDS_E, OBJECTPOINT, 241),
/* Do not send any tftp option requests to the server */
CINIT(TFTP_NO_OPTIONS, LONG, 242),
/* Linked-list of host:port:connect-to-host:connect-to-port,
overrides the URL's host:port (only for the network layer) */
CINIT(CONNECT_TO, OBJECTPOINT, 243),
/* Set TCP Fast Open */
CINIT(TCP_FASTOPEN, LONG, 244),
/* Continue to send data if the server responds early with an
* HTTP status code >= 300 */
CINIT(KEEP_SENDING_ON_ERROR, LONG, 245),
/* The CApath or CAfile used to validate the proxy certificate
this option is used only if PROXY_SSL_VERIFYPEER is true */
CINIT(PROXY_CAINFO, STRINGPOINT, 246),
/* The CApath directory used to validate the proxy certificate
this option is used only if PROXY_SSL_VERIFYPEER is true */
CINIT(PROXY_CAPATH, STRINGPOINT, 247),
/* Set if we should verify the proxy in ssl handshake,
set 1 to verify. */
CINIT(PROXY_SSL_VERIFYPEER, LONG, 248),
/* Set if we should verify the Common name from the proxy certificate in ssl
* handshake, set 1 to check existence, 2 to ensure that it matches
* the provided hostname. */
CINIT(PROXY_SSL_VERIFYHOST, LONG, 249),
/* What version to specifically try to use for proxy.
See CURL_SSLVERSION defines below. */
CINIT(PROXY_SSLVERSION, LONG, 250),
/* Set a username for authenticated TLS for proxy */
CINIT(PROXY_TLSAUTH_USERNAME, STRINGPOINT, 251),
/* Set a password for authenticated TLS for proxy */
CINIT(PROXY_TLSAUTH_PASSWORD, STRINGPOINT, 252),
/* Set authentication type for authenticated TLS for proxy */
CINIT(PROXY_TLSAUTH_TYPE, STRINGPOINT, 253),
/* name of the file keeping your private SSL-certificate for proxy */
CINIT(PROXY_SSLCERT, STRINGPOINT, 254),
/* type of the file keeping your SSL-certificate ("DER", "PEM", "ENG") for
proxy */
CINIT(PROXY_SSLCERTTYPE, STRINGPOINT, 255),
/* name of the file keeping your private SSL-key for proxy */
CINIT(PROXY_SSLKEY, STRINGPOINT, 256),
/* type of the file keeping your private SSL-key ("DER", "PEM", "ENG") for
proxy */
CINIT(PROXY_SSLKEYTYPE, STRINGPOINT, 257),
/* password for the SSL private key for proxy */
CINIT(PROXY_KEYPASSWD, STRINGPOINT, 258),
/* Specify which SSL ciphers to use for proxy */
CINIT(PROXY_SSL_CIPHER_LIST, STRINGPOINT, 259),
/* CRL file for proxy */
CINIT(PROXY_CRLFILE, STRINGPOINT, 260),
/* Enable/disable specific SSL features with a bitmask for proxy, see
CURLSSLOPT_* */
CINIT(PROXY_SSL_OPTIONS, LONG, 261),
/* Name of pre proxy to use. */
CINIT(PRE_PROXY, STRINGPOINT, 262),
/* The public key in DER form used to validate the proxy public key
this option is used only if PROXY_SSL_VERIFYPEER is true */
CINIT(PROXY_PINNEDPUBLICKEY, STRINGPOINT, 263),
/* Path to an abstract Unix domain socket */
CINIT(ABSTRACT_UNIX_SOCKET, STRINGPOINT, 264),
/* Suppress proxy CONNECT response headers from user callbacks */
CINIT(SUPPRESS_CONNECT_HEADERS, LONG, 265),
/* The request target, instead of extracted from the URL */
CINIT(REQUEST_TARGET, STRINGPOINT, 266),
/* bitmask of allowed auth methods for connections to SOCKS5 proxies */
CINIT(SOCKS5_AUTH, LONG, 267),
/* Enable/disable SSH compression */
CINIT(SSH_COMPRESSION, LONG, 268),
/* Post MIME data. */
CINIT(MIMEPOST, OBJECTPOINT, 269),
/* Time to use with the CURLOPT_TIMECONDITION. Specified in number of
seconds since 1 Jan 1970. */
CINIT(TIMEVALUE_LARGE, OFF_T, 270),
/* Head start in milliseconds to give happy eyeballs. */
CINIT(HAPPY_EYEBALLS_TIMEOUT_MS, LONG, 271),
/* Function that will be called before a resolver request is made */
CINIT(RESOLVER_START_FUNCTION, FUNCTIONPOINT, 272),
/* User data to pass to the resolver start callback. */
CINIT(RESOLVER_START_DATA, OBJECTPOINT, 273),
/* send HAProxy PROXY protocol header? */
CINIT(HAPROXYPROTOCOL, LONG, 274),
/* shuffle addresses before use when DNS returns multiple */
CINIT(DNS_SHUFFLE_ADDRESSES, LONG, 275),
/* Specify which TLS 1.3 ciphers suites to use */
CINIT(TLS13_CIPHERS, STRINGPOINT, 276),
CINIT(PROXY_TLS13_CIPHERS, STRINGPOINT, 277),
/* Disallow specifying username/login in URL. */
CINIT(DISALLOW_USERNAME_IN_URL, LONG, 278),
/* DNS-over-HTTPS URL */
CINIT(DOH_URL, STRINGPOINT, 279),
/* Preferred buffer size to use for uploads */
CINIT(UPLOAD_BUFFERSIZE, LONG, 280),
/* Time in ms between connection upkeep calls for long-lived connections. */
CINIT(UPKEEP_INTERVAL_MS, LONG, 281),
/* Specify URL using CURL URL API. */
CINIT(CURLU, OBJECTPOINT, 282),
/* add trailing data just after no more data is available */
CINIT(TRAILERFUNCTION, FUNCTIONPOINT, 283),
/* pointer to be passed to HTTP_TRAILER_FUNCTION */
CINIT(TRAILERDATA, OBJECTPOINT, 284),
/* set this to 1L to allow HTTP/0.9 responses or 0L to disallow */
CINIT(HTTP09_ALLOWED, LONG, 285),
/* alt-svc control bitmask */
CINIT(ALTSVC_CTRL, LONG, 286),
/* alt-svc cache file name to possibly read from/write to */
CINIT(ALTSVC, STRINGPOINT, 287),
/* maximum age of a connection to consider it for reuse (in seconds) */
CINIT(MAXAGE_CONN, LONG, 288),
CURLOPT_LASTENTRY /* the last unused */
} CURLoption;
#ifndef CURL_NO_OLDIES /* define this to test if your app builds with all
the obsolete stuff removed! */
/* Backwards compatibility with older names */
/* These are scheduled to disappear by 2011 */
/* This was added in version 7.19.1 */
#define CURLOPT_POST301 CURLOPT_POSTREDIR
/* These are scheduled to disappear by 2009 */
/* The following were added in 7.17.0 */
#define CURLOPT_SSLKEYPASSWD CURLOPT_KEYPASSWD
#define CURLOPT_FTPAPPEND CURLOPT_APPEND
#define CURLOPT_FTPLISTONLY CURLOPT_DIRLISTONLY
#define CURLOPT_FTP_SSL CURLOPT_USE_SSL
/* The following were added earlier */
#define CURLOPT_SSLCERTPASSWD CURLOPT_KEYPASSWD
#define CURLOPT_KRB4LEVEL CURLOPT_KRBLEVEL
#else
/* This is set if CURL_NO_OLDIES is defined at compile-time */
#undef CURLOPT_DNS_USE_GLOBAL_CACHE /* soon obsolete */
#endif
/* Below here follows defines for the CURLOPT_IPRESOLVE option. If a host
name resolves addresses using more than one IP protocol version, this
option might be handy to force libcurl to use a specific IP version. */
#define CURL_IPRESOLVE_WHATEVER 0 /* default, resolves addresses to all IP
versions that your system allows */
#define CURL_IPRESOLVE_V4 1 /* resolve to IPv4 addresses */
#define CURL_IPRESOLVE_V6 2 /* resolve to IPv6 addresses */
/* three convenient "aliases" that follow the name scheme better */
#define CURLOPT_RTSPHEADER CURLOPT_HTTPHEADER
/* These enums are for use with the CURLOPT_HTTP_VERSION option. */
enum {
CURL_HTTP_VERSION_NONE, /* setting this means we don't care, and that we'd
like the library to choose the best possible
for us! */
CURL_HTTP_VERSION_1_0, /* please use HTTP 1.0 in the request */
CURL_HTTP_VERSION_1_1, /* please use HTTP 1.1 in the request */
CURL_HTTP_VERSION_2_0, /* please use HTTP 2 in the request */
CURL_HTTP_VERSION_2TLS, /* use version 2 for HTTPS, version 1.1 for HTTP */
CURL_HTTP_VERSION_2_PRIOR_KNOWLEDGE, /* please use HTTP 2 without HTTP/1.1
Upgrade */
CURL_HTTP_VERSION_LAST /* *ILLEGAL* http version */
};
/* Convenience definition simple because the name of the version is HTTP/2 and
not 2.0. The 2_0 version of the enum name was set while the version was
still planned to be 2.0 and we stick to it for compatibility. */
#define CURL_HTTP_VERSION_2 CURL_HTTP_VERSION_2_0
/*
* Public API enums for RTSP requests
*/
enum {
CURL_RTSPREQ_NONE, /* first in list */
CURL_RTSPREQ_OPTIONS,
CURL_RTSPREQ_DESCRIBE,
CURL_RTSPREQ_ANNOUNCE,
CURL_RTSPREQ_SETUP,
CURL_RTSPREQ_PLAY,
CURL_RTSPREQ_PAUSE,
CURL_RTSPREQ_TEARDOWN,
CURL_RTSPREQ_GET_PARAMETER,
CURL_RTSPREQ_SET_PARAMETER,
CURL_RTSPREQ_RECORD,
CURL_RTSPREQ_RECEIVE,
CURL_RTSPREQ_LAST /* last in list */
};
/* These enums are for use with the CURLOPT_NETRC option. */
enum CURL_NETRC_OPTION {
CURL_NETRC_IGNORED, /* The .netrc will never be read.
* This is the default. */
CURL_NETRC_OPTIONAL, /* A user:password in the URL will be preferred
* to one in the .netrc. */
CURL_NETRC_REQUIRED, /* A user:password in the URL will be ignored.
* Unless one is set programmatically, the .netrc
* will be queried. */
CURL_NETRC_LAST
};
enum {
CURL_SSLVERSION_DEFAULT,
CURL_SSLVERSION_TLSv1, /* TLS 1.x */
CURL_SSLVERSION_SSLv2,
CURL_SSLVERSION_SSLv3,
CURL_SSLVERSION_TLSv1_0,
CURL_SSLVERSION_TLSv1_1,
CURL_SSLVERSION_TLSv1_2,
CURL_SSLVERSION_TLSv1_3,
CURL_SSLVERSION_LAST /* never use, keep last */
};
enum {
CURL_SSLVERSION_MAX_NONE = 0,
CURL_SSLVERSION_MAX_DEFAULT = (CURL_SSLVERSION_TLSv1 << 16),
CURL_SSLVERSION_MAX_TLSv1_0 = (CURL_SSLVERSION_TLSv1_0 << 16),
CURL_SSLVERSION_MAX_TLSv1_1 = (CURL_SSLVERSION_TLSv1_1 << 16),
CURL_SSLVERSION_MAX_TLSv1_2 = (CURL_SSLVERSION_TLSv1_2 << 16),
CURL_SSLVERSION_MAX_TLSv1_3 = (CURL_SSLVERSION_TLSv1_3 << 16),
/* never use, keep last */
CURL_SSLVERSION_MAX_LAST = (CURL_SSLVERSION_LAST << 16)
};
enum CURL_TLSAUTH {
CURL_TLSAUTH_NONE,
CURL_TLSAUTH_SRP,
CURL_TLSAUTH_LAST /* never use, keep last */
};
/* symbols to use with CURLOPT_POSTREDIR.
CURL_REDIR_POST_301, CURL_REDIR_POST_302 and CURL_REDIR_POST_303
can be bitwise ORed so that CURL_REDIR_POST_301 | CURL_REDIR_POST_302
| CURL_REDIR_POST_303 == CURL_REDIR_POST_ALL */
#define CURL_REDIR_GET_ALL 0
#define CURL_REDIR_POST_301 1
#define CURL_REDIR_POST_302 2
#define CURL_REDIR_POST_303 4
#define CURL_REDIR_POST_ALL \
(CURL_REDIR_POST_301|CURL_REDIR_POST_302|CURL_REDIR_POST_303)
typedef enum {
CURL_TIMECOND_NONE,
CURL_TIMECOND_IFMODSINCE,
CURL_TIMECOND_IFUNMODSINCE,
CURL_TIMECOND_LASTMOD,
CURL_TIMECOND_LAST
} curl_TimeCond;
/* Special size_t value signaling a zero-terminated string. */
#define CURL_ZERO_TERMINATED ((size_t) -1)
/* curl_strequal() and curl_strnequal() are subject for removal in a future
release */
CURL_EXTERN int curl_strequal(const char *s1, const char *s2);
CURL_EXTERN int curl_strnequal(const char *s1, const char *s2, size_t n);
/* Mime/form handling support. */
typedef struct curl_mime_s curl_mime; /* Mime context. */
typedef struct curl_mimepart_s curl_mimepart; /* Mime part context. */
/*
* NAME curl_mime_init()
*
* DESCRIPTION
*
* Create a mime context and return its handle. The easy parameter is the
* target handle.
*/
CURL_EXTERN curl_mime *curl_mime_init(CURL *easy);
/*
* NAME curl_mime_free()
*
* DESCRIPTION
*
* release a mime handle and its substructures.
*/
CURL_EXTERN void curl_mime_free(curl_mime *mime);
/*
* NAME curl_mime_addpart()
*
* DESCRIPTION
*
* Append a new empty part to the given mime context and return a handle to
* the created part.
*/
CURL_EXTERN curl_mimepart *curl_mime_addpart(curl_mime *mime);
/*
* NAME curl_mime_name()
*
* DESCRIPTION
*
* Set mime/form part name.
*/
CURL_EXTERN CURLcode curl_mime_name(curl_mimepart *part, const char *name);
/*
* NAME curl_mime_filename()
*
* DESCRIPTION
*
* Set mime part remote file name.
*/
CURL_EXTERN CURLcode curl_mime_filename(curl_mimepart *part,
const char *filename);
/*
* NAME curl_mime_type()
*
* DESCRIPTION
*
* Set mime part type.
*/
CURL_EXTERN CURLcode curl_mime_type(curl_mimepart *part, const char *mimetype);
/*
* NAME curl_mime_encoder()
*
* DESCRIPTION
*
* Set mime data transfer encoder.
*/
CURL_EXTERN CURLcode curl_mime_encoder(curl_mimepart *part,
const char *encoding);
/*
* NAME curl_mime_data()
*
* DESCRIPTION
*
* Set mime part data source from memory data,
*/
CURL_EXTERN CURLcode curl_mime_data(curl_mimepart *part,
const char *data, size_t datasize);
/*
* NAME curl_mime_filedata()
*
* DESCRIPTION
*
* Set mime part data source from named file.
*/
CURL_EXTERN CURLcode curl_mime_filedata(curl_mimepart *part,
const char *filename);
/*
* NAME curl_mime_data_cb()
*
* DESCRIPTION
*
* Set mime part data source from callback function.
*/
CURL_EXTERN CURLcode curl_mime_data_cb(curl_mimepart *part,
curl_off_t datasize,
curl_read_callback readfunc,
curl_seek_callback seekfunc,
curl_free_callback freefunc,
void *arg);
/*
* NAME curl_mime_subparts()
*
* DESCRIPTION
*
* Set mime part data source from subparts.
*/
CURL_EXTERN CURLcode curl_mime_subparts(curl_mimepart *part,
curl_mime *subparts);
/*
* NAME curl_mime_headers()
*
* DESCRIPTION
*
* Set mime part headers.
*/
CURL_EXTERN CURLcode curl_mime_headers(curl_mimepart *part,
struct curl_slist *headers,
int take_ownership);
/* Old form API. */
/* name is uppercase CURLFORM_<name> */
#ifdef CFINIT
#undef CFINIT
#endif
#ifdef CURL_ISOCPP
#define CFINIT(name) CURLFORM_ ## name
#else
/* The macro "##" is ISO C, we assume pre-ISO C doesn't support it. */
#define CFINIT(name) CURLFORM_/**/name
#endif
typedef enum {
CFINIT(NOTHING), /********* the first one is unused ************/
/* */
CFINIT(COPYNAME),
CFINIT(PTRNAME),
CFINIT(NAMELENGTH),
CFINIT(COPYCONTENTS),
CFINIT(PTRCONTENTS),
CFINIT(CONTENTSLENGTH),
CFINIT(FILECONTENT),
CFINIT(ARRAY),
CFINIT(OBSOLETE),
CFINIT(FILE),
CFINIT(BUFFER),
CFINIT(BUFFERPTR),
CFINIT(BUFFERLENGTH),
CFINIT(CONTENTTYPE),
CFINIT(CONTENTHEADER),
CFINIT(FILENAME),
CFINIT(END),
CFINIT(OBSOLETE2),
CFINIT(STREAM),
CFINIT(CONTENTLEN), /* added in 7.46.0, provide a curl_off_t length */
CURLFORM_LASTENTRY /* the last unused */
} CURLformoption;
#undef CFINIT /* done */
/* structure to be used as parameter for CURLFORM_ARRAY */
struct curl_forms {
CURLformoption option;
const char *value;
};
/* use this for multipart formpost building */
/* Returns code for curl_formadd()
*
* Returns:
* CURL_FORMADD_OK on success
* CURL_FORMADD_MEMORY if the FormInfo allocation fails
* CURL_FORMADD_OPTION_TWICE if one option is given twice for one Form
* CURL_FORMADD_NULL if a null pointer was given for a char
* CURL_FORMADD_MEMORY if the allocation of a FormInfo struct failed
* CURL_FORMADD_UNKNOWN_OPTION if an unknown option was used
* CURL_FORMADD_INCOMPLETE if the some FormInfo is not complete (or error)
* CURL_FORMADD_MEMORY if a curl_httppost struct cannot be allocated
* CURL_FORMADD_MEMORY if some allocation for string copying failed.
* CURL_FORMADD_ILLEGAL_ARRAY if an illegal option is used in an array
*
***************************************************************************/
typedef enum {
CURL_FORMADD_OK, /* first, no error */
CURL_FORMADD_MEMORY,
CURL_FORMADD_OPTION_TWICE,
CURL_FORMADD_NULL,
CURL_FORMADD_UNKNOWN_OPTION,
CURL_FORMADD_INCOMPLETE,
CURL_FORMADD_ILLEGAL_ARRAY,
CURL_FORMADD_DISABLED, /* libcurl was built with this disabled */
CURL_FORMADD_LAST /* last */
} CURLFORMcode;
/*
* NAME curl_formadd()
*
* DESCRIPTION
*
* Pretty advanced function for building multi-part formposts. Each invoke
* adds one part that together construct a full post. Then use
* CURLOPT_HTTPPOST to send it off to libcurl.
*/
CURL_EXTERN CURLFORMcode curl_formadd(struct curl_httppost **httppost,
struct curl_httppost **last_post,
...);
/*
* callback function for curl_formget()
* The void *arg pointer will be the one passed as second argument to
* curl_formget().
* The character buffer passed to it must not be freed.
* Should return the buffer length passed to it as the argument "len" on
* success.
*/
typedef size_t (*curl_formget_callback)(void *arg, const char *buf,
size_t len);
/*
* NAME curl_formget()
*
* DESCRIPTION
*
* Serialize a curl_httppost struct built with curl_formadd().
* Accepts a void pointer as second argument which will be passed to
* the curl_formget_callback function.
* Returns 0 on success.
*/
CURL_EXTERN int curl_formget(struct curl_httppost *form, void *arg,
curl_formget_callback append);
/*
* NAME curl_formfree()
*
* DESCRIPTION
*
* Free a multipart formpost previously built with curl_formadd().
*/
CURL_EXTERN void curl_formfree(struct curl_httppost *form);
/*
* NAME curl_getenv()
*
* DESCRIPTION
*
* Returns a malloc()'ed string that MUST be curl_free()ed after usage is
* complete. DEPRECATED - see lib/README.curlx
*/
CURL_EXTERN char *curl_getenv(const char *variable);
/*
* NAME curl_version()
*
* DESCRIPTION
*
* Returns a static ascii string of the libcurl version.
*/
CURL_EXTERN char *curl_version(void);
/*
* NAME curl_easy_escape()
*
* DESCRIPTION
*
* Escapes URL strings (converts all letters consider illegal in URLs to their
* %XX versions). This function returns a new allocated string or NULL if an
* error occurred.
*/
CURL_EXTERN char *curl_easy_escape(CURL *handle,
const char *string,
int length);
/* the previous version: */
CURL_EXTERN char *curl_escape(const char *string,
int length);
/*
* NAME curl_easy_unescape()
*
* DESCRIPTION
*
* Unescapes URL encoding in strings (converts all %XX codes to their 8bit
* versions). This function returns a new allocated string or NULL if an error
* occurred.
* Conversion Note: On non-ASCII platforms the ASCII %XX codes are
* converted into the host encoding.
*/
CURL_EXTERN char *curl_easy_unescape(CURL *handle,
const char *string,
int length,
int *outlength);
/* the previous version */
CURL_EXTERN char *curl_unescape(const char *string,
int length);
/*
* NAME curl_free()
*
* DESCRIPTION
*
* Provided for de-allocation in the same translation unit that did the
* allocation. Added in libcurl 7.10
*/
CURL_EXTERN void curl_free(void *p);
/*
* NAME curl_global_init()
*
* DESCRIPTION
*
* curl_global_init() should be invoked exactly once for each application that
* uses libcurl and before any call of other libcurl functions.
*
* This function is not thread-safe!
*/
CURL_EXTERN CURLcode curl_global_init(long flags);
/*
* NAME curl_global_init_mem()
*
* DESCRIPTION
*
* curl_global_init() or curl_global_init_mem() should be invoked exactly once
* for each application that uses libcurl. This function can be used to
* initialize libcurl and set user defined memory management callback
* functions. Users can implement memory management routines to check for
* memory leaks, check for mis-use of the curl library etc. User registered
* callback routines with be invoked by this library instead of the system
* memory management routines like malloc, free etc.
*/
CURL_EXTERN CURLcode curl_global_init_mem(long flags,
curl_malloc_callback m,
curl_free_callback f,
curl_realloc_callback r,
curl_strdup_callback s,
curl_calloc_callback c);
/*
* NAME curl_global_cleanup()
*
* DESCRIPTION
*
* curl_global_cleanup() should be invoked exactly once for each application
* that uses libcurl
*/
CURL_EXTERN void curl_global_cleanup(void);
/* linked-list structure for the CURLOPT_QUOTE option (and other) */
struct curl_slist {
char *data;
struct curl_slist *next;
};
/*
* NAME curl_global_sslset()
*
* DESCRIPTION
*
* When built with multiple SSL backends, curl_global_sslset() allows to
* choose one. This function can only be called once, and it must be called
* *before* curl_global_init().
*
* The backend can be identified by the id (e.g. CURLSSLBACKEND_OPENSSL). The
* backend can also be specified via the name parameter (passing -1 as id).
* If both id and name are specified, the name will be ignored. If neither id
* nor name are specified, the function will fail with
* CURLSSLSET_UNKNOWN_BACKEND and set the "avail" pointer to the
* NULL-terminated list of available backends.
*
* Upon success, the function returns CURLSSLSET_OK.
*
* If the specified SSL backend is not available, the function returns
* CURLSSLSET_UNKNOWN_BACKEND and sets the "avail" pointer to a NULL-terminated
* list of available SSL backends.
*
* The SSL backend can be set only once. If it has already been set, a
* subsequent attempt to change it will result in a CURLSSLSET_TOO_LATE.
*/
typedef struct {
curl_sslbackend id;
const char *name;
} curl_ssl_backend;
typedef enum {
CURLSSLSET_OK = 0,
CURLSSLSET_UNKNOWN_BACKEND,
CURLSSLSET_TOO_LATE,
CURLSSLSET_NO_BACKENDS /* libcurl was built without any SSL support */
} CURLsslset;
CURL_EXTERN CURLsslset curl_global_sslset(curl_sslbackend id, const char *name,
const curl_ssl_backend ***avail);
/*
* NAME curl_slist_append()
*
* DESCRIPTION
*
* Appends a string to a linked list. If no list exists, it will be created
* first. Returns the new list, after appending.
*/
CURL_EXTERN struct curl_slist *curl_slist_append(struct curl_slist *,
const char *);
/*
* NAME curl_slist_free_all()
*
* DESCRIPTION
*
* free a previously built curl_slist.
*/
CURL_EXTERN void curl_slist_free_all(struct curl_slist *);
/*
* NAME curl_getdate()
*
* DESCRIPTION
*
* Returns the time, in seconds since 1 Jan 1970 of the time string given in
* the first argument. The time argument in the second parameter is unused
* and should be set to NULL.
*/
CURL_EXTERN time_t curl_getdate(const char *p, const time_t *unused);
/* info about the certificate chain, only for OpenSSL builds. Asked
for with CURLOPT_CERTINFO / CURLINFO_CERTINFO */
struct curl_certinfo {
int num_of_certs; /* number of certificates with information */
struct curl_slist **certinfo; /* for each index in this array, there's a
linked list with textual information in the
format "name: value" */
};
/* Information about the SSL library used and the respective internal SSL
handle, which can be used to obtain further information regarding the
connection. Asked for with CURLINFO_TLS_SSL_PTR or CURLINFO_TLS_SESSION. */
struct curl_tlssessioninfo {
curl_sslbackend backend;
void *internals;
};
#define CURLINFO_STRING 0x100000
#define CURLINFO_LONG 0x200000
#define CURLINFO_DOUBLE 0x300000
#define CURLINFO_SLIST 0x400000
#define CURLINFO_PTR 0x400000 /* same as SLIST */
#define CURLINFO_SOCKET 0x500000
#define CURLINFO_OFF_T 0x600000
#define CURLINFO_MASK 0x0fffff
#define CURLINFO_TYPEMASK 0xf00000
typedef enum {
CURLINFO_NONE, /* first, never use this */
CURLINFO_EFFECTIVE_URL = CURLINFO_STRING + 1,
CURLINFO_RESPONSE_CODE = CURLINFO_LONG + 2,
CURLINFO_TOTAL_TIME = CURLINFO_DOUBLE + 3,
CURLINFO_NAMELOOKUP_TIME = CURLINFO_DOUBLE + 4,
CURLINFO_CONNECT_TIME = CURLINFO_DOUBLE + 5,
CURLINFO_PRETRANSFER_TIME = CURLINFO_DOUBLE + 6,
CURLINFO_SIZE_UPLOAD = CURLINFO_DOUBLE + 7,
CURLINFO_SIZE_UPLOAD_T = CURLINFO_OFF_T + 7,
CURLINFO_SIZE_DOWNLOAD = CURLINFO_DOUBLE + 8,
CURLINFO_SIZE_DOWNLOAD_T = CURLINFO_OFF_T + 8,
CURLINFO_SPEED_DOWNLOAD = CURLINFO_DOUBLE + 9,
CURLINFO_SPEED_DOWNLOAD_T = CURLINFO_OFF_T + 9,
CURLINFO_SPEED_UPLOAD = CURLINFO_DOUBLE + 10,
CURLINFO_SPEED_UPLOAD_T = CURLINFO_OFF_T + 10,
CURLINFO_HEADER_SIZE = CURLINFO_LONG + 11,
CURLINFO_REQUEST_SIZE = CURLINFO_LONG + 12,
CURLINFO_SSL_VERIFYRESULT = CURLINFO_LONG + 13,
CURLINFO_FILETIME = CURLINFO_LONG + 14,
CURLINFO_FILETIME_T = CURLINFO_OFF_T + 14,
CURLINFO_CONTENT_LENGTH_DOWNLOAD = CURLINFO_DOUBLE + 15,
CURLINFO_CONTENT_LENGTH_DOWNLOAD_T = CURLINFO_OFF_T + 15,
CURLINFO_CONTENT_LENGTH_UPLOAD = CURLINFO_DOUBLE + 16,
CURLINFO_CONTENT_LENGTH_UPLOAD_T = CURLINFO_OFF_T + 16,
CURLINFO_STARTTRANSFER_TIME = CURLINFO_DOUBLE + 17,
CURLINFO_CONTENT_TYPE = CURLINFO_STRING + 18,
CURLINFO_REDIRECT_TIME = CURLINFO_DOUBLE + 19,
CURLINFO_REDIRECT_COUNT = CURLINFO_LONG + 20,
CURLINFO_PRIVATE = CURLINFO_STRING + 21,
CURLINFO_HTTP_CONNECTCODE = CURLINFO_LONG + 22,
CURLINFO_HTTPAUTH_AVAIL = CURLINFO_LONG + 23,
CURLINFO_PROXYAUTH_AVAIL = CURLINFO_LONG + 24,
CURLINFO_OS_ERRNO = CURLINFO_LONG + 25,
CURLINFO_NUM_CONNECTS = CURLINFO_LONG + 26,
CURLINFO_SSL_ENGINES = CURLINFO_SLIST + 27,
CURLINFO_COOKIELIST = CURLINFO_SLIST + 28,
CURLINFO_LASTSOCKET = CURLINFO_LONG + 29,
CURLINFO_FTP_ENTRY_PATH = CURLINFO_STRING + 30,
CURLINFO_REDIRECT_URL = CURLINFO_STRING + 31,
CURLINFO_PRIMARY_IP = CURLINFO_STRING + 32,
CURLINFO_APPCONNECT_TIME = CURLINFO_DOUBLE + 33,
CURLINFO_CERTINFO = CURLINFO_PTR + 34,
CURLINFO_CONDITION_UNMET = CURLINFO_LONG + 35,
CURLINFO_RTSP_SESSION_ID = CURLINFO_STRING + 36,
CURLINFO_RTSP_CLIENT_CSEQ = CURLINFO_LONG + 37,
CURLINFO_RTSP_SERVER_CSEQ = CURLINFO_LONG + 38,
CURLINFO_RTSP_CSEQ_RECV = CURLINFO_LONG + 39,
CURLINFO_PRIMARY_PORT = CURLINFO_LONG + 40,
CURLINFO_LOCAL_IP = CURLINFO_STRING + 41,
CURLINFO_LOCAL_PORT = CURLINFO_LONG + 42,
CURLINFO_TLS_SESSION = CURLINFO_PTR + 43,
CURLINFO_ACTIVESOCKET = CURLINFO_SOCKET + 44,
CURLINFO_TLS_SSL_PTR = CURLINFO_PTR + 45,
CURLINFO_HTTP_VERSION = CURLINFO_LONG + 46,
CURLINFO_PROXY_SSL_VERIFYRESULT = CURLINFO_LONG + 47,
CURLINFO_PROTOCOL = CURLINFO_LONG + 48,
CURLINFO_SCHEME = CURLINFO_STRING + 49,
/* Fill in new entries below here! */
/* Preferably these would be defined conditionally based on the
sizeof curl_off_t being 64-bits */
CURLINFO_TOTAL_TIME_T = CURLINFO_OFF_T + 50,
CURLINFO_NAMELOOKUP_TIME_T = CURLINFO_OFF_T + 51,
CURLINFO_CONNECT_TIME_T = CURLINFO_OFF_T + 52,
CURLINFO_PRETRANSFER_TIME_T = CURLINFO_OFF_T + 53,
CURLINFO_STARTTRANSFER_TIME_T = CURLINFO_OFF_T + 54,
CURLINFO_REDIRECT_TIME_T = CURLINFO_OFF_T + 55,
CURLINFO_APPCONNECT_TIME_T = CURLINFO_OFF_T + 56,
CURLINFO_LASTONE = 56
} CURLINFO;
/* CURLINFO_RESPONSE_CODE is the new name for the option previously known as
CURLINFO_HTTP_CODE */
#define CURLINFO_HTTP_CODE CURLINFO_RESPONSE_CODE
typedef enum {
CURLCLOSEPOLICY_NONE, /* first, never use this */
CURLCLOSEPOLICY_OLDEST,
CURLCLOSEPOLICY_LEAST_RECENTLY_USED,
CURLCLOSEPOLICY_LEAST_TRAFFIC,
CURLCLOSEPOLICY_SLOWEST,
CURLCLOSEPOLICY_CALLBACK,
CURLCLOSEPOLICY_LAST /* last, never use this */
} curl_closepolicy;
#define CURL_GLOBAL_SSL (1<<0) /* no purpose since since 7.57.0 */
#define CURL_GLOBAL_WIN32 (1<<1)
#define CURL_GLOBAL_ALL (CURL_GLOBAL_SSL|CURL_GLOBAL_WIN32)
#define CURL_GLOBAL_NOTHING 0
#define CURL_GLOBAL_DEFAULT CURL_GLOBAL_ALL
#define CURL_GLOBAL_ACK_EINTR (1<<2)
/*****************************************************************************
* Setup defines, protos etc for the sharing stuff.
*/
/* Different data locks for a single share */
typedef enum {
CURL_LOCK_DATA_NONE = 0,
/* CURL_LOCK_DATA_SHARE is used internally to say that
* the locking is just made to change the internal state of the share
* itself.
*/
CURL_LOCK_DATA_SHARE,
CURL_LOCK_DATA_COOKIE,
CURL_LOCK_DATA_DNS,
CURL_LOCK_DATA_SSL_SESSION,
CURL_LOCK_DATA_CONNECT,
CURL_LOCK_DATA_PSL,
CURL_LOCK_DATA_LAST
} curl_lock_data;
/* Different lock access types */
typedef enum {
CURL_LOCK_ACCESS_NONE = 0, /* unspecified action */
CURL_LOCK_ACCESS_SHARED = 1, /* for read perhaps */
CURL_LOCK_ACCESS_SINGLE = 2, /* for write perhaps */
CURL_LOCK_ACCESS_LAST /* never use */
} curl_lock_access;
typedef void (*curl_lock_function)(CURL *handle,
curl_lock_data data,
curl_lock_access locktype,
void *userptr);
typedef void (*curl_unlock_function)(CURL *handle,
curl_lock_data data,
void *userptr);
typedef enum {
CURLSHE_OK, /* all is fine */
CURLSHE_BAD_OPTION, /* 1 */
CURLSHE_IN_USE, /* 2 */
CURLSHE_INVALID, /* 3 */
CURLSHE_NOMEM, /* 4 out of memory */
CURLSHE_NOT_BUILT_IN, /* 5 feature not present in lib */
CURLSHE_LAST /* never use */
} CURLSHcode;
typedef enum {
CURLSHOPT_NONE, /* don't use */
CURLSHOPT_SHARE, /* specify a data type to share */
CURLSHOPT_UNSHARE, /* specify which data type to stop sharing */
CURLSHOPT_LOCKFUNC, /* pass in a 'curl_lock_function' pointer */
CURLSHOPT_UNLOCKFUNC, /* pass in a 'curl_unlock_function' pointer */
CURLSHOPT_USERDATA, /* pass in a user data pointer used in the lock/unlock
callback functions */
CURLSHOPT_LAST /* never use */
} CURLSHoption;
CURL_EXTERN CURLSH *curl_share_init(void);
CURL_EXTERN CURLSHcode curl_share_setopt(CURLSH *, CURLSHoption option, ...);
CURL_EXTERN CURLSHcode curl_share_cleanup(CURLSH *);
/****************************************************************************
* Structures for querying information about the curl library at runtime.
*/
typedef enum {
CURLVERSION_FIRST,
CURLVERSION_SECOND,
CURLVERSION_THIRD,
CURLVERSION_FOURTH,
CURLVERSION_FIFTH,
CURLVERSION_LAST /* never actually use this */
} CURLversion;
/* The 'CURLVERSION_NOW' is the symbolic name meant to be used by
basically all programs ever that want to get version information. It is
meant to be a built-in version number for what kind of struct the caller
expects. If the struct ever changes, we redefine the NOW to another enum
from above. */
#define CURLVERSION_NOW CURLVERSION_FIFTH
typedef struct {
CURLversion age; /* age of the returned struct */
const char *version; /* LIBCURL_VERSION */
unsigned int version_num; /* LIBCURL_VERSION_NUM */
const char *host; /* OS/host/cpu/machine when configured */
int features; /* bitmask, see defines below */
const char *ssl_version; /* human readable string */
long ssl_version_num; /* not used anymore, always 0 */
const char *libz_version; /* human readable string */
/* protocols is terminated by an entry with a NULL protoname */
const char * const *protocols;
/* The fields below this were added in CURLVERSION_SECOND */
const char *ares;
int ares_num;
/* This field was added in CURLVERSION_THIRD */
const char *libidn;
/* These field were added in CURLVERSION_FOURTH */
/* Same as '_libiconv_version' if built with HAVE_ICONV */
int iconv_ver_num;
const char *libssh_version; /* human readable string */
/* These fields were added in CURLVERSION_FIFTH */
unsigned int brotli_ver_num; /* Numeric Brotli version
(MAJOR << 24) | (MINOR << 12) | PATCH */
const char *brotli_version; /* human readable string. */
} curl_version_info_data;
#define CURL_VERSION_IPV6 (1<<0) /* IPv6-enabled */
#define CURL_VERSION_KERBEROS4 (1<<1) /* Kerberos V4 auth is supported
(deprecated) */
#define CURL_VERSION_SSL (1<<2) /* SSL options are present */
#define CURL_VERSION_LIBZ (1<<3) /* libz features are present */
#define CURL_VERSION_NTLM (1<<4) /* NTLM auth is supported */
#define CURL_VERSION_GSSNEGOTIATE (1<<5) /* Negotiate auth is supported
(deprecated) */
#define CURL_VERSION_DEBUG (1<<6) /* Built with debug capabilities */
#define CURL_VERSION_ASYNCHDNS (1<<7) /* Asynchronous DNS resolves */
#define CURL_VERSION_SPNEGO (1<<8) /* SPNEGO auth is supported */
#define CURL_VERSION_LARGEFILE (1<<9) /* Supports files larger than 2GB */
#define CURL_VERSION_IDN (1<<10) /* Internationized Domain Names are
supported */
#define CURL_VERSION_SSPI (1<<11) /* Built against Windows SSPI */
#define CURL_VERSION_CONV (1<<12) /* Character conversions supported */
#define CURL_VERSION_CURLDEBUG (1<<13) /* Debug memory tracking supported */
#define CURL_VERSION_TLSAUTH_SRP (1<<14) /* TLS-SRP auth is supported */
#define CURL_VERSION_NTLM_WB (1<<15) /* NTLM delegation to winbind helper
is supported */
#define CURL_VERSION_HTTP2 (1<<16) /* HTTP2 support built-in */
#define CURL_VERSION_GSSAPI (1<<17) /* Built against a GSS-API library */
#define CURL_VERSION_KERBEROS5 (1<<18) /* Kerberos V5 auth is supported */
#define CURL_VERSION_UNIX_SOCKETS (1<<19) /* Unix domain sockets support */
#define CURL_VERSION_PSL (1<<20) /* Mozilla's Public Suffix List, used
for cookie domain verification */
#define CURL_VERSION_HTTPS_PROXY (1<<21) /* HTTPS-proxy support built-in */
#define CURL_VERSION_MULTI_SSL (1<<22) /* Multiple SSL backends available */
#define CURL_VERSION_BROTLI (1<<23) /* Brotli features are present. */
#define CURL_VERSION_ALTSVC (1<<24) /* Alt-Svc handling built-in */
/*
* NAME curl_version_info()
*
* DESCRIPTION
*
* This function returns a pointer to a static copy of the version info
* struct. See above.
*/
CURL_EXTERN curl_version_info_data *curl_version_info(CURLversion);
/*
* NAME curl_easy_strerror()
*
* DESCRIPTION
*
* The curl_easy_strerror function may be used to turn a CURLcode value
* into the equivalent human readable error string. This is useful
* for printing meaningful error messages.
*/
CURL_EXTERN const char *curl_easy_strerror(CURLcode);
/*
* NAME curl_share_strerror()
*
* DESCRIPTION
*
* The curl_share_strerror function may be used to turn a CURLSHcode value
* into the equivalent human readable error string. This is useful
* for printing meaningful error messages.
*/
CURL_EXTERN const char *curl_share_strerror(CURLSHcode);
/*
* NAME curl_easy_pause()
*
* DESCRIPTION
*
* The curl_easy_pause function pauses or unpauses transfers. Select the new
* state by setting the bitmask, use the convenience defines below.
*
*/
CURL_EXTERN CURLcode curl_easy_pause(CURL *handle, int bitmask);
#define CURLPAUSE_RECV (1<<0)
#define CURLPAUSE_RECV_CONT (0)
#define CURLPAUSE_SEND (1<<2)
#define CURLPAUSE_SEND_CONT (0)
#define CURLPAUSE_ALL (CURLPAUSE_RECV|CURLPAUSE_SEND)
#define CURLPAUSE_CONT (CURLPAUSE_RECV_CONT|CURLPAUSE_SEND_CONT)
#ifdef __cplusplus
}
#endif
/* unfortunately, the easy.h and multi.h include files need options and info
stuff before they can be included! */
#include "easy.h" /* nothing in curl is fun without the easy stuff */
#include "multi.h"
#include "urlapi.h"
/* the typechecker doesn't work in C++ (yet) */
#if defined(__GNUC__) && defined(__GNUC_MINOR__) && \
((__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)) && \
!defined(__cplusplus) && !defined(CURL_DISABLE_TYPECHECK)
#include "typecheck-gcc.h"
#else
#if defined(__STDC__) && (__STDC__ >= 1)
/* This preprocessor magic that replaces a call with the exact same call is
only done to make sure application authors pass exactly three arguments
to these functions. */
#define curl_easy_setopt(handle,opt,param) curl_easy_setopt(handle,opt,param)
#define curl_easy_getinfo(handle,info,arg) curl_easy_getinfo(handle,info,arg)
#define curl_share_setopt(share,opt,param) curl_share_setopt(share,opt,param)
#define curl_multi_setopt(handle,opt,param) curl_multi_setopt(handle,opt,param)
#endif /* __STDC__ >= 1 */
#endif /* gcc >= 4.3 && !__cplusplus */
#endif /* __CURL_CURL_H */
| YifuLiu/AliOS-Things | components/curl/include/curl/curl.h | C | apache-2.0 | 106,482 |
#ifndef __CURL_CURLVER_H
#define __CURL_CURLVER_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/* This header file contains nothing but libcurl version info, generated by
a script at release-time. This was made its own header file in 7.11.2 */
/* This is the global package copyright */
#define LIBCURL_COPYRIGHT "1996 - 2019 Daniel Stenberg, <daniel@haxx.se>."
/* This is the version number of the libcurl package from which this header
file origins: */
#define LIBCURL_VERSION "7.65.0-DEV"
/* The numeric version number is also available "in parts" by using these
defines: */
#define LIBCURL_VERSION_MAJOR 7
#define LIBCURL_VERSION_MINOR 65
#define LIBCURL_VERSION_PATCH 0
/* This is the numeric version of the libcurl version number, meant for easier
parsing and comparions by programs. The LIBCURL_VERSION_NUM define will
always follow this syntax:
0xXXYYZZ
Where XX, YY and ZZ are the main version, release and patch numbers in
hexadecimal (using 8 bits each). All three numbers are always represented
using two digits. 1.2 would appear as "0x010200" while version 9.11.7
appears as "0x090b07".
This 6-digit (24 bits) hexadecimal number does not show pre-release number,
and it is always a greater number in a more recent release. It makes
comparisons with greater than and less than work.
Note: This define is the full hex number and _does not_ use the
CURL_VERSION_BITS() macro since curl's own configure script greps for it
and needs it to contain the full number.
*/
#define LIBCURL_VERSION_NUM 0x074100
/*
* This is the date and time when the full source package was created. The
* timestamp is not stored in git, as the timestamp is properly set in the
* tarballs by the maketgz script.
*
* The format of the date follows this template:
*
* "2007-11-23"
*/
#define LIBCURL_TIMESTAMP "[unreleased]"
#define CURL_VERSION_BITS(x,y,z) ((x)<<16|(y)<<8|(z))
#define CURL_AT_LEAST_VERSION(x,y,z) \
(LIBCURL_VERSION_NUM >= CURL_VERSION_BITS(x, y, z))
#endif /* __CURL_CURLVER_H */
| YifuLiu/AliOS-Things | components/curl/include/curl/curlver.h | C | apache-2.0 | 3,042 |
#ifndef __CURL_EASY_H
#define __CURL_EASY_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2016, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
CURL_EXTERN CURL *curl_easy_init(void);
CURL_EXTERN CURLcode curl_easy_setopt(CURL *curl, CURLoption option, ...);
CURL_EXTERN CURLcode curl_easy_perform(CURL *curl);
CURL_EXTERN void curl_easy_cleanup(CURL *curl);
/*
* NAME curl_easy_getinfo()
*
* DESCRIPTION
*
* Request internal information from the curl session with this function. The
* third argument MUST be a pointer to a long, a pointer to a char * or a
* pointer to a double (as the documentation describes elsewhere). The data
* pointed to will be filled in accordingly and can be relied upon only if the
* function returns CURLE_OK. This function is intended to get used *AFTER* a
* performed transfer, all results from this function are undefined until the
* transfer is completed.
*/
CURL_EXTERN CURLcode curl_easy_getinfo(CURL *curl, CURLINFO info, ...);
/*
* NAME curl_easy_duphandle()
*
* DESCRIPTION
*
* Creates a new curl session handle with the same options set for the handle
* passed in. Duplicating a handle could only be a matter of cloning data and
* options, internal state info and things like persistent connections cannot
* be transferred. It is useful in multithreaded applications when you can run
* curl_easy_duphandle() for each new thread to avoid a series of identical
* curl_easy_setopt() invokes in every thread.
*/
CURL_EXTERN CURL *curl_easy_duphandle(CURL *curl);
/*
* NAME curl_easy_reset()
*
* DESCRIPTION
*
* Re-initializes a CURL handle to the default values. This puts back the
* handle to the same state as it was in when it was just created.
*
* It does keep: live connections, the Session ID cache, the DNS cache and the
* cookies.
*/
CURL_EXTERN void curl_easy_reset(CURL *curl);
/*
* NAME curl_easy_recv()
*
* DESCRIPTION
*
* Receives data from the connected socket. Use after successful
* curl_easy_perform() with CURLOPT_CONNECT_ONLY option.
*/
CURL_EXTERN CURLcode curl_easy_recv(CURL *curl, void *buffer, size_t buflen,
size_t *n);
/*
* NAME curl_easy_send()
*
* DESCRIPTION
*
* Sends data over the connected socket. Use after successful
* curl_easy_perform() with CURLOPT_CONNECT_ONLY option.
*/
CURL_EXTERN CURLcode curl_easy_send(CURL *curl, const void *buffer,
size_t buflen, size_t *n);
/*
* NAME curl_easy_upkeep()
*
* DESCRIPTION
*
* Performs connection upkeep for the given session handle.
*/
CURL_EXTERN CURLcode curl_easy_upkeep(CURL *curl);
#ifdef __cplusplus
}
#endif
#endif
| YifuLiu/AliOS-Things | components/curl/include/curl/easy.h | C | apache-2.0 | 3,641 |
#ifndef __CURL_MPRINTF_H
#define __CURL_MPRINTF_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2016, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include <stdarg.h>
#include <stdio.h> /* needed for FILE */
#include "curl/curl.h" /* for CURL_EXTERN */
#ifdef __cplusplus
extern "C" {
#endif
CURL_EXTERN int curl_mprintf(const char *format, ...);
CURL_EXTERN int curl_mfprintf(FILE *fd, const char *format, ...);
CURL_EXTERN int curl_msprintf(char *buffer, const char *format, ...);
CURL_EXTERN int curl_msnprintf(char *buffer, size_t maxlength,
const char *format, ...);
CURL_EXTERN int curl_mvprintf(const char *format, va_list args);
CURL_EXTERN int curl_mvfprintf(FILE *fd, const char *format, va_list args);
CURL_EXTERN int curl_mvsprintf(char *buffer, const char *format, va_list args);
CURL_EXTERN int curl_mvsnprintf(char *buffer, size_t maxlength,
const char *format, va_list args);
CURL_EXTERN char *curl_maprintf(const char *format, ...);
CURL_EXTERN char *curl_mvaprintf(const char *format, va_list args);
#ifdef __cplusplus
}
#endif
#endif /* __CURL_MPRINTF_H */
| YifuLiu/AliOS-Things | components/curl/include/curl/mprintf.h | C | apache-2.0 | 2,076 |
#ifndef __CURL_MULTI_H
#define __CURL_MULTI_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2017, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/*
This is an "external" header file. Don't give away any internals here!
GOALS
o Enable a "pull" interface. The application that uses libcurl decides where
and when to ask libcurl to get/send data.
o Enable multiple simultaneous transfers in the same thread without making it
complicated for the application.
o Enable the application to select() on its own file descriptors and curl's
file descriptors simultaneous easily.
*/
/*
* This header file should not really need to include "curl.h" since curl.h
* itself includes this file and we expect user applications to do #include
* <curl/curl.h> without the need for especially including multi.h.
*
* For some reason we added this include here at one point, and rather than to
* break existing (wrongly written) libcurl applications, we leave it as-is
* but with this warning attached.
*/
#include "curl.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BUILDING_LIBCURL) || defined(CURL_STRICTER)
typedef struct Curl_multi CURLM;
#else
typedef void CURLM;
#endif
typedef enum {
CURLM_CALL_MULTI_PERFORM = -1, /* please call curl_multi_perform() or
curl_multi_socket*() soon */
CURLM_OK,
CURLM_BAD_HANDLE, /* the passed-in handle is not a valid CURLM handle */
CURLM_BAD_EASY_HANDLE, /* an easy handle was not good/valid */
CURLM_OUT_OF_MEMORY, /* if you ever get this, you're in deep sh*t */
CURLM_INTERNAL_ERROR, /* this is a libcurl bug */
CURLM_BAD_SOCKET, /* the passed in socket argument did not match */
CURLM_UNKNOWN_OPTION, /* curl_multi_setopt() with unsupported option */
CURLM_ADDED_ALREADY, /* an easy handle already added to a multi handle was
attempted to get added - again */
CURLM_RECURSIVE_API_CALL, /* an api function was called from inside a
callback */
CURLM_LAST
} CURLMcode;
/* just to make code nicer when using curl_multi_socket() you can now check
for CURLM_CALL_MULTI_SOCKET too in the same style it works for
curl_multi_perform() and CURLM_CALL_MULTI_PERFORM */
#define CURLM_CALL_MULTI_SOCKET CURLM_CALL_MULTI_PERFORM
/* bitmask bits for CURLMOPT_PIPELINING */
#define CURLPIPE_NOTHING 0L
#define CURLPIPE_HTTP1 1L
#define CURLPIPE_MULTIPLEX 2L
typedef enum {
CURLMSG_NONE, /* first, not used */
CURLMSG_DONE, /* This easy handle has completed. 'result' contains
the CURLcode of the transfer */
CURLMSG_LAST /* last, not used */
} CURLMSG;
struct CURLMsg {
CURLMSG msg; /* what this message means */
CURL *easy_handle; /* the handle it concerns */
union {
void *whatever; /* message-specific data */
CURLcode result; /* return code for transfer */
} data;
};
typedef struct CURLMsg CURLMsg;
/* Based on poll(2) structure and values.
* We don't use pollfd and POLL* constants explicitly
* to cover platforms without poll(). */
#define CURL_WAIT_POLLIN 0x0001
#define CURL_WAIT_POLLPRI 0x0002
#define CURL_WAIT_POLLOUT 0x0004
struct curl_waitfd {
curl_socket_t fd;
short events;
short revents; /* not supported yet */
};
/*
* Name: curl_multi_init()
*
* Desc: inititalize multi-style curl usage
*
* Returns: a new CURLM handle to use in all 'curl_multi' functions.
*/
CURL_EXTERN CURLM *curl_multi_init(void);
/*
* Name: curl_multi_add_handle()
*
* Desc: add a standard curl handle to the multi stack
*
* Returns: CURLMcode type, general multi error code.
*/
CURL_EXTERN CURLMcode curl_multi_add_handle(CURLM *multi_handle,
CURL *curl_handle);
/*
* Name: curl_multi_remove_handle()
*
* Desc: removes a curl handle from the multi stack again
*
* Returns: CURLMcode type, general multi error code.
*/
CURL_EXTERN CURLMcode curl_multi_remove_handle(CURLM *multi_handle,
CURL *curl_handle);
/*
* Name: curl_multi_fdset()
*
* Desc: Ask curl for its fd_set sets. The app can use these to select() or
* poll() on. We want curl_multi_perform() called as soon as one of
* them are ready.
*
* Returns: CURLMcode type, general multi error code.
*/
CURL_EXTERN CURLMcode curl_multi_fdset(CURLM *multi_handle,
fd_set *read_fd_set,
fd_set *write_fd_set,
fd_set *exc_fd_set,
int *max_fd);
/*
* Name: curl_multi_wait()
*
* Desc: Poll on all fds within a CURLM set as well as any
* additional fds passed to the function.
*
* Returns: CURLMcode type, general multi error code.
*/
CURL_EXTERN CURLMcode curl_multi_wait(CURLM *multi_handle,
struct curl_waitfd extra_fds[],
unsigned int extra_nfds,
int timeout_ms,
int *ret);
/*
* Name: curl_multi_perform()
*
* Desc: When the app thinks there's data available for curl it calls this
* function to read/write whatever there is right now. This returns
* as soon as the reads and writes are done. This function does not
* require that there actually is data available for reading or that
* data can be written, it can be called just in case. It returns
* the number of handles that still transfer data in the second
* argument's integer-pointer.
*
* Returns: CURLMcode type, general multi error code. *NOTE* that this only
* returns errors etc regarding the whole multi stack. There might
* still have occurred problems on individual transfers even when
* this returns OK.
*/
CURL_EXTERN CURLMcode curl_multi_perform(CURLM *multi_handle,
int *running_handles);
/*
* Name: curl_multi_cleanup()
*
* Desc: Cleans up and removes a whole multi stack. It does not free or
* touch any individual easy handles in any way. We need to define
* in what state those handles will be if this function is called
* in the middle of a transfer.
*
* Returns: CURLMcode type, general multi error code.
*/
CURL_EXTERN CURLMcode curl_multi_cleanup(CURLM *multi_handle);
/*
* Name: curl_multi_info_read()
*
* Desc: Ask the multi handle if there's any messages/informationals from
* the individual transfers. Messages include informationals such as
* error code from the transfer or just the fact that a transfer is
* completed. More details on these should be written down as well.
*
* Repeated calls to this function will return a new struct each
* time, until a special "end of msgs" struct is returned as a signal
* that there is no more to get at this point.
*
* The data the returned pointer points to will not survive calling
* curl_multi_cleanup().
*
* The 'CURLMsg' struct is meant to be very simple and only contain
* very basic information. If more involved information is wanted,
* we will provide the particular "transfer handle" in that struct
* and that should/could/would be used in subsequent
* curl_easy_getinfo() calls (or similar). The point being that we
* must never expose complex structs to applications, as then we'll
* undoubtably get backwards compatibility problems in the future.
*
* Returns: A pointer to a filled-in struct, or NULL if it failed or ran out
* of structs. It also writes the number of messages left in the
* queue (after this read) in the integer the second argument points
* to.
*/
CURL_EXTERN CURLMsg *curl_multi_info_read(CURLM *multi_handle,
int *msgs_in_queue);
/*
* Name: curl_multi_strerror()
*
* Desc: The curl_multi_strerror function may be used to turn a CURLMcode
* value into the equivalent human readable error string. This is
* useful for printing meaningful error messages.
*
* Returns: A pointer to a zero-terminated error message.
*/
CURL_EXTERN const char *curl_multi_strerror(CURLMcode);
/*
* Name: curl_multi_socket() and
* curl_multi_socket_all()
*
* Desc: An alternative version of curl_multi_perform() that allows the
* application to pass in one of the file descriptors that have been
* detected to have "action" on them and let libcurl perform.
* See man page for details.
*/
#define CURL_POLL_NONE 0
#define CURL_POLL_IN 1
#define CURL_POLL_OUT 2
#define CURL_POLL_INOUT 3
#define CURL_POLL_REMOVE 4
#define CURL_SOCKET_TIMEOUT CURL_SOCKET_BAD
#define CURL_CSELECT_IN 0x01
#define CURL_CSELECT_OUT 0x02
#define CURL_CSELECT_ERR 0x04
typedef int (*curl_socket_callback)(CURL *easy, /* easy handle */
curl_socket_t s, /* socket */
int what, /* see above */
void *userp, /* private callback
pointer */
void *socketp); /* private socket
pointer */
/*
* Name: curl_multi_timer_callback
*
* Desc: Called by libcurl whenever the library detects a change in the
* maximum number of milliseconds the app is allowed to wait before
* curl_multi_socket() or curl_multi_perform() must be called
* (to allow libcurl's timed events to take place).
*
* Returns: The callback should return zero.
*/
typedef int (*curl_multi_timer_callback)(CURLM *multi, /* multi handle */
long timeout_ms, /* see above */
void *userp); /* private callback
pointer */
CURL_EXTERN CURLMcode curl_multi_socket(CURLM *multi_handle, curl_socket_t s,
int *running_handles);
CURL_EXTERN CURLMcode curl_multi_socket_action(CURLM *multi_handle,
curl_socket_t s,
int ev_bitmask,
int *running_handles);
CURL_EXTERN CURLMcode curl_multi_socket_all(CURLM *multi_handle,
int *running_handles);
#ifndef CURL_ALLOW_OLD_MULTI_SOCKET
/* This macro below was added in 7.16.3 to push users who recompile to use
the new curl_multi_socket_action() instead of the old curl_multi_socket()
*/
#define curl_multi_socket(x,y,z) curl_multi_socket_action(x,y,0,z)
#endif
/*
* Name: curl_multi_timeout()
*
* Desc: Returns the maximum number of milliseconds the app is allowed to
* wait before curl_multi_socket() or curl_multi_perform() must be
* called (to allow libcurl's timed events to take place).
*
* Returns: CURLM error code.
*/
CURL_EXTERN CURLMcode curl_multi_timeout(CURLM *multi_handle,
long *milliseconds);
#undef CINIT /* re-using the same name as in curl.h */
#ifdef CURL_ISOCPP
#define CINIT(name,type,num) CURLMOPT_ ## name = CURLOPTTYPE_ ## type + num
#else
/* The macro "##" is ISO C, we assume pre-ISO C doesn't support it. */
#define LONG CURLOPTTYPE_LONG
#define OBJECTPOINT CURLOPTTYPE_OBJECTPOINT
#define FUNCTIONPOINT CURLOPTTYPE_FUNCTIONPOINT
#define OFF_T CURLOPTTYPE_OFF_T
#define CINIT(name,type,number) CURLMOPT_/**/name = type + number
#endif
typedef enum {
/* This is the socket callback function pointer */
CINIT(SOCKETFUNCTION, FUNCTIONPOINT, 1),
/* This is the argument passed to the socket callback */
CINIT(SOCKETDATA, OBJECTPOINT, 2),
/* set to 1 to enable pipelining for this multi handle */
CINIT(PIPELINING, LONG, 3),
/* This is the timer callback function pointer */
CINIT(TIMERFUNCTION, FUNCTIONPOINT, 4),
/* This is the argument passed to the timer callback */
CINIT(TIMERDATA, OBJECTPOINT, 5),
/* maximum number of entries in the connection cache */
CINIT(MAXCONNECTS, LONG, 6),
/* maximum number of (pipelining) connections to one host */
CINIT(MAX_HOST_CONNECTIONS, LONG, 7),
/* maximum number of requests in a pipeline */
CINIT(MAX_PIPELINE_LENGTH, LONG, 8),
/* a connection with a content-length longer than this
will not be considered for pipelining */
CINIT(CONTENT_LENGTH_PENALTY_SIZE, OFF_T, 9),
/* a connection with a chunk length longer than this
will not be considered for pipelining */
CINIT(CHUNK_LENGTH_PENALTY_SIZE, OFF_T, 10),
/* a list of site names(+port) that are blacklisted from
pipelining */
CINIT(PIPELINING_SITE_BL, OBJECTPOINT, 11),
/* a list of server types that are blacklisted from
pipelining */
CINIT(PIPELINING_SERVER_BL, OBJECTPOINT, 12),
/* maximum number of open connections in total */
CINIT(MAX_TOTAL_CONNECTIONS, LONG, 13),
/* This is the server push callback function pointer */
CINIT(PUSHFUNCTION, FUNCTIONPOINT, 14),
/* This is the argument passed to the server push callback */
CINIT(PUSHDATA, OBJECTPOINT, 15),
CURLMOPT_LASTENTRY /* the last unused */
} CURLMoption;
/*
* Name: curl_multi_setopt()
*
* Desc: Sets options for the multi handle.
*
* Returns: CURLM error code.
*/
CURL_EXTERN CURLMcode curl_multi_setopt(CURLM *multi_handle,
CURLMoption option, ...);
/*
* Name: curl_multi_assign()
*
* Desc: This function sets an association in the multi handle between the
* given socket and a private pointer of the application. This is
* (only) useful for curl_multi_socket uses.
*
* Returns: CURLM error code.
*/
CURL_EXTERN CURLMcode curl_multi_assign(CURLM *multi_handle,
curl_socket_t sockfd, void *sockp);
/*
* Name: curl_push_callback
*
* Desc: This callback gets called when a new stream is being pushed by the
* server. It approves or denies the new stream.
*
* Returns: CURL_PUSH_OK or CURL_PUSH_DENY.
*/
#define CURL_PUSH_OK 0
#define CURL_PUSH_DENY 1
struct curl_pushheaders; /* forward declaration only */
CURL_EXTERN char *curl_pushheader_bynum(struct curl_pushheaders *h,
size_t num);
CURL_EXTERN char *curl_pushheader_byname(struct curl_pushheaders *h,
const char *name);
typedef int (*curl_push_callback)(CURL *parent,
CURL *easy,
size_t num_headers,
struct curl_pushheaders *headers,
void *userp);
#ifdef __cplusplus
} /* end of extern "C" */
#endif
#endif
| YifuLiu/AliOS-Things | components/curl/include/curl/multi.h | C | apache-2.0 | 16,211 |
#ifndef __STDC_HEADERS_H
#define __STDC_HEADERS_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2016, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include <sys/types.h>
size_t fread(void *, size_t, size_t, FILE *);
size_t fwrite(const void *, size_t, size_t, FILE *);
int strcasecmp(const char *, const char *);
int strncasecmp(const char *, const char *, size_t);
#endif /* __STDC_HEADERS_H */
| YifuLiu/AliOS-Things | components/curl/include/curl/stdcheaders.h | C | apache-2.0 | 1,329 |
#ifndef __CURL_SYSTEM_H
#define __CURL_SYSTEM_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2017, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/*
* Try to keep one section per platform, compiler and architecture, otherwise,
* if an existing section is reused for a different one and later on the
* original is adjusted, probably the piggybacking one can be adversely
* changed.
*
* In order to differentiate between platforms/compilers/architectures use
* only compiler built in predefined preprocessor symbols.
*
* curl_off_t
* ----------
*
* For any given platform/compiler curl_off_t must be typedef'ed to a 64-bit
* wide signed integral data type. The width of this data type must remain
* constant and independent of any possible large file support settings.
*
* As an exception to the above, curl_off_t shall be typedef'ed to a 32-bit
* wide signed integral data type if there is no 64-bit type.
*
* As a general rule, curl_off_t shall not be mapped to off_t. This rule shall
* only be violated if off_t is the only 64-bit data type available and the
* size of off_t is independent of large file support settings. Keep your
* build on the safe side avoiding an off_t gating. If you have a 64-bit
* off_t then take for sure that another 64-bit data type exists, dig deeper
* and you will find it.
*
*/
#if defined(__DJGPP__) || defined(__GO32__)
# if defined(__DJGPP__) && (__DJGPP__ > 1)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# else
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__SALFORDC__)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__BORLANDC__)
# if (__BORLANDC__ < 0x520)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# else
# define CURL_TYPEOF_CURL_OFF_T __int64
# define CURL_FORMAT_CURL_OFF_T "I64d"
# define CURL_FORMAT_CURL_OFF_TU "I64u"
# define CURL_SUFFIX_CURL_OFF_T i64
# define CURL_SUFFIX_CURL_OFF_TU ui64
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__TURBOC__)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__WATCOMC__)
# if defined(__386__)
# define CURL_TYPEOF_CURL_OFF_T __int64
# define CURL_FORMAT_CURL_OFF_T "I64d"
# define CURL_FORMAT_CURL_OFF_TU "I64u"
# define CURL_SUFFIX_CURL_OFF_T i64
# define CURL_SUFFIX_CURL_OFF_TU ui64
# else
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__POCC__)
# if (__POCC__ < 280)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# elif defined(_MSC_VER)
# define CURL_TYPEOF_CURL_OFF_T __int64
# define CURL_FORMAT_CURL_OFF_T "I64d"
# define CURL_FORMAT_CURL_OFF_TU "I64u"
# define CURL_SUFFIX_CURL_OFF_T i64
# define CURL_SUFFIX_CURL_OFF_TU ui64
# else
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__LCC__)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__SYMBIAN32__)
# if defined(__EABI__) /* Treat all ARM compilers equally */
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# elif defined(__CW32__)
# pragma longlong on
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# elif defined(__VC32__)
# define CURL_TYPEOF_CURL_OFF_T __int64
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T unsigned int
#elif defined(__MWERKS__)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(_WIN32_WCE)
# define CURL_TYPEOF_CURL_OFF_T __int64
# define CURL_FORMAT_CURL_OFF_T "I64d"
# define CURL_FORMAT_CURL_OFF_TU "I64u"
# define CURL_SUFFIX_CURL_OFF_T i64
# define CURL_SUFFIX_CURL_OFF_TU ui64
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__MINGW32__)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "I64d"
# define CURL_FORMAT_CURL_OFF_TU "I64u"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_WS2TCPIP_H 1
#elif defined(__VMS)
# if defined(__VAX)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# else
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T unsigned int
#elif defined(__OS400__)
# if defined(__ILEC400__)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
# endif
#elif defined(__MVS__)
# if defined(__IBMC__) || defined(__IBMCPP__)
# if defined(_ILP32)
# elif defined(_LP64)
# endif
# if defined(_LONG_LONG)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# elif defined(_LP64)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# else
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
# endif
#elif defined(__370__)
# if defined(__IBMC__) || defined(__IBMCPP__)
# if defined(_ILP32)
# elif defined(_LP64)
# endif
# if defined(_LONG_LONG)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# elif defined(_LP64)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# else
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
# endif
#elif defined(TPF)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#elif defined(__TINYC__) /* also known as tcc */
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) /* Oracle Solaris Studio */
# if !defined(__LP64) && (defined(__ILP32) || \
defined(__i386) || \
defined(__sparcv8) || \
defined(__sparcv8plus))
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# elif defined(__LP64) || \
defined(__amd64) || defined(__sparcv9)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
#elif defined(__xlc__) /* IBM xlc compiler */
# if !defined(_LP64)
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# else
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
/* ===================================== */
/* KEEP MSVC THE PENULTIMATE ENTRY */
/* ===================================== */
#elif defined(_MSC_VER)
# if (_MSC_VER >= 900) && (_INTEGRAL_MAX_BITS >= 64)
# define CURL_TYPEOF_CURL_OFF_T __int64
# define CURL_FORMAT_CURL_OFF_T "I64d"
# define CURL_FORMAT_CURL_OFF_TU "I64u"
# define CURL_SUFFIX_CURL_OFF_T i64
# define CURL_SUFFIX_CURL_OFF_TU ui64
# else
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T int
/* ===================================== */
/* KEEP GENERIC GCC THE LAST ENTRY */
/* ===================================== */
#elif defined(__GNUC__) && !defined(_SCO_DS)
# if !defined(__LP64__) && \
(defined(__ILP32__) || defined(__i386__) || defined(__hppa__) || \
defined(__ppc__) || defined(__powerpc__) || defined(__arm__) || \
defined(__sparc__) || defined(__mips__) || defined(__sh__) || \
defined(__XTENSA__) || \
(defined(__SIZEOF_LONG__) && __SIZEOF_LONG__ == 4) || \
(defined(__LONG_MAX__) && __LONG_MAX__ == 2147483647L))
# define CURL_TYPEOF_CURL_OFF_T long long
# define CURL_FORMAT_CURL_OFF_T "lld"
# define CURL_FORMAT_CURL_OFF_TU "llu"
# define CURL_SUFFIX_CURL_OFF_T LL
# define CURL_SUFFIX_CURL_OFF_TU ULL
# elif defined(__LP64__) || \
defined(__x86_64__) || defined(__ppc64__) || defined(__sparc64__) || \
(defined(__SIZEOF_LONG__) && __SIZEOF_LONG__ == 8) || \
(defined(__LONG_MAX__) && __LONG_MAX__ == 9223372036854775807L)
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# endif
# define CURL_TYPEOF_CURL_SOCKLEN_T socklen_t
# define CURL_PULL_SYS_TYPES_H 1
# define CURL_PULL_SYS_SOCKET_H 1
#else
/* generic "safe guess" on old 32 bit style */
# define CURL_TYPEOF_CURL_OFF_T long
# define CURL_FORMAT_CURL_OFF_T "ld"
# define CURL_FORMAT_CURL_OFF_TU "lu"
# define CURL_SUFFIX_CURL_OFF_T L
# define CURL_SUFFIX_CURL_OFF_TU UL
# define CURL_TYPEOF_CURL_SOCKLEN_T int
#endif
#ifdef _AIX
/* AIX needs <sys/poll.h> */
#define CURL_PULL_SYS_POLL_H
#endif
/* CURL_PULL_WS2TCPIP_H is defined above when inclusion of header file */
/* ws2tcpip.h is required here to properly make type definitions below. */
#ifdef CURL_PULL_WS2TCPIP_H
# include <winsock2.h>
# include <windows.h>
# include <ws2tcpip.h>
#endif
/* CURL_PULL_SYS_TYPES_H is defined above when inclusion of header file */
/* sys/types.h is required here to properly make type definitions below. */
#ifdef CURL_PULL_SYS_TYPES_H
# include <sys/types.h>
#endif
/* CURL_PULL_SYS_SOCKET_H is defined above when inclusion of header file */
/* sys/socket.h is required here to properly make type definitions below. */
#ifdef CURL_PULL_SYS_SOCKET_H
#ifdef USE_LWIPSOCK
# include <lwip/sockets.h>
#else
# include <sys/socket.h>
#endif
#endif
/* CURL_PULL_SYS_POLL_H is defined above when inclusion of header file */
/* sys/poll.h is required here to properly make type definitions below. */
#ifdef CURL_PULL_SYS_POLL_H
# include <sys/poll.h>
#endif
/* Data type definition of curl_socklen_t. */
#ifdef CURL_TYPEOF_CURL_SOCKLEN_T
typedef CURL_TYPEOF_CURL_SOCKLEN_T curl_socklen_t;
#endif
/* Data type definition of curl_off_t. */
#ifdef CURL_TYPEOF_CURL_OFF_T
typedef CURL_TYPEOF_CURL_OFF_T curl_off_t;
#endif
/*
* CURL_ISOCPP and CURL_OFF_T_C definitions are done here in order to allow
* these to be visible and exported by the external libcurl interface API,
* while also making them visible to the library internals, simply including
* curl_setup.h, without actually needing to include curl.h internally.
* If some day this section would grow big enough, all this should be moved
* to its own header file.
*/
/*
* Figure out if we can use the ## preprocessor operator, which is supported
* by ISO/ANSI C and C++. Some compilers support it without setting __STDC__
* or __cplusplus so we need to carefully check for them too.
*/
#if defined(__STDC__) || defined(_MSC_VER) || defined(__cplusplus) || \
defined(__HP_aCC) || defined(__BORLANDC__) || defined(__LCC__) || \
defined(__POCC__) || defined(__SALFORDC__) || defined(__HIGHC__) || \
defined(__ILEC400__)
/* This compiler is believed to have an ISO compatible preprocessor */
#define CURL_ISOCPP
#else
/* This compiler is believed NOT to have an ISO compatible preprocessor */
#undef CURL_ISOCPP
#endif
/*
* Macros for minimum-width signed and unsigned curl_off_t integer constants.
*/
#if defined(__BORLANDC__) && (__BORLANDC__ == 0x0551)
# define __CURL_OFF_T_C_HLPR2(x) x
# define __CURL_OFF_T_C_HLPR1(x) __CURL_OFF_T_C_HLPR2(x)
# define CURL_OFF_T_C(Val) __CURL_OFF_T_C_HLPR1(Val) ## \
__CURL_OFF_T_C_HLPR1(CURL_SUFFIX_CURL_OFF_T)
# define CURL_OFF_TU_C(Val) __CURL_OFF_T_C_HLPR1(Val) ## \
__CURL_OFF_T_C_HLPR1(CURL_SUFFIX_CURL_OFF_TU)
#else
# ifdef CURL_ISOCPP
# define __CURL_OFF_T_C_HLPR2(Val,Suffix) Val ## Suffix
# else
# define __CURL_OFF_T_C_HLPR2(Val,Suffix) Val/**/Suffix
# endif
# define __CURL_OFF_T_C_HLPR1(Val,Suffix) __CURL_OFF_T_C_HLPR2(Val,Suffix)
# define CURL_OFF_T_C(Val) __CURL_OFF_T_C_HLPR1(Val,CURL_SUFFIX_CURL_OFF_T)
# define CURL_OFF_TU_C(Val) __CURL_OFF_T_C_HLPR1(Val,CURL_SUFFIX_CURL_OFF_TU)
#endif
#endif /* __CURL_SYSTEM_H */
| YifuLiu/AliOS-Things | components/curl/include/curl/system.h | C | apache-2.0 | 18,574 |
#ifndef __CURL_TYPECHECK_GCC_H
#define __CURL_TYPECHECK_GCC_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/* wraps curl_easy_setopt() with typechecking */
/* To add a new kind of warning, add an
* if(_curl_is_sometype_option(_curl_opt))
* if(!_curl_is_sometype(value))
* _curl_easy_setopt_err_sometype();
* block and define _curl_is_sometype_option, _curl_is_sometype and
* _curl_easy_setopt_err_sometype below
*
* NOTE: We use two nested 'if' statements here instead of the && operator, in
* order to work around gcc bug #32061. It affects only gcc 4.3.x/4.4.x
* when compiling with -Wlogical-op.
*
* To add an option that uses the same type as an existing option, you'll just
* need to extend the appropriate _curl_*_option macro
*/
#define curl_easy_setopt(handle, option, value) \
__extension__ ({ \
__typeof__(option) _curl_opt = option; \
if(__builtin_constant_p(_curl_opt)) { \
if(_curl_is_long_option(_curl_opt)) \
if(!_curl_is_long(value)) \
_curl_easy_setopt_err_long(); \
if(_curl_is_off_t_option(_curl_opt)) \
if(!_curl_is_off_t(value)) \
_curl_easy_setopt_err_curl_off_t(); \
if(_curl_is_string_option(_curl_opt)) \
if(!_curl_is_string(value)) \
_curl_easy_setopt_err_string(); \
if(_curl_is_write_cb_option(_curl_opt)) \
if(!_curl_is_write_cb(value)) \
_curl_easy_setopt_err_write_callback(); \
if((_curl_opt) == CURLOPT_RESOLVER_START_FUNCTION) \
if(!_curl_is_resolver_start_callback(value)) \
_curl_easy_setopt_err_resolver_start_callback(); \
if((_curl_opt) == CURLOPT_READFUNCTION) \
if(!_curl_is_read_cb(value)) \
_curl_easy_setopt_err_read_cb(); \
if((_curl_opt) == CURLOPT_IOCTLFUNCTION) \
if(!_curl_is_ioctl_cb(value)) \
_curl_easy_setopt_err_ioctl_cb(); \
if((_curl_opt) == CURLOPT_SOCKOPTFUNCTION) \
if(!_curl_is_sockopt_cb(value)) \
_curl_easy_setopt_err_sockopt_cb(); \
if((_curl_opt) == CURLOPT_OPENSOCKETFUNCTION) \
if(!_curl_is_opensocket_cb(value)) \
_curl_easy_setopt_err_opensocket_cb(); \
if((_curl_opt) == CURLOPT_PROGRESSFUNCTION) \
if(!_curl_is_progress_cb(value)) \
_curl_easy_setopt_err_progress_cb(); \
if((_curl_opt) == CURLOPT_DEBUGFUNCTION) \
if(!_curl_is_debug_cb(value)) \
_curl_easy_setopt_err_debug_cb(); \
if((_curl_opt) == CURLOPT_SSL_CTX_FUNCTION) \
if(!_curl_is_ssl_ctx_cb(value)) \
_curl_easy_setopt_err_ssl_ctx_cb(); \
if(_curl_is_conv_cb_option(_curl_opt)) \
if(!_curl_is_conv_cb(value)) \
_curl_easy_setopt_err_conv_cb(); \
if((_curl_opt) == CURLOPT_SEEKFUNCTION) \
if(!_curl_is_seek_cb(value)) \
_curl_easy_setopt_err_seek_cb(); \
if(_curl_is_cb_data_option(_curl_opt)) \
if(!_curl_is_cb_data(value)) \
_curl_easy_setopt_err_cb_data(); \
if((_curl_opt) == CURLOPT_ERRORBUFFER) \
if(!_curl_is_error_buffer(value)) \
_curl_easy_setopt_err_error_buffer(); \
if((_curl_opt) == CURLOPT_STDERR) \
if(!_curl_is_FILE(value)) \
_curl_easy_setopt_err_FILE(); \
if(_curl_is_postfields_option(_curl_opt)) \
if(!_curl_is_postfields(value)) \
_curl_easy_setopt_err_postfields(); \
if((_curl_opt) == CURLOPT_HTTPPOST) \
if(!_curl_is_arr((value), struct curl_httppost)) \
_curl_easy_setopt_err_curl_httpost(); \
if((_curl_opt) == CURLOPT_MIMEPOST) \
if(!_curl_is_ptr((value), curl_mime)) \
_curl_easy_setopt_err_curl_mimepost(); \
if(_curl_is_slist_option(_curl_opt)) \
if(!_curl_is_arr((value), struct curl_slist)) \
_curl_easy_setopt_err_curl_slist(); \
if((_curl_opt) == CURLOPT_SHARE) \
if(!_curl_is_ptr((value), CURLSH)) \
_curl_easy_setopt_err_CURLSH(); \
} \
curl_easy_setopt(handle, _curl_opt, value); \
})
/* wraps curl_easy_getinfo() with typechecking */
#define curl_easy_getinfo(handle, info, arg) \
__extension__ ({ \
__typeof__(info) _curl_info = info; \
if(__builtin_constant_p(_curl_info)) { \
if(_curl_is_string_info(_curl_info)) \
if(!_curl_is_arr((arg), char *)) \
_curl_easy_getinfo_err_string(); \
if(_curl_is_long_info(_curl_info)) \
if(!_curl_is_arr((arg), long)) \
_curl_easy_getinfo_err_long(); \
if(_curl_is_double_info(_curl_info)) \
if(!_curl_is_arr((arg), double)) \
_curl_easy_getinfo_err_double(); \
if(_curl_is_slist_info(_curl_info)) \
if(!_curl_is_arr((arg), struct curl_slist *)) \
_curl_easy_getinfo_err_curl_slist(); \
if(_curl_is_tlssessioninfo_info(_curl_info)) \
if(!_curl_is_arr((arg), struct curl_tlssessioninfo *)) \
_curl_easy_getinfo_err_curl_tlssesssioninfo(); \
if(_curl_is_certinfo_info(_curl_info)) \
if(!_curl_is_arr((arg), struct curl_certinfo *)) \
_curl_easy_getinfo_err_curl_certinfo(); \
if(_curl_is_socket_info(_curl_info)) \
if(!_curl_is_arr((arg), curl_socket_t)) \
_curl_easy_getinfo_err_curl_socket(); \
if(_curl_is_off_t_info(_curl_info)) \
if(!_curl_is_arr((arg), curl_off_t)) \
_curl_easy_getinfo_err_curl_off_t(); \
} \
curl_easy_getinfo(handle, _curl_info, arg); \
})
/*
* For now, just make sure that the functions are called with three arguments
*/
#define curl_share_setopt(share,opt,param) curl_share_setopt(share,opt,param)
#define curl_multi_setopt(handle,opt,param) curl_multi_setopt(handle,opt,param)
/* the actual warnings, triggered by calling the _curl_easy_setopt_err*
* functions */
/* To define a new warning, use _CURL_WARNING(identifier, "message") */
#define _CURL_WARNING(id, message) \
static void __attribute__((__warning__(message))) \
__attribute__((__unused__)) __attribute__((__noinline__)) \
id(void) { __asm__(""); }
_CURL_WARNING(_curl_easy_setopt_err_long,
"curl_easy_setopt expects a long argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_curl_off_t,
"curl_easy_setopt expects a curl_off_t argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_string,
"curl_easy_setopt expects a "
"string ('char *' or char[]) argument for this option"
)
_CURL_WARNING(_curl_easy_setopt_err_write_callback,
"curl_easy_setopt expects a curl_write_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_resolver_start_callback,
"curl_easy_setopt expects a "
"curl_resolver_start_callback argument for this option"
)
_CURL_WARNING(_curl_easy_setopt_err_read_cb,
"curl_easy_setopt expects a curl_read_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_ioctl_cb,
"curl_easy_setopt expects a curl_ioctl_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_sockopt_cb,
"curl_easy_setopt expects a curl_sockopt_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_opensocket_cb,
"curl_easy_setopt expects a "
"curl_opensocket_callback argument for this option"
)
_CURL_WARNING(_curl_easy_setopt_err_progress_cb,
"curl_easy_setopt expects a curl_progress_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_debug_cb,
"curl_easy_setopt expects a curl_debug_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_ssl_ctx_cb,
"curl_easy_setopt expects a curl_ssl_ctx_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_conv_cb,
"curl_easy_setopt expects a curl_conv_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_seek_cb,
"curl_easy_setopt expects a curl_seek_callback argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_cb_data,
"curl_easy_setopt expects a "
"private data pointer as argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_error_buffer,
"curl_easy_setopt expects a "
"char buffer of CURL_ERROR_SIZE as argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_FILE,
"curl_easy_setopt expects a 'FILE *' argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_postfields,
"curl_easy_setopt expects a 'void *' or 'char *' argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_curl_httpost,
"curl_easy_setopt expects a 'struct curl_httppost *' "
"argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_curl_mimepost,
"curl_easy_setopt expects a 'curl_mime *' "
"argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_curl_slist,
"curl_easy_setopt expects a 'struct curl_slist *' argument for this option")
_CURL_WARNING(_curl_easy_setopt_err_CURLSH,
"curl_easy_setopt expects a CURLSH* argument for this option")
_CURL_WARNING(_curl_easy_getinfo_err_string,
"curl_easy_getinfo expects a pointer to 'char *' for this info")
_CURL_WARNING(_curl_easy_getinfo_err_long,
"curl_easy_getinfo expects a pointer to long for this info")
_CURL_WARNING(_curl_easy_getinfo_err_double,
"curl_easy_getinfo expects a pointer to double for this info")
_CURL_WARNING(_curl_easy_getinfo_err_curl_slist,
"curl_easy_getinfo expects a pointer to 'struct curl_slist *' for this info")
_CURL_WARNING(_curl_easy_getinfo_err_curl_tlssesssioninfo,
"curl_easy_getinfo expects a pointer to "
"'struct curl_tlssessioninfo *' for this info")
_CURL_WARNING(_curl_easy_getinfo_err_curl_certinfo,
"curl_easy_getinfo expects a pointer to "
"'struct curl_certinfo *' for this info")
_CURL_WARNING(_curl_easy_getinfo_err_curl_socket,
"curl_easy_getinfo expects a pointer to curl_socket_t for this info")
_CURL_WARNING(_curl_easy_getinfo_err_curl_off_t,
"curl_easy_getinfo expects a pointer to curl_off_t for this info")
/* groups of curl_easy_setops options that take the same type of argument */
/* To add a new option to one of the groups, just add
* (option) == CURLOPT_SOMETHING
* to the or-expression. If the option takes a long or curl_off_t, you don't
* have to do anything
*/
/* evaluates to true if option takes a long argument */
#define _curl_is_long_option(option) \
(0 < (option) && (option) < CURLOPTTYPE_OBJECTPOINT)
#define _curl_is_off_t_option(option) \
((option) > CURLOPTTYPE_OFF_T)
/* evaluates to true if option takes a char* argument */
#define _curl_is_string_option(option) \
((option) == CURLOPT_ABSTRACT_UNIX_SOCKET || \
(option) == CURLOPT_ACCEPT_ENCODING || \
(option) == CURLOPT_ALTSVC || \
(option) == CURLOPT_CAINFO || \
(option) == CURLOPT_CAPATH || \
(option) == CURLOPT_COOKIE || \
(option) == CURLOPT_COOKIEFILE || \
(option) == CURLOPT_COOKIEJAR || \
(option) == CURLOPT_COOKIELIST || \
(option) == CURLOPT_CRLFILE || \
(option) == CURLOPT_CUSTOMREQUEST || \
(option) == CURLOPT_DEFAULT_PROTOCOL || \
(option) == CURLOPT_DNS_INTERFACE || \
(option) == CURLOPT_DNS_LOCAL_IP4 || \
(option) == CURLOPT_DNS_LOCAL_IP6 || \
(option) == CURLOPT_DNS_SERVERS || \
(option) == CURLOPT_DOH_URL || \
(option) == CURLOPT_EGDSOCKET || \
(option) == CURLOPT_FTPPORT || \
(option) == CURLOPT_FTP_ACCOUNT || \
(option) == CURLOPT_FTP_ALTERNATIVE_TO_USER || \
(option) == CURLOPT_INTERFACE || \
(option) == CURLOPT_ISSUERCERT || \
(option) == CURLOPT_KEYPASSWD || \
(option) == CURLOPT_KRBLEVEL || \
(option) == CURLOPT_LOGIN_OPTIONS || \
(option) == CURLOPT_MAIL_AUTH || \
(option) == CURLOPT_MAIL_FROM || \
(option) == CURLOPT_NETRC_FILE || \
(option) == CURLOPT_NOPROXY || \
(option) == CURLOPT_PASSWORD || \
(option) == CURLOPT_PINNEDPUBLICKEY || \
(option) == CURLOPT_PRE_PROXY || \
(option) == CURLOPT_PROXY || \
(option) == CURLOPT_PROXYPASSWORD || \
(option) == CURLOPT_PROXYUSERNAME || \
(option) == CURLOPT_PROXYUSERPWD || \
(option) == CURLOPT_PROXY_CAINFO || \
(option) == CURLOPT_PROXY_CAPATH || \
(option) == CURLOPT_PROXY_CRLFILE || \
(option) == CURLOPT_PROXY_KEYPASSWD || \
(option) == CURLOPT_PROXY_PINNEDPUBLICKEY || \
(option) == CURLOPT_PROXY_SERVICE_NAME || \
(option) == CURLOPT_PROXY_SSLCERT || \
(option) == CURLOPT_PROXY_SSLCERTTYPE || \
(option) == CURLOPT_PROXY_SSLKEY || \
(option) == CURLOPT_PROXY_SSLKEYTYPE || \
(option) == CURLOPT_PROXY_SSL_CIPHER_LIST || \
(option) == CURLOPT_PROXY_TLSAUTH_PASSWORD || \
(option) == CURLOPT_PROXY_TLSAUTH_USERNAME || \
(option) == CURLOPT_PROXY_TLSAUTH_TYPE || \
(option) == CURLOPT_RANDOM_FILE || \
(option) == CURLOPT_RANGE || \
(option) == CURLOPT_REFERER || \
(option) == CURLOPT_RTSP_SESSION_ID || \
(option) == CURLOPT_RTSP_STREAM_URI || \
(option) == CURLOPT_RTSP_TRANSPORT || \
(option) == CURLOPT_SERVICE_NAME || \
(option) == CURLOPT_SOCKS5_GSSAPI_SERVICE || \
(option) == CURLOPT_SSH_HOST_PUBLIC_KEY_MD5 || \
(option) == CURLOPT_SSH_KNOWNHOSTS || \
(option) == CURLOPT_SSH_PRIVATE_KEYFILE || \
(option) == CURLOPT_SSH_PUBLIC_KEYFILE || \
(option) == CURLOPT_SSLCERT || \
(option) == CURLOPT_SSLCERTTYPE || \
(option) == CURLOPT_SSLENGINE || \
(option) == CURLOPT_SSLKEY || \
(option) == CURLOPT_SSLKEYTYPE || \
(option) == CURLOPT_SSL_CIPHER_LIST || \
(option) == CURLOPT_TLSAUTH_PASSWORD || \
(option) == CURLOPT_TLSAUTH_TYPE || \
(option) == CURLOPT_TLSAUTH_USERNAME || \
(option) == CURLOPT_UNIX_SOCKET_PATH || \
(option) == CURLOPT_URL || \
(option) == CURLOPT_USERAGENT || \
(option) == CURLOPT_USERNAME || \
(option) == CURLOPT_USERPWD || \
(option) == CURLOPT_XOAUTH2_BEARER || \
0)
/* evaluates to true if option takes a curl_write_callback argument */
#define _curl_is_write_cb_option(option) \
((option) == CURLOPT_HEADERFUNCTION || \
(option) == CURLOPT_WRITEFUNCTION)
/* evaluates to true if option takes a curl_conv_callback argument */
#define _curl_is_conv_cb_option(option) \
((option) == CURLOPT_CONV_TO_NETWORK_FUNCTION || \
(option) == CURLOPT_CONV_FROM_NETWORK_FUNCTION || \
(option) == CURLOPT_CONV_FROM_UTF8_FUNCTION)
/* evaluates to true if option takes a data argument to pass to a callback */
#define _curl_is_cb_data_option(option) \
((option) == CURLOPT_CHUNK_DATA || \
(option) == CURLOPT_CLOSESOCKETDATA || \
(option) == CURLOPT_DEBUGDATA || \
(option) == CURLOPT_FNMATCH_DATA || \
(option) == CURLOPT_HEADERDATA || \
(option) == CURLOPT_INTERLEAVEDATA || \
(option) == CURLOPT_IOCTLDATA || \
(option) == CURLOPT_OPENSOCKETDATA || \
(option) == CURLOPT_PRIVATE || \
(option) == CURLOPT_PROGRESSDATA || \
(option) == CURLOPT_READDATA || \
(option) == CURLOPT_SEEKDATA || \
(option) == CURLOPT_SOCKOPTDATA || \
(option) == CURLOPT_SSH_KEYDATA || \
(option) == CURLOPT_SSL_CTX_DATA || \
(option) == CURLOPT_WRITEDATA || \
(option) == CURLOPT_RESOLVER_START_DATA || \
(option) == CURLOPT_CURLU || \
0)
/* evaluates to true if option takes a POST data argument (void* or char*) */
#define _curl_is_postfields_option(option) \
((option) == CURLOPT_POSTFIELDS || \
(option) == CURLOPT_COPYPOSTFIELDS || \
0)
/* evaluates to true if option takes a struct curl_slist * argument */
#define _curl_is_slist_option(option) \
((option) == CURLOPT_HTTP200ALIASES || \
(option) == CURLOPT_HTTPHEADER || \
(option) == CURLOPT_MAIL_RCPT || \
(option) == CURLOPT_POSTQUOTE || \
(option) == CURLOPT_PREQUOTE || \
(option) == CURLOPT_PROXYHEADER || \
(option) == CURLOPT_QUOTE || \
(option) == CURLOPT_RESOLVE || \
(option) == CURLOPT_TELNETOPTIONS || \
0)
/* groups of curl_easy_getinfo infos that take the same type of argument */
/* evaluates to true if info expects a pointer to char * argument */
#define _curl_is_string_info(info) \
(CURLINFO_STRING < (info) && (info) < CURLINFO_LONG)
/* evaluates to true if info expects a pointer to long argument */
#define _curl_is_long_info(info) \
(CURLINFO_LONG < (info) && (info) < CURLINFO_DOUBLE)
/* evaluates to true if info expects a pointer to double argument */
#define _curl_is_double_info(info) \
(CURLINFO_DOUBLE < (info) && (info) < CURLINFO_SLIST)
/* true if info expects a pointer to struct curl_slist * argument */
#define _curl_is_slist_info(info) \
(((info) == CURLINFO_SSL_ENGINES) || ((info) == CURLINFO_COOKIELIST))
/* true if info expects a pointer to struct curl_tlssessioninfo * argument */
#define _curl_is_tlssessioninfo_info(info) \
(((info) == CURLINFO_TLS_SSL_PTR) || ((info) == CURLINFO_TLS_SESSION))
/* true if info expects a pointer to struct curl_certinfo * argument */
#define _curl_is_certinfo_info(info) ((info) == CURLINFO_CERTINFO)
/* true if info expects a pointer to struct curl_socket_t argument */
#define _curl_is_socket_info(info) \
(CURLINFO_SOCKET < (info) && (info) < CURLINFO_OFF_T)
/* true if info expects a pointer to curl_off_t argument */
#define _curl_is_off_t_info(info) \
(CURLINFO_OFF_T < (info))
/* typecheck helpers -- check whether given expression has requested type*/
/* For pointers, you can use the _curl_is_ptr/_curl_is_arr macros,
* otherwise define a new macro. Search for __builtin_types_compatible_p
* in the GCC manual.
* NOTE: these macros MUST NOT EVALUATE their arguments! The argument is
* the actual expression passed to the curl_easy_setopt macro. This
* means that you can only apply the sizeof and __typeof__ operators, no
* == or whatsoever.
*/
/* XXX: should evaluate to true if expr is a pointer */
#define _curl_is_any_ptr(expr) \
(sizeof(expr) == sizeof(void *))
/* evaluates to true if expr is NULL */
/* XXX: must not evaluate expr, so this check is not accurate */
#define _curl_is_NULL(expr) \
(__builtin_types_compatible_p(__typeof__(expr), __typeof__(NULL)))
/* evaluates to true if expr is type*, const type* or NULL */
#define _curl_is_ptr(expr, type) \
(_curl_is_NULL(expr) || \
__builtin_types_compatible_p(__typeof__(expr), type *) || \
__builtin_types_compatible_p(__typeof__(expr), const type *))
/* evaluates to true if expr is one of type[], type*, NULL or const type* */
#define _curl_is_arr(expr, type) \
(_curl_is_ptr((expr), type) || \
__builtin_types_compatible_p(__typeof__(expr), type []))
/* evaluates to true if expr is a string */
#define _curl_is_string(expr) \
(_curl_is_arr((expr), char) || \
_curl_is_arr((expr), signed char) || \
_curl_is_arr((expr), unsigned char))
/* evaluates to true if expr is a long (no matter the signedness)
* XXX: for now, int is also accepted (and therefore short and char, which
* are promoted to int when passed to a variadic function) */
#define _curl_is_long(expr) \
(__builtin_types_compatible_p(__typeof__(expr), long) || \
__builtin_types_compatible_p(__typeof__(expr), signed long) || \
__builtin_types_compatible_p(__typeof__(expr), unsigned long) || \
__builtin_types_compatible_p(__typeof__(expr), int) || \
__builtin_types_compatible_p(__typeof__(expr), signed int) || \
__builtin_types_compatible_p(__typeof__(expr), unsigned int) || \
__builtin_types_compatible_p(__typeof__(expr), short) || \
__builtin_types_compatible_p(__typeof__(expr), signed short) || \
__builtin_types_compatible_p(__typeof__(expr), unsigned short) || \
__builtin_types_compatible_p(__typeof__(expr), char) || \
__builtin_types_compatible_p(__typeof__(expr), signed char) || \
__builtin_types_compatible_p(__typeof__(expr), unsigned char))
/* evaluates to true if expr is of type curl_off_t */
#define _curl_is_off_t(expr) \
(__builtin_types_compatible_p(__typeof__(expr), curl_off_t))
/* evaluates to true if expr is abuffer suitable for CURLOPT_ERRORBUFFER */
/* XXX: also check size of an char[] array? */
#define _curl_is_error_buffer(expr) \
(_curl_is_NULL(expr) || \
__builtin_types_compatible_p(__typeof__(expr), char *) || \
__builtin_types_compatible_p(__typeof__(expr), char[]))
/* evaluates to true if expr is of type (const) void* or (const) FILE* */
#if 0
#define _curl_is_cb_data(expr) \
(_curl_is_ptr((expr), void) || \
_curl_is_ptr((expr), FILE))
#else /* be less strict */
#define _curl_is_cb_data(expr) \
_curl_is_any_ptr(expr)
#endif
/* evaluates to true if expr is of type FILE* */
#define _curl_is_FILE(expr) \
(_curl_is_NULL(expr) || \
(__builtin_types_compatible_p(__typeof__(expr), FILE *)))
/* evaluates to true if expr can be passed as POST data (void* or char*) */
#define _curl_is_postfields(expr) \
(_curl_is_ptr((expr), void) || \
_curl_is_arr((expr), char) || \
_curl_is_arr((expr), unsigned char))
/* helper: __builtin_types_compatible_p distinguishes between functions and
* function pointers, hide it */
#define _curl_callback_compatible(func, type) \
(__builtin_types_compatible_p(__typeof__(func), type) || \
__builtin_types_compatible_p(__typeof__(func) *, type))
/* evaluates to true if expr is of type curl_resolver_start_callback */
#define _curl_is_resolver_start_callback(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_resolver_start_callback))
/* evaluates to true if expr is of type curl_read_callback or "similar" */
#define _curl_is_read_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), __typeof__(fread) *) || \
_curl_callback_compatible((expr), curl_read_callback) || \
_curl_callback_compatible((expr), _curl_read_callback1) || \
_curl_callback_compatible((expr), _curl_read_callback2) || \
_curl_callback_compatible((expr), _curl_read_callback3) || \
_curl_callback_compatible((expr), _curl_read_callback4) || \
_curl_callback_compatible((expr), _curl_read_callback5) || \
_curl_callback_compatible((expr), _curl_read_callback6))
typedef size_t (*_curl_read_callback1)(char *, size_t, size_t, void *);
typedef size_t (*_curl_read_callback2)(char *, size_t, size_t, const void *);
typedef size_t (*_curl_read_callback3)(char *, size_t, size_t, FILE *);
typedef size_t (*_curl_read_callback4)(void *, size_t, size_t, void *);
typedef size_t (*_curl_read_callback5)(void *, size_t, size_t, const void *);
typedef size_t (*_curl_read_callback6)(void *, size_t, size_t, FILE *);
/* evaluates to true if expr is of type curl_write_callback or "similar" */
#define _curl_is_write_cb(expr) \
(_curl_is_read_cb(expr) || \
_curl_callback_compatible((expr), __typeof__(fwrite) *) || \
_curl_callback_compatible((expr), curl_write_callback) || \
_curl_callback_compatible((expr), _curl_write_callback1) || \
_curl_callback_compatible((expr), _curl_write_callback2) || \
_curl_callback_compatible((expr), _curl_write_callback3) || \
_curl_callback_compatible((expr), _curl_write_callback4) || \
_curl_callback_compatible((expr), _curl_write_callback5) || \
_curl_callback_compatible((expr), _curl_write_callback6))
typedef size_t (*_curl_write_callback1)(const char *, size_t, size_t, void *);
typedef size_t (*_curl_write_callback2)(const char *, size_t, size_t,
const void *);
typedef size_t (*_curl_write_callback3)(const char *, size_t, size_t, FILE *);
typedef size_t (*_curl_write_callback4)(const void *, size_t, size_t, void *);
typedef size_t (*_curl_write_callback5)(const void *, size_t, size_t,
const void *);
typedef size_t (*_curl_write_callback6)(const void *, size_t, size_t, FILE *);
/* evaluates to true if expr is of type curl_ioctl_callback or "similar" */
#define _curl_is_ioctl_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_ioctl_callback) || \
_curl_callback_compatible((expr), _curl_ioctl_callback1) || \
_curl_callback_compatible((expr), _curl_ioctl_callback2) || \
_curl_callback_compatible((expr), _curl_ioctl_callback3) || \
_curl_callback_compatible((expr), _curl_ioctl_callback4))
typedef curlioerr (*_curl_ioctl_callback1)(CURL *, int, void *);
typedef curlioerr (*_curl_ioctl_callback2)(CURL *, int, const void *);
typedef curlioerr (*_curl_ioctl_callback3)(CURL *, curliocmd, void *);
typedef curlioerr (*_curl_ioctl_callback4)(CURL *, curliocmd, const void *);
/* evaluates to true if expr is of type curl_sockopt_callback or "similar" */
#define _curl_is_sockopt_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_sockopt_callback) || \
_curl_callback_compatible((expr), _curl_sockopt_callback1) || \
_curl_callback_compatible((expr), _curl_sockopt_callback2))
typedef int (*_curl_sockopt_callback1)(void *, curl_socket_t, curlsocktype);
typedef int (*_curl_sockopt_callback2)(const void *, curl_socket_t,
curlsocktype);
/* evaluates to true if expr is of type curl_opensocket_callback or
"similar" */
#define _curl_is_opensocket_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_opensocket_callback) || \
_curl_callback_compatible((expr), _curl_opensocket_callback1) || \
_curl_callback_compatible((expr), _curl_opensocket_callback2) || \
_curl_callback_compatible((expr), _curl_opensocket_callback3) || \
_curl_callback_compatible((expr), _curl_opensocket_callback4))
typedef curl_socket_t (*_curl_opensocket_callback1)
(void *, curlsocktype, struct curl_sockaddr *);
typedef curl_socket_t (*_curl_opensocket_callback2)
(void *, curlsocktype, const struct curl_sockaddr *);
typedef curl_socket_t (*_curl_opensocket_callback3)
(const void *, curlsocktype, struct curl_sockaddr *);
typedef curl_socket_t (*_curl_opensocket_callback4)
(const void *, curlsocktype, const struct curl_sockaddr *);
/* evaluates to true if expr is of type curl_progress_callback or "similar" */
#define _curl_is_progress_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_progress_callback) || \
_curl_callback_compatible((expr), _curl_progress_callback1) || \
_curl_callback_compatible((expr), _curl_progress_callback2))
typedef int (*_curl_progress_callback1)(void *,
double, double, double, double);
typedef int (*_curl_progress_callback2)(const void *,
double, double, double, double);
/* evaluates to true if expr is of type curl_debug_callback or "similar" */
#define _curl_is_debug_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_debug_callback) || \
_curl_callback_compatible((expr), _curl_debug_callback1) || \
_curl_callback_compatible((expr), _curl_debug_callback2) || \
_curl_callback_compatible((expr), _curl_debug_callback3) || \
_curl_callback_compatible((expr), _curl_debug_callback4) || \
_curl_callback_compatible((expr), _curl_debug_callback5) || \
_curl_callback_compatible((expr), _curl_debug_callback6) || \
_curl_callback_compatible((expr), _curl_debug_callback7) || \
_curl_callback_compatible((expr), _curl_debug_callback8))
typedef int (*_curl_debug_callback1) (CURL *,
curl_infotype, char *, size_t, void *);
typedef int (*_curl_debug_callback2) (CURL *,
curl_infotype, char *, size_t, const void *);
typedef int (*_curl_debug_callback3) (CURL *,
curl_infotype, const char *, size_t, void *);
typedef int (*_curl_debug_callback4) (CURL *,
curl_infotype, const char *, size_t, const void *);
typedef int (*_curl_debug_callback5) (CURL *,
curl_infotype, unsigned char *, size_t, void *);
typedef int (*_curl_debug_callback6) (CURL *,
curl_infotype, unsigned char *, size_t, const void *);
typedef int (*_curl_debug_callback7) (CURL *,
curl_infotype, const unsigned char *, size_t, void *);
typedef int (*_curl_debug_callback8) (CURL *,
curl_infotype, const unsigned char *, size_t, const void *);
/* evaluates to true if expr is of type curl_ssl_ctx_callback or "similar" */
/* this is getting even messier... */
#define _curl_is_ssl_ctx_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_ssl_ctx_callback) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback1) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback2) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback3) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback4) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback5) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback6) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback7) || \
_curl_callback_compatible((expr), _curl_ssl_ctx_callback8))
typedef CURLcode (*_curl_ssl_ctx_callback1)(CURL *, void *, void *);
typedef CURLcode (*_curl_ssl_ctx_callback2)(CURL *, void *, const void *);
typedef CURLcode (*_curl_ssl_ctx_callback3)(CURL *, const void *, void *);
typedef CURLcode (*_curl_ssl_ctx_callback4)(CURL *, const void *,
const void *);
#ifdef HEADER_SSL_H
/* hack: if we included OpenSSL's ssl.h, we know about SSL_CTX
* this will of course break if we're included before OpenSSL headers...
*/
typedef CURLcode (*_curl_ssl_ctx_callback5)(CURL *, SSL_CTX, void *);
typedef CURLcode (*_curl_ssl_ctx_callback6)(CURL *, SSL_CTX, const void *);
typedef CURLcode (*_curl_ssl_ctx_callback7)(CURL *, const SSL_CTX, void *);
typedef CURLcode (*_curl_ssl_ctx_callback8)(CURL *, const SSL_CTX,
const void *);
#else
typedef _curl_ssl_ctx_callback1 _curl_ssl_ctx_callback5;
typedef _curl_ssl_ctx_callback1 _curl_ssl_ctx_callback6;
typedef _curl_ssl_ctx_callback1 _curl_ssl_ctx_callback7;
typedef _curl_ssl_ctx_callback1 _curl_ssl_ctx_callback8;
#endif
/* evaluates to true if expr is of type curl_conv_callback or "similar" */
#define _curl_is_conv_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_conv_callback) || \
_curl_callback_compatible((expr), _curl_conv_callback1) || \
_curl_callback_compatible((expr), _curl_conv_callback2) || \
_curl_callback_compatible((expr), _curl_conv_callback3) || \
_curl_callback_compatible((expr), _curl_conv_callback4))
typedef CURLcode (*_curl_conv_callback1)(char *, size_t length);
typedef CURLcode (*_curl_conv_callback2)(const char *, size_t length);
typedef CURLcode (*_curl_conv_callback3)(void *, size_t length);
typedef CURLcode (*_curl_conv_callback4)(const void *, size_t length);
/* evaluates to true if expr is of type curl_seek_callback or "similar" */
#define _curl_is_seek_cb(expr) \
(_curl_is_NULL(expr) || \
_curl_callback_compatible((expr), curl_seek_callback) || \
_curl_callback_compatible((expr), _curl_seek_callback1) || \
_curl_callback_compatible((expr), _curl_seek_callback2))
typedef CURLcode (*_curl_seek_callback1)(void *, curl_off_t, int);
typedef CURLcode (*_curl_seek_callback2)(const void *, curl_off_t, int);
#endif /* __CURL_TYPECHECK_GCC_H */
| YifuLiu/AliOS-Things | components/curl/include/curl/typecheck-gcc.h | C | apache-2.0 | 43,280 |
#ifndef __CURL_URLAPI_H
#define __CURL_URLAPI_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 2018 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl.h"
#ifdef __cplusplus
extern "C" {
#endif
/* the error codes for the URL API */
typedef enum {
CURLUE_OK,
CURLUE_BAD_HANDLE, /* 1 */
CURLUE_BAD_PARTPOINTER, /* 2 */
CURLUE_MALFORMED_INPUT, /* 3 */
CURLUE_BAD_PORT_NUMBER, /* 4 */
CURLUE_UNSUPPORTED_SCHEME, /* 5 */
CURLUE_URLDECODE, /* 6 */
CURLUE_OUT_OF_MEMORY, /* 7 */
CURLUE_USER_NOT_ALLOWED, /* 8 */
CURLUE_UNKNOWN_PART, /* 9 */
CURLUE_NO_SCHEME, /* 10 */
CURLUE_NO_USER, /* 11 */
CURLUE_NO_PASSWORD, /* 12 */
CURLUE_NO_OPTIONS, /* 13 */
CURLUE_NO_HOST, /* 14 */
CURLUE_NO_PORT, /* 15 */
CURLUE_NO_QUERY, /* 16 */
CURLUE_NO_FRAGMENT /* 17 */
} CURLUcode;
typedef enum {
CURLUPART_URL,
CURLUPART_SCHEME,
CURLUPART_USER,
CURLUPART_PASSWORD,
CURLUPART_OPTIONS,
CURLUPART_HOST,
CURLUPART_PORT,
CURLUPART_PATH,
CURLUPART_QUERY,
CURLUPART_FRAGMENT,
CURLUPART_ZONEID /* added in 7.65.0 */
} CURLUPart;
#define CURLU_DEFAULT_PORT (1<<0) /* return default port number */
#define CURLU_NO_DEFAULT_PORT (1<<1) /* act as if no port number was set,
if the port number matches the
default for the scheme */
#define CURLU_DEFAULT_SCHEME (1<<2) /* return default scheme if
missing */
#define CURLU_NON_SUPPORT_SCHEME (1<<3) /* allow non-supported scheme */
#define CURLU_PATH_AS_IS (1<<4) /* leave dot sequences */
#define CURLU_DISALLOW_USER (1<<5) /* no user+password allowed */
#define CURLU_URLDECODE (1<<6) /* URL decode on get */
#define CURLU_URLENCODE (1<<7) /* URL encode on set */
#define CURLU_APPENDQUERY (1<<8) /* append a form style part */
#define CURLU_GUESS_SCHEME (1<<9) /* legacy curl-style guessing */
typedef struct Curl_URL CURLU;
/*
* curl_url() creates a new CURLU handle and returns a pointer to it.
* Must be freed with curl_url_cleanup().
*/
CURL_EXTERN CURLU *curl_url(void);
/*
* curl_url_cleanup() frees the CURLU handle and related resources used for
* the URL parsing. It will not free strings previously returned with the URL
* API.
*/
CURL_EXTERN void curl_url_cleanup(CURLU *handle);
/*
* curl_url_dup() duplicates a CURLU handle and returns a new copy. The new
* handle must also be freed with curl_url_cleanup().
*/
CURL_EXTERN CURLU *curl_url_dup(CURLU *in);
/*
* curl_url_get() extracts a specific part of the URL from a CURLU
* handle. Returns error code. The returned pointer MUST be freed with
* curl_free() afterwards.
*/
CURL_EXTERN CURLUcode curl_url_get(CURLU *handle, CURLUPart what,
char **part, unsigned int flags);
/*
* curl_url_set() sets a specific part of the URL in a CURLU handle. Returns
* error code. The passed in string will be copied. Passing a NULL instead of
* a part string, clears that part.
*/
CURL_EXTERN CURLUcode curl_url_set(CURLU *handle, CURLUPart what,
const char *part, unsigned int flags);
#ifdef __cplusplus
} /* end of extern "C" */
#endif
#endif
| YifuLiu/AliOS-Things | components/curl/include/curl/urlapi.h | C | apache-2.0 | 4,327 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/*
* The Alt-Svc: header is defined in RFC 7838:
* https://tools.ietf.org/html/rfc7838
*/
#include "curl_setup.h"
#if !defined(CURL_DISABLE_HTTP) && defined(USE_ALTSVC)
#include <curl/curl.h>
#include "urldata.h"
#include "altsvc.h"
#include "curl_get_line.h"
#include "strcase.h"
#include "parsedate.h"
#include "sendf.h"
#include "warnless.h"
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
#define MAX_ALTSVC_LINE 4095
#define MAX_ALTSVC_DATELENSTR "64"
#define MAX_ALTSVC_DATELEN 64
#define MAX_ALTSVC_HOSTLENSTR "512"
#define MAX_ALTSVC_HOSTLEN 512
#define MAX_ALTSVC_ALPNLENSTR "10"
#define MAX_ALTSVC_ALPNLEN 10
static enum alpnid alpn2alpnid(char *name)
{
if(strcasecompare(name, "h1"))
return ALPN_h1;
if(strcasecompare(name, "h2"))
return ALPN_h2;
if(strcasecompare(name, "h2c"))
return ALPN_h2c;
if(strcasecompare(name, "h3"))
return ALPN_h3;
return ALPN_none; /* unknown, probably rubbish input */
}
/* Given the ALPN ID, return the name */
const char *Curl_alpnid2str(enum alpnid id)
{
switch(id) {
case ALPN_h1:
return "h1";
case ALPN_h2:
return "h2";
case ALPN_h2c:
return "h2c";
case ALPN_h3:
return "h3";
default:
return ""; /* bad */
}
}
static void altsvc_free(struct altsvc *as)
{
free(as->srchost);
free(as->dsthost);
free(as);
}
static struct altsvc *altsvc_createid(const char *srchost,
const char *dsthost,
enum alpnid srcalpnid,
enum alpnid dstalpnid,
unsigned int srcport,
unsigned int dstport)
{
struct altsvc *as = calloc(sizeof(struct altsvc), 1);
if(!as)
return NULL;
as->srchost = strdup(srchost);
if(!as->srchost)
goto error;
as->dsthost = strdup(dsthost);
if(!as->dsthost)
goto error;
as->srcalpnid = srcalpnid;
as->dstalpnid = dstalpnid;
as->srcport = curlx_ultous(srcport);
as->dstport = curlx_ultous(dstport);
return as;
error:
altsvc_free(as);
return NULL;
}
static struct altsvc *altsvc_create(char *srchost,
char *dsthost,
char *srcalpn,
char *dstalpn,
unsigned int srcport,
unsigned int dstport)
{
enum alpnid dstalpnid = alpn2alpnid(dstalpn);
enum alpnid srcalpnid = alpn2alpnid(srcalpn);
if(!srcalpnid || !dstalpnid)
return NULL;
return altsvc_createid(srchost, dsthost, srcalpnid, dstalpnid,
srcport, dstport);
}
/* only returns SERIOUS errors */
static CURLcode altsvc_add(struct altsvcinfo *asi, char *line)
{
/* Example line:
h2 example.com 443 h3 shiny.example.com 8443 "20191231 10:00:00" 1
*/
char srchost[MAX_ALTSVC_HOSTLEN + 1];
char dsthost[MAX_ALTSVC_HOSTLEN + 1];
char srcalpn[MAX_ALTSVC_ALPNLEN + 1];
char dstalpn[MAX_ALTSVC_ALPNLEN + 1];
char date[MAX_ALTSVC_DATELEN + 1];
unsigned int srcport;
unsigned int dstport;
unsigned int prio;
unsigned int persist;
int rc;
rc = sscanf(line,
"%" MAX_ALTSVC_ALPNLENSTR "s %" MAX_ALTSVC_HOSTLENSTR "s %u "
"%" MAX_ALTSVC_ALPNLENSTR "s %" MAX_ALTSVC_HOSTLENSTR "s %u "
"\"%" MAX_ALTSVC_DATELENSTR "[^\"]\" %u %u",
srcalpn, srchost, &srcport,
dstalpn, dsthost, &dstport,
date, &persist, &prio);
if(9 == rc) {
struct altsvc *as;
time_t expires = curl_getdate(date, NULL);
as = altsvc_create(srchost, dsthost, srcalpn, dstalpn, srcport, dstport);
if(as) {
as->expires = expires;
as->prio = prio;
as->persist = persist ? 1 : 0;
Curl_llist_insert_next(&asi->list, asi->list.tail, as, &as->node);
asi->num++; /* one more entry */
}
}
return CURLE_OK;
}
/*
* Load alt-svc entries from the given file. The text based line-oriented file
* format is documented here:
* https://github.com/curl/curl/wiki/QUIC-implementation
*
* This function only returns error on major problems that prevents alt-svc
* handling to work completely. It will ignore individual syntactical errors
* etc.
*/
static CURLcode altsvc_load(struct altsvcinfo *asi, const char *file)
{
CURLcode result = CURLE_OK;
char *line = NULL;
FILE *fp = fopen(file, FOPEN_READTEXT);
if(fp) {
line = malloc(MAX_ALTSVC_LINE);
if(!line)
goto fail;
while(Curl_get_line(line, MAX_ALTSVC_LINE, fp)) {
char *lineptr = line;
while(*lineptr && ISBLANK(*lineptr))
lineptr++;
if(*lineptr == '#')
/* skip commented lines */
continue;
altsvc_add(asi, lineptr);
}
free(line); /* free the line buffer */
fclose(fp);
}
return result;
fail:
free(line);
fclose(fp);
return CURLE_OUT_OF_MEMORY;
}
/*
* Write this single altsvc entry to a single output line
*/
static CURLcode altsvc_out(struct altsvc *as, FILE *fp)
{
struct tm stamp;
CURLcode result = Curl_gmtime(as->expires, &stamp);
if(result)
return result;
fprintf(fp,
"%s %s %u "
"%s %s %u "
"\"%d%02d%02d "
"%02d:%02d:%02d\" "
"%u %d\n",
Curl_alpnid2str(as->srcalpnid), as->srchost, as->srcport,
Curl_alpnid2str(as->dstalpnid), as->dsthost, as->dstport,
stamp.tm_year + 1900, stamp.tm_mon + 1, stamp.tm_mday,
stamp.tm_hour, stamp.tm_min, stamp.tm_sec,
as->persist, as->prio);
return CURLE_OK;
}
/* ---- library-wide functions below ---- */
/*
* Curl_altsvc_init() creates a new altsvc cache.
* It returns the new instance or NULL if something goes wrong.
*/
struct altsvcinfo *Curl_altsvc_init(void)
{
struct altsvcinfo *asi = calloc(sizeof(struct altsvcinfo), 1);
if(!asi)
return NULL;
Curl_llist_init(&asi->list, NULL);
/* set default behavior */
asi->flags = CURLALTSVC_H1
#ifdef USE_NGHTTP2
| CURLALTSVC_H2
#endif
#ifdef USE_HTTP3
| CURLALTSVC_H3
#endif
;
return asi;
}
/*
* Curl_altsvc_load() loads alt-svc from file.
*/
CURLcode Curl_altsvc_load(struct altsvcinfo *asi, const char *file)
{
CURLcode result;
DEBUGASSERT(asi);
result = altsvc_load(asi, file);
return result;
}
/*
* Curl_altsvc_ctrl() passes on the external bitmask.
*/
CURLcode Curl_altsvc_ctrl(struct altsvcinfo *asi, const long ctrl)
{
DEBUGASSERT(asi);
if(!ctrl)
/* unexpected */
return CURLE_BAD_FUNCTION_ARGUMENT;
asi->flags = ctrl;
return CURLE_OK;
}
/*
* Curl_altsvc_cleanup() frees an altsvc cache instance and all associated
* resources.
*/
void Curl_altsvc_cleanup(struct altsvcinfo *altsvc)
{
struct curl_llist_element *e;
struct curl_llist_element *n;
if(altsvc) {
for(e = altsvc->list.head; e; e = n) {
struct altsvc *as = e->ptr;
n = e->next;
altsvc_free(as);
}
free(altsvc);
}
}
/*
* Curl_altsvc_save() writes the altsvc cache to a file.
*/
CURLcode Curl_altsvc_save(struct altsvcinfo *altsvc, const char *file)
{
struct curl_llist_element *e;
struct curl_llist_element *n;
CURLcode result = CURLE_OK;
FILE *out;
if(!altsvc)
/* no cache activated */
return CURLE_OK;
if((altsvc->flags & CURLALTSVC_READONLYFILE) || !file[0])
/* marked as read-only or zero length file name */
return CURLE_OK;
out = fopen(file, FOPEN_WRITETEXT);
if(!out)
return CURLE_WRITE_ERROR;
fputs("# Your alt-svc cache. https://curl.haxx.se/docs/alt-svc.html\n"
"# This file was generated by libcurl! Edit at your own risk.\n",
out);
for(e = altsvc->list.head; e; e = n) {
struct altsvc *as = e->ptr;
n = e->next;
result = altsvc_out(as, out);
if(result)
break;
}
fclose(out);
return result;
}
static CURLcode getalnum(const char **ptr, char *alpnbuf, size_t buflen)
{
size_t len;
const char *protop;
const char *p = *ptr;
while(*p && ISBLANK(*p))
p++;
protop = p;
while(*p && ISALNUM(*p))
p++;
len = p - protop;
if(!len || (len >= buflen))
return CURLE_BAD_FUNCTION_ARGUMENT;
memcpy(alpnbuf, protop, len);
alpnbuf[len] = 0;
*ptr = p;
return CURLE_OK;
}
/* altsvc_flush() removes all alternatives for this source origin from the
list */
static void altsvc_flush(struct altsvcinfo *asi, enum alpnid srcalpnid,
const char *srchost, unsigned short srcport)
{
struct curl_llist_element *e;
struct curl_llist_element *n;
for(e = asi->list.head; e; e = n) {
struct altsvc *as = e->ptr;
n = e->next;
if((srcalpnid == as->srcalpnid) &&
(srcport == as->srcport) &&
strcasecompare(srchost, as->srchost)) {
Curl_llist_remove(&asi->list, e, NULL);
altsvc_free(as);
asi->num--;
}
}
}
#ifdef DEBUGBUILD
/* to play well with debug builds, we can *set* a fixed time this will
return */
static time_t debugtime(void *unused)
{
char *timestr = getenv("CURL_TIME");
(void)unused;
if(timestr) {
unsigned long val = strtol(timestr, NULL, 10);
return (time_t)val;
}
return time(NULL);
}
#define time(x) debugtime(x)
#endif
/*
* Curl_altsvc_parse() takes an incoming alt-svc response header and stores
* the data correctly in the cache.
*
* 'value' points to the header *value*. That's contents to the right of the
* header name.
*/
CURLcode Curl_altsvc_parse(struct Curl_easy *data,
struct altsvcinfo *asi, const char *value,
enum alpnid srcalpnid, const char *srchost,
unsigned short srcport)
{
const char *p = value;
size_t len;
enum alpnid dstalpnid = srcalpnid; /* the same by default */
char namebuf[MAX_ALTSVC_HOSTLEN] = "";
char alpnbuf[MAX_ALTSVC_ALPNLEN] = "";
struct altsvc *as;
unsigned short dstport = srcport; /* the same by default */
const char *semip;
time_t maxage = 24 * 3600; /* default is 24 hours */
bool persist = FALSE;
CURLcode result = getalnum(&p, alpnbuf, sizeof(alpnbuf));
if(result)
return result;
DEBUGASSERT(asi);
/* Flush all cached alternatives for this source origin, if any */
altsvc_flush(asi, srcalpnid, srchost, srcport);
/* "clear" is a magic keyword */
if(strcasecompare(alpnbuf, "clear")) {
return CURLE_OK;
}
/* The 'ma' and 'persist' flags are annoyingly meant for all alternatives
but are set after the list on the line. Scan for the semicolons and get
those fields first! */
semip = p;
do {
semip = strchr(semip, ';');
if(semip) {
char option[32];
unsigned long num;
char *end_ptr;
semip++; /* pass the semicolon */
result = getalnum(&semip, option, sizeof(option));
if(result)
break;
while(*semip && ISBLANK(*semip))
semip++;
if(*semip != '=')
continue;
semip++;
num = strtoul(semip, &end_ptr, 10);
if(num < ULONG_MAX) {
if(strcasecompare("ma", option))
maxage = num;
else if(strcasecompare("persist", option) && (num == 1))
persist = TRUE;
}
semip = end_ptr;
}
} while(semip);
do {
if(*p == '=') {
/* [protocol]="[host][:port]" */
dstalpnid = alpn2alpnid(alpnbuf);
if(!dstalpnid) {
infof(data, "Unknown alt-svc protocol \"%s\", ignoring...\n", alpnbuf);
return CURLE_OK;
}
p++;
if(*p == '\"') {
const char *dsthost;
p++;
if(*p != ':') {
/* host name starts here */
const char *hostp = p;
while(*p && (ISALNUM(*p) || (*p == '.') || (*p == '-')))
p++;
len = p - hostp;
if(!len || (len >= MAX_ALTSVC_HOSTLEN))
return CURLE_BAD_FUNCTION_ARGUMENT;
memcpy(namebuf, hostp, len);
namebuf[len] = 0;
dsthost = namebuf;
}
else {
/* no destination name, use source host */
dsthost = srchost;
}
if(*p == ':') {
/* a port number */
char *end_ptr;
unsigned long port = strtoul(++p, &end_ptr, 10);
if(port > USHRT_MAX || end_ptr == p || *end_ptr != '\"') {
infof(data, "Unknown alt-svc port number, ignoring...\n");
return CURLE_OK;
}
p = end_ptr;
dstport = curlx_ultous(port);
}
if(*p++ != '\"')
return CURLE_BAD_FUNCTION_ARGUMENT;
as = altsvc_createid(srchost, dsthost,
srcalpnid, dstalpnid,
srcport, dstport);
if(as) {
/* The expires time also needs to take the Age: value (if any) into
account. [See RFC 7838 section 3.1] */
as->expires = maxage + time(NULL);
as->persist = persist;
Curl_llist_insert_next(&asi->list, asi->list.tail, as, &as->node);
asi->num++; /* one more entry */
infof(data, "Added alt-svc: %s:%d over %s\n", dsthost, dstport,
Curl_alpnid2str(dstalpnid));
}
}
/* after the double quote there can be a comma if there's another
string or a semicolon if no more */
if(*p == ',') {
/* comma means another alternative is presented */
p++;
result = getalnum(&p, alpnbuf, sizeof(alpnbuf));
if(result)
/* failed to parse, but since we already did at least one host we
return OK */
return CURLE_OK;
}
}
} while(*p && (*p != ';') && (*p != '\n') && (*p != '\r'));
return CURLE_OK;
}
/*
* Return TRUE on a match
*/
bool Curl_altsvc_lookup(struct altsvcinfo *asi,
enum alpnid srcalpnid, const char *srchost,
int srcport,
enum alpnid *dstalpnid, const char **dsthost,
int *dstport)
{
struct curl_llist_element *e;
struct curl_llist_element *n;
time_t now = time(NULL);
DEBUGASSERT(asi);
DEBUGASSERT(srchost);
DEBUGASSERT(dsthost);
for(e = asi->list.head; e; e = n) {
struct altsvc *as = e->ptr;
n = e->next;
if(as->expires < now) {
/* an expired entry, remove */
altsvc_free(as);
continue;
}
if((as->srcalpnid == srcalpnid) &&
strcasecompare(as->srchost, srchost) &&
as->srcport == srcport) {
/* match */
*dstalpnid = as->dstalpnid;
*dsthost = as->dsthost;
*dstport = as->dstport;
return TRUE;
}
}
return FALSE;
}
#endif /* CURL_DISABLE_HTTP || USE_ALTSVC */
| YifuLiu/AliOS-Things | components/curl/lib/altsvc.c | C | apache-2.0 | 15,740 |
#ifndef HEADER_CURL_ALTSVC_H
#define HEADER_CURL_ALTSVC_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#if !defined(CURL_DISABLE_HTTP) && defined(USE_ALTSVC)
#include <curl/curl.h>
#include "llist.h"
enum alpnid {
ALPN_none,
ALPN_h1,
ALPN_h2,
ALPN_h2c,
ALPN_h3
};
struct altsvc {
char *srchost;
char *dsthost;
unsigned short srcport;
unsigned short dstport;
enum alpnid srcalpnid;
enum alpnid dstalpnid;
time_t expires;
bool persist;
int prio;
struct curl_llist_element node;
};
struct altsvcinfo {
char *filename;
struct curl_llist list; /* list of entries */
size_t num; /* number of alt-svc entries */
long flags; /* the publicly set bitmask */
};
const char *Curl_alpnid2str(enum alpnid id);
struct altsvcinfo *Curl_altsvc_init(void);
CURLcode Curl_altsvc_load(struct altsvcinfo *asi, const char *file);
CURLcode Curl_altsvc_save(struct altsvcinfo *asi, const char *file);
CURLcode Curl_altsvc_ctrl(struct altsvcinfo *asi, const long ctrl);
void Curl_altsvc_cleanup(struct altsvcinfo *altsvc);
CURLcode Curl_altsvc_parse(struct Curl_easy *data,
struct altsvcinfo *altsvc, const char *value,
enum alpnid srcalpn, const char *srchost,
unsigned short srcport);
bool Curl_altsvc_lookup(struct altsvcinfo *asi,
enum alpnid srcalpnid, const char *srchost,
int srcport,
enum alpnid *dstalpnid, const char **dsthost,
int *dstport);
#else
/* disabled */
#define Curl_altsvc_save(a,b)
#endif /* CURL_DISABLE_HTTP || USE_ALTSVC */
#endif /* HEADER_CURL_ALTSVC_H */
| YifuLiu/AliOS-Things | components/curl/lib/altsvc.h | C | apache-2.0 | 2,676 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#ifdef __AMIGA__
# include "amigaos.h"
# if defined(HAVE_PROTO_BSDSOCKET_H) && !defined(USE_AMISSL)
# include <amitcp/socketbasetags.h>
# endif
# ifdef __libnix__
# include <stabs.h>
# endif
#endif
/* The last #include files should be: */
#include "curl_memory.h"
#include "memdebug.h"
#ifdef __AMIGA__
#if defined(HAVE_PROTO_BSDSOCKET_H) && !defined(USE_AMISSL)
struct Library *SocketBase = NULL;
extern int errno, h_errno;
#ifdef __libnix__
void __request(const char *msg);
#else
# define __request(msg) Printf(msg "\n\a")
#endif
void Curl_amiga_cleanup()
{
if(SocketBase) {
CloseLibrary(SocketBase);
SocketBase = NULL;
}
}
bool Curl_amiga_init()
{
if(!SocketBase)
SocketBase = OpenLibrary("bsdsocket.library", 4);
if(!SocketBase) {
__request("No TCP/IP Stack running!");
return FALSE;
}
if(SocketBaseTags(SBTM_SETVAL(SBTC_ERRNOPTR(sizeof(errno))), (ULONG) &errno,
SBTM_SETVAL(SBTC_LOGTAGPTR), (ULONG) "curl",
TAG_DONE)) {
__request("SocketBaseTags ERROR");
return FALSE;
}
#ifndef __libnix__
atexit(Curl_amiga_cleanup);
#endif
return TRUE;
}
#ifdef __libnix__
ADD2EXIT(Curl_amiga_cleanup, -50);
#endif
#endif /* HAVE_PROTO_BSDSOCKET_H */
#ifdef USE_AMISSL
void Curl_amiga_X509_free(X509 *a)
{
X509_free(a);
}
#endif /* USE_AMISSL */
#endif /* __AMIGA__ */
| YifuLiu/AliOS-Things | components/curl/lib/amigaos.c | C | apache-2.0 | 2,429 |
#ifndef HEADER_CURL_AMIGAOS_H
#define HEADER_CURL_AMIGAOS_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#if defined(__AMIGA__) && defined(HAVE_BSDSOCKET_H) && !defined(USE_AMISSL)
bool Curl_amiga_init();
void Curl_amiga_cleanup();
#else
#define Curl_amiga_init() 1
#define Curl_amiga_cleanup() Curl_nop_stmt
#endif
#ifdef USE_AMISSL
#include <openssl/x509v3.h>
void Curl_amiga_X509_free(X509 *a);
#endif /* USE_AMISSL */
#endif /* HEADER_CURL_AMIGAOS_H */
| YifuLiu/AliOS-Things | components/curl/lib/amigaos.h | C | apache-2.0 | 1,470 |
#ifndef HEADER_CURL_ARPA_TELNET_H
#define HEADER_CURL_ARPA_TELNET_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2018, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#ifndef CURL_DISABLE_TELNET
/*
* Telnet option defines. Add more here if in need.
*/
#define CURL_TELOPT_BINARY 0 /* binary 8bit data */
#define CURL_TELOPT_ECHO 1 /* just echo! */
#define CURL_TELOPT_SGA 3 /* Suppress Go Ahead */
#define CURL_TELOPT_EXOPL 255 /* EXtended OPtions List */
#define CURL_TELOPT_TTYPE 24 /* Terminal TYPE */
#define CURL_TELOPT_NAWS 31 /* Negotiate About Window Size */
#define CURL_TELOPT_XDISPLOC 35 /* X DISPlay LOCation */
#define CURL_TELOPT_NEW_ENVIRON 39 /* NEW ENVIRONment variables */
#define CURL_NEW_ENV_VAR 0
#define CURL_NEW_ENV_VALUE 1
#ifndef CURL_DISABLE_VERBOSE_STRINGS
/*
* The telnet options represented as strings
*/
static const char * const telnetoptions[]=
{
"BINARY", "ECHO", "RCP", "SUPPRESS GO AHEAD",
"NAME", "STATUS", "TIMING MARK", "RCTE",
"NAOL", "NAOP", "NAOCRD", "NAOHTS",
"NAOHTD", "NAOFFD", "NAOVTS", "NAOVTD",
"NAOLFD", "EXTEND ASCII", "LOGOUT", "BYTE MACRO",
"DE TERMINAL", "SUPDUP", "SUPDUP OUTPUT", "SEND LOCATION",
"TERM TYPE", "END OF RECORD", "TACACS UID", "OUTPUT MARKING",
"TTYLOC", "3270 REGIME", "X3 PAD", "NAWS",
"TERM SPEED", "LFLOW", "LINEMODE", "XDISPLOC",
"OLD-ENVIRON", "AUTHENTICATION", "ENCRYPT", "NEW-ENVIRON"
};
#endif
#define CURL_TELOPT_MAXIMUM CURL_TELOPT_NEW_ENVIRON
#define CURL_TELOPT_OK(x) ((x) <= CURL_TELOPT_MAXIMUM)
#define CURL_TELOPT(x) telnetoptions[x]
#define CURL_NTELOPTS 40
/*
* First some defines
*/
#define CURL_xEOF 236 /* End Of File */
#define CURL_SE 240 /* Sub negotiation End */
#define CURL_NOP 241 /* No OPeration */
#define CURL_DM 242 /* Data Mark */
#define CURL_GA 249 /* Go Ahead, reverse the line */
#define CURL_SB 250 /* SuBnegotiation */
#define CURL_WILL 251 /* Our side WILL use this option */
#define CURL_WONT 252 /* Our side WON'T use this option */
#define CURL_DO 253 /* DO use this option! */
#define CURL_DONT 254 /* DON'T use this option! */
#define CURL_IAC 255 /* Interpret As Command */
#ifndef CURL_DISABLE_VERBOSE_STRINGS
/*
* Then those numbers represented as strings:
*/
static const char * const telnetcmds[]=
{
"EOF", "SUSP", "ABORT", "EOR", "SE",
"NOP", "DMARK", "BRK", "IP", "AO",
"AYT", "EC", "EL", "GA", "SB",
"WILL", "WONT", "DO", "DONT", "IAC"
};
#endif
#define CURL_TELCMD_MINIMUM CURL_xEOF /* the first one */
#define CURL_TELCMD_MAXIMUM CURL_IAC /* surprise, 255 is the last one! ;-) */
#define CURL_TELQUAL_IS 0
#define CURL_TELQUAL_SEND 1
#define CURL_TELQUAL_INFO 2
#define CURL_TELQUAL_NAME 3
#define CURL_TELCMD_OK(x) ( ((unsigned int)(x) >= CURL_TELCMD_MINIMUM) && \
((unsigned int)(x) <= CURL_TELCMD_MAXIMUM) )
#define CURL_TELCMD(x) telnetcmds[(x)-CURL_TELCMD_MINIMUM]
#endif /* CURL_DISABLE_TELNET */
#endif /* HEADER_CURL_ARPA_TELNET_H */
| YifuLiu/AliOS-Things | components/curl/lib/arpa_telnet.h | C | apache-2.0 | 4,081 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
/***********************************************************************
* Only for ares-enabled builds
* And only for functions that fulfill the asynch resolver backend API
* as defined in asyn.h, nothing else belongs in this file!
**********************************************************************/
#ifdef CURLRES_ARES
#include <limits.h>
#ifdef HAVE_NETINET_IN_H
#include <netinet/in.h>
#endif
#ifdef HAVE_NETDB_H
#include <netdb.h>
#endif
#ifdef HAVE_ARPA_INET_H
#include <arpa/inet.h>
#endif
#ifdef __VMS
#include <in.h>
#include <inet.h>
#endif
#ifdef HAVE_PROCESS_H
#include <process.h>
#endif
#if (defined(NETWARE) && defined(__NOVELL_LIBC__))
#undef in_addr_t
#define in_addr_t unsigned long
#endif
#include "urldata.h"
#include "sendf.h"
#include "hostip.h"
#include "hash.h"
#include "share.h"
#include "strerror.h"
#include "url.h"
#include "multiif.h"
#include "inet_pton.h"
#include "connect.h"
#include "select.h"
#include "progress.h"
# if defined(CURL_STATICLIB) && !defined(CARES_STATICLIB) && \
(defined(WIN32) || defined(__SYMBIAN32__))
# define CARES_STATICLIB
# endif
# include <ares.h>
# include <ares_version.h> /* really old c-ares didn't include this by
itself */
#if ARES_VERSION >= 0x010500
/* c-ares 1.5.0 or later, the callback proto is modified */
#define HAVE_CARES_CALLBACK_TIMEOUTS 1
#endif
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
struct ResolverResults {
int num_pending; /* number of ares_gethostbyname() requests */
Curl_addrinfo *temp_ai; /* intermediary result while fetching c-ares parts */
int last_status;
struct curltime happy_eyeballs_dns_time; /* when this timer started, or 0 */
};
/* How long we are willing to wait for additional parallel responses after
obtaining a "definitive" one.
This is intended to equal the c-ares default timeout. cURL always uses that
default value. Unfortunately, c-ares doesn't expose its default timeout in
its API, but it is officially documented as 5 seconds.
See query_completed_cb() for an explanation of how this is used.
*/
#define HAPPY_EYEBALLS_DNS_TIMEOUT 5000
/*
* Curl_resolver_global_init() - the generic low-level asynchronous name
* resolve API. Called from curl_global_init() to initialize global resolver
* environment. Initializes ares library.
*/
int Curl_resolver_global_init(void)
{
#ifdef CARES_HAVE_ARES_LIBRARY_INIT
if(ares_library_init(ARES_LIB_INIT_ALL)) {
return CURLE_FAILED_INIT;
}
#endif
return CURLE_OK;
}
/*
* Curl_resolver_global_cleanup()
*
* Called from curl_global_cleanup() to destroy global resolver environment.
* Deinitializes ares library.
*/
void Curl_resolver_global_cleanup(void)
{
#ifdef CARES_HAVE_ARES_LIBRARY_CLEANUP
ares_library_cleanup();
#endif
}
static void Curl_ares_sock_state_cb(void *data, ares_socket_t socket_fd,
int readable, int writable)
{
struct Curl_easy *easy = data;
if(!readable && !writable) {
DEBUGASSERT(easy);
Curl_multi_closed(easy, socket_fd);
}
}
/*
* Curl_resolver_init()
*
* Called from curl_easy_init() -> Curl_open() to initialize resolver
* URL-state specific environment ('resolver' member of the UrlState
* structure). Fills the passed pointer by the initialized ares_channel.
*/
CURLcode Curl_resolver_init(struct Curl_easy *easy, void **resolver)
{
int status;
struct ares_options options;
int optmask = ARES_OPT_SOCK_STATE_CB;
options.sock_state_cb = Curl_ares_sock_state_cb;
options.sock_state_cb_data = easy;
status = ares_init_options((ares_channel*)resolver, &options, optmask);
if(status != ARES_SUCCESS) {
if(status == ARES_ENOMEM)
return CURLE_OUT_OF_MEMORY;
else
return CURLE_FAILED_INIT;
}
return CURLE_OK;
/* make sure that all other returns from this function should destroy the
ares channel before returning error! */
}
/*
* Curl_resolver_cleanup()
*
* Called from curl_easy_cleanup() -> Curl_close() to cleanup resolver
* URL-state specific environment ('resolver' member of the UrlState
* structure). Destroys the ares channel.
*/
void Curl_resolver_cleanup(void *resolver)
{
ares_destroy((ares_channel)resolver);
}
/*
* Curl_resolver_duphandle()
*
* Called from curl_easy_duphandle() to duplicate resolver URL-state specific
* environment ('resolver' member of the UrlState structure). Duplicates the
* 'from' ares channel and passes the resulting channel to the 'to' pointer.
*/
CURLcode Curl_resolver_duphandle(struct Curl_easy *easy, void **to, void *from)
{
(void)from;
/*
* it would be better to call ares_dup instead, but right now
* it is not possible to set 'sock_state_cb_data' outside of
* ares_init_options
*/
return Curl_resolver_init(easy, to);
}
static void destroy_async_data(struct Curl_async *async);
/*
* Cancel all possibly still on-going resolves for this connection.
*/
void Curl_resolver_cancel(struct connectdata *conn)
{
if(conn->data && conn->data->state.resolver)
ares_cancel((ares_channel)conn->data->state.resolver);
destroy_async_data(&conn->async);
}
/*
* We're equivalent to Curl_resolver_cancel() for the c-ares resolver. We
* never block.
*/
void Curl_resolver_kill(struct connectdata *conn)
{
/* We don't need to check the resolver state because we can be called safely
at any time and we always do the same thing. */
Curl_resolver_cancel(conn);
}
/*
* destroy_async_data() cleans up async resolver data.
*/
static void destroy_async_data(struct Curl_async *async)
{
free(async->hostname);
if(async->os_specific) {
struct ResolverResults *res = (struct ResolverResults *)async->os_specific;
if(res) {
if(res->temp_ai) {
Curl_freeaddrinfo(res->temp_ai);
res->temp_ai = NULL;
}
free(res);
}
async->os_specific = NULL;
}
async->hostname = NULL;
}
/*
* Curl_resolver_getsock() is called when someone from the outside world
* (using curl_multi_fdset()) wants to get our fd_set setup and we're talking
* with ares. The caller must make sure that this function is only called when
* we have a working ares channel.
*
* Returns: sockets-in-use-bitmap
*/
int Curl_resolver_getsock(struct connectdata *conn,
curl_socket_t *socks,
int numsocks)
{
struct timeval maxtime;
struct timeval timebuf;
struct timeval *timeout;
long milli;
int max = ares_getsock((ares_channel)conn->data->state.resolver,
(ares_socket_t *)socks, numsocks);
maxtime.tv_sec = CURL_TIMEOUT_RESOLVE;
maxtime.tv_usec = 0;
timeout = ares_timeout((ares_channel)conn->data->state.resolver, &maxtime,
&timebuf);
milli = (timeout->tv_sec * 1000) + (timeout->tv_usec/1000);
if(milli == 0)
milli += 10;
Curl_expire(conn->data, milli, EXPIRE_ASYNC_NAME);
return max;
}
/*
* waitperform()
*
* 1) Ask ares what sockets it currently plays with, then
* 2) wait for the timeout period to check for action on ares' sockets.
* 3) tell ares to act on all the sockets marked as "with action"
*
* return number of sockets it worked on
*/
static int waitperform(struct connectdata *conn, int timeout_ms)
{
struct Curl_easy *data = conn->data;
int nfds;
int bitmask;
ares_socket_t socks[ARES_GETSOCK_MAXNUM];
struct pollfd pfd[ARES_GETSOCK_MAXNUM];
int i;
int num = 0;
bitmask = ares_getsock((ares_channel)data->state.resolver, socks,
ARES_GETSOCK_MAXNUM);
for(i = 0; i < ARES_GETSOCK_MAXNUM; i++) {
pfd[i].events = 0;
pfd[i].revents = 0;
if(ARES_GETSOCK_READABLE(bitmask, i)) {
pfd[i].fd = socks[i];
pfd[i].events |= POLLRDNORM|POLLIN;
}
if(ARES_GETSOCK_WRITABLE(bitmask, i)) {
pfd[i].fd = socks[i];
pfd[i].events |= POLLWRNORM|POLLOUT;
}
if(pfd[i].events != 0)
num++;
else
break;
}
if(num)
nfds = Curl_poll(pfd, num, timeout_ms);
else
nfds = 0;
if(!nfds)
/* Call ares_process() unconditonally here, even if we simply timed out
above, as otherwise the ares name resolve won't timeout! */
ares_process_fd((ares_channel)data->state.resolver, ARES_SOCKET_BAD,
ARES_SOCKET_BAD);
else {
/* move through the descriptors and ask for processing on them */
for(i = 0; i < num; i++)
ares_process_fd((ares_channel)data->state.resolver,
(pfd[i].revents & (POLLRDNORM|POLLIN))?
pfd[i].fd:ARES_SOCKET_BAD,
(pfd[i].revents & (POLLWRNORM|POLLOUT))?
pfd[i].fd:ARES_SOCKET_BAD);
}
return nfds;
}
/*
* Curl_resolver_is_resolved() is called repeatedly to check if a previous
* name resolve request has completed. It should also make sure to time-out if
* the operation seems to take too long.
*
* Returns normal CURLcode errors.
*/
CURLcode Curl_resolver_is_resolved(struct connectdata *conn,
struct Curl_dns_entry **dns)
{
struct Curl_easy *data = conn->data;
struct ResolverResults *res = (struct ResolverResults *)
conn->async.os_specific;
CURLcode result = CURLE_OK;
if(dns)
*dns = NULL;
waitperform(conn, 0);
/* Now that we've checked for any last minute results above, see if there are
any responses still pending when the EXPIRE_HAPPY_EYEBALLS_DNS timer
expires. */
if(res
&& res->num_pending
/* This is only set to non-zero if the timer was started. */
&& (res->happy_eyeballs_dns_time.tv_sec
|| res->happy_eyeballs_dns_time.tv_usec)
&& (Curl_timediff(Curl_now(), res->happy_eyeballs_dns_time)
>= HAPPY_EYEBALLS_DNS_TIMEOUT)) {
/* Remember that the EXPIRE_HAPPY_EYEBALLS_DNS timer is no longer
running. */
memset(
&res->happy_eyeballs_dns_time, 0, sizeof(res->happy_eyeballs_dns_time));
/* Cancel the raw c-ares request, which will fire query_completed_cb() with
ARES_ECANCELLED synchronously for all pending responses. This will
leave us with res->num_pending == 0, which is perfect for the next
block. */
ares_cancel((ares_channel)data->state.resolver);
DEBUGASSERT(res->num_pending == 0);
}
if(res && !res->num_pending) {
if(dns) {
(void)Curl_addrinfo_callback(conn, res->last_status, res->temp_ai);
/* temp_ai ownership is moved to the connection, so we need not free-up
them */
res->temp_ai = NULL;
}
if(!conn->async.dns) {
failf(data, "Could not resolve: %s (%s)",
conn->async.hostname, ares_strerror(conn->async.status));
result = conn->bits.proxy?CURLE_COULDNT_RESOLVE_PROXY:
CURLE_COULDNT_RESOLVE_HOST;
}
else if(dns)
*dns = conn->async.dns;
destroy_async_data(&conn->async);
}
return result;
}
/*
* Curl_resolver_wait_resolv()
*
* Waits for a resolve to finish. This function should be avoided since using
* this risk getting the multi interface to "hang".
*
* If 'entry' is non-NULL, make it point to the resolved dns entry
*
* Returns CURLE_COULDNT_RESOLVE_HOST if the host was not resolved,
* CURLE_OPERATION_TIMEDOUT if a time-out occurred, or other errors.
*/
CURLcode Curl_resolver_wait_resolv(struct connectdata *conn,
struct Curl_dns_entry **entry)
{
CURLcode result = CURLE_OK;
struct Curl_easy *data = conn->data;
timediff_t timeout;
struct curltime now = Curl_now();
struct Curl_dns_entry *temp_entry;
if(entry)
*entry = NULL; /* clear on entry */
timeout = Curl_timeleft(data, &now, TRUE);
if(timeout < 0) {
/* already expired! */
connclose(conn, "Timed out before name resolve started");
return CURLE_OPERATION_TIMEDOUT;
}
if(!timeout)
timeout = CURL_TIMEOUT_RESOLVE * 1000; /* default name resolve timeout */
/* Wait for the name resolve query to complete. */
while(!result) {
struct timeval *tvp, tv, store;
int itimeout;
int timeout_ms;
itimeout = (timeout > (long)INT_MAX) ? INT_MAX : (int)timeout;
store.tv_sec = itimeout/1000;
store.tv_usec = (itimeout%1000)*1000;
tvp = ares_timeout((ares_channel)data->state.resolver, &store, &tv);
/* use the timeout period ares returned to us above if less than one
second is left, otherwise just use 1000ms to make sure the progress
callback gets called frequent enough */
if(!tvp->tv_sec)
timeout_ms = (int)(tvp->tv_usec/1000);
else
timeout_ms = 1000;
waitperform(conn, timeout_ms);
result = Curl_resolver_is_resolved(conn, entry?&temp_entry:NULL);
if(result || conn->async.done)
break;
if(Curl_pgrsUpdate(conn))
result = CURLE_ABORTED_BY_CALLBACK;
else {
struct curltime now2 = Curl_now();
timediff_t timediff = Curl_timediff(now2, now); /* spent time */
if(timediff <= 0)
timeout -= 1; /* always deduct at least 1 */
else if(timediff > timeout)
timeout = -1;
else
timeout -= (long)timediff;
now = now2; /* for next loop */
}
if(timeout < 0)
result = CURLE_OPERATION_TIMEDOUT;
}
if(result)
/* failure, so we cancel the ares operation */
ares_cancel((ares_channel)data->state.resolver);
/* Operation complete, if the lookup was successful we now have the entry
in the cache. */
if(entry)
*entry = conn->async.dns;
if(result)
/* close the connection, since we can't return failure here without
cleaning up this connection properly. */
connclose(conn, "c-ares resolve failed");
return result;
}
/* Connects results to the list */
static void compound_results(struct ResolverResults *res,
Curl_addrinfo *ai)
{
Curl_addrinfo *ai_tail;
if(!ai)
return;
ai_tail = ai;
while(ai_tail->ai_next)
ai_tail = ai_tail->ai_next;
/* Add the new results to the list of old results. */
ai_tail->ai_next = res->temp_ai;
res->temp_ai = ai;
}
/*
* ares_query_completed_cb() is the callback that ares will call when
* the host query initiated by ares_gethostbyname() from Curl_getaddrinfo(),
* when using ares, is completed either successfully or with failure.
*/
static void query_completed_cb(void *arg, /* (struct connectdata *) */
int status,
#ifdef HAVE_CARES_CALLBACK_TIMEOUTS
int timeouts,
#endif
struct hostent *hostent)
{
struct connectdata *conn = (struct connectdata *)arg;
struct ResolverResults *res;
#ifdef HAVE_CARES_CALLBACK_TIMEOUTS
(void)timeouts; /* ignored */
#endif
if(ARES_EDESTRUCTION == status)
/* when this ares handle is getting destroyed, the 'arg' pointer may not
be valid so only defer it when we know the 'status' says its fine! */
return;
res = (struct ResolverResults *)conn->async.os_specific;
if(res) {
res->num_pending--;
if(CURL_ASYNC_SUCCESS == status) {
Curl_addrinfo *ai = Curl_he2ai(hostent, conn->async.port);
if(ai) {
compound_results(res, ai);
}
}
/* A successful result overwrites any previous error */
if(res->last_status != ARES_SUCCESS)
res->last_status = status;
/* If there are responses still pending, we presume they must be the
complementary IPv4 or IPv6 lookups that we started in parallel in
Curl_resolver_getaddrinfo() (for Happy Eyeballs). If we've got a
"definitive" response from one of a set of parallel queries, we need to
think about how long we're willing to wait for more responses. */
if(res->num_pending
/* Only these c-ares status values count as "definitive" for these
purposes. For example, ARES_ENODATA is what we expect when there is
no IPv6 entry for a domain name, and that's not a reason to get more
aggressive in our timeouts for the other response. Other errors are
either a result of bad input (which should affect all parallel
requests), local or network conditions, non-definitive server
responses, or us cancelling the request. */
&& (status == ARES_SUCCESS || status == ARES_ENOTFOUND)) {
/* Right now, there can only be up to two parallel queries, so don't
bother handling any other cases. */
DEBUGASSERT(res->num_pending == 1);
/* It's possible that one of these parallel queries could succeed
quickly, but the other could always fail or timeout (when we're
talking to a pool of DNS servers that can only successfully resolve
IPv4 address, for example).
It's also possible that the other request could always just take
longer because it needs more time or only the second DNS server can
fulfill it successfully. But, to align with the philosophy of Happy
Eyeballs, we don't want to wait _too_ long or users will think
requests are slow when IPv6 lookups don't actually work (but IPv4 ones
do).
So, now that we have a usable answer (some IPv4 addresses, some IPv6
addresses, or "no such domain"), we start a timeout for the remaining
pending responses. Even though it is typical that this resolved
request came back quickly, that needn't be the case. It might be that
this completing request didn't get a result from the first DNS server
or even the first round of the whole DNS server pool. So it could
already be quite some time after we issued the DNS queries in the
first place. Without modifying c-ares, we can't know exactly where in
its retry cycle we are. We could guess based on how much time has
gone by, but it doesn't really matter. Happy Eyeballs tells us that,
given usable information in hand, we simply don't want to wait "too
much longer" after we get a result.
We simply wait an additional amount of time equal to the default
c-ares query timeout. That is enough time for a typical parallel
response to arrive without being "too long". Even on a network
where one of the two types of queries is failing or timing out
constantly, this will usually mean we wait a total of the default
c-ares timeout (5 seconds) plus the round trip time for the successful
request, which seems bearable. The downside is that c-ares might race
with us to issue one more retry just before we give up, but it seems
better to "waste" that request instead of trying to guess the perfect
timeout to prevent it. After all, we don't even know where in the
c-ares retry cycle each request is.
*/
res->happy_eyeballs_dns_time = Curl_now();
Curl_expire(
conn->data, HAPPY_EYEBALLS_DNS_TIMEOUT, EXPIRE_HAPPY_EYEBALLS_DNS);
}
}
}
/*
* Curl_resolver_getaddrinfo() - when using ares
*
* Returns name information about the given hostname and port number. If
* successful, the 'hostent' is returned and the forth argument will point to
* memory we need to free after use. That memory *MUST* be freed with
* Curl_freeaddrinfo(), nothing else.
*/
Curl_addrinfo *Curl_resolver_getaddrinfo(struct connectdata *conn,
const char *hostname,
int port,
int *waitp)
{
char *bufp;
struct Curl_easy *data = conn->data;
struct in_addr in;
int family = PF_INET;
#ifdef ENABLE_IPV6 /* CURLRES_IPV6 */
struct in6_addr in6;
#endif /* CURLRES_IPV6 */
*waitp = 0; /* default to synchronous response */
/* First check if this is an IPv4 address string */
if(Curl_inet_pton(AF_INET, hostname, &in) > 0) {
/* This is a dotted IP address 123.123.123.123-style */
return Curl_ip2addr(AF_INET, &in, hostname, port);
}
#ifdef ENABLE_IPV6 /* CURLRES_IPV6 */
/* Otherwise, check if this is an IPv6 address string */
if(Curl_inet_pton (AF_INET6, hostname, &in6) > 0)
/* This must be an IPv6 address literal. */
return Curl_ip2addr(AF_INET6, &in6, hostname, port);
switch(conn->ip_version) {
default:
#if ARES_VERSION >= 0x010601
family = PF_UNSPEC; /* supported by c-ares since 1.6.1, so for older
c-ares versions this just falls through and defaults
to PF_INET */
break;
#endif
case CURL_IPRESOLVE_V4:
family = PF_INET;
break;
case CURL_IPRESOLVE_V6:
family = PF_INET6;
break;
}
#endif /* CURLRES_IPV6 */
bufp = strdup(hostname);
if(bufp) {
struct ResolverResults *res = NULL;
free(conn->async.hostname);
conn->async.hostname = bufp;
conn->async.port = port;
conn->async.done = FALSE; /* not done */
conn->async.status = 0; /* clear */
conn->async.dns = NULL; /* clear */
res = calloc(sizeof(struct ResolverResults), 1);
if(!res) {
free(conn->async.hostname);
conn->async.hostname = NULL;
return NULL;
}
conn->async.os_specific = res;
/* initial status - failed */
res->last_status = ARES_ENOTFOUND;
#ifdef ENABLE_IPV6 /* CURLRES_IPV6 */
if(family == PF_UNSPEC) {
if(Curl_ipv6works()) {
res->num_pending = 2;
/* areschannel is already setup in the Curl_open() function */
ares_gethostbyname((ares_channel)data->state.resolver, hostname,
PF_INET, query_completed_cb, conn);
ares_gethostbyname((ares_channel)data->state.resolver, hostname,
PF_INET6, query_completed_cb, conn);
}
else {
res->num_pending = 1;
/* areschannel is already setup in the Curl_open() function */
ares_gethostbyname((ares_channel)data->state.resolver, hostname,
PF_INET, query_completed_cb, conn);
}
}
else
#endif /* CURLRES_IPV6 */
{
res->num_pending = 1;
/* areschannel is already setup in the Curl_open() function */
ares_gethostbyname((ares_channel)data->state.resolver, hostname, family,
query_completed_cb, conn);
}
*waitp = 1; /* expect asynchronous response */
}
return NULL; /* no struct yet */
}
CURLcode Curl_set_dns_servers(struct Curl_easy *data,
char *servers)
{
CURLcode result = CURLE_NOT_BUILT_IN;
int ares_result;
/* If server is NULL or empty, this would purge all DNS servers
* from ares library, which will cause any and all queries to fail.
* So, just return OK if none are configured and don't actually make
* any changes to c-ares. This lets c-ares use it's defaults, which
* it gets from the OS (for instance from /etc/resolv.conf on Linux).
*/
if(!(servers && servers[0]))
return CURLE_OK;
#if (ARES_VERSION >= 0x010704)
ares_result = ares_set_servers_csv(data->state.resolver, servers);
switch(ares_result) {
case ARES_SUCCESS:
result = CURLE_OK;
break;
case ARES_ENOMEM:
result = CURLE_OUT_OF_MEMORY;
break;
case ARES_ENOTINITIALIZED:
case ARES_ENODATA:
case ARES_EBADSTR:
default:
result = CURLE_BAD_FUNCTION_ARGUMENT;
break;
}
#else /* too old c-ares version! */
(void)data;
(void)(ares_result);
#endif
return result;
}
CURLcode Curl_set_dns_interface(struct Curl_easy *data,
const char *interf)
{
#if (ARES_VERSION >= 0x010704)
if(!interf)
interf = "";
ares_set_local_dev((ares_channel)data->state.resolver, interf);
return CURLE_OK;
#else /* c-ares version too old! */
(void)data;
(void)interf;
return CURLE_NOT_BUILT_IN;
#endif
}
CURLcode Curl_set_dns_local_ip4(struct Curl_easy *data,
const char *local_ip4)
{
#if (ARES_VERSION >= 0x010704)
struct in_addr a4;
if((!local_ip4) || (local_ip4[0] == 0)) {
a4.s_addr = 0; /* disabled: do not bind to a specific address */
}
else {
if(Curl_inet_pton(AF_INET, local_ip4, &a4) != 1) {
return CURLE_BAD_FUNCTION_ARGUMENT;
}
}
ares_set_local_ip4((ares_channel)data->state.resolver, ntohl(a4.s_addr));
return CURLE_OK;
#else /* c-ares version too old! */
(void)data;
(void)local_ip4;
return CURLE_NOT_BUILT_IN;
#endif
}
CURLcode Curl_set_dns_local_ip6(struct Curl_easy *data,
const char *local_ip6)
{
#if (ARES_VERSION >= 0x010704) && defined(ENABLE_IPV6)
unsigned char a6[INET6_ADDRSTRLEN];
if((!local_ip6) || (local_ip6[0] == 0)) {
/* disabled: do not bind to a specific address */
memset(a6, 0, sizeof(a6));
}
else {
if(Curl_inet_pton(AF_INET6, local_ip6, a6) != 1) {
return CURLE_BAD_FUNCTION_ARGUMENT;
}
}
ares_set_local_ip6((ares_channel)data->state.resolver, a6);
return CURLE_OK;
#else /* c-ares version too old! */
(void)data;
(void)local_ip6;
return CURLE_NOT_BUILT_IN;
#endif
}
#endif /* CURLRES_ARES */
| YifuLiu/AliOS-Things | components/curl/lib/asyn-ares.c | C | apache-2.0 | 26,188 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
/***********************************************************************
* Only for threaded name resolves builds
**********************************************************************/
#ifdef CURLRES_THREADED
#ifdef HAVE_NETINET_IN_H
#include <netinet/in.h>
#endif
#ifdef HAVE_NETDB_H
#include <netdb.h>
#endif
#ifdef HAVE_ARPA_INET_H
#include <arpa/inet.h>
#endif
#ifdef __VMS
#include <in.h>
#include <inet.h>
#endif
#if defined(USE_THREADS_POSIX)
# ifdef HAVE_PTHREAD_H
# include <pthread.h>
# endif
#elif defined(USE_THREADS_WIN32)
# ifdef HAVE_PROCESS_H
# include <process.h>
# endif
#endif
#if (defined(NETWARE) && defined(__NOVELL_LIBC__))
#undef in_addr_t
#define in_addr_t unsigned long
#endif
#ifdef HAVE_GETADDRINFO
# define RESOLVER_ENOMEM EAI_MEMORY
#else
# define RESOLVER_ENOMEM ENOMEM
#endif
#include "urldata.h"
#include "sendf.h"
#include "hostip.h"
#include "hash.h"
#include "share.h"
#include "strerror.h"
#include "url.h"
#include "multiif.h"
#include "inet_pton.h"
#include "inet_ntop.h"
#include "curl_threads.h"
#include "connect.h"
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
struct resdata {
struct curltime start;
};
/*
* Curl_resolver_global_init()
* Called from curl_global_init() to initialize global resolver environment.
* Does nothing here.
*/
int Curl_resolver_global_init(void)
{
return CURLE_OK;
}
/*
* Curl_resolver_global_cleanup()
* Called from curl_global_cleanup() to destroy global resolver environment.
* Does nothing here.
*/
void Curl_resolver_global_cleanup(void)
{
}
/*
* Curl_resolver_init()
* Called from curl_easy_init() -> Curl_open() to initialize resolver
* URL-state specific environment ('resolver' member of the UrlState
* structure).
*/
CURLcode Curl_resolver_init(struct Curl_easy *easy, void **resolver)
{
(void)easy;
*resolver = calloc(1, sizeof(struct resdata));
if(!*resolver)
return CURLE_OUT_OF_MEMORY;
return CURLE_OK;
}
/*
* Curl_resolver_cleanup()
* Called from curl_easy_cleanup() -> Curl_close() to cleanup resolver
* URL-state specific environment ('resolver' member of the UrlState
* structure).
*/
void Curl_resolver_cleanup(void *resolver)
{
free(resolver);
}
/*
* Curl_resolver_duphandle()
* Called from curl_easy_duphandle() to duplicate resolver URL state-specific
* environment ('resolver' member of the UrlState structure).
*/
CURLcode Curl_resolver_duphandle(struct Curl_easy *easy, void **to, void *from)
{
(void)from;
return Curl_resolver_init(easy, to);
}
static void destroy_async_data(struct Curl_async *);
/*
* Cancel all possibly still on-going resolves for this connection.
*/
void Curl_resolver_cancel(struct connectdata *conn)
{
destroy_async_data(&conn->async);
}
/* This function is used to init a threaded resolve */
static bool init_resolve_thread(struct connectdata *conn,
const char *hostname, int port,
const struct addrinfo *hints);
/* Data for synchronization between resolver thread and its parent */
struct thread_sync_data {
curl_mutex_t * mtx;
int done;
char *hostname; /* hostname to resolve, Curl_async.hostname
duplicate */
int port;
int sock_error;
Curl_addrinfo *res;
#ifdef HAVE_GETADDRINFO
struct addrinfo hints;
#endif
struct thread_data *td; /* for thread-self cleanup */
};
struct thread_data {
curl_thread_t thread_hnd;
unsigned int poll_interval;
time_t interval_end;
struct thread_sync_data tsd;
};
static struct thread_sync_data *conn_thread_sync_data(struct connectdata *conn)
{
return &(((struct thread_data *)conn->async.os_specific)->tsd);
}
/* Destroy resolver thread synchronization data */
static
void destroy_thread_sync_data(struct thread_sync_data * tsd)
{
if(tsd->mtx) {
Curl_mutex_destroy(tsd->mtx);
free(tsd->mtx);
}
free(tsd->hostname);
if(tsd->res)
Curl_freeaddrinfo(tsd->res);
memset(tsd, 0, sizeof(*tsd));
}
/* Initialize resolver thread synchronization data */
static
int init_thread_sync_data(struct thread_data * td,
const char *hostname,
int port,
const struct addrinfo *hints)
{
struct thread_sync_data *tsd = &td->tsd;
memset(tsd, 0, sizeof(*tsd));
tsd->td = td;
tsd->port = port;
/* Treat the request as done until the thread actually starts so any early
* cleanup gets done properly.
*/
tsd->done = 1;
#ifdef HAVE_GETADDRINFO
DEBUGASSERT(hints);
tsd->hints = *hints;
#else
(void) hints;
#endif
tsd->mtx = malloc(sizeof(curl_mutex_t));
if(tsd->mtx == NULL)
goto err_exit;
Curl_mutex_init(tsd->mtx);
tsd->sock_error = CURL_ASYNC_SUCCESS;
/* Copying hostname string because original can be destroyed by parent
* thread during gethostbyname execution.
*/
tsd->hostname = strdup(hostname);
if(!tsd->hostname)
goto err_exit;
return 1;
err_exit:
/* Memory allocation failed */
destroy_thread_sync_data(tsd);
return 0;
}
static int getaddrinfo_complete(struct connectdata *conn)
{
struct thread_sync_data *tsd = conn_thread_sync_data(conn);
int rc;
rc = Curl_addrinfo_callback(conn, tsd->sock_error, tsd->res);
/* The tsd->res structure has been copied to async.dns and perhaps the DNS
cache. Set our copy to NULL so destroy_thread_sync_data doesn't free it.
*/
tsd->res = NULL;
return rc;
}
#ifdef HAVE_GETADDRINFO
/*
* getaddrinfo_thread() resolves a name and then exits.
*
* For builds without ARES, but with ENABLE_IPV6, create a resolver thread
* and wait on it.
*/
static unsigned int CURL_STDCALL getaddrinfo_thread(void *arg)
{
struct thread_sync_data *tsd = (struct thread_sync_data*)arg;
struct thread_data *td = tsd->td;
char service[12];
int rc;
msnprintf(service, sizeof(service), "%d", tsd->port);
rc = Curl_getaddrinfo_ex(tsd->hostname, service, &tsd->hints, &tsd->res);
if(rc != 0) {
tsd->sock_error = SOCKERRNO?SOCKERRNO:rc;
if(tsd->sock_error == 0)
tsd->sock_error = RESOLVER_ENOMEM;
}
else {
Curl_addrinfo_set_port(tsd->res, tsd->port);
}
Curl_mutex_acquire(tsd->mtx);
if(tsd->done) {
/* too late, gotta clean up the mess */
Curl_mutex_release(tsd->mtx);
destroy_thread_sync_data(tsd);
free(td);
}
else {
tsd->done = 1;
Curl_mutex_release(tsd->mtx);
}
return 0;
}
#else /* HAVE_GETADDRINFO */
/*
* gethostbyname_thread() resolves a name and then exits.
*/
static unsigned int CURL_STDCALL gethostbyname_thread(void *arg)
{
struct thread_sync_data *tsd = (struct thread_sync_data *)arg;
struct thread_data *td = tsd->td;
tsd->res = Curl_ipv4_resolve_r(tsd->hostname, tsd->port);
if(!tsd->res) {
tsd->sock_error = SOCKERRNO;
if(tsd->sock_error == 0)
tsd->sock_error = RESOLVER_ENOMEM;
}
Curl_mutex_acquire(tsd->mtx);
if(tsd->done) {
/* too late, gotta clean up the mess */
Curl_mutex_release(tsd->mtx);
destroy_thread_sync_data(tsd);
free(td);
}
else {
tsd->done = 1;
Curl_mutex_release(tsd->mtx);
}
return 0;
}
#endif /* HAVE_GETADDRINFO */
/*
* destroy_async_data() cleans up async resolver data and thread handle.
*/
static void destroy_async_data(struct Curl_async *async)
{
if(async->os_specific) {
struct thread_data *td = (struct thread_data*) async->os_specific;
int done;
/*
* if the thread is still blocking in the resolve syscall, detach it and
* let the thread do the cleanup...
*/
Curl_mutex_acquire(td->tsd.mtx);
done = td->tsd.done;
td->tsd.done = 1;
Curl_mutex_release(td->tsd.mtx);
if(!done) {
Curl_thread_destroy(td->thread_hnd);
}
else {
if(td->thread_hnd != curl_thread_t_null)
Curl_thread_join(&td->thread_hnd);
destroy_thread_sync_data(&td->tsd);
free(async->os_specific);
}
}
async->os_specific = NULL;
free(async->hostname);
async->hostname = NULL;
}
/*
* init_resolve_thread() starts a new thread that performs the actual
* resolve. This function returns before the resolve is done.
*
* Returns FALSE in case of failure, otherwise TRUE.
*/
static bool init_resolve_thread(struct connectdata *conn,
const char *hostname, int port,
const struct addrinfo *hints)
{
struct thread_data *td = calloc(1, sizeof(struct thread_data));
int err = ENOMEM;
conn->async.os_specific = (void *)td;
if(!td)
goto errno_exit;
conn->async.port = port;
conn->async.done = FALSE;
conn->async.status = 0;
conn->async.dns = NULL;
td->thread_hnd = curl_thread_t_null;
if(!init_thread_sync_data(td, hostname, port, hints)) {
conn->async.os_specific = NULL;
free(td);
goto errno_exit;
}
free(conn->async.hostname);
conn->async.hostname = strdup(hostname);
if(!conn->async.hostname)
goto err_exit;
/* The thread will set this to 1 when complete. */
td->tsd.done = 0;
#ifdef HAVE_GETADDRINFO
td->thread_hnd = Curl_thread_create(getaddrinfo_thread, &td->tsd);
#else
td->thread_hnd = Curl_thread_create(gethostbyname_thread, &td->tsd);
#endif
if(!td->thread_hnd) {
/* The thread never started, so mark it as done here for proper cleanup. */
td->tsd.done = 1;
err = errno;
goto err_exit;
}
return TRUE;
err_exit:
destroy_async_data(&conn->async);
errno_exit:
errno = err;
return FALSE;
}
/*
* resolver_error() calls failf() with the appropriate message after a resolve
* error
*/
static CURLcode resolver_error(struct connectdata *conn)
{
const char *host_or_proxy;
CURLcode result;
if(conn->bits.httpproxy) {
host_or_proxy = "proxy";
result = CURLE_COULDNT_RESOLVE_PROXY;
}
else {
host_or_proxy = "host";
result = CURLE_COULDNT_RESOLVE_HOST;
}
failf(conn->data, "Could not resolve %s: %s", host_or_proxy,
conn->async.hostname);
return result;
}
static CURLcode thread_wait_resolv(struct connectdata *conn,
struct Curl_dns_entry **entry,
bool report)
{
struct thread_data *td = (struct thread_data*) conn->async.os_specific;
CURLcode result = CURLE_OK;
DEBUGASSERT(conn && td);
DEBUGASSERT(td->thread_hnd != curl_thread_t_null);
/* wait for the thread to resolve the name */
if(Curl_thread_join(&td->thread_hnd)) {
if(entry)
result = getaddrinfo_complete(conn);
}
else
DEBUGASSERT(0);
conn->async.done = TRUE;
if(entry)
*entry = conn->async.dns;
if(!conn->async.dns && report)
/* a name was not resolved, report error */
result = resolver_error(conn);
destroy_async_data(&conn->async);
if(!conn->async.dns && report)
connclose(conn, "asynch resolve failed");
return result;
}
/*
* Until we gain a way to signal the resolver threads to stop early, we must
* simply wait for them and ignore their results.
*/
void Curl_resolver_kill(struct connectdata *conn)
{
struct thread_data *td = (struct thread_data*) conn->async.os_specific;
/* If we're still resolving, we must wait for the threads to fully clean up,
unfortunately. Otherwise, we can simply cancel to clean up any resolver
data. */
if(td && td->thread_hnd != curl_thread_t_null)
(void)thread_wait_resolv(conn, NULL, FALSE);
else
Curl_resolver_cancel(conn);
}
/*
* Curl_resolver_wait_resolv()
*
* Waits for a resolve to finish. This function should be avoided since using
* this risk getting the multi interface to "hang".
*
* If 'entry' is non-NULL, make it point to the resolved dns entry
*
* Returns CURLE_COULDNT_RESOLVE_HOST if the host was not resolved,
* CURLE_OPERATION_TIMEDOUT if a time-out occurred, or other errors.
*
* This is the version for resolves-in-a-thread.
*/
CURLcode Curl_resolver_wait_resolv(struct connectdata *conn,
struct Curl_dns_entry **entry)
{
return thread_wait_resolv(conn, entry, TRUE);
}
/*
* Curl_resolver_is_resolved() is called repeatedly to check if a previous
* name resolve request has completed. It should also make sure to time-out if
* the operation seems to take too long.
*/
CURLcode Curl_resolver_is_resolved(struct connectdata *conn,
struct Curl_dns_entry **entry)
{
struct Curl_easy *data = conn->data;
struct thread_data *td = (struct thread_data*) conn->async.os_specific;
int done = 0;
*entry = NULL;
if(!td) {
DEBUGASSERT(td);
return CURLE_COULDNT_RESOLVE_HOST;
}
Curl_mutex_acquire(td->tsd.mtx);
done = td->tsd.done;
Curl_mutex_release(td->tsd.mtx);
if(done) {
getaddrinfo_complete(conn);
if(!conn->async.dns) {
CURLcode result = resolver_error(conn);
destroy_async_data(&conn->async);
return result;
}
destroy_async_data(&conn->async);
*entry = conn->async.dns;
}
else {
/* poll for name lookup done with exponential backoff up to 250ms */
timediff_t elapsed = Curl_timediff(Curl_now(),
data->progress.t_startsingle);
if(elapsed < 0)
elapsed = 0;
if(td->poll_interval == 0)
/* Start at 1ms poll interval */
td->poll_interval = 1;
else if(elapsed >= td->interval_end)
/* Back-off exponentially if last interval expired */
td->poll_interval *= 2;
if(td->poll_interval > 250)
td->poll_interval = 250;
td->interval_end = elapsed + td->poll_interval;
Curl_expire(conn->data, td->poll_interval, EXPIRE_ASYNC_NAME);
}
return CURLE_OK;
}
int Curl_resolver_getsock(struct connectdata *conn,
curl_socket_t *socks,
int numsocks)
{
time_t milli;
timediff_t ms;
struct Curl_easy *data = conn->data;
struct resdata *reslv = (struct resdata *)data->state.resolver;
(void)socks;
(void)numsocks;
ms = Curl_timediff(Curl_now(), reslv->start);
if(ms < 3)
milli = 0;
else if(ms <= 50)
milli = ms/3;
else if(ms <= 250)
milli = 50;
else
milli = 200;
Curl_expire(data, milli, EXPIRE_ASYNC_NAME);
return 0;
}
#ifndef HAVE_GETADDRINFO
/*
* Curl_getaddrinfo() - for platforms without getaddrinfo
*/
Curl_addrinfo *Curl_resolver_getaddrinfo(struct connectdata *conn,
const char *hostname,
int port,
int *waitp)
{
struct in_addr in;
struct Curl_easy *data = conn->data;
struct resdata *reslv = (struct resdata *)data->state.resolver;
*waitp = 0; /* default to synchronous response */
if(Curl_inet_pton(AF_INET, hostname, &in) > 0)
/* This is a dotted IP address 123.123.123.123-style */
return Curl_ip2addr(AF_INET, &in, hostname, port);
reslv->start = Curl_now();
/* fire up a new resolver thread! */
if(init_resolve_thread(conn, hostname, port, NULL)) {
*waitp = 1; /* expect asynchronous response */
return NULL;
}
failf(conn->data, "getaddrinfo() thread failed\n");
return NULL;
}
#else /* !HAVE_GETADDRINFO */
/*
* Curl_resolver_getaddrinfo() - for getaddrinfo
*/
Curl_addrinfo *Curl_resolver_getaddrinfo(struct connectdata *conn,
const char *hostname,
int port,
int *waitp)
{
struct addrinfo hints;
char sbuf[12];
int pf = PF_INET;
struct Curl_easy *data = conn->data;
struct resdata *reslv = (struct resdata *)data->state.resolver;
*waitp = 0; /* default to synchronous response */
#ifndef USE_RESOLVE_ON_IPS
{
struct in_addr in;
/* First check if this is an IPv4 address string */
if(Curl_inet_pton(AF_INET, hostname, &in) > 0)
/* This is a dotted IP address 123.123.123.123-style */
return Curl_ip2addr(AF_INET, &in, hostname, port);
}
#ifdef CURLRES_IPV6
{
struct in6_addr in6;
/* check if this is an IPv6 address string */
if(Curl_inet_pton(AF_INET6, hostname, &in6) > 0)
/* This is an IPv6 address literal */
return Curl_ip2addr(AF_INET6, &in6, hostname, port);
}
#endif /* CURLRES_IPV6 */
#endif /* !USE_RESOLVE_ON_IPS */
#ifdef CURLRES_IPV6
/*
* Check if a limited name resolve has been requested.
*/
switch(conn->ip_version) {
case CURL_IPRESOLVE_V4:
pf = PF_INET;
break;
case CURL_IPRESOLVE_V6:
pf = PF_INET6;
break;
default:
pf = PF_UNSPEC;
break;
}
if((pf != PF_INET) && !Curl_ipv6works())
/* The stack seems to be a non-IPv6 one */
pf = PF_INET;
#endif /* CURLRES_IPV6 */
memset(&hints, 0, sizeof(hints));
hints.ai_family = pf;
hints.ai_socktype = conn->socktype;
msnprintf(sbuf, sizeof(sbuf), "%d", port);
reslv->start = Curl_now();
/* fire up a new resolver thread! */
if(init_resolve_thread(conn, hostname, port, &hints)) {
*waitp = 1; /* expect asynchronous response */
return NULL;
}
failf(data, "getaddrinfo() thread failed to start\n");
return NULL;
}
#endif /* !HAVE_GETADDRINFO */
CURLcode Curl_set_dns_servers(struct Curl_easy *data,
char *servers)
{
(void)data;
(void)servers;
return CURLE_NOT_BUILT_IN;
}
CURLcode Curl_set_dns_interface(struct Curl_easy *data,
const char *interf)
{
(void)data;
(void)interf;
return CURLE_NOT_BUILT_IN;
}
CURLcode Curl_set_dns_local_ip4(struct Curl_easy *data,
const char *local_ip4)
{
(void)data;
(void)local_ip4;
return CURLE_NOT_BUILT_IN;
}
CURLcode Curl_set_dns_local_ip6(struct Curl_easy *data,
const char *local_ip6)
{
(void)data;
(void)local_ip6;
return CURLE_NOT_BUILT_IN;
}
#endif /* CURLRES_THREADED */
| YifuLiu/AliOS-Things | components/curl/lib/asyn-thread.c | C | apache-2.0 | 18,989 |
#ifndef HEADER_CURL_ASYN_H
#define HEADER_CURL_ASYN_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#include "curl_addrinfo.h"
struct addrinfo;
struct hostent;
struct Curl_easy;
struct connectdata;
struct Curl_dns_entry;
/*
* This header defines all functions in the internal asynch resolver interface.
* All asynch resolvers need to provide these functions.
* asyn-ares.c and asyn-thread.c are the current implementations of asynch
* resolver backends.
*/
/*
* Curl_resolver_global_init()
*
* Called from curl_global_init() to initialize global resolver environment.
* Returning anything else than CURLE_OK fails curl_global_init().
*/
int Curl_resolver_global_init(void);
/*
* Curl_resolver_global_cleanup()
* Called from curl_global_cleanup() to destroy global resolver environment.
*/
void Curl_resolver_global_cleanup(void);
/*
* Curl_resolver_init()
* Called from curl_easy_init() -> Curl_open() to initialize resolver
* URL-state specific environment ('resolver' member of the UrlState
* structure). Should fill the passed pointer by the initialized handler.
* Returning anything else than CURLE_OK fails curl_easy_init() with the
* correspondent code.
*/
CURLcode Curl_resolver_init(struct Curl_easy *easy, void **resolver);
/*
* Curl_resolver_cleanup()
* Called from curl_easy_cleanup() -> Curl_close() to cleanup resolver
* URL-state specific environment ('resolver' member of the UrlState
* structure). Should destroy the handler and free all resources connected to
* it.
*/
void Curl_resolver_cleanup(void *resolver);
/*
* Curl_resolver_duphandle()
* Called from curl_easy_duphandle() to duplicate resolver URL-state specific
* environment ('resolver' member of the UrlState structure). Should
* duplicate the 'from' handle and pass the resulting handle to the 'to'
* pointer. Returning anything else than CURLE_OK causes failed
* curl_easy_duphandle() call.
*/
CURLcode Curl_resolver_duphandle(struct Curl_easy *easy, void **to,
void *from);
/*
* Curl_resolver_cancel().
*
* It is called from inside other functions to cancel currently performing
* resolver request. Should also free any temporary resources allocated to
* perform a request. This never waits for resolver threads to complete.
*
* It is safe to call this when conn is in any state.
*/
void Curl_resolver_cancel(struct connectdata *conn);
/*
* Curl_resolver_kill().
*
* This acts like Curl_resolver_cancel() except it will block until any threads
* associated with the resolver are complete. This never blocks for resolvers
* that do not use threads. This is intended to be the "last chance" function
* that cleans up an in-progress resolver completely (before its owner is about
* to die).
*
* It is safe to call this when conn is in any state.
*/
void Curl_resolver_kill(struct connectdata *conn);
/* Curl_resolver_getsock()
*
* This function is called from the multi_getsock() function. 'sock' is a
* pointer to an array to hold the file descriptors, with 'numsock' being the
* size of that array (in number of entries). This function is supposed to
* return bitmask indicating what file descriptors (referring to array indexes
* in the 'sock' array) to wait for, read/write.
*/
int Curl_resolver_getsock(struct connectdata *conn, curl_socket_t *sock,
int numsocks);
/*
* Curl_resolver_is_resolved()
*
* Called repeatedly to check if a previous name resolve request has
* completed. It should also make sure to time-out if the operation seems to
* take too long.
*
* Returns normal CURLcode errors.
*/
CURLcode Curl_resolver_is_resolved(struct connectdata *conn,
struct Curl_dns_entry **dns);
/*
* Curl_resolver_wait_resolv()
*
* Waits for a resolve to finish. This function should be avoided since using
* this risk getting the multi interface to "hang".
*
* If 'entry' is non-NULL, make it point to the resolved dns entry
*
* Returns CURLE_COULDNT_RESOLVE_HOST if the host was not resolved,
* CURLE_OPERATION_TIMEDOUT if a time-out occurred, or other errors.
*/
CURLcode Curl_resolver_wait_resolv(struct connectdata *conn,
struct Curl_dns_entry **dnsentry);
/*
* Curl_resolver_getaddrinfo() - when using this resolver
*
* Returns name information about the given hostname and port number. If
* successful, the 'hostent' is returned and the forth argument will point to
* memory we need to free after use. That memory *MUST* be freed with
* Curl_freeaddrinfo(), nothing else.
*
* Each resolver backend must of course make sure to return data in the
* correct format to comply with this.
*/
Curl_addrinfo *Curl_resolver_getaddrinfo(struct connectdata *conn,
const char *hostname,
int port,
int *waitp);
#ifndef CURLRES_ASYNCH
/* convert these functions if an asynch resolver isn't used */
#define Curl_resolver_cancel(x) Curl_nop_stmt
#define Curl_resolver_kill(x) Curl_nop_stmt
#define Curl_resolver_is_resolved(x,y) CURLE_COULDNT_RESOLVE_HOST
#define Curl_resolver_wait_resolv(x,y) CURLE_COULDNT_RESOLVE_HOST
#define Curl_resolver_getsock(x,y,z) 0
#define Curl_resolver_duphandle(x,y,z) CURLE_OK
#define Curl_resolver_init(x,y) CURLE_OK
#define Curl_resolver_global_init() CURLE_OK
#define Curl_resolver_global_cleanup() Curl_nop_stmt
#define Curl_resolver_cleanup(x) Curl_nop_stmt
#endif
#ifdef CURLRES_ASYNCH
#define Curl_resolver_asynch() 1
#else
#define Curl_resolver_asynch() 0
#endif
/********** end of generic resolver interface functions *****************/
#endif /* HEADER_CURL_ASYN_H */
| YifuLiu/AliOS-Things | components/curl/lib/asyn.h | C | apache-2.0 | 6,748 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/* Base64 encoding/decoding */
#include "curl_setup.h"
#if !defined(CURL_DISABLE_HTTP_AUTH) || defined(USE_LIBSSH2) || \
defined(USE_LIBSSH) || !defined(CURL_DISABLE_LDAP) || \
!defined(CURL_DISABLE_DOH) || defined(USE_SSL)
#include "urldata.h" /* for the Curl_easy definition */
#include "warnless.h"
#include "curl_base64.h"
#include "non-ascii.h"
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
/* ---- Base64 Encoding/Decoding Table --- */
static const char base64[]=
"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
/* The Base 64 encoding with an URL and filename safe alphabet, RFC 4648
section 5 */
static const char base64url[]=
"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789-_";
static size_t decodeQuantum(unsigned char *dest, const char *src)
{
size_t padding = 0;
const char *s, *p;
unsigned long i, x = 0;
for(i = 0, s = src; i < 4; i++, s++) {
if(*s == '=') {
x = (x << 6);
padding++;
}
else {
unsigned long v = 0;
p = base64;
while(*p && (*p != *s)) {
v++;
p++;
}
if(*p == *s)
x = (x << 6) + v;
else
return 0;
}
}
if(padding < 1)
dest[2] = curlx_ultouc(x & 0xFFUL);
x >>= 8;
if(padding < 2)
dest[1] = curlx_ultouc(x & 0xFFUL);
x >>= 8;
dest[0] = curlx_ultouc(x & 0xFFUL);
return 3 - padding;
}
/*
* Curl_base64_decode()
*
* Given a base64 NUL-terminated string at src, decode it and return a
* pointer in *outptr to a newly allocated memory area holding decoded
* data. Size of decoded data is returned in variable pointed by outlen.
*
* Returns CURLE_OK on success, otherwise specific error code. Function
* output shall not be considered valid unless CURLE_OK is returned.
*
* When decoded data length is 0, returns NULL in *outptr.
*
* @unittest: 1302
*/
CURLcode Curl_base64_decode(const char *src,
unsigned char **outptr, size_t *outlen)
{
size_t srclen = 0;
size_t length = 0;
size_t padding = 0;
size_t i;
size_t numQuantums;
size_t rawlen = 0;
unsigned char *pos;
unsigned char *newstr;
*outptr = NULL;
*outlen = 0;
srclen = strlen(src);
/* Check the length of the input string is valid */
if(!srclen || srclen % 4)
return CURLE_BAD_CONTENT_ENCODING;
/* Find the position of any = padding characters */
while((src[length] != '=') && src[length])
length++;
/* A maximum of two = padding characters is allowed */
if(src[length] == '=') {
padding++;
if(src[length + 1] == '=')
padding++;
}
/* Check the = padding characters weren't part way through the input */
if(length + padding != srclen)
return CURLE_BAD_CONTENT_ENCODING;
/* Calculate the number of quantums */
numQuantums = srclen / 4;
/* Calculate the size of the decoded string */
rawlen = (numQuantums * 3) - padding;
/* Allocate our buffer including room for a zero terminator */
newstr = malloc(rawlen + 1);
if(!newstr)
return CURLE_OUT_OF_MEMORY;
pos = newstr;
/* Decode the quantums */
for(i = 0; i < numQuantums; i++) {
size_t result = decodeQuantum(pos, src);
if(!result) {
free(newstr);
return CURLE_BAD_CONTENT_ENCODING;
}
pos += result;
src += 4;
}
/* Zero terminate */
*pos = '\0';
/* Return the decoded data */
*outptr = newstr;
*outlen = rawlen;
return CURLE_OK;
}
static CURLcode base64_encode(const char *table64,
struct Curl_easy *data,
const char *inputbuff, size_t insize,
char **outptr, size_t *outlen)
{
CURLcode result;
unsigned char ibuf[3];
unsigned char obuf[4];
int i;
int inputparts;
char *output;
char *base64data;
char *convbuf = NULL;
const char *indata = inputbuff;
*outptr = NULL;
*outlen = 0;
if(!insize)
insize = strlen(indata);
#if SIZEOF_SIZE_T == 4
if(insize > UINT_MAX/4)
return CURLE_OUT_OF_MEMORY;
#endif
base64data = output = malloc(insize * 4 / 3 + 4);
if(!output)
return CURLE_OUT_OF_MEMORY;
/*
* The base64 data needs to be created using the network encoding
* not the host encoding. And we can't change the actual input
* so we copy it to a buffer, translate it, and use that instead.
*/
result = Curl_convert_clone(data, indata, insize, &convbuf);
if(result) {
free(output);
return result;
}
if(convbuf)
indata = (char *)convbuf;
while(insize > 0) {
for(i = inputparts = 0; i < 3; i++) {
if(insize > 0) {
inputparts++;
ibuf[i] = (unsigned char) *indata;
indata++;
insize--;
}
else
ibuf[i] = 0;
}
obuf[0] = (unsigned char) ((ibuf[0] & 0xFC) >> 2);
obuf[1] = (unsigned char) (((ibuf[0] & 0x03) << 4) | \
((ibuf[1] & 0xF0) >> 4));
obuf[2] = (unsigned char) (((ibuf[1] & 0x0F) << 2) | \
((ibuf[2] & 0xC0) >> 6));
obuf[3] = (unsigned char) (ibuf[2] & 0x3F);
switch(inputparts) {
case 1: /* only one byte read */
msnprintf(output, 5, "%c%c==",
table64[obuf[0]],
table64[obuf[1]]);
break;
case 2: /* two bytes read */
msnprintf(output, 5, "%c%c%c=",
table64[obuf[0]],
table64[obuf[1]],
table64[obuf[2]]);
break;
default:
msnprintf(output, 5, "%c%c%c%c",
table64[obuf[0]],
table64[obuf[1]],
table64[obuf[2]],
table64[obuf[3]]);
break;
}
output += 4;
}
/* Zero terminate */
*output = '\0';
/* Return the pointer to the new data (allocated memory) */
*outptr = base64data;
free(convbuf);
/* Return the length of the new data */
*outlen = strlen(base64data);
return CURLE_OK;
}
/*
* Curl_base64_encode()
*
* Given a pointer to an input buffer and an input size, encode it and
* return a pointer in *outptr to a newly allocated memory area holding
* encoded data. Size of encoded data is returned in variable pointed by
* outlen.
*
* Input length of 0 indicates input buffer holds a NUL-terminated string.
*
* Returns CURLE_OK on success, otherwise specific error code. Function
* output shall not be considered valid unless CURLE_OK is returned.
*
* When encoded data length is 0, returns NULL in *outptr.
*
* @unittest: 1302
*/
CURLcode Curl_base64_encode(struct Curl_easy *data,
const char *inputbuff, size_t insize,
char **outptr, size_t *outlen)
{
return base64_encode(base64, data, inputbuff, insize, outptr, outlen);
}
/*
* Curl_base64url_encode()
*
* Given a pointer to an input buffer and an input size, encode it and
* return a pointer in *outptr to a newly allocated memory area holding
* encoded data. Size of encoded data is returned in variable pointed by
* outlen.
*
* Input length of 0 indicates input buffer holds a NUL-terminated string.
*
* Returns CURLE_OK on success, otherwise specific error code. Function
* output shall not be considered valid unless CURLE_OK is returned.
*
* When encoded data length is 0, returns NULL in *outptr.
*
* @unittest: 1302
*/
CURLcode Curl_base64url_encode(struct Curl_easy *data,
const char *inputbuff, size_t insize,
char **outptr, size_t *outlen)
{
return base64_encode(base64url, data, inputbuff, insize, outptr, outlen);
}
#endif /* no users so disabled */
| YifuLiu/AliOS-Things | components/curl/lib/base64.c | C | apache-2.0 | 8,729 |
#!/usr/bin/env perl
#***************************************************************************
# _ _ ____ _
# Project ___| | | | _ \| |
# / __| | | | |_) | |
# | (__| |_| | _ <| |___
# \___|\___/|_| \_\_____|
#
# Copyright (C) 2011 - 2018, Daniel Stenberg, <daniel@haxx.se>, et al.
#
# This software is licensed as described in the file COPYING, which
# you should have received as part of this distribution. The terms
# are also available at https://curl.haxx.se/docs/copyright.html.
#
# You may opt to use, copy, modify, merge, publish, distribute and/or sell
# copies of the Software, and permit persons to whom the Software is
# furnished to do so, under the terms of the COPYING file.
#
# This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
# KIND, either express or implied.
#
###########################################################################
use strict;
use warnings;
my $max_column = 79;
my $indent = 2;
my $warnings = 0;
my $swarnings = 0;
my $errors = 0;
my $serrors = 0;
my $suppressed; # whitelisted problems
my $file;
my $dir=".";
my $wlist="";
my @alist;
my $windows_os = $^O eq 'MSWin32' || $^O eq 'msys' || $^O eq 'cygwin';
my $verbose;
my %whitelist;
my %ignore;
my %ignore_set;
my %ignore_used;
my @ignore_line;
my %warnings_extended = (
'COPYRIGHTYEAR' => 'copyright year incorrect',
);
my %warnings = (
'LONGLINE' => "Line longer than $max_column",
'TABS' => 'TAB characters not allowed',
'TRAILINGSPACE' => 'Trailing white space on the line',
'CPPCOMMENTS' => '// comment detected',
'SPACEBEFOREPAREN' => 'space before an open parenthesis',
'SPACEAFTERPAREN' => 'space after open parenthesis',
'SPACEBEFORECLOSE' => 'space before a close parenthesis',
'SPACEBEFORECOMMA' => 'space before a comma',
'RETURNNOSPACE' => 'return without space',
'COMMANOSPACE' => 'comma without following space',
'BRACEELSE' => '} else on the same line',
'PARENBRACE' => '){ without sufficient space',
'SPACESEMICOLON' => 'space before semicolon',
'BANNEDFUNC' => 'a banned function was used',
'FOPENMODE' => 'fopen needs a macro for the mode string',
'BRACEPOS' => 'wrong position for an open brace',
'INDENTATION' => 'wrong start column for code',
'COPYRIGHT' => 'file missing a copyright statement',
'BADCOMMAND' => 'bad !checksrc! instruction',
'UNUSEDIGNORE' => 'a warning ignore was not used',
'OPENCOMMENT' => 'file ended with a /* comment still "open"',
'ASTERISKSPACE' => 'pointer declared with space after asterisk',
'ASTERISKNOSPACE' => 'pointer declared without space before asterisk',
'ASSIGNWITHINCONDITION' => 'assignment within conditional expression',
'EQUALSNOSPACE' => 'equals sign without following space',
'NOSPACEEQUALS' => 'equals sign without preceding space',
'SEMINOSPACE' => 'semicolon without following space',
'MULTISPACE' => 'multiple spaces used when not suitable',
'SIZEOFNOPAREN' => 'use of sizeof without parentheses',
'SNPRINTF' => 'use of snprintf',
);
sub readwhitelist {
open(W, "<$dir/checksrc.whitelist") or return;
my @all=<W>;
for(@all) {
$windows_os ? $_ =~ s/\r?\n$// : chomp;
$whitelist{$_}=1;
}
close(W);
}
# Reads the .checksrc in $dir for any extended warnings to enable locally.
# Currently there is no support for disabling warnings from the standard set,
# and since that's already handled via !checksrc! commands there is probably
# little use to add it.
sub readlocalfile {
my $i = 0;
open(my $rcfile, "<", "$dir/.checksrc") or return;
while(<$rcfile>) {
$i++;
# Lines starting with '#' are considered comments
if (/^\s*(#.*)/) {
next;
}
elsif (/^\s*enable ([A-Z]+)$/) {
if(!defined($warnings_extended{$1})) {
print STDERR "invalid warning specified in .checksrc: \"$1\"\n";
next;
}
$warnings{$1} = $warnings_extended{$1};
}
else {
die "Invalid format in $dir/.checksrc on line $i\n";
}
}
}
sub checkwarn {
my ($name, $num, $col, $file, $line, $msg, $error) = @_;
my $w=$error?"error":"warning";
my $nowarn=0;
#if(!$warnings{$name}) {
# print STDERR "Dev! there's no description for $name!\n";
#}
# checksrc.whitelist
if($whitelist{$line}) {
$nowarn = 1;
}
# !checksrc! controlled
elsif($ignore{$name}) {
$ignore{$name}--;
$ignore_used{$name}++;
$nowarn = 1;
if(!$ignore{$name}) {
# reached zero, enable again
enable_warn($name, $num, $file, $line);
}
}
if($nowarn) {
$suppressed++;
if($w) {
$swarnings++;
}
else {
$serrors++;
}
return;
}
if($w) {
$warnings++;
}
else {
$errors++;
}
$col++;
print "$file:$num:$col: $w: $msg ($name)\n";
print " $line\n";
if($col < 80) {
my $pref = (' ' x $col);
print "${pref}^\n";
}
}
$file = shift @ARGV;
while(1) {
if($file =~ /-D(.*)/) {
$dir = $1;
$file = shift @ARGV;
next;
}
elsif($file =~ /-W(.*)/) {
$wlist .= " $1 ";
$file = shift @ARGV;
next;
}
elsif($file =~ /-A(.+)/) {
push @alist, $1;
$file = shift @ARGV;
next;
}
elsif($file =~ /-i([1-9])/) {
$indent = $1 + 0;
$file = shift @ARGV;
next;
}
elsif($file =~ /-m([0-9]+)/) {
$max_column = $1 + 0;
$file = shift @ARGV;
next;
}
elsif($file =~ /^(-h|--help)/) {
undef $file;
last;
}
last;
}
if(!$file) {
print "checksrc.pl [option] <file1> [file2] ...\n";
print " Options:\n";
print " -A[rule] Accept this violation, can be used multiple times\n";
print " -D[DIR] Directory to prepend file names\n";
print " -h Show help output\n";
print " -W[file] Whitelist the given file - ignore all its flaws\n";
print " -i<n> Indent spaces. Default: 2\n";
print " -m<n> Maximum line length. Default: 79\n";
print "\nDetects and warns for these problems:\n";
for(sort keys %warnings) {
printf (" %-18s: %s\n", $_, $warnings{$_});
}
exit;
}
readwhitelist();
readlocalfile();
do {
if("$wlist" !~ / $file /) {
my $fullname = $file;
$fullname = "$dir/$file" if ($fullname !~ '^\.?\.?/');
scanfile($fullname);
}
$file = shift @ARGV;
} while($file);
sub accept_violations {
for my $r (@alist) {
if(!$warnings{$r}) {
print "'$r' is not a warning to accept!\n";
exit;
}
$ignore{$r}=999999;
$ignore_used{$r}=0;
}
}
sub checksrc_clear {
undef %ignore;
undef %ignore_set;
undef @ignore_line;
}
sub checksrc_endoffile {
my ($file) = @_;
for(keys %ignore_set) {
if($ignore_set{$_} && !$ignore_used{$_}) {
checkwarn("UNUSEDIGNORE", $ignore_set{$_},
length($_)+11, $file,
$ignore_line[$ignore_set{$_}],
"Unused ignore: $_");
}
}
}
sub enable_warn {
my ($what, $line, $file, $l) = @_;
# switch it back on, but warn if not triggered!
if(!$ignore_used{$what}) {
checkwarn("UNUSEDIGNORE",
$line, length($what) + 11, $file, $l,
"No warning was inhibited!");
}
$ignore_set{$what}=0;
$ignore_used{$what}=0;
$ignore{$what}=0;
}
sub checksrc {
my ($cmd, $line, $file, $l) = @_;
if($cmd =~ / *([^ ]*) *(.*)/) {
my ($enable, $what) = ($1, $2);
$what =~ s: *\*/$::; # cut off end of C comment
# print "ENABLE $enable WHAT $what\n";
if($enable eq "disable") {
my ($warn, $scope)=($1, $2);
if($what =~ /([^ ]*) +(.*)/) {
($warn, $scope)=($1, $2);
}
else {
$warn = $what;
$scope = 1;
}
# print "IGNORE $warn for SCOPE $scope\n";
if($scope eq "all") {
$scope=999999;
}
# Comparing for a literal zero rather than the scalar value zero
# covers the case where $scope contains the ending '*' from the
# comment. If we use a scalar comparison (==) we induce warnings
# on non-scalar contents.
if($scope eq "0") {
checkwarn("BADCOMMAND",
$line, 0, $file, $l,
"Disable zero not supported, did you mean to enable?");
}
elsif($ignore_set{$warn}) {
checkwarn("BADCOMMAND",
$line, 0, $file, $l,
"$warn already disabled from line $ignore_set{$warn}");
}
else {
$ignore{$warn}=$scope;
$ignore_set{$warn}=$line;
$ignore_line[$line]=$l;
}
}
elsif($enable eq "enable") {
enable_warn($what, $line, $file, $l);
}
else {
checkwarn("BADCOMMAND",
$line, 0, $file, $l,
"Illegal !checksrc! command");
}
}
}
sub nostrings {
my ($str) = @_;
$str =~ s/\".*\"//g;
return $str;
}
sub scanfile {
my ($file) = @_;
my $line = 1;
my $prevl="";
my $l;
open(R, "<$file") || die "failed to open $file";
my $incomment=0;
my @copyright=();
checksrc_clear(); # for file based ignores
accept_violations();
while(<R>) {
$windows_os ? $_ =~ s/\r?\n$// : chomp;
my $l = $_;
my $ol = $l; # keep the unmodified line for error reporting
my $column = 0;
# check for !checksrc! commands
if($l =~ /\!checksrc\! (.*)/) {
my $cmd = $1;
checksrc($cmd, $line, $file, $l)
}
# check for a copyright statement and save the years
if($l =~ /\* +copyright .* \d\d\d\d/i) {
while($l =~ /([\d]{4})/g) {
push @copyright, {
year => $1,
line => $line,
col => index($l, $1),
code => $l
};
}
}
# detect long lines
if(length($l) > $max_column) {
checkwarn("LONGLINE", $line, length($l), $file, $l,
"Longer than $max_column columns");
}
# detect TAB characters
if($l =~ /^(.*)\t/) {
checkwarn("TABS",
$line, length($1), $file, $l, "Contains TAB character", 1);
}
# detect trailing white space
if($l =~ /^(.*)[ \t]+\z/) {
checkwarn("TRAILINGSPACE",
$line, length($1), $file, $l, "Trailing whitespace");
}
# ------------------------------------------------------------
# Above this marker, the checks were done on lines *including*
# comments
# ------------------------------------------------------------
# strip off C89 comments
comment:
if(!$incomment) {
if($l =~ s/\/\*.*\*\// /g) {
# full /* comments */ were removed!
}
if($l =~ s/\/\*.*//) {
# start of /* comment was removed
$incomment = 1;
}
}
else {
if($l =~ s/.*\*\///) {
# end of comment */ was removed
$incomment = 0;
goto comment;
}
else {
# still within a comment
$l="";
}
}
# ------------------------------------------------------------
# Below this marker, the checks were done on lines *without*
# comments
# ------------------------------------------------------------
# crude attempt to detect // comments without too many false
# positives
if($l =~ /^([^"\*]*)[^:"]\/\//) {
checkwarn("CPPCOMMENTS",
$line, length($1), $file, $l, "\/\/ comment");
}
my $nostr = nostrings($l);
# check spaces after for/if/while/function call
if($nostr =~ /^(.*)(for|if|while| ([a-zA-Z0-9_]+)) \((.)/) {
if($1 =~ / *\#/) {
# this is a #if, treat it differently
}
elsif(defined $3 && $3 eq "return") {
# return must have a space
}
elsif(defined $3 && $3 eq "case") {
# case must have a space
}
elsif($4 eq "*") {
# (* beginning makes the space OK!
}
elsif($1 =~ / *typedef/) {
# typedefs can use space-paren
}
else {
checkwarn("SPACEBEFOREPAREN", $line, length($1)+length($2), $file, $l,
"$2 with space");
}
}
if($nostr =~ /^((.*)(if) *\()(.*)\)/) {
my $pos = length($1);
if($4 =~ / = /) {
checkwarn("ASSIGNWITHINCONDITION",
$line, $pos+1, $file, $l,
"assignment within conditional expression");
}
}
# check spaces after open parentheses
if($l =~ /^(.*[a-z])\( /i) {
checkwarn("SPACEAFTERPAREN",
$line, length($1)+1, $file, $l,
"space after open parenthesis");
}
# check spaces before close parentheses, unless it was a space or a
# close parenthesis!
if($l =~ /(.*[^\) ]) \)/) {
checkwarn("SPACEBEFORECLOSE",
$line, length($1)+1, $file, $l,
"space before close parenthesis");
}
# check spaces before comma!
if($l =~ /(.*[^ ]) ,/) {
checkwarn("SPACEBEFORECOMMA",
$line, length($1)+1, $file, $l,
"space before comma");
}
# check for "return(" without space
if($l =~ /^(.*)return\(/) {
if($1 =~ / *\#/) {
# this is a #if, treat it differently
}
else {
checkwarn("RETURNNOSPACE", $line, length($1)+6, $file, $l,
"return without space before paren");
}
}
# check for "sizeof" without parenthesis
if(($l =~ /^(.*)sizeof *([ (])/) && ($2 ne "(")) {
if($1 =~ / *\#/) {
# this is a #if, treat it differently
}
else {
checkwarn("SIZEOFNOPAREN", $line, length($1)+6, $file, $l,
"sizeof without parenthesis");
}
}
# check for comma without space
if($l =~ /^(.*),[^ \n]/) {
my $pref=$1;
my $ign=0;
if($pref =~ / *\#/) {
# this is a #if, treat it differently
$ign=1;
}
elsif($pref =~ /\/\*/) {
# this is a comment
$ign=1;
}
elsif($pref =~ /[\"\']/) {
$ign = 1;
# There is a quote here, figure out whether the comma is
# within a string or '' or not.
if($pref =~ /\"/) {
# within a string
}
elsif($pref =~ /\'$/) {
# a single letter
}
else {
$ign = 0;
}
}
if(!$ign) {
checkwarn("COMMANOSPACE", $line, length($pref)+1, $file, $l,
"comma without following space");
}
}
# check for "} else"
if($l =~ /^(.*)\} *else/) {
checkwarn("BRACEELSE",
$line, length($1), $file, $l, "else after closing brace on same line");
}
# check for "){"
if($l =~ /^(.*)\)\{/) {
checkwarn("PARENBRACE",
$line, length($1)+1, $file, $l, "missing space after close paren");
}
# check for space before the semicolon last in a line
if($l =~ /^(.*[^ ].*) ;$/) {
checkwarn("SPACESEMICOLON",
$line, length($1), $file, $ol, "space before last semicolon");
}
# scan for use of banned functions
if($l =~ /^(.*\W)
(gets|
strtok|
v?sprintf|
(str|_mbs|_tcs|_wcs)n?cat|
LoadLibrary(Ex)?(A|W)?)
\s*\(
/x) {
checkwarn("BANNEDFUNC",
$line, length($1), $file, $ol,
"use of $2 is banned");
}
# scan for use of snprintf for curl-internals reasons
if($l =~ /^(.*\W)(v?snprintf)\s*\(/x) {
checkwarn("SNPRINTF",
$line, length($1), $file, $ol,
"use of $2 is banned");
}
# scan for use of non-binary fopen without the macro
if($l =~ /^(.*\W)fopen\s*\([^,]*, *\"([^"]*)/) {
my $mode = $2;
if($mode !~ /b/) {
checkwarn("FOPENMODE",
$line, length($1), $file, $ol,
"use of non-binary fopen without FOPEN_* macro: $mode");
}
}
# check for open brace first on line but not first column
# only alert if previous line ended with a close paren and wasn't a cpp
# line
if((($prevl =~ /\)\z/) && ($prevl !~ /^ *#/)) && ($l =~ /^( +)\{/)) {
checkwarn("BRACEPOS",
$line, length($1), $file, $ol, "badly placed open brace");
}
# if the previous line starts with if/while/for AND ends with an open
# brace, or an else statement, check that this line is indented $indent
# more steps, if not a cpp line
if($prevl =~ /^( *)((if|while|for)\(.*\{|else)\z/) {
my $first = length($1);
# this line has some character besides spaces
if(($l !~ /^ *#/) && ($l =~ /^( *)[^ ]/)) {
my $second = length($1);
my $expect = $first+$indent;
if($expect != $second) {
my $diff = $second - $first;
checkwarn("INDENTATION", $line, length($1), $file, $ol,
"not indented $indent steps (uses $diff)");
}
}
}
# check for 'char * name'
if(($l =~ /(^.*(char|int|long|void|curl_slist|CURL|CURLM|CURLMsg|curl_httppost) *(\*+)) (\w+)/) && ($4 ne "const")) {
checkwarn("ASTERISKNOSPACE",
$line, length($1), $file, $ol,
"no space after declarative asterisk");
}
# check for 'char*'
if(($l =~ /(^.*(char|int|long|void|curl_slist|CURL|CURLM|CURLMsg|curl_httppost|sockaddr_in|FILE)\*)/)) {
checkwarn("ASTERISKNOSPACE",
$line, length($1)-1, $file, $ol,
"no space before asterisk");
}
# check for 'void func() {', but avoid false positives by requiring
# both an open and closed parentheses before the open brace
if($l =~ /^((\w).*)\{\z/) {
my $k = $1;
$k =~ s/const *//;
$k =~ s/static *//;
if($k =~ /\(.*\)/) {
checkwarn("BRACEPOS",
$line, length($l)-1, $file, $ol,
"wrongly placed open brace");
}
}
# check for equals sign without spaces next to it
if($nostr =~ /(.*)\=[a-z0-9]/i) {
checkwarn("EQUALSNOSPACE",
$line, length($1)+1, $file, $ol,
"no space after equals sign");
}
# check for equals sign without spaces before it
elsif($nostr =~ /(.*)[a-z0-9]\=/i) {
checkwarn("NOSPACEEQUALS",
$line, length($1)+1, $file, $ol,
"no space before equals sign");
}
# check for plus signs without spaces next to it
if($nostr =~ /(.*)[^+]\+[a-z0-9]/i) {
checkwarn("PLUSNOSPACE",
$line, length($1)+1, $file, $ol,
"no space after plus sign");
}
# check for plus sign without spaces before it
elsif($nostr =~ /(.*)[a-z0-9]\+[^+]/i) {
checkwarn("NOSPACEPLUS",
$line, length($1)+1, $file, $ol,
"no space before plus sign");
}
# check for semicolons without space next to it
if($nostr =~ /(.*)\;[a-z0-9]/i) {
checkwarn("SEMINOSPACE",
$line, length($1)+1, $file, $ol,
"no space after semicolon");
}
# check for more than one consecutive space before open brace or
# question mark. Skip lines containing strings since they make it hard
# due to artificially getting multiple spaces
if(($l eq $nostr) &&
$nostr =~ /^(.*(\S)) + [{?]/i) {
checkwarn("MULTISPACE",
$line, length($1)+1, $file, $ol,
"multiple space");
print STDERR "L: $l\n";
print STDERR "nostr: $nostr\n";
}
$line++;
$prevl = $ol;
}
if(!scalar(@copyright)) {
checkwarn("COPYRIGHT", 1, 0, $file, "", "Missing copyright statement", 1);
}
# COPYRIGHTYEAR is a extended warning so we must first see if it has been
# enabled in .checksrc
if(defined($warnings{"COPYRIGHTYEAR"})) {
# The check for updated copyrightyear is overly complicated in order to
# not punish current hacking for past sins. The copyright years are
# right now a bit behind, so enforcing copyright year checking on all
# files would cause hundreds of errors. Instead we only look at files
# which are tracked in the Git repo and edited in the workdir, or
# committed locally on the branch without being in upstream master.
#
# The simple and naive test is to simply check for the current year,
# but updating the year even without an edit is against project policy
# (and it would fail every file on January 1st).
#
# A rather more interesting, and correct, check would be to not test
# only locally committed files but inspect all files wrt the year of
# their last commit. Removing the `git rev-list origin/master..HEAD`
# condition below will enfore copyright year checks against the year
# the file was last committed (and thus edited to some degree).
my $commityear = undef;
@copyright = sort {$$b{year} cmp $$a{year}} @copyright;
if(`git status -s -- $file` =~ /^ [MARCU]/) {
$commityear = (localtime(time))[5] + 1900;
}
elsif (`git rev-list --count origin/master..HEAD -- $file` !~ /^0/) {
my $grl = `git rev-list --max-count=1 --timestamp HEAD -- $file`;
$commityear = (localtime((split(/ /, $grl))[0]))[5] + 1900;
}
if(defined($commityear) && scalar(@copyright) &&
$copyright[0]{year} != $commityear) {
checkwarn("COPYRIGHTYEAR", $copyright[0]{line}, $copyright[0]{col},
$file, $copyright[0]{code},
"Copyright year out of date, should be $commityear, " .
"is $copyright[0]{year}", 1);
}
}
if($incomment) {
checkwarn("OPENCOMMENT", 1, 0, $file, "", "Missing closing comment", 1);
}
checksrc_endoffile($file);
close(R);
}
if($errors || $warnings || $verbose) {
printf "checksrc: %d errors and %d warnings\n", $errors, $warnings;
if($suppressed) {
printf "checksrc: %d errors and %d warnings suppressed\n",
$serrors,
$swarnings;
}
exit 5; # return failure
}
| YifuLiu/AliOS-Things | components/curl/lib/checksrc.pl | Perl | apache-2.0 | 24,730 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 2012 - 2016, Linus Nielsen Feltzing, <linus@haxx.se>
* Copyright (C) 2012 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#include <curl/curl.h>
#include "urldata.h"
#include "url.h"
#include "progress.h"
#include "multiif.h"
#include "sendf.h"
#include "conncache.h"
#include "share.h"
#include "sigpipe.h"
#include "connect.h"
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
#ifdef CURLDEBUG
/* the debug versions of these macros make extra certain that the lock is
never doubly locked or unlocked */
#define CONN_LOCK(x) if((x)->share) { \
Curl_share_lock((x), CURL_LOCK_DATA_CONNECT, CURL_LOCK_ACCESS_SINGLE); \
DEBUGASSERT(!(x)->state.conncache_lock); \
(x)->state.conncache_lock = TRUE; \
}
#define CONN_UNLOCK(x) if((x)->share) { \
DEBUGASSERT((x)->state.conncache_lock); \
(x)->state.conncache_lock = FALSE; \
Curl_share_unlock((x), CURL_LOCK_DATA_CONNECT); \
}
#else
#define CONN_LOCK(x) if((x)->share) \
Curl_share_lock((x), CURL_LOCK_DATA_CONNECT, CURL_LOCK_ACCESS_SINGLE)
#define CONN_UNLOCK(x) if((x)->share) \
Curl_share_unlock((x), CURL_LOCK_DATA_CONNECT)
#endif
static void conn_llist_dtor(void *user, void *element)
{
struct connectdata *conn = element;
(void)user;
conn->bundle = NULL;
}
static CURLcode bundle_create(struct Curl_easy *data,
struct connectbundle **cb_ptr)
{
(void)data;
DEBUGASSERT(*cb_ptr == NULL);
*cb_ptr = malloc(sizeof(struct connectbundle));
if(!*cb_ptr)
return CURLE_OUT_OF_MEMORY;
(*cb_ptr)->num_connections = 0;
(*cb_ptr)->multiuse = BUNDLE_UNKNOWN;
Curl_llist_init(&(*cb_ptr)->conn_list, (curl_llist_dtor) conn_llist_dtor);
return CURLE_OK;
}
static void bundle_destroy(struct connectbundle *cb_ptr)
{
if(!cb_ptr)
return;
Curl_llist_destroy(&cb_ptr->conn_list, NULL);
free(cb_ptr);
}
/* Add a connection to a bundle */
static void bundle_add_conn(struct connectbundle *cb_ptr,
struct connectdata *conn)
{
Curl_llist_insert_next(&cb_ptr->conn_list, cb_ptr->conn_list.tail, conn,
&conn->bundle_node);
conn->bundle = cb_ptr;
cb_ptr->num_connections++;
}
/* Remove a connection from a bundle */
static int bundle_remove_conn(struct connectbundle *cb_ptr,
struct connectdata *conn)
{
struct curl_llist_element *curr;
curr = cb_ptr->conn_list.head;
while(curr) {
if(curr->ptr == conn) {
Curl_llist_remove(&cb_ptr->conn_list, curr, NULL);
cb_ptr->num_connections--;
conn->bundle = NULL;
return 1; /* we removed a handle */
}
curr = curr->next;
}
return 0;
}
static void free_bundle_hash_entry(void *freethis)
{
struct connectbundle *b = (struct connectbundle *) freethis;
bundle_destroy(b);
}
int Curl_conncache_init(struct conncache *connc, int size)
{
int rc;
/* allocate a new easy handle to use when closing cached connections */
connc->closure_handle = curl_easy_init();
if(!connc->closure_handle)
return 1; /* bad */
rc = Curl_hash_init(&connc->hash, size, Curl_hash_str,
Curl_str_key_compare, free_bundle_hash_entry);
if(rc) {
Curl_close(connc->closure_handle);
connc->closure_handle = NULL;
}
else
connc->closure_handle->state.conn_cache = connc;
return rc;
}
void Curl_conncache_destroy(struct conncache *connc)
{
if(connc)
Curl_hash_destroy(&connc->hash);
}
/* creates a key to find a bundle for this connection */
static void hashkey(struct connectdata *conn, char *buf,
size_t len) /* something like 128 is fine */
{
const char *hostname;
if(conn->bits.socksproxy)
hostname = conn->socks_proxy.host.name;
else if(conn->bits.httpproxy)
hostname = conn->http_proxy.host.name;
else if(conn->bits.conn_to_host)
hostname = conn->conn_to_host.name;
else
hostname = conn->host.name;
DEBUGASSERT(len > 32);
/* put the number first so that the hostname gets cut off if too long */
msnprintf(buf, len, "%ld%s", conn->port, hostname);
}
void Curl_conncache_unlock(struct Curl_easy *data)
{
CONN_UNLOCK(data);
}
/* Returns number of connections currently held in the connection cache.
Locks/unlocks the cache itself!
*/
size_t Curl_conncache_size(struct Curl_easy *data)
{
size_t num;
CONN_LOCK(data);
num = data->state.conn_cache->num_conn;
CONN_UNLOCK(data);
return num;
}
/* Returns number of connections currently held in the connections's bundle
Locks/unlocks the cache itself!
*/
size_t Curl_conncache_bundle_size(struct connectdata *conn)
{
size_t num;
CONN_LOCK(conn->data);
num = conn->bundle->num_connections;
CONN_UNLOCK(conn->data);
return num;
}
/* Look up the bundle with all the connections to the same host this
connectdata struct is setup to use.
**NOTE**: When it returns, it holds the connection cache lock! */
struct connectbundle *Curl_conncache_find_bundle(struct connectdata *conn,
struct conncache *connc)
{
struct connectbundle *bundle = NULL;
CONN_LOCK(conn->data);
if(connc) {
char key[128];
hashkey(conn, key, sizeof(key));
bundle = Curl_hash_pick(&connc->hash, key, strlen(key));
}
return bundle;
}
static bool conncache_add_bundle(struct conncache *connc,
char *key,
struct connectbundle *bundle)
{
void *p = Curl_hash_add(&connc->hash, key, strlen(key), bundle);
return p?TRUE:FALSE;
}
static void conncache_remove_bundle(struct conncache *connc,
struct connectbundle *bundle)
{
struct curl_hash_iterator iter;
struct curl_hash_element *he;
if(!connc)
return;
Curl_hash_start_iterate(&connc->hash, &iter);
he = Curl_hash_next_element(&iter);
while(he) {
if(he->ptr == bundle) {
/* The bundle is destroyed by the hash destructor function,
free_bundle_hash_entry() */
Curl_hash_delete(&connc->hash, he->key, he->key_len);
return;
}
he = Curl_hash_next_element(&iter);
}
}
CURLcode Curl_conncache_add_conn(struct conncache *connc,
struct connectdata *conn)
{
CURLcode result = CURLE_OK;
struct connectbundle *bundle;
struct connectbundle *new_bundle = NULL;
struct Curl_easy *data = conn->data;
/* *find_bundle() locks the connection cache */
bundle = Curl_conncache_find_bundle(conn, data->state.conn_cache);
if(!bundle) {
int rc;
char key[128];
result = bundle_create(data, &new_bundle);
if(result) {
goto unlock;
}
hashkey(conn, key, sizeof(key));
rc = conncache_add_bundle(data->state.conn_cache, key, new_bundle);
if(!rc) {
bundle_destroy(new_bundle);
result = CURLE_OUT_OF_MEMORY;
goto unlock;
}
bundle = new_bundle;
}
bundle_add_conn(bundle, conn);
conn->connection_id = connc->next_connection_id++;
connc->num_conn++;
DEBUGF(infof(conn->data, "Added connection %ld. "
"The cache now contains %zu members\n",
conn->connection_id, connc->num_conn));
unlock:
CONN_UNLOCK(data);
return result;
}
/*
* Removes the connectdata object from the connection cache *and* clears the
* ->data pointer association. Pass TRUE/FALSE in the 'lock' argument
* depending on if the parent function already holds the lock or not.
*/
void Curl_conncache_remove_conn(struct Curl_easy *data,
struct connectdata *conn, bool lock)
{
struct connectbundle *bundle = conn->bundle;
struct conncache *connc = data->state.conn_cache;
/* The bundle pointer can be NULL, since this function can be called
due to a failed connection attempt, before being added to a bundle */
if(bundle) {
if(lock) {
CONN_LOCK(data);
}
bundle_remove_conn(bundle, conn);
if(bundle->num_connections == 0)
conncache_remove_bundle(connc, bundle);
conn->bundle = NULL; /* removed from it */
if(connc) {
connc->num_conn--;
DEBUGF(infof(data, "The cache now contains %zu members\n",
connc->num_conn));
}
conn->data = NULL; /* clear the association */
if(lock) {
CONN_UNLOCK(data);
}
}
}
/* This function iterates the entire connection cache and calls the function
func() with the connection pointer as the first argument and the supplied
'param' argument as the other.
The conncache lock is still held when the callback is called. It needs it,
so that it can safely continue traversing the lists once the callback
returns.
Returns 1 if the loop was aborted due to the callback's return code.
Return 0 from func() to continue the loop, return 1 to abort it.
*/
bool Curl_conncache_foreach(struct Curl_easy *data,
struct conncache *connc,
void *param,
int (*func)(struct connectdata *conn, void *param))
{
struct curl_hash_iterator iter;
struct curl_llist_element *curr;
struct curl_hash_element *he;
if(!connc)
return FALSE;
CONN_LOCK(data);
Curl_hash_start_iterate(&connc->hash, &iter);
he = Curl_hash_next_element(&iter);
while(he) {
struct connectbundle *bundle;
bundle = he->ptr;
he = Curl_hash_next_element(&iter);
curr = bundle->conn_list.head;
while(curr) {
/* Yes, we need to update curr before calling func(), because func()
might decide to remove the connection */
struct connectdata *conn = curr->ptr;
curr = curr->next;
if(1 == func(conn, param)) {
CONN_UNLOCK(data);
return TRUE;
}
}
}
CONN_UNLOCK(data);
return FALSE;
}
/* Return the first connection found in the cache. Used when closing all
connections.
NOTE: no locking is done here as this is presumably only done when cleaning
up a cache!
*/
static struct connectdata *
conncache_find_first_connection(struct conncache *connc)
{
struct curl_hash_iterator iter;
struct curl_hash_element *he;
struct connectbundle *bundle;
Curl_hash_start_iterate(&connc->hash, &iter);
he = Curl_hash_next_element(&iter);
while(he) {
struct curl_llist_element *curr;
bundle = he->ptr;
curr = bundle->conn_list.head;
if(curr) {
return curr->ptr;
}
he = Curl_hash_next_element(&iter);
}
return NULL;
}
/*
* Give ownership of a connection back to the connection cache. Might
* disconnect the oldest existing in there to make space.
*
* Return TRUE if stored, FALSE if closed.
*/
bool Curl_conncache_return_conn(struct connectdata *conn)
{
struct Curl_easy *data = conn->data;
/* data->multi->maxconnects can be negative, deal with it. */
size_t maxconnects =
(data->multi->maxconnects < 0) ? data->multi->num_easy * 4:
data->multi->maxconnects;
struct connectdata *conn_candidate = NULL;
conn->data = NULL; /* no owner anymore */
conn->lastused = Curl_now(); /* it was used up until now */
if(maxconnects > 0 &&
Curl_conncache_size(data) > maxconnects) {
infof(data, "Connection cache is full, closing the oldest one.\n");
conn_candidate = Curl_conncache_extract_oldest(data);
if(conn_candidate) {
/* the winner gets the honour of being disconnected */
(void)Curl_disconnect(data, conn_candidate, /* dead_connection */ FALSE);
}
}
return (conn_candidate == conn) ? FALSE : TRUE;
}
/*
* This function finds the connection in the connection bundle that has been
* unused for the longest time.
*
* Does not lock the connection cache!
*
* Returns the pointer to the oldest idle connection, or NULL if none was
* found.
*/
struct connectdata *
Curl_conncache_extract_bundle(struct Curl_easy *data,
struct connectbundle *bundle)
{
struct curl_llist_element *curr;
timediff_t highscore = -1;
timediff_t score;
struct curltime now;
struct connectdata *conn_candidate = NULL;
struct connectdata *conn;
(void)data;
now = Curl_now();
curr = bundle->conn_list.head;
while(curr) {
conn = curr->ptr;
if(!CONN_INUSE(conn) && !conn->data) {
/* Set higher score for the age passed since the connection was used */
score = Curl_timediff(now, conn->lastused);
if(score > highscore) {
highscore = score;
conn_candidate = conn;
}
}
curr = curr->next;
}
if(conn_candidate) {
/* remove it to prevent another thread from nicking it */
bundle_remove_conn(bundle, conn_candidate);
data->state.conn_cache->num_conn--;
DEBUGF(infof(data, "The cache now contains %zu members\n",
data->state.conn_cache->num_conn));
conn_candidate->data = data; /* associate! */
}
return conn_candidate;
}
/*
* This function finds the connection in the connection cache that has been
* unused for the longest time and extracts that from the bundle.
*
* Returns the pointer to the connection, or NULL if none was found.
*/
struct connectdata *
Curl_conncache_extract_oldest(struct Curl_easy *data)
{
struct conncache *connc = data->state.conn_cache;
struct curl_hash_iterator iter;
struct curl_llist_element *curr;
struct curl_hash_element *he;
timediff_t highscore =- 1;
timediff_t score;
struct curltime now;
struct connectdata *conn_candidate = NULL;
struct connectbundle *bundle;
struct connectbundle *bundle_candidate = NULL;
now = Curl_now();
CONN_LOCK(data);
Curl_hash_start_iterate(&connc->hash, &iter);
he = Curl_hash_next_element(&iter);
while(he) {
struct connectdata *conn;
bundle = he->ptr;
curr = bundle->conn_list.head;
while(curr) {
conn = curr->ptr;
if(!CONN_INUSE(conn) && !conn->data) {
/* Set higher score for the age passed since the connection was used */
score = Curl_timediff(now, conn->lastused);
if(score > highscore) {
highscore = score;
conn_candidate = conn;
bundle_candidate = bundle;
}
}
curr = curr->next;
}
he = Curl_hash_next_element(&iter);
}
if(conn_candidate) {
/* remove it to prevent another thread from nicking it */
bundle_remove_conn(bundle_candidate, conn_candidate);
connc->num_conn--;
DEBUGF(infof(data, "The cache now contains %zu members\n",
connc->num_conn));
conn_candidate->data = data; /* associate! */
}
CONN_UNLOCK(data);
return conn_candidate;
}
void Curl_conncache_close_all_connections(struct conncache *connc)
{
struct connectdata *conn;
conn = conncache_find_first_connection(connc);
while(conn) {
SIGPIPE_VARIABLE(pipe_st);
conn->data = connc->closure_handle;
sigpipe_ignore(conn->data, &pipe_st);
/* This will remove the connection from the cache */
connclose(conn, "kill all");
(void)Curl_disconnect(connc->closure_handle, conn, FALSE);
sigpipe_restore(&pipe_st);
conn = conncache_find_first_connection(connc);
}
if(connc->closure_handle) {
SIGPIPE_VARIABLE(pipe_st);
sigpipe_ignore(connc->closure_handle, &pipe_st);
Curl_hostcache_clean(connc->closure_handle,
connc->closure_handle->dns.hostcache);
Curl_close(connc->closure_handle);
sigpipe_restore(&pipe_st);
}
}
#if 0
/* Useful for debugging the connection cache */
void Curl_conncache_print(struct conncache *connc)
{
struct curl_hash_iterator iter;
struct curl_llist_element *curr;
struct curl_hash_element *he;
if(!connc)
return;
fprintf(stderr, "=Bundle cache=\n");
Curl_hash_start_iterate(connc->hash, &iter);
he = Curl_hash_next_element(&iter);
while(he) {
struct connectbundle *bundle;
struct connectdata *conn;
bundle = he->ptr;
fprintf(stderr, "%s -", he->key);
curr = bundle->conn_list->head;
while(curr) {
conn = curr->ptr;
fprintf(stderr, " [%p %d]", (void *)conn, conn->inuse);
curr = curr->next;
}
fprintf(stderr, "\n");
he = Curl_hash_next_element(&iter);
}
}
#endif
| YifuLiu/AliOS-Things | components/curl/lib/conncache.c | C | apache-2.0 | 17,425 |
#ifndef HEADER_CURL_CONNCACHE_H
#define HEADER_CURL_CONNCACHE_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 2015 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
* Copyright (C) 2012 - 2014, Linus Nielsen Feltzing, <linus@haxx.se>
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
/*
* All accesses to struct fields and changing of data in the connection cache
* and connectbundles must be done with the conncache LOCKED. The cache might
* be shared.
*/
struct conncache {
struct curl_hash hash;
size_t num_conn;
long next_connection_id;
struct curltime last_cleanup;
/* handle used for closing cached connections */
struct Curl_easy *closure_handle;
};
#define BUNDLE_NO_MULTIUSE -1
#define BUNDLE_UNKNOWN 0 /* initial value */
#define BUNDLE_MULTIPLEX 2
struct connectbundle {
int multiuse; /* supports multi-use */
size_t num_connections; /* Number of connections in the bundle */
struct curl_llist conn_list; /* The connectdata members of the bundle */
};
/* returns 1 on error, 0 is fine */
int Curl_conncache_init(struct conncache *, int size);
void Curl_conncache_destroy(struct conncache *connc);
/* return the correct bundle, to a host or a proxy */
struct connectbundle *Curl_conncache_find_bundle(struct connectdata *conn,
struct conncache *connc);
void Curl_conncache_unlock(struct Curl_easy *data);
/* returns number of connections currently held in the connection cache */
size_t Curl_conncache_size(struct Curl_easy *data);
size_t Curl_conncache_bundle_size(struct connectdata *conn);
bool Curl_conncache_return_conn(struct connectdata *conn);
CURLcode Curl_conncache_add_conn(struct conncache *connc,
struct connectdata *conn) WARN_UNUSED_RESULT;
void Curl_conncache_remove_conn(struct Curl_easy *data,
struct connectdata *conn,
bool lock);
bool Curl_conncache_foreach(struct Curl_easy *data,
struct conncache *connc,
void *param,
int (*func)(struct connectdata *conn,
void *param));
struct connectdata *
Curl_conncache_find_first_connection(struct conncache *connc);
struct connectdata *
Curl_conncache_extract_bundle(struct Curl_easy *data,
struct connectbundle *bundle);
struct connectdata *
Curl_conncache_extract_oldest(struct Curl_easy *data);
void Curl_conncache_close_all_connections(struct conncache *connc);
void Curl_conncache_print(struct conncache *connc);
#endif /* HEADER_CURL_CONNCACHE_H */
| YifuLiu/AliOS-Things | components/curl/lib/conncache.h | C | apache-2.0 | 3,564 |
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#ifdef HAVE_NETINET_IN_H
#include <netinet/in.h> /* <netinet/tcp.h> may need it */
#endif
#ifdef HAVE_SYS_UN_H
#include <sys/un.h> /* for sockaddr_un */
#endif
#ifdef HAVE_LINUX_TCP_H
#include <linux/tcp.h>
#elif defined(HAVE_NETINET_TCP_H)
#include <netinet/tcp.h>
#endif
#ifdef HAVE_SYS_IOCTL_H
#include <sys/ioctl.h>
#endif
#ifdef HAVE_NETDB_H
#ifdef USE_LWIPSOCK
#include <sys/socket.h>
#include <lwip/netdb.h>
#else
#include <netdb.h>
#endif
#endif
#ifdef HAVE_FCNTL_H
#include <fcntl.h>
#endif
#ifdef HAVE_ARPA_INET_H
#include <arpa/inet.h>
#endif
#if (defined(HAVE_IOCTL_FIONBIO) && defined(NETWARE))
#include <sys/filio.h>
#endif
#ifdef NETWARE
#undef in_addr_t
#define in_addr_t unsigned long
#endif
#ifdef __VMS
#include <in.h>
#include <inet.h>
#endif
#include "urldata.h"
#include "sendf.h"
#include "if2ip.h"
#include "strerror.h"
#include "connect.h"
#include "select.h"
#include "url.h" /* for Curl_safefree() */
#include "multiif.h"
#include "sockaddr.h" /* required for Curl_sockaddr_storage */
#include "inet_ntop.h"
#include "inet_pton.h"
#include "vtls/vtls.h" /* for Curl_ssl_check_cxn() */
#include "progress.h"
#include "warnless.h"
#include "conncache.h"
#include "multihandle.h"
#include "system_win32.h"
/* The last 3 #include files should be in this order */
#include "curl_printf.h"
#include "curl_memory.h"
#include "memdebug.h"
#ifdef __SYMBIAN32__
/* This isn't actually supported under Symbian OS */
#undef SO_NOSIGPIPE
#endif
static bool verifyconnect(curl_socket_t sockfd, int *error);
#if defined(__DragonFly__) || defined(HAVE_WINSOCK_H)
/* DragonFlyBSD and Windows use millisecond units */
#define KEEPALIVE_FACTOR(x) (x *= 1000)
#else
#define KEEPALIVE_FACTOR(x)
#endif
#if defined(HAVE_WINSOCK2_H) && !defined(SIO_KEEPALIVE_VALS)
#define SIO_KEEPALIVE_VALS _WSAIOW(IOC_VENDOR,4)
struct tcp_keepalive {
u_long onoff;
u_long keepalivetime;
u_long keepaliveinterval;
};
#endif
static void
tcpkeepalive(struct Curl_easy *data,
curl_socket_t sockfd)
{
int optval = data->set.tcp_keepalive?1:0;
/* only set IDLE and INTVL if setting KEEPALIVE is successful */
if(setsockopt(sockfd, SOL_SOCKET, SO_KEEPALIVE,
(void *)&optval, sizeof(optval)) < 0) {
infof(data, "Failed to set SO_KEEPALIVE on fd %d\n", sockfd);
}
else {
#if defined(SIO_KEEPALIVE_VALS)
struct tcp_keepalive vals;
DWORD dummy;
vals.onoff = 1;
optval = curlx_sltosi(data->set.tcp_keepidle);
KEEPALIVE_FACTOR(optval);
vals.keepalivetime = optval;
optval = curlx_sltosi(data->set.tcp_keepintvl);
KEEPALIVE_FACTOR(optval);
vals.keepaliveinterval = optval;
if(WSAIoctl(sockfd, SIO_KEEPALIVE_VALS, (LPVOID) &vals, sizeof(vals),
NULL, 0, &dummy, NULL, NULL) != 0) {
infof(data, "Failed to set SIO_KEEPALIVE_VALS on fd %d: %d\n",
(int)sockfd, WSAGetLastError());
}
#else
#ifdef TCP_KEEPIDLE
optval = curlx_sltosi(data->set.tcp_keepidle);
KEEPALIVE_FACTOR(optval);
if(setsockopt(sockfd, IPPROTO_TCP, TCP_KEEPIDLE,
(void *)&optval, sizeof(optval)) < 0) {
infof(data, "Failed to set TCP_KEEPIDLE on fd %d\n", sockfd);
}
#endif
#ifdef TCP_KEEPINTVL
optval = curlx_sltosi(data->set.tcp_keepintvl);
KEEPALIVE_FACTOR(optval);
if(setsockopt(sockfd, IPPROTO_TCP, TCP_KEEPINTVL,
(void *)&optval, sizeof(optval)) < 0) {
infof(data, "Failed to set TCP_KEEPINTVL on fd %d\n", sockfd);
}
#endif
#ifdef TCP_KEEPALIVE
/* Mac OS X style */
optval = curlx_sltosi(data->set.tcp_keepidle);
KEEPALIVE_FACTOR(optval);
if(setsockopt(sockfd, IPPROTO_TCP, TCP_KEEPALIVE,
(void *)&optval, sizeof(optval)) < 0) {
infof(data, "Failed to set TCP_KEEPALIVE on fd %d\n", sockfd);
}
#endif
#endif
}
}
static CURLcode
singleipconnect(struct connectdata *conn,
const Curl_addrinfo *ai, /* start connecting to this */
curl_socket_t *sock);
/*
* Curl_timeleft() returns the amount of milliseconds left allowed for the
* transfer/connection. If the value is negative, the timeout time has already
* elapsed.
*
* The start time is stored in progress.t_startsingle - as set with
* Curl_pgrsTime(..., TIMER_STARTSINGLE);
*
* If 'nowp' is non-NULL, it points to the current time.
* 'duringconnect' is FALSE if not during a connect, as then of course the
* connect timeout is not taken into account!
*
* @unittest: 1303
*/
timediff_t Curl_timeleft(struct Curl_easy *data,
struct curltime *nowp,
bool duringconnect)
{
int timeout_set = 0;
timediff_t timeout_ms = duringconnect?DEFAULT_CONNECT_TIMEOUT:0;
struct curltime now;
/* if a timeout is set, use the most restrictive one */
if(data->set.timeout > 0)
timeout_set |= 1;
if(duringconnect && (data->set.connecttimeout > 0))
timeout_set |= 2;
switch(timeout_set) {
case 1:
timeout_ms = data->set.timeout;
break;
case 2:
timeout_ms = data->set.connecttimeout;
break;
case 3:
if(data->set.timeout < data->set.connecttimeout)
timeout_ms = data->set.timeout;
else
timeout_ms = data->set.connecttimeout;
break;
default:
/* use the default */
if(!duringconnect)
/* if we're not during connect, there's no default timeout so if we're
at zero we better just return zero and not make it a negative number
by the math below */
return 0;
break;
}
if(!nowp) {
now = Curl_now();
nowp = &now;
}
/* subtract elapsed time */
if(duringconnect)
/* since this most recent connect started */
timeout_ms -= Curl_timediff(*nowp, data->progress.t_startsingle);
else
/* since the entire operation started */
timeout_ms -= Curl_timediff(*nowp, data->progress.t_startop);
if(!timeout_ms)
/* avoid returning 0 as that means no timeout! */
return -1;
return timeout_ms;
}
static CURLcode bindlocal(struct connectdata *conn,
curl_socket_t sockfd, int af, unsigned int scope)
{
struct Curl_easy *data = conn->data;
struct Curl_sockaddr_storage sa;
struct sockaddr *sock = (struct sockaddr *)&sa; /* bind to this address */
curl_socklen_t sizeof_sa = 0; /* size of the data sock points to */
struct sockaddr_in *si4 = (struct sockaddr_in *)&sa;
#ifdef ENABLE_IPV6
struct sockaddr_in6 *si6 = (struct sockaddr_in6 *)&sa;
#endif
struct Curl_dns_entry *h = NULL;
unsigned short port = data->set.localport; /* use this port number, 0 for
"random" */
/* how many port numbers to try to bind to, increasing one at a time */
int portnum = data->set.localportrange;
const char *dev = data->set.str[STRING_DEVICE];
int error;
/*************************************************************
* Select device to bind socket to
*************************************************************/
if(!dev && !port)
/* no local kind of binding was requested */
return CURLE_OK;
memset(&sa, 0, sizeof(struct Curl_sockaddr_storage));
if(dev && (strlen(dev)<255) ) {
char myhost[256] = "";
int done = 0; /* -1 for error, 1 for address found */
bool is_interface = FALSE;
bool is_host = FALSE;
static const char *if_prefix = "if!";
static const char *host_prefix = "host!";
if(strncmp(if_prefix, dev, strlen(if_prefix)) == 0) {
dev += strlen(if_prefix);
is_interface = TRUE;
}
else if(strncmp(host_prefix, dev, strlen(host_prefix)) == 0) {
dev += strlen(host_prefix);
is_host = TRUE;
}
/* interface */
if(!is_host) {
#ifdef SO_BINDTODEVICE
/* I am not sure any other OSs than Linux that provide this feature,
* and at the least I cannot test. --Ben
*
* This feature allows one to tightly bind the local socket to a
* particular interface. This will force even requests to other
* local interfaces to go out the external interface.
*
*
* Only bind to the interface when specified as interface, not just
* as a hostname or ip address.
*
* interface might be a VRF, eg: vrf-blue, which means it cannot be
* converted to an IP address and would fail Curl_if2ip. Simply try
* to use it straight away.
*/
if(setsockopt(sockfd, SOL_SOCKET, SO_BINDTODEVICE,
dev, (curl_socklen_t)strlen(dev) + 1) == 0) {
/* This is typically "errno 1, error: Operation not permitted" if
* you're not running as root or another suitable privileged
* user.
* If it succeeds it means the parameter was a valid interface and
* not an IP address. Return immediately.
*/
return CURLE_OK;
}
#endif
switch(Curl_if2ip(af, scope, conn->scope_id, dev,
myhost, sizeof(myhost))) {
case IF2IP_NOT_FOUND:
if(is_interface) {
/* Do not fall back to treating it as a host name */
failf(data, "Couldn't bind to interface '%s'", dev);
return CURLE_INTERFACE_FAILED;
}
break;
case IF2IP_AF_NOT_SUPPORTED:
/* Signal the caller to try another address family if available */
return CURLE_UNSUPPORTED_PROTOCOL;
case IF2IP_FOUND:
is_interface = TRUE;
/*
* We now have the numerical IP address in the 'myhost' buffer
*/
infof(data, "Local Interface %s is ip %s using address family %i\n",
dev, myhost, af);
done = 1;
break;
}
}
if(!is_interface) {
/*
* This was not an interface, resolve the name as a host name
* or IP number
*
* Temporarily force name resolution to use only the address type
* of the connection. The resolve functions should really be changed
* to take a type parameter instead.
*/
long ipver = conn->ip_version;
int rc;
if(af == AF_INET)
conn->ip_version = CURL_IPRESOLVE_V4;
#ifdef ENABLE_IPV6
else if(af == AF_INET6)
conn->ip_version = CURL_IPRESOLVE_V6;
#endif
rc = Curl_resolv(conn, dev, 0, FALSE, &h);
if(rc == CURLRESOLV_PENDING)
(void)Curl_resolver_wait_resolv(conn, &h);
conn->ip_version = ipver;
if(h) {
/* convert the resolved address, sizeof myhost >= INET_ADDRSTRLEN */
Curl_printable_address(h->addr, myhost, sizeof(myhost));
infof(data, "Name '%s' family %i resolved to '%s' family %i\n",
dev, af, myhost, h->addr->ai_family);
Curl_resolv_unlock(data, h);
done = 1;
}
else {
/*
* provided dev was no interface (or interfaces are not supported
* e.g. solaris) no ip address and no domain we fail here
*/
done = -1;
}
}
if(done > 0) {
#ifdef ENABLE_IPV6
/* IPv6 address */
if(af == AF_INET6) {
#ifdef HAVE_SOCKADDR_IN6_SIN6_SCOPE_ID
char *scope_ptr = strchr(myhost, '%');
if(scope_ptr)
*(scope_ptr++) = 0;
#endif
if(Curl_inet_pton(AF_INET6, myhost, &si6->sin6_addr) > 0) {
si6->sin6_family = AF_INET6;
si6->sin6_port = htons(port);
#ifdef HAVE_SOCKADDR_IN6_SIN6_SCOPE_ID
if(scope_ptr)
/* The "myhost" string either comes from Curl_if2ip or from
Curl_printable_address. The latter returns only numeric scope
IDs and the former returns none at all. So the scope ID, if
present, is known to be numeric */
si6->sin6_scope_id = atoi(scope_ptr);
#endif
}
sizeof_sa = sizeof(struct sockaddr_in6);
}
else
#endif
/* IPv4 address */
if((af == AF_INET) &&
(Curl_inet_pton(AF_INET, myhost, &si4->sin_addr) > 0)) {
si4->sin_family = AF_INET;
si4->sin_port = htons(port);
sizeof_sa = sizeof(struct sockaddr_in);
}
}
if(done < 1) {
/* errorbuf is set false so failf will overwrite any message already in
the error buffer, so the user receives this error message instead of a
generic resolve error. */
data->state.errorbuf = FALSE;
failf(data, "Couldn't bind to '%s'", dev);
return CURLE_INTERFACE_FAILED;
}
}
else {
/* no device was given, prepare sa to match af's needs */
#ifdef ENABLE_IPV6
if(af == AF_INET6) {
si6->sin6_family = AF_INET6;
si6->sin6_port = htons(port);
sizeof_sa = sizeof(struct sockaddr_in6);
}
else
#endif
if(af == AF_INET) {
si4->sin_family = AF_INET;
si4->sin_port = htons(port);
sizeof_sa = sizeof(struct sockaddr_in);
}
}
for(;;) {
if(bind(sockfd, sock, sizeof_sa) >= 0) {
/* we succeeded to bind */
struct Curl_sockaddr_storage add;
curl_socklen_t size = sizeof(add);
memset(&add, 0, sizeof(struct Curl_sockaddr_storage));
if(getsockname(sockfd, (struct sockaddr *) &add, &size) < 0) {
char buffer[STRERROR_LEN];
data->state.os_errno = error = SOCKERRNO;
failf(data, "getsockname() failed with errno %d: %s",
error, Curl_strerror(error, buffer, sizeof(buffer)));
return CURLE_INTERFACE_FAILED;
}
infof(data, "Local port: %hu\n", port);
conn->bits.bound = TRUE;
return CURLE_OK;
}
if(--portnum > 0) {
infof(data, "Bind to local port %hu failed, trying next\n", port);
port++; /* try next port */
/* We re-use/clobber the port variable here below */
if(sock->sa_family == AF_INET)
si4->sin_port = ntohs(port);
#ifdef ENABLE_IPV6
else
si6->sin6_port = ntohs(port);
#endif
}
else
break;
}
{
char buffer[STRERROR_LEN];
data->state.os_errno = error = SOCKERRNO;
failf(data, "bind failed with errno %d: %s",
error, Curl_strerror(error, buffer, sizeof(buffer)));
}
return CURLE_INTERFACE_FAILED;
}
/*
* verifyconnect() returns TRUE if the connect really has happened.
*/
static bool verifyconnect(curl_socket_t sockfd, int *error)
{
bool rc = TRUE;
#ifdef SO_ERROR
int err = 0;
curl_socklen_t errSize = sizeof(err);
#ifdef WIN32
/*
* In October 2003 we effectively nullified this function on Windows due to
* problems with it using all CPU in multi-threaded cases.
*
* In May 2004, we bring it back to offer more info back on connect failures.
* Gisle Vanem could reproduce the former problems with this function, but
* could avoid them by adding this SleepEx() call below:
*
* "I don't have Rational Quantify, but the hint from his post was
* ntdll::NtRemoveIoCompletion(). So I'd assume the SleepEx (or maybe
* just Sleep(0) would be enough?) would release whatever
* mutex/critical-section the ntdll call is waiting on.
*
* Someone got to verify this on Win-NT 4.0, 2000."
*/
#ifdef _WIN32_WCE
Sleep(0);
#else
SleepEx(0, FALSE);
#endif
#endif
if(0 != getsockopt(sockfd, SOL_SOCKET, SO_ERROR, (void *)&err, &errSize))
err = SOCKERRNO;
#ifdef _WIN32_WCE
/* Old WinCE versions don't support SO_ERROR */
if(WSAENOPROTOOPT == err) {
SET_SOCKERRNO(0);
err = 0;
}
#endif
#if defined(EBADIOCTL) && defined(__minix)
/* Minix 3.1.x doesn't support getsockopt on UDP sockets */
if(EBADIOCTL == err) {
SET_SOCKERRNO(0);
err = 0;
}
#endif
if((0 == err) || (EISCONN == err))
/* we are connected, awesome! */
rc = TRUE;
else
/* This wasn't a successful connect */
rc = FALSE;
if(error)
*error = err;
#else
(void)sockfd;
if(error)
*error = SOCKERRNO;
#endif
return rc;
}
/* Used within the multi interface. Try next IP address, return TRUE if no
more address exists or error */
static CURLcode trynextip(struct connectdata *conn,
int sockindex,
int tempindex)
{
const int other = tempindex ^ 1;
CURLcode result = CURLE_COULDNT_CONNECT;
/* First clean up after the failed socket.
Don't close it yet to ensure that the next IP's socket gets a different
file descriptor, which can prevent bugs when the curl_multi_socket_action
interface is used with certain select() replacements such as kqueue. */
curl_socket_t fd_to_close = conn->tempsock[tempindex];
conn->tempsock[tempindex] = CURL_SOCKET_BAD;
if(sockindex == FIRSTSOCKET) {
Curl_addrinfo *ai = NULL;
int family = AF_UNSPEC;
if(conn->tempaddr[tempindex]) {
/* find next address in the same protocol family */
family = conn->tempaddr[tempindex]->ai_family;
ai = conn->tempaddr[tempindex]->ai_next;
}
#ifdef ENABLE_IPV6
else if(conn->tempaddr[0]) {
/* happy eyeballs - try the other protocol family */
int firstfamily = conn->tempaddr[0]->ai_family;
family = (firstfamily == AF_INET) ? AF_INET6 : AF_INET;
ai = conn->tempaddr[0]->ai_next;
}
#endif
while(ai) {
if(conn->tempaddr[other]) {
/* we can safely skip addresses of the other protocol family */
while(ai && ai->ai_family != family)
ai = ai->ai_next;
}
if(ai) {
result = singleipconnect(conn, ai, &conn->tempsock[tempindex]);
if(result == CURLE_COULDNT_CONNECT) {
ai = ai->ai_next;
continue;
}
conn->tempaddr[tempindex] = ai;
}
break;
}
}
if(fd_to_close != CURL_SOCKET_BAD)
Curl_closesocket(conn, fd_to_close);
return result;
}
/* Copies connection info into the session handle to make it available
when the session handle is no longer associated with a connection. */
void Curl_persistconninfo(struct connectdata *conn)
{
memcpy(conn->data->info.conn_primary_ip, conn->primary_ip, MAX_IPADR_LEN);
memcpy(conn->data->info.conn_local_ip, conn->local_ip, MAX_IPADR_LEN);
conn->data->info.conn_scheme = conn->handler->scheme;
conn->data->info.conn_protocol = conn->handler->protocol;
conn->data->info.conn_primary_port = conn->primary_port;
conn->data->info.conn_local_port = conn->local_port;
}
UNITTEST bool getaddressinfo(struct sockaddr *sa, char *addr,
long *port);
/* retrieves ip address and port from a sockaddr structure.
note it calls Curl_inet_ntop which sets errno on fail, not SOCKERRNO. */
UNITTEST bool getaddressinfo(struct sockaddr *sa, char *addr,
long *port)
{
struct sockaddr_in *si = NULL;
#ifdef ENABLE_IPV6
struct sockaddr_in6 *si6 = NULL;
#endif
#if defined(HAVE_SYS_UN_H) && defined(AF_UNIX)
struct sockaddr_un *su = NULL;
#endif
switch(sa->sa_family) {
case AF_INET:
si = (struct sockaddr_in *)(void *) sa;
if(Curl_inet_ntop(sa->sa_family, &si->sin_addr,
addr, MAX_IPADR_LEN)) {
unsigned short us_port = ntohs(si->sin_port);
*port = us_port;
return TRUE;
}
break;
#ifdef ENABLE_IPV6
case AF_INET6:
si6 = (struct sockaddr_in6 *)(void *) sa;
if(Curl_inet_ntop(sa->sa_family, &si6->sin6_addr,
addr, MAX_IPADR_LEN)) {
unsigned short us_port = ntohs(si6->sin6_port);
*port = us_port;
return TRUE;
}
break;
#endif
#if defined(HAVE_SYS_UN_H) && defined(AF_UNIX)
case AF_UNIX:
su = (struct sockaddr_un*)sa;
msnprintf(addr, MAX_IPADR_LEN, "%s", su->sun_path);
*port = 0;
return TRUE;
#endif
default:
break;
}
addr[0] = '\0';
*port = 0;
errno = EAFNOSUPPORT;
return FALSE;
}
/* retrieves the start/end point information of a socket of an established
connection */
void Curl_updateconninfo(struct connectdata *conn, curl_socket_t sockfd)
{
if(conn->socktype == SOCK_DGRAM)
/* there's no connection! */
return;
#if defined(HAVE_GETPEERNAME) || defined(HAVE_GETSOCKNAME)
if(!conn->bits.reuse && !conn->bits.tcp_fastopen) {
struct Curl_easy *data = conn->data;
char buffer[STRERROR_LEN];
struct Curl_sockaddr_storage ssrem;
struct Curl_sockaddr_storage ssloc;
curl_socklen_t len;
#ifdef HAVE_GETPEERNAME
len = sizeof(struct Curl_sockaddr_storage);
if(getpeername(sockfd, (struct sockaddr*) &ssrem, &len)) {
int error = SOCKERRNO;
failf(data, "getpeername() failed with errno %d: %s",
error, Curl_strerror(error, buffer, sizeof(buffer)));
return;
}
#endif
#ifdef HAVE_GETSOCKNAME
len = sizeof(struct Curl_sockaddr_storage);
memset(&ssloc, 0, sizeof(ssloc));
if(getsockname(sockfd, (struct sockaddr*) &ssloc, &len)) {
int error = SOCKERRNO;
failf(data, "getsockname() failed with errno %d: %s",
error, Curl_strerror(error, buffer, sizeof(buffer)));
return;
}
#endif
#ifdef HAVE_GETPEERNAME
if(!getaddressinfo((struct sockaddr*)&ssrem,
conn->primary_ip, &conn->primary_port)) {
failf(data, "ssrem inet_ntop() failed with errno %d: %s",
errno, Curl_strerror(errno, buffer, sizeof(buffer)));
return;
}
memcpy(conn->ip_addr_str, conn->primary_ip, MAX_IPADR_LEN);
#endif
#ifdef HAVE_GETSOCKNAME
if(!getaddressinfo((struct sockaddr*)&ssloc,
conn->local_ip, &conn->local_port)) {
failf(data, "ssloc inet_ntop() failed with errno %d: %s",
errno, Curl_strerror(errno, buffer, sizeof(buffer)));
return;
}
#endif
}
#else /* !HAVE_GETSOCKNAME && !HAVE_GETPEERNAME */
(void)sockfd; /* unused */
#endif
/* persist connection info in session handle */
Curl_persistconninfo(conn);
}
/*
* Curl_is_connected() checks if the socket has connected.
*/
CURLcode Curl_is_connected(struct connectdata *conn,
int sockindex,
bool *connected)
{
struct Curl_easy *data = conn->data;
CURLcode result = CURLE_OK;
timediff_t allow;
int error = 0;
struct curltime now;
int rc;
int i;
DEBUGASSERT(sockindex >= FIRSTSOCKET && sockindex <= SECONDARYSOCKET);
*connected = FALSE; /* a very negative world view is best */
if(conn->bits.tcpconnect[sockindex]) {
/* we are connected already! */
*connected = TRUE;
return CURLE_OK;
}
now = Curl_now();
/* figure out how long time we have left to connect */
allow = Curl_timeleft(data, &now, TRUE);
if(allow < 0) {
/* time-out, bail out, go home */
failf(data, "Connection time-out");
return CURLE_OPERATION_TIMEDOUT;
}
for(i = 0; i<2; i++) {
const int other = i ^ 1;
if(conn->tempsock[i] == CURL_SOCKET_BAD)
continue;
#ifdef mpeix
/* Call this function once now, and ignore the results. We do this to
"clear" the error state on the socket so that we can later read it
reliably. This is reported necessary on the MPE/iX operating system. */
(void)verifyconnect(conn->tempsock[i], NULL);
#endif
/* check socket for connect */
rc = SOCKET_WRITABLE(conn->tempsock[i], 0);
if(rc == 0) { /* no connection yet */
error = 0;
if(Curl_timediff(now, conn->connecttime) >= conn->timeoutms_per_addr) {
infof(data, "After %ldms connect time, move on!\n",
conn->timeoutms_per_addr);
error = ETIMEDOUT;
}
/* should we try another protocol family? */
if(i == 0 && conn->tempaddr[1] == NULL &&
(Curl_timediff(now, conn->connecttime) >=
data->set.happy_eyeballs_timeout)) {
trynextip(conn, sockindex, 1);
}
}
else if(rc == CURL_CSELECT_OUT || conn->bits.tcp_fastopen) {
if(verifyconnect(conn->tempsock[i], &error)) {
/* we are connected with TCP, awesome! */
/* use this socket from now on */
conn->sock[sockindex] = conn->tempsock[i];
conn->ip_addr = conn->tempaddr[i];
conn->tempsock[i] = CURL_SOCKET_BAD;
#ifdef ENABLE_IPV6
conn->bits.ipv6 = (conn->ip_addr->ai_family == AF_INET6)?TRUE:FALSE;
#endif
/* close the other socket, if open */
if(conn->tempsock[other] != CURL_SOCKET_BAD) {
Curl_closesocket(conn, conn->tempsock[other]);
conn->tempsock[other] = CURL_SOCKET_BAD;
}
/* see if we need to do any proxy magic first once we connected */
result = Curl_connected_proxy(conn, sockindex);
if(result)
return result;
conn->bits.tcpconnect[sockindex] = TRUE;
*connected = TRUE;
if(sockindex == FIRSTSOCKET)
Curl_pgrsTime(data, TIMER_CONNECT); /* connect done */
Curl_updateconninfo(conn, conn->sock[sockindex]);
Curl_verboseconnect(conn);
return CURLE_OK;
}
infof(data, "Connection failed\n");
}
else if(rc & CURL_CSELECT_ERR)
(void)verifyconnect(conn->tempsock[i], &error);
/*
* The connection failed here, we should attempt to connect to the "next
* address" for the given host. But first remember the latest error.
*/
if(error) {
data->state.os_errno = error;
SET_SOCKERRNO(error);
if(conn->tempaddr[i]) {
CURLcode status;
char ipaddress[MAX_IPADR_LEN];
char buffer[STRERROR_LEN];
Curl_printable_address(conn->tempaddr[i], ipaddress, MAX_IPADR_LEN);
infof(data, "connect to %s port %ld failed: %s\n",
ipaddress, conn->port,
Curl_strerror(error, buffer, sizeof(buffer)));
conn->timeoutms_per_addr = conn->tempaddr[i]->ai_next == NULL ?
allow : allow / 2;
status = trynextip(conn, sockindex, i);
if(status != CURLE_COULDNT_CONNECT
|| conn->tempsock[other] == CURL_SOCKET_BAD)
/* the last attempt failed and no other sockets remain open */
result = status;
}
}
}
if(result) {
/* no more addresses to try */
const char *hostname;
char buffer[STRERROR_LEN];
/* if the first address family runs out of addresses to try before
the happy eyeball timeout, go ahead and try the next family now */
if(conn->tempaddr[1] == NULL) {
result = trynextip(conn, sockindex, 1);
if(!result)
return result;
}
if(conn->bits.socksproxy)
hostname = conn->socks_proxy.host.name;
else if(conn->bits.httpproxy)
hostname = conn->http_proxy.host.name;
else if(conn->bits.conn_to_host)
hostname = conn->conn_to_host.name;
else
hostname = conn->host.name;
failf(data, "Failed to connect to %s port %ld: %s",
hostname, conn->port,
Curl_strerror(error, buffer, sizeof(buffer)));
}
return result;
}
static void tcpnodelay(struct connectdata *conn, curl_socket_t sockfd)
{
#if defined(TCP_NODELAY)
#if !defined(CURL_DISABLE_VERBOSE_STRINGS)
struct Curl_easy *data = conn->data;
#endif
curl_socklen_t onoff = (curl_socklen_t) 1;
int level = IPPROTO_TCP;
char buffer[STRERROR_LEN];
#if defined(CURL_DISABLE_VERBOSE_STRINGS)
(void) conn;
#endif
if(setsockopt(sockfd, level, TCP_NODELAY, (void *)&onoff,
sizeof(onoff)) < 0)
infof(data, "Could not set TCP_NODELAY: %s\n",
Curl_strerror(SOCKERRNO, buffer, sizeof(buffer)));
else
infof(data, "TCP_NODELAY set\n");
#else
(void)conn;
(void)sockfd;
#endif
}
#ifdef SO_NOSIGPIPE
/* The preferred method on Mac OS X (10.2 and later) to prevent SIGPIPEs when
sending data to a dead peer (instead of relying on the 4th argument to send
being MSG_NOSIGNAL). Possibly also existing and in use on other BSD
systems? */
static void nosigpipe(struct connectdata *conn,
curl_socket_t sockfd)
{
struct Curl_easy *data = conn->data;
int onoff = 1;
if(setsockopt(sockfd, SOL_SOCKET, SO_NOSIGPIPE, (void *)&onoff,
sizeof(onoff)) < 0) {
char buffer[STRERROR_LEN];
infof(data, "Could not set SO_NOSIGPIPE: %s\n",
Curl_strerror(SOCKERRNO, buffer, sizeof(buffer)));
}
}
#else
#define nosigpipe(x,y) Curl_nop_stmt
#endif
#ifdef USE_WINSOCK
/* When you run a program that uses the Windows Sockets API, you may
experience slow performance when you copy data to a TCP server.
https://support.microsoft.com/kb/823764
Work-around: Make the Socket Send Buffer Size Larger Than the Program Send
Buffer Size
The problem described in this knowledge-base is applied only to pre-Vista
Windows. Following function trying to detect OS version and skips
SO_SNDBUF adjustment for Windows Vista and above.
*/
#define DETECT_OS_NONE 0
#define DETECT_OS_PREVISTA 1
#define DETECT_OS_VISTA_OR_LATER 2
void Curl_sndbufset(curl_socket_t sockfd)
{
int val = CURL_MAX_WRITE_SIZE + 32;
int curval = 0;
int curlen = sizeof(curval);
static int detectOsState = DETECT_OS_NONE;
if(detectOsState == DETECT_OS_NONE) {
if(Curl_verify_windows_version(6, 0, PLATFORM_WINNT,
VERSION_GREATER_THAN_EQUAL))
detectOsState = DETECT_OS_VISTA_OR_LATER;
else
detectOsState = DETECT_OS_PREVISTA;
}
if(detectOsState == DETECT_OS_VISTA_OR_LATER)
return;
if(getsockopt(sockfd, SOL_SOCKET, SO_SNDBUF, (char *)&curval, &curlen) == 0)
if(curval > val)
return;
setsockopt(sockfd, SOL_SOCKET, SO_SNDBUF, (const char *)&val, sizeof(val));
}
#endif
/*
* singleipconnect()
*
* Note that even on connect fail it returns CURLE_OK, but with 'sock' set to
* CURL_SOCKET_BAD. Other errors will however return proper errors.
*
* singleipconnect() connects to the given IP only, and it may return without
* having connected.
*/
static CURLcode singleipconnect(struct connectdata *conn,
const Curl_addrinfo *ai,
curl_socket_t *sockp)
{
struct Curl_sockaddr_ex addr;
int rc = -1;
int error = 0;
bool isconnected = FALSE;
struct Curl_easy *data = conn->data;
curl_socket_t sockfd;
CURLcode result;
char ipaddress[MAX_IPADR_LEN];
long port;
bool is_tcp;
#ifdef TCP_FASTOPEN_CONNECT
int optval = 1;
#endif
char buffer[STRERROR_LEN];
*sockp = CURL_SOCKET_BAD;
result = Curl_socket(conn, ai, &addr, &sockfd);
if(result)
/* Failed to create the socket, but still return OK since we signal the
lack of socket as well. This allows the parent function to keep looping
over alternative addresses/socket families etc. */
return CURLE_OK;
/* store remote address and port used in this connection attempt */
if(!getaddressinfo((struct sockaddr*)&addr.sa_addr,
ipaddress, &port)) {
/* malformed address or bug in inet_ntop, try next address */
failf(data, "sa_addr inet_ntop() failed with errno %d: %s",
errno, Curl_strerror(errno, buffer, sizeof(buffer)));
Curl_closesocket(conn, sockfd);
return CURLE_OK;
}
infof(data, " Trying %s:%ld...\n", ipaddress, port);
#ifdef ENABLE_IPV6
is_tcp = (addr.family == AF_INET || addr.family == AF_INET6) &&
addr.socktype == SOCK_STREAM;
#else
is_tcp = (addr.family == AF_INET) && addr.socktype == SOCK_STREAM;
#endif
if(is_tcp && data->set.tcp_nodelay)
tcpnodelay(conn, sockfd);
nosigpipe(conn, sockfd);
Curl_sndbufset(sockfd);
if(is_tcp && data->set.tcp_keepalive)
tcpkeepalive(data, sockfd);
if(data->set.fsockopt) {
/* activate callback for setting socket options */
Curl_set_in_callback(data, true);
error = data->set.fsockopt(data->set.sockopt_client,
sockfd,
CURLSOCKTYPE_IPCXN);
Curl_set_in_callback(data, false);
if(error == CURL_SOCKOPT_ALREADY_CONNECTED)
isconnected = TRUE;
else if(error) {
Curl_closesocket(conn, sockfd); /* close the socket and bail out */
return CURLE_ABORTED_BY_CALLBACK;
}
}
/* possibly bind the local end to an IP, interface or port */
if(addr.family == AF_INET
#ifdef ENABLE_IPV6
|| addr.family == AF_INET6
#endif
) {
result = bindlocal(conn, sockfd, addr.family,
Curl_ipv6_scope((struct sockaddr*)&addr.sa_addr));
if(result) {
Curl_closesocket(conn, sockfd); /* close socket and bail out */
if(result == CURLE_UNSUPPORTED_PROTOCOL) {
/* The address family is not supported on this interface.
We can continue trying addresses */
return CURLE_COULDNT_CONNECT;
}
return result;
}
}
/* set socket non-blocking */
(void)curlx_nonblock(sockfd, TRUE);
conn->connecttime = Curl_now();
if(conn->num_addr > 1)
Curl_expire(data, conn->timeoutms_per_addr, EXPIRE_DNS_PER_NAME);
/* Connect TCP sockets, bind UDP */
if(!isconnected && (conn->socktype == SOCK_STREAM)) {
if(conn->bits.tcp_fastopen) {
#if defined(CONNECT_DATA_IDEMPOTENT) /* Darwin */
# if defined(HAVE_BUILTIN_AVAILABLE)
/* while connectx function is available since macOS 10.11 / iOS 9,
it did not have the interface declared correctly until
Xcode 9 / macOS SDK 10.13 */
if(__builtin_available(macOS 10.11, iOS 9.0, tvOS 9.0, watchOS 2.0, *)) {
sa_endpoints_t endpoints;
endpoints.sae_srcif = 0;
endpoints.sae_srcaddr = NULL;
endpoints.sae_srcaddrlen = 0;
endpoints.sae_dstaddr = &addr.sa_addr;
endpoints.sae_dstaddrlen = addr.addrlen;
rc = connectx(sockfd, &endpoints, SAE_ASSOCID_ANY,
CONNECT_RESUME_ON_READ_WRITE | CONNECT_DATA_IDEMPOTENT,
NULL, 0, NULL, NULL);
}
else {
rc = connect(sockfd, &addr.sa_addr, addr.addrlen);
}
# else
rc = connect(sockfd, &addr.sa_addr, addr.addrlen);
# endif /* HAVE_BUILTIN_AVAILABLE */
#elif defined(TCP_FASTOPEN_CONNECT) /* Linux >= 4.11 */
if(setsockopt(sockfd, IPPROTO_TCP, TCP_FASTOPEN_CONNECT,
(void *)&optval, sizeof(optval)) < 0)
infof(data, "Failed to enable TCP Fast Open on fd %d\n", sockfd);
else
infof(data, "TCP_FASTOPEN_CONNECT set\n");
rc = connect(sockfd, &addr.sa_addr, addr.addrlen);
#elif defined(MSG_FASTOPEN) /* old Linux */
if(conn->given->flags & PROTOPT_SSL)
rc = connect(sockfd, &addr.sa_addr, addr.addrlen);
else
rc = 0; /* Do nothing */
#endif
}
else {
rc = connect(sockfd, &addr.sa_addr, addr.addrlen);
}
if(-1 == rc)
error = SOCKERRNO;
}
else {
*sockp = sockfd;
return CURLE_OK;
}
if(-1 == rc) {
switch(error) {
case EINPROGRESS:
case EWOULDBLOCK:
#if defined(EAGAIN)
#if (EAGAIN) != (EWOULDBLOCK)
/* On some platforms EAGAIN and EWOULDBLOCK are the
* same value, and on others they are different, hence
* the odd #if
*/
case EAGAIN:
#endif
#endif
result = CURLE_OK;
break;
default:
/* unknown error, fallthrough and try another address! */
infof(data, "Immediate connect fail for %s: %s\n",
ipaddress, Curl_strerror(error, buffer, sizeof(buffer)));
data->state.os_errno = error;
/* connect failed */
Curl_closesocket(conn, sockfd);
result = CURLE_COULDNT_CONNECT;
}
}
if(!result)
*sockp = sockfd;
return result;
}
/*
* TCP connect to the given host with timeout, proxy or remote doesn't matter.
* There might be more than one IP address to try out. Fill in the passed
* pointer with the connected socket.
*/
CURLcode Curl_connecthost(struct connectdata *conn, /* context */
const struct Curl_dns_entry *remotehost)
{
struct Curl_easy *data = conn->data;
struct curltime before = Curl_now();
CURLcode result = CURLE_COULDNT_CONNECT;
timediff_t timeout_ms = Curl_timeleft(data, &before, TRUE);
if(timeout_ms < 0) {
/* a precaution, no need to continue if time already is up */
failf(data, "Connection time-out");
return CURLE_OPERATION_TIMEDOUT;
}
conn->num_addr = Curl_num_addresses(remotehost->addr);
conn->tempaddr[0] = remotehost->addr;
conn->tempaddr[1] = NULL;
conn->tempsock[0] = CURL_SOCKET_BAD;
conn->tempsock[1] = CURL_SOCKET_BAD;
/* Max time for the next connection attempt */
conn->timeoutms_per_addr =
conn->tempaddr[0]->ai_next == NULL ? timeout_ms : timeout_ms / 2;
/* start connecting to first IP */
while(conn->tempaddr[0]) {
result = singleipconnect(conn, conn->tempaddr[0], &(conn->tempsock[0]));
if(!result)
break;
conn->tempaddr[0] = conn->tempaddr[0]->ai_next;
}
if(conn->tempsock[0] == CURL_SOCKET_BAD) {
if(!result)
result = CURLE_COULDNT_CONNECT;
return result;
}
data->info.numconnects++; /* to track the number of connections made */
Curl_expire(conn->data, data->set.happy_eyeballs_timeout,
EXPIRE_HAPPY_EYEBALLS);
return CURLE_OK;
}
struct connfind {
struct connectdata *tofind;
bool found;
};
static int conn_is_conn(struct connectdata *conn, void *param)
{
struct connfind *f = (struct connfind *)param;
if(conn == f->tofind) {
f->found = TRUE;
return 1;
}
return 0;
}
/*
* Used to extract socket and connectdata struct for the most recent
* transfer on the given Curl_easy.
*
* The returned socket will be CURL_SOCKET_BAD in case of failure!
*/
curl_socket_t Curl_getconnectinfo(struct Curl_easy *data,
struct connectdata **connp)
{
DEBUGASSERT(data);
/* this works for an easy handle:
* - that has been used for curl_easy_perform()
* - that is associated with a multi handle, and whose connection
* was detached with CURLOPT_CONNECT_ONLY
*/
if(data->state.lastconnect && (data->multi_easy || data->multi)) {
struct connectdata *c = data->state.lastconnect;
struct connfind find;
find.tofind = data->state.lastconnect;
find.found = FALSE;
Curl_conncache_foreach(data, data->multi_easy?
&data->multi_easy->conn_cache:
&data->multi->conn_cache, &find, conn_is_conn);
if(!find.found) {
data->state.lastconnect = NULL;
return CURL_SOCKET_BAD;
}
if(connp) {
/* only store this if the caller cares for it */
*connp = c;
c->data = data;
}
return c->sock[FIRSTSOCKET];
}
else
return CURL_SOCKET_BAD;
}
/*
* Check if a connection seems to be alive.
*/
bool Curl_connalive(struct connectdata *conn)
{
/* First determine if ssl */
if(conn->ssl[FIRSTSOCKET].use) {
/* use the SSL context */
if(!Curl_ssl_check_cxn(conn))
return false; /* FIN received */
}
/* Minix 3.1 doesn't support any flags on recv; just assume socket is OK */
#ifdef MSG_PEEK
else if(conn->sock[FIRSTSOCKET] == CURL_SOCKET_BAD)
return false;
else {
/* use the socket */
char buf;
if(recv((RECV_TYPE_ARG1)conn->sock[FIRSTSOCKET], (RECV_TYPE_ARG2)&buf,
(RECV_TYPE_ARG3)1, (RECV_TYPE_ARG4)MSG_PEEK) == 0) {
return false; /* FIN received */
}
}
#endif
return true;
}
/*
* Close a socket.
*
* 'conn' can be NULL, beware!
*/
int Curl_closesocket(struct connectdata *conn,
curl_socket_t sock)
{
if(conn && conn->fclosesocket) {
if((sock == conn->sock[SECONDARYSOCKET]) &&
conn->sock_accepted[SECONDARYSOCKET])
/* if this socket matches the second socket, and that was created with
accept, then we MUST NOT call the callback but clear the accepted
status */
conn->sock_accepted[SECONDARYSOCKET] = FALSE;
else {
int rc;
Curl_multi_closed(conn->data, sock);
Curl_set_in_callback(conn->data, true);
rc = conn->fclosesocket(conn->closesocket_client, sock);
Curl_set_in_callback(conn->data, false);
return rc;
}
}
if(conn)
/* tell the multi-socket code about this */
Curl_multi_closed(conn->data, sock);
sclose(sock);
return 0;
}
/*
* Create a socket based on info from 'conn' and 'ai'.
*
* 'addr' should be a pointer to the correct struct to get data back, or NULL.
* 'sockfd' must be a pointer to a socket descriptor.
*
* If the open socket callback is set, used that!
*
*/
CURLcode Curl_socket(struct connectdata *conn,
const Curl_addrinfo *ai,
struct Curl_sockaddr_ex *addr,
curl_socket_t *sockfd)
{
struct Curl_easy *data = conn->data;
struct Curl_sockaddr_ex dummy;
if(!addr)
/* if the caller doesn't want info back, use a local temp copy */
addr = &dummy;
/*
* The Curl_sockaddr_ex structure is basically libcurl's external API
* curl_sockaddr structure with enough space available to directly hold
* any protocol-specific address structures. The variable declared here
* will be used to pass / receive data to/from the fopensocket callback
* if this has been set, before that, it is initialized from parameters.
*/
addr->family = ai->ai_family;
addr->socktype = conn->socktype;
addr->protocol = conn->socktype == SOCK_DGRAM?IPPROTO_UDP:ai->ai_protocol;
addr->addrlen = ai->ai_addrlen;
if(addr->addrlen > sizeof(addr->_sa_ex_u))
addr->addrlen = sizeof(addr->_sa_ex_u);
memcpy(&addr->_sa_ex_u, ai->ai_addr, addr->addrlen);
if(data->set.fopensocket) {
/*
* If the opensocket callback is set, all the destination address
* information is passed to the callback. Depending on this information the
* callback may opt to abort the connection, this is indicated returning
* CURL_SOCKET_BAD; otherwise it will return a not-connected socket. When
* the callback returns a valid socket the destination address information
* might have been changed and this 'new' address will actually be used
* here to connect.
*/
Curl_set_in_callback(data, true);
*sockfd = data->set.fopensocket(data->set.opensocket_client,
CURLSOCKTYPE_IPCXN,
(struct curl_sockaddr *)addr);
Curl_set_in_callback(data, false);
}
else
/* opensocket callback not set, so simply create the socket now */
*sockfd = socket(addr->family, addr->socktype, addr->protocol);
if(*sockfd == CURL_SOCKET_BAD)
/* no socket, no connection */
return CURLE_COULDNT_CONNECT;
#if defined(ENABLE_IPV6) && defined(HAVE_SOCKADDR_IN6_SIN6_SCOPE_ID)
if(conn->scope_id && (addr->family == AF_INET6)) {
struct sockaddr_in6 * const sa6 = (void *)&addr->sa_addr;
sa6->sin6_scope_id = conn->scope_id;
}
#endif
return CURLE_OK;
}
/*
* Curl_conncontrol() marks streams or connection for closure.
*/
void Curl_conncontrol(struct connectdata *conn,
int ctrl /* see defines in header */
#if defined(DEBUGBUILD) && !defined(CURL_DISABLE_VERBOSE_STRINGS)
, const char *reason
#endif
)
{
/* close if a connection, or a stream that isn't multiplexed */
bool closeit = (ctrl == CONNCTRL_CONNECTION) ||
((ctrl == CONNCTRL_STREAM) && !(conn->handler->flags & PROTOPT_STREAM));
if((ctrl == CONNCTRL_STREAM) &&
(conn->handler->flags & PROTOPT_STREAM))
DEBUGF(infof(conn->data, "Kill stream: %s\n", reason));
else if((bit)closeit != conn->bits.close) {
DEBUGF(infof(conn->data, "Marked for [%s]: %s\n",
closeit?"closure":"keep alive", reason));
conn->bits.close = closeit; /* the only place in the source code that
should assign this bit */
}
}
/* Data received can be cached at various levels, so check them all here. */
bool Curl_conn_data_pending(struct connectdata *conn, int sockindex)
{
int readable;
if(Curl_ssl_data_pending(conn, sockindex) ||
Curl_recv_has_postponed_data(conn, sockindex))
return true;
readable = SOCKET_READABLE(conn->sock[sockindex], 0);
return (readable > 0 && (readable & CURL_CSELECT_IN));
}
| YifuLiu/AliOS-Things | components/curl/lib/connect.c | C | apache-2.0 | 44,976 |
#ifndef HEADER_CURL_CONNECT_H
#define HEADER_CURL_CONNECT_H
/***************************************************************************
* _ _ ____ _
* Project ___| | | | _ \| |
* / __| | | | |_) | |
* | (__| |_| | _ <| |___
* \___|\___/|_| \_\_____|
*
* Copyright (C) 1998 - 2019, Daniel Stenberg, <daniel@haxx.se>, et al.
*
* This software is licensed as described in the file COPYING, which
* you should have received as part of this distribution. The terms
* are also available at https://curl.haxx.se/docs/copyright.html.
*
* You may opt to use, copy, modify, merge, publish, distribute and/or sell
* copies of the Software, and permit persons to whom the Software is
* furnished to do so, under the terms of the COPYING file.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
***************************************************************************/
#include "curl_setup.h"
#include "nonblock.h" /* for curlx_nonblock(), formerly Curl_nonblock() */
#include "sockaddr.h"
#include "timeval.h"
CURLcode Curl_is_connected(struct connectdata *conn,
int sockindex,
bool *connected);
CURLcode Curl_connecthost(struct connectdata *conn,
const struct Curl_dns_entry *host);
/* generic function that returns how much time there's left to run, according
to the timeouts set */
timediff_t Curl_timeleft(struct Curl_easy *data,
struct curltime *nowp,
bool duringconnect);
#define DEFAULT_CONNECT_TIMEOUT 300000 /* milliseconds == five minutes */
/*
* Used to extract socket and connectdata struct for the most recent
* transfer on the given Curl_easy.
*
* The returned socket will be CURL_SOCKET_BAD in case of failure!
*/
curl_socket_t Curl_getconnectinfo(struct Curl_easy *data,
struct connectdata **connp);
/*
* Check if a connection seems to be alive.
*/
bool Curl_connalive(struct connectdata *conn);
#ifdef USE_WINSOCK
/* When you run a program that uses the Windows Sockets API, you may
experience slow performance when you copy data to a TCP server.
https://support.microsoft.com/kb/823764
Work-around: Make the Socket Send Buffer Size Larger Than the Program Send
Buffer Size
*/
void Curl_sndbufset(curl_socket_t sockfd);
#else
#define Curl_sndbufset(y) Curl_nop_stmt
#endif
void Curl_updateconninfo(struct connectdata *conn, curl_socket_t sockfd);
void Curl_persistconninfo(struct connectdata *conn);
int Curl_closesocket(struct connectdata *conn, curl_socket_t sock);
/*
* The Curl_sockaddr_ex structure is basically libcurl's external API
* curl_sockaddr structure with enough space available to directly hold any
* protocol-specific address structures. The variable declared here will be
* used to pass / receive data to/from the fopensocket callback if this has
* been set, before that, it is initialized from parameters.
*/
struct Curl_sockaddr_ex {
int family;
int socktype;
int protocol;
unsigned int addrlen;
union {
struct sockaddr addr;
struct Curl_sockaddr_storage buff;
} _sa_ex_u;
};
#define sa_addr _sa_ex_u.addr
/*
* Create a socket based on info from 'conn' and 'ai'.
*
* Fill in 'addr' and 'sockfd' accordingly if OK is returned. If the open
* socket callback is set, used that!
*
*/
CURLcode Curl_socket(struct connectdata *conn,
const Curl_addrinfo *ai,
struct Curl_sockaddr_ex *addr,
curl_socket_t *sockfd);
/*
* Curl_conncontrol() marks the end of a connection/stream. The 'closeit'
* argument specifies if it is the end of a connection or a stream.
*
* For stream-based protocols (such as HTTP/2), a stream close will not cause
* a connection close. Other protocols will close the connection for both
* cases.
*
* It sets the bit.close bit to TRUE (with an explanation for debug builds),
* when the connection will close.
*/
#define CONNCTRL_KEEP 0 /* undo a marked closure */
#define CONNCTRL_CONNECTION 1
#define CONNCTRL_STREAM 2
void Curl_conncontrol(struct connectdata *conn,
int closeit
#if defined(DEBUGBUILD) && !defined(CURL_DISABLE_VERBOSE_STRINGS)
, const char *reason
#endif
);
#if defined(DEBUGBUILD) && !defined(CURL_DISABLE_VERBOSE_STRINGS)
#define streamclose(x,y) Curl_conncontrol(x, CONNCTRL_STREAM, y)
#define connclose(x,y) Curl_conncontrol(x, CONNCTRL_CONNECTION, y)
#define connkeep(x,y) Curl_conncontrol(x, CONNCTRL_KEEP, y)
#else /* if !DEBUGBUILD || CURL_DISABLE_VERBOSE_STRINGS */
#define streamclose(x,y) Curl_conncontrol(x, CONNCTRL_STREAM)
#define connclose(x,y) Curl_conncontrol(x, CONNCTRL_CONNECTION)
#define connkeep(x,y) Curl_conncontrol(x, CONNCTRL_KEEP)
#endif
bool Curl_conn_data_pending(struct connectdata *conn, int sockindex);
#endif /* HEADER_CURL_CONNECT_H */
| YifuLiu/AliOS-Things | components/curl/lib/connect.h | C | apache-2.0 | 5,115 |