content stringlengths 1 1.04M ⌀ |
|---|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
ELSE
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
ELSE
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
-------------------------------------------------------------------------------
-- Title : Top Level Test Bench
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : tb_top.vhd
-- Created : 2016-02-22
-- Last update: 2016-02-22
-- Sta... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:35 2019
-- Host : varun-laptop running 64-bit Serv... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Gigabits buffer with the differential signals.
----------------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Gigabits buffer with the differential signals.
----------------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Gigabits buffer with the differential signals.
----------------------------------------------------------------------... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
-- $Id: serport_2clock.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
entity ieee4 is
end entity;
library ieee;
use ieee.math_real.all;
architecture test of ieee4 is
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
begin
process is
variable s1, s2 : integer;
variable r : real;
beg... |
entity ieee4 is
end entity;
library ieee;
use ieee.math_real.all;
architecture test of ieee4 is
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
begin
process is
variable s1, s2 : integer;
variable r : real;
beg... |
-- NEED RESULT: ARCH00401.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00401: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00401: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00401: One i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
--Módulo para contador de programa PC
--Declaracao de bibliotecas
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PC is
generic (DATA_WIDTH : natural := 32); --ULA faz operacoes com dados de 32 bits
port (
clk, rst : in std_logic;
add_in: in std_logic_vector(DATA_WIDTH-1 ... |
--Módulo para contador de programa PC
--Declaracao de bibliotecas
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PC is
generic (DATA_WIDTH : natural := 32); --ULA faz operacoes com dados de 32 bits
port (
clk, rst : in std_logic;
add_in: in std_logic_vector(DATA_WIDTH-1 ... |
-------------------------------------------------------------------------------
-- Title : 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : types_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization:... |
-------------------------------------------------------------------------------
-- Title : 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : types_pkg.vhd
-- Author : susanne.reinfelder@men.de
-- Organization:... |
package types_pkg is
type generic_type is array(0 to 3) of integer;
end package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity scharr_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in s... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Perform (right-)shift and add multiplication.
--------------------------------------------------------------------------------
library ieee;
... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_topentity_0 is
port(i : in packetprocessordf_types.tup2;
-- clock
... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_topentity_0 is
port(i : in packetprocessordf_types.tup2;
-- clock
... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:00 2017
-- Host : DarkCube running 64-bit major re... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest(fum)
port map (
a => a,
... |
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest(fum)
port map (
a => a,
... |
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest(fum)
port map (
a => a,
... |
entity portlisttest is
port (
signal a: in bit;
signal b: out bit
);
end entity;
entity portlisttest is
end entity;
architecture foo of portlisttest is
signal a: bit;
signal b: bit;
begin
DUT:
entity work.portlisttest(fum)
port map (
a => a,
... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor co... |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
-- PSHDL is a library and (trans-)compiler for PSHDL input. It generates
-- output suitable for implementation or simulation of it.
--
-- Copyright (C) 2013 Karsten Becker (feedback (at) pshdl (dot) org)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the term... |
-- Generic size register made with D Flip Flops
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Generic_register IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector... |
library verilog;
use verilog.vl_types.all;
entity F2AB is
generic(
WIDTH : integer := 32;
DAC_RESOLUTION : vl_logic_vector(5 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
ANALOG_QUAD_NUM : integer := 6... |
library verilog;
use verilog.vl_types.all;
entity F2AB is
generic(
WIDTH : integer := 32;
DAC_RESOLUTION : vl_logic_vector(5 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
ANALOG_QUAD_NUM : integer := 6... |
library verilog;
use verilog.vl_types.all;
entity F2AB is
generic(
WIDTH : integer := 32;
DAC_RESOLUTION : vl_logic_vector(5 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
WARNING_MSGS_ON : integer := 1;
FAST_ADC_CONV_SIM: integer := 0;
ANALOG_QUAD_NUM : integer := 6... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_endpoint_eval_in_vhdl is
end entity psl_endpoint_eval_in_vhdl;
architecture test of psl_endpoint_eval_in_vhdl is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_wri... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_endpoint_eval_in_vhdl is
end entity psl_endpoint_eval_in_vhdl;
architecture test of psl_endpoint_eval_in_vhdl is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_wri... |
-------------------------------------------------------------------------------
--
-- T400 Microcontroller Core
--
-- $Id: t400_core-c.vhd,v 1.3 2006-05-22 00:03:29 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
--------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- Title : sfh
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:33 11/30/2015
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-- $Id: sys_w11a_n4.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n4 - syn
-- Description: w11a tes... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- system_v_tc_vid_out_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00520
--
-- AUTHOR:
--
-- A. Wilm... |
--HIDE_STR entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY HIDE_STR IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN... |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux2_1Demo is
port( SW : in STD_LOGIC_VECTOR(3 downto 0);
KEY : in STD_LOGIC_VECTOR(3 downto 2);
LEDR : out STD_LOGIC_VECTOR(0 downto 0));
end Mux2_1Demo;
Architecture Shell of Mux2_1Demo is
begin
system_core: entity work.Mux2_1(BehavProcess)
port map... |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux2_1Demo is
port( SW : in STD_LOGIC_VECTOR(3 downto 0);
KEY : in STD_LOGIC_VECTOR(3 downto 2);
LEDR : out STD_LOGIC_VECTOR(0 downto 0));
end Mux2_1Demo;
Architecture Shell of Mux2_1Demo is
begin
system_core: entity work.Mux2_1(BehavProcess)
port map... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights rese... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END ENTITY mux;
ARCHITECTURE Behavior OF mux IS
SIGNAL Qs : STD_LOGIC_VECTOR(N-1 DOWNTO ... |
-------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_40_a;
use micr... |
-- Gray_Processing_GN_Gray_Processing_Gray_Processing_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:14:00
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
port (
eop : in std_logic ... |
-- Gray_Processing_GN_Gray_Processing_Gray_Processing_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:14:00
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
port (
eop : in std_logic ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_quant_tbl_no is
port (
wa0_data : in std_logic_vector(1 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:35:03 05/28/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_screen_position_gen.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
-- This is one layer of a neural network
-- It contains several neurons that process input frames
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
entity nnlayer is
generic (
-- Parameters for the neurons
WDATA : natural := 16;
WWEIGHT : natural := 16;
WACC... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY LCD_MOD IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
PC : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
KEYB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
H_STATE : IN STD_LOGIC;
LCD_DATA : OUT STD_LOGIC... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY LCD_MOD IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
PC : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
KEYB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
H_STATE : IN STD_LOGIC;
LCD_DATA : OUT STD_LOGIC... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY LCD_MOD IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
PC : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
KEYB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
H_STATE : IN STD_LOGIC;
LCD_DATA : OUT STD_LOGIC... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 12-02-2016
-- Module Name: sr-latch.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity addern is
generic(
width : integer := 8
);
port(
A, B : in std_logic_vector(width - 1 downto 0);
Y : out std_logic_vector(width - 1 downto 0)
);
end addern;
architecture bhv of addern is
begin
Y <= A + B;
end bhv;
Libra... |
-- Controller implementation for the IS61LV25616-10 memory
-- Copyright erik@zachrisson.info 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity SramController is
generic (
AddrW : positive := 18;
DataW : positive := 16
... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Added these lines on rev. 42 in order to remove the commit message saying that
-- there is a bug in the implementation, since the bug has been fixed in the same rev.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity node_port_writermux is
Port ( I_portID : in STD_LOGIC_VECTOR (2 downto 0);
I_isD... |
-- NEED RESULT: ARCH00622: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00622.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00622: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00622: One transport transaction occurred on a concurrent signal asg passed
-- NEE... |
-- VHDL Entity lab11_MemoryArbiter_lib.MemoryArbiter.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 02:31:01 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY MemoryArbiter IS
POR... |
--------------------------------------------------------------------------
-- uart.vhd
-- Simple RS232 like uart tx/rx design
-- Does not handle any flow control.
-- Does not perform any meaning full buffering.
--
-- Peter Fetterer <kb3gtn@gmail.com>
---------------------------------------------------------------------... |
--------------------------------------------------------------------------
-- uart.vhd
-- Simple RS232 like uart tx/rx design
-- Does not handle any flow control.
-- Does not perform any meaning full buffering.
--
-- Peter Fetterer <kb3gtn@gmail.com>
---------------------------------------------------------------------... |
--------------------------------------------------------------------------
-- uart.vhd
-- Simple RS232 like uart tx/rx design
-- Does not handle any flow control.
-- Does not perform any meaning full buffering.
--
-- Peter Fetterer <kb3gtn@gmail.com>
---------------------------------------------------------------------... |
-- $Id: sys_conf1.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst... |
entity sub1 is
end entity;
architecture a of sub1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
-------------------------------------------------------------------------------
... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.