content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:19:54 10/27/2009
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
... |
entity tb_rec02 is
end tb_rec02;
library ieee;
use ieee.std_logic_1164.all;
use work.rec02_pkg.all;
architecture behav of tb_rec02 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec02
port map (inp => inp, o => r);
process
begin
inp.a <= 5;
inp.b <= '1';
wait for 1 ns;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic ( use_else_output : natural := 0;
bwr : natural :... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:11 04/07/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/Project1/Fetch_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versio... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_DUMMY is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector(DATA_WIDTH-1 downto... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_DUMMY is
port (
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector(DATA_WIDTH-1 downto... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilin... |
----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty E... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- $Id: xbic_dbeat_control.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_dbeat_control.vhd
-------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- channel.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE C... |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : dp_bank_sdp_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- $Id: rgbdrv_3x2mux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_3x2mux - syn
-- Description: rgbled ... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_204;
architecture augh of cmp_204 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_204;
architecture augh of cmp_204 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
use work.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i... |
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity DPATH is
port(
EN: in std_logic;
--operation type
OT: in std_logic_vector(2 downto 0);
--operand
OP1: in std_logic_vector(7 downto 0);
RES: out std_logic_vector(7 downto 0);
--zero flag
ZF:... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------
-- Datapath : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 20/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Datapath is
port (
clock, reset : in std_logic; -- clock and reset... |
-- ======================================================================
-- DES encryption/decryption
-- package file with functions
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-... |
-- a, b, c and d are the inputs
-- sel is the input selection
-- z is the output
ENTITY mux4x1 IS
PORT (a: IN std_logic;
b: IN std_logic;
c: IN std_logic;
d: IN std_logic;
z: OUT std_logic;
sel: IN std_logic_vector(1 DOWNTO 0));
END mux4x1;
ARCHITECTURE rtl of ... |
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- ... |
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 13:29:42 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity multiplexer_4x8 is
generic (
N: natural := 8; -- bits in in/out signals
M: natural := 2); -- bits in select
port (
mux_inp0: in std_logic_vector(N-1 downto 0);
mux_inp1: in std_lo... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:10:36 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
... |
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
... |
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
... |
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
... |
entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target D... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target D... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target D... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 17:13:00 11/14/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_mulitplexer.vhd
-- Project Name: idea_rcs1
-- Target D... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY Adder_TEST IS
END Adder_TEST;
ARCHITECTURE behavior OF Adder_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder
PORT(
CarryIn : IN unsigned(3 downto 0);
A : IN unsigned(3 downto 0)... |
-- multiple1902 <multple1902@gmail.com>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (op : in std_logic_vector(3 downto 0);
clk : in std_logic;
result : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end decoder;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity stack is
Port ( clk, reset : in STD_LOGIC;
push, pop : in STD_LOGIC;
pcin : in STD_LOGIC_VECTOR (12 downto 0);
pcout : out STD_LOGIC_VECTOR (12 downto 0));
end stack;
architecture ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:56:19 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/mips_simu.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Te... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:56:19 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/mips_simu.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Te... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
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