content stringlengths 1 1.04M ⌀ |
|---|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block6.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
-------------------------------------------------------------------------------
-- system_led_pwm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library led_pwm_v1_01_a;
use led_pwm_v1... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:08:19 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by M... |
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler is
generic(
PERIOD:natural := 1000000 --1MHz
);
port(
clk: in std_logic;
rst: in std_logic;
enabler_out: out std_logic
);
end;
architecture generic_enabler_arq of generic_enabler is
component generic_counter is
gene... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu2register_reg is
port(
clk, rst : in std_logic;
raddr_in : in std_logic_vector(3 downto 0);
op_in : in std_logic_vector(1 downto 0);
result_in : in std_logic_vector(7 downto 0);
reg... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Sep 27 18:05:22 2017
-- Host : vldmr-PC running 64-bit Service ... |
--LSB_DETECT entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY LSB_DETECT IS
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
RESULT: OUT STD_LOGIC_VECTOR(... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 18:14:28 2015
-- Host : Vangelis-PC running 64-bit major rel... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Thu Aug 24 05:36:23 2017
-- Host : ACER-BLUES running 64-bit major rele... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if val... |
entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if val... |
entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if val... |
entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if val... |
entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if val... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end GENERATE;
IF_LABEL : if a = '1' generate
end GEN... |
library ieee;
use ieee.std_logic_1164.all;
entity dec3to8 is
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end dec3to8;
architecture Behavior of dec3to8 is
begin
process (W, En)
begin
if En = '1' then
case W is
when "000" => Y <= "10000000";
w... |
library ieee;
use ieee.std_logic_1164.all;
entity dec3to8 is
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end dec3to8;
architecture Behavior of dec3to8 is
begin
process (W, En)
begin
if En = '1' then
case W is
when "000" => Y <= "10000000";
w... |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eithe... |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eithe... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
architecture rtl of fifo is
alias designator : subtype_indication is name;
alias designator : subtype_indication is name;
alias designator : subtype_indication is name;
begin
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2015/03/01 00:47:15
-- Design Name:
-- Module Name: simrom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- R... |
-- Automatically generated: write_netlist -wrapapp -vhdl -architecture reconflogic-wrapadt7310-a.vhd
architecture WrapADT7310 of MyReconfigLogic is
component ADT7310
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
ADT7310CS... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
library verilog;
use verilog.vl_types.all;
entity counter is
generic(
CTR_LEN : integer := 27
);
port(
clk : in vl_logic;
rst : in vl_logic;
value : out vl_logic_vector(7 downto 0)
);
attribute mti_svvh_generic_type... |
-- -------------------------------------------------------------
--
-- Entity Declaration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-e... |
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retai... |
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retai... |
entity array4 is
end entity;
architecture test of array4 is
type ma_t is array (1 downto 0, 7 downto 0) of bit_vector(7 downto 0);
signal ma : ma_t;
begin
process is
begin
ma <= (others => (others => (others => '0')));
wait for 1 ns;
assert ma(1, 2) = X"00";
wait;
e... |
entity array4 is
end entity;
architecture test of array4 is
type ma_t is array (1 downto 0, 7 downto 0) of bit_vector(7 downto 0);
signal ma : ma_t;
begin
process is
begin
ma <= (others => (others => (others => '0')));
wait for 1 ns;
assert ma(1, 2) = X"00";
wait;
e... |
entity array4 is
end entity;
architecture test of array4 is
type ma_t is array (1 downto 0, 7 downto 0) of bit_vector(7 downto 0);
signal ma : ma_t;
begin
process is
begin
ma <= (others => (others => (others => '0')));
wait for 1 ns;
assert ma(1, 2) = X"00";
wait;
e... |
entity array4 is
end entity;
architecture test of array4 is
type ma_t is array (1 downto 0, 7 downto 0) of bit_vector(7 downto 0);
signal ma : ma_t;
begin
process is
begin
ma <= (others => (others => (others => '0')));
wait for 1 ns;
assert ma(1, 2) = X"00";
wait;
e... |
entity array4 is
end entity;
architecture test of array4 is
type ma_t is array (1 downto 0, 7 downto 0) of bit_vector(7 downto 0);
signal ma : ma_t;
begin
process is
begin
ma <= (others => (others => (others => '0')));
wait for 1 ns;
assert ma(1, 2) = X"00";
wait;
e... |
entity func11 is
end entity;
architecture test of func11 is
function foo(x : integer) return integer is
begin
return x + 1;
end function;
function foo(x : integer) return real is
begin
return real(x) + 1.0;
end function;
begin
process is
begin
assert foo(1) =... |
entity func11 is
end entity;
architecture test of func11 is
function foo(x : integer) return integer is
begin
return x + 1;
end function;
function foo(x : integer) return real is
begin
return real(x) + 1.0;
end function;
begin
process is
begin
assert foo(1) =... |
entity func11 is
end entity;
architecture test of func11 is
function foo(x : integer) return integer is
begin
return x + 1;
end function;
function foo(x : integer) return real is
begin
return real(x) + 1.0;
end function;
begin
process is
begin
assert foo(1) =... |
entity func11 is
end entity;
architecture test of func11 is
function foo(x : integer) return integer is
begin
return x + 1;
end function;
function foo(x : integer) return real is
begin
return real(x) + 1.0;
end function;
begin
process is
begin
assert foo(1) =... |
entity func11 is
end entity;
architecture test of func11 is
function foo(x : integer) return integer is
begin
return x + 1;
end function;
function foo(x : integer) return real is
begin
return real(x) + 1.0;
end function;
begin
process is
begin
assert foo(1) =... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk_in : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk_in : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk_in : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk_in : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal de... |
-------------------------------------------------------------------------------
-- Title : Interface for Microchip AD7266 (ADC)
-- Project : Loa
-------------------------------------------------------------------------------
-- Description: Interface to Microchip's 12 channel 12-bit ADC (AD7266).
--
-- ... |
-------------------------------------------------------------------------------
-- Title : Interface for Microchip AD7266 (ADC)
-- Project : Loa
-------------------------------------------------------------------------------
-- Description: Interface to Microchip's 12 channel 12-bit ADC (AD7266).
--
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Thibault Bailly
--
-- create date: 07-03-2017
-- design name:
-- module name: generic_Detect_Rising_Edge
-- description: Generic Detect Rising Edge
--
-- dependencies:
--
-- revision: Initial release
--
-- additional comments:
--
... |
------------------------------------------------------------------------------
-- Title : Position Calcualtion Error Counters
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2014-01-13
-- Platform : ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library verilog;
use verilog.vl_types.all;
entity Apod is
port(
address : in vl_logic_vector(10 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(63 downto 0)
);
end Apod;
|
library verilog;
use verilog.vl_types.all;
entity Apod is
port(
address : in vl_logic_vector(10 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(63 downto 0)
);
end Apod;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Auth... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Auth... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Auth... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Auth... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PRBS_tb IS
END PRBS_tb;
ARCHITECTURE behavior OF PRBS_tb IS
COMPONENT PRBS
PORT(
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
rand : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
... |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Component declarations for Viterbi decoder
--! @author Markus Fehrenz
--! @date 2011/04/07
--!
--!
l... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:15 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module converts a 16 bit burst into 32 bits for reads,
-- and vice ve... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module converts a 16 bit burst into 32 bits for reads,
-- and vice ve... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module converts a 16 bit burst into 32 bits for reads,
-- and vice ve... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module converts a 16 bit burst into 32 bits for reads,
-- and vice ve... |
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module converts a 16 bit burst into 32 bits for reads,
-- and vice ve... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.Display_Management_pkg.all;
entity Display_Management is --=====================================================================
generic(
enable_debug : boolean := true;
resolution : string := "1920x1080@60Hz"
)... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 25-04-2016
-- Module Name: p5.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:32:05 11/08/2013
-- Design Name:
-- Module Name: Divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the follow... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_aa
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autoge... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- ACLK : Synchronous clock
-- ARESETN : System reset, active low
-- S_AXIS_TREADY : Ready to accept data in
-- S_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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