content stringlengths 1 1.04M ⌀ |
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-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(v... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.core_defs.all;
entity register_sp is
port
(
clk : in std_logic; -- Clock signal
reset : in std_logic; -- Reset signal
we_sp : in std_logic; -- write enab... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package pack is
type r1 is record
x : integer;
y : character;
end record;
type r1_vec is array (natural range <>) of r1;
type r2 is record
p : r1;
q : r1_vec(1 to 2);
end record;
type r2_vec is array (natural range <>) of r2;
end package;
-------------------... |
-- $Id: sys_conf.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_break is
port(
clk : in vl_logic;
dbrk_break : in vl_logic;
dbrk_goto0 : in vl_logic;
dbrk_goto1 : in vl_logic;
jdo : in vl_logic_vector(37 ... |
-------------------------------------------------------------------------------
--
-- Testbench for the
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: tb-c.vhd,v 1.2 2004-10-10 17:27:36 arniml Exp $
--
------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:38:29 11/20/2013
-- Design Name:
-- Module Name: CSA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
-- Violation below
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
end a... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity registerFile_tb is
end registerFile_tb;
architecture behv of registerFile_tb is
component register_file
port (
clk : in std_logic;
data : in std_logic_vector (31 downto 0);
reg_write : in std_logic_vector(4... |
-------------------------------------------------------------------------------------
-- FILE NAME : performance.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - toplevel_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity compar_tb is
end entity;
architecture behav of compar_tb is
component compar is
port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
so_a : out std_logic;
so_b : out std_logic
);
end com... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:58:35 12/03/2017
-- Design Name:
-- Module Name: Barra2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
library verilog;
use verilog.vl_types.all;
entity InstrucDecoder is
generic(
nop : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi1, Hi0, Hi0);
add : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
sub : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 ... |
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
--------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity tb_concat01 is
end tb_concat01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_concat01 is
signal a : std_logic_vector(15 downto 0);
begin
dut: entity work.concat01
port map (a);
process
begin
wait for 1 ns;
assert a = x"ab9e" severity failure;
wait;
end process... |
entity FIFO is
generic (
G_GEN1 : std_logic,
G_GEN2 : std_logic_vector(3 downto 0),
G_GEN3 : integer,
G_GEN4 : signed(15 downto 0),
G_GEN5 : unsigned(7 downto 0)
);
port (
I_PORT1 : in integer;
I_PORT2 : in std_logic;
I_PORTA : in t_user2;
I_PORT3 : in std_logic_vector(3 down... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely -... |
-- $Id: pdp11_sequencer.vhd 1321 2022-11-24 15:06:47Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sequencer - syn
-- Description: ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_... |
-------------------------------------------------------------------------------
--! @file alteraHostInterface.vhd
--
--! @brief toplevel of host interface for Altera FPGA
--
--! @details This toplevel interfaces to Altera specific implementation.
--
----------------------------------------------------------------------... |
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:01 2017
-- Host : GILAMONSTER running 64-bit major rel... |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
-- NEED RESULT: ARCH00699: Formal generics with default expression may be left unassociated in an association list passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------... |
-------------------------------------------------------------------------------
-- Title : u2p_dut
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Toplevel for u2p_dut.
------------------------------------... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00466
--
-- AUTHOR:
--
-- G. Tomi... |
library verilog;
use verilog.vl_types.all;
entity HexDriver is
port(
In0 : in vl_logic_vector(3 downto 0);
Out0 : out vl_logic_vector(6 downto 0)
);
end HexDriver;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
library verilog;
use verilog.vl_types.all;
entity flexible_lvds_tx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_input: string := "ON";
use_new_coreclk_ckt: string := "FALSE";
outclock_multiply_by: integer := 1;
outcl... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sserial is
Port ( address : in STD_LOGIC_VECTOR (7 downto 0);
data : inout STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
read : in STD_LOGIC;
wr... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 8
);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(N-1 downto 0);
IRQ1, IRQ2 : out std_logic... |
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_tdp is
generic(
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 9
);
port(
-- Port A
a_clk : in std_logic;
a_we : in std_logic;
a... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer :=... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_SVT : integer := CONFIG_IU... |
-- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_SVT : integer := CONFIG_IU... |
-- $Id: s7_cmt_sfs_2_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs_2 - syn
-- Description: Ser... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_log... |
--!
--! Simple PWM generator
--!
--! PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--!
--! Example:
--! clk = 50 MHz
--! clk_en = constant '1' (no prescaler)
--! width = 8 => value = 0..255
--!
--! => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
--!
--! Value (for width = 8):
--! 0 =>... |
--!
--! Simple PWM generator
--!
--! PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--!
--! Example:
--! clk = 50 MHz
--! clk_en = constant '1' (no prescaler)
--! width = 8 => value = 0..255
--!
--! => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
--!
--! Value (for width = 8):
--! 0 =>... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--- 0 1 2 | Q W E
--- 3 4 5 | A S D
--- 6 7 8 | Z X C
entity board_dec is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
char : in std_logic_vector(6 downto 0);
single_0 :... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_duo.vhf
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
EN... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:33:05 07/07/2015
-- Design Name:
-- Module Name: OFDM_ESTyEQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY pala IS
GENERIC (
DEFAULT_POS_X : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 10)
);
PORT (
-- Puertos para dibujado
vert_sync : IN STD_LOGIC;
... |
-- NEED RESULT: *** An assertion follows with severity level FAILURE
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------... |
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1987
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <R... |
library verilog;
use verilog.vl_types.all;
entity altmult_accum is
generic(
width_a : integer := 2;
width_b : integer := 2;
width_c : integer := 22;
width_result : integer := 5;
number_of_multipliers: integer := 1;
input_reg_a : string ... |
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-- -------------------------------------------------------------
--
-- Entity Declaration for clkgen
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity assert5 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
clk : std_logic;
rst : std_logic;
res : out std_logic);
end;
architecture behav of assert5 is
begin
process (clk, rst)
begin
if rst = '1' then
res <= '0... |
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