content stringlengths 1 1.04M ⌀ |
|---|
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
-- Do round
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
wait;
end process;
END;
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Clock edge detector
-- -----------------------------------------------------------------------
-- emuclk - Emulation clock
-- edge - Which edge to detect 0 is falling, 1 is rising
-- d - Input signal to sample
-- ena - One clock high when edge has been detected
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_edge is
port (
emuclk : in std_logic;
edge: in std_logic;
d : in ttl_t;
ena : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of ttl_edge is
signal d_dly : std_logic := '0';
begin
ena <=
'1' when edge = '0' and is_low(d) and d_dly = '1' else
'1' when edge = '1' and is_high(d) and d_dly = '0' else
'0';
process(emuclk)
begin
if rising_edge(emuclk) then
d_dly <= ttl2std(d);
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.core_defs.all;
entity register_sp is
port
(
clk : in std_logic; -- Clock signal
reset : in std_logic; -- Reset signal
we_sp : in std_logic; -- write enable
in_sp : in std_logic_vector (data_bits-1 downto 0); -- data input
out_sp : out std_logic_vector (data_bits-1 downto 0) -- Operand A port read
);
end register_sp;
architecture register_sp_impl of register_sp is
signal sp_reg : std_logic_vector (data_bits-1 downto 0);
begin
process(clk,reset) begin
if reset = '0' then
sp_reg <= others => '0';
elsif rising_edge(clk) and we_esp = '1' then
sp_reg <= in_sp;
end if;
end process;
process(all)
begin
out_sp <= sp_reg;
end process;
end register_sp_impl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1252.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01252ent IS
END c08s02b00x00p04n02i01252ent;
ARCHITECTURE c08s02b00x00p04n02i01252arch OF c08s02b00x00p04n02i01252ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
assert FALSE
report "Report this Note"
severity k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01252 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01252arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1252.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01252ent IS
END c08s02b00x00p04n02i01252ent;
ARCHITECTURE c08s02b00x00p04n02i01252arch OF c08s02b00x00p04n02i01252ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
assert FALSE
report "Report this Note"
severity k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01252 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01252arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1252.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01252ent IS
END c08s02b00x00p04n02i01252ent;
ARCHITECTURE c08s02b00x00p04n02i01252arch OF c08s02b00x00p04n02i01252ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
assert FALSE
report "Report this Note"
severity k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01252 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01252arch;
|
package pack is
type r1 is record
x : integer;
y : character;
end record;
type r1_vec is array (natural range <>) of r1;
type r2 is record
p : r1;
q : r1_vec(1 to 2);
end record;
type r2_vec is array (natural range <>) of r2;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in r2;
y : out r2_vec(1 to 3) );
end entity;
architecture test of sub is
begin
p1: process is
begin
wait for 1 ns;
assert x = ( ( 1, '2' ), ( ( 3, '4' ), ( 5, '6' ) ) );
y(3) <= ( ( 7, 'a' ), ( ( 8, 'b' ), ( 9, 'c' ) ) );
wait on x;
assert x = ( ( 1, '2' ), ( ( 42, '4' ), ( 5, '6' ) ) );
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record22 is
end entity;
use work.pack.all;
architecture test of record22 is
signal s : r2;
signal t : r2_vec(1 to 3);
begin
uut: entity work.sub port map ( s, t );
main: process is
begin
s <= ( ( 1, '2' ), ( ( 3, '4' ), ( 5, '6' ) ) );
wait for 2 ns;
assert t(3) = ( ( 7, 'a' ), ( ( 8, 'b' ), ( 9, 'c' ) ) );
s.q(1).x <= 42;
wait;
end process;
end architecture;
|
-- $Id: sys_conf.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_atlys (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-06 472 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_break is
port(
clk : in vl_logic;
dbrk_break : in vl_logic;
dbrk_goto0 : in vl_logic;
dbrk_goto1 : in vl_logic;
jdo : in vl_logic_vector(37 downto 0);
jrst_n : in vl_logic;
reset_n : in vl_logic;
take_action_break_a: in vl_logic;
take_action_break_b: in vl_logic;
take_action_break_c: in vl_logic;
take_no_action_break_a: in vl_logic;
take_no_action_break_b: in vl_logic;
take_no_action_break_c: in vl_logic;
xbrk_goto0 : in vl_logic;
xbrk_goto1 : in vl_logic;
break_readreg : out vl_logic_vector(31 downto 0);
dbrk_hit0_latch : out vl_logic;
dbrk_hit1_latch : out vl_logic;
dbrk_hit2_latch : out vl_logic;
dbrk_hit3_latch : out vl_logic;
trigbrktype : out vl_logic;
trigger_state_0 : out vl_logic;
trigger_state_1 : out vl_logic;
xbrk_ctrl0 : out vl_logic_vector(7 downto 0);
xbrk_ctrl1 : out vl_logic_vector(7 downto 0);
xbrk_ctrl2 : out vl_logic_vector(7 downto 0);
xbrk_ctrl3 : out vl_logic_vector(7 downto 0)
);
end finalproject_cpu_nios2_oci_break;
|
-------------------------------------------------------------------------------
--
-- Testbench for the
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: tb-c.vhd,v 1.2 2004-10-10 17:27:36 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_behav_c0 of tb is
for behav
for basic_b : gcpad_basic
use configuration work.gcpad_basic_struct_c0;
end for;
for full_b : gcpad_full
use configuration work.gcpad_full_struct_c0;
end for;
for all : gcpad_mod
use configuration work.gcpad_mod_behav_c0;
end for;
end for;
end tb_behav_c0;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:38:29 11/20/2013
-- Design Name:
-- Module Name: CSA8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CSA8 is
generic (width : integer := 32);
Port ( a : in STD_LOGIC_VECTOR (width-1 downto 0);
b : in STD_LOGIC_VECTOR (width-1 downto 0);
o : out STD_LOGIC_VECTOR (width-1 downto 0);
cout : out STD_LOGIC);
end CSA8;
architecture Behavioral of CSA8 is
component HalfAdder
port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end component;
component ResultGen
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out PairT;
c : out PairT);
end component;
component Selector
generic (
num_sum: integer := 0;
num_buffer: integer := 0
);
Port ( cIn : in PairT;
cSel : in PairT;
cOut : out PairT;
sumIn : in PairArr(num_sum downto 0);
sumOut : out PairArr(num_sum downto 0);
bufferIn: in PairArr(num_buffer downto 0);
bufferOut:out PairArr(num_buffer downto 0));
end component;
component SelectorLSB
generic (
num_sum: integer := 0
);
Port ( cIn : in PairT;
cSel : in std_logic;
cOut : out std_logic;
sumIn : in PairArr(num_sum downto 0);
sumOut : out std_logic_vector(num_sum downto 0));
end component;
type PairArrArr is array (natural range <>) of PairArr(width-1 downto 1);
--TODO: reduce msb to log2_ceil(width) - 1 and direct output correctly
signal cSN_LSB : std_logic_vector(log2_ceil(width) downto 0);
signal tempC : PairArrArr(log2_ceil(width) downto 0);
signal tempS : PairArrArr(log2_ceil(width) downto 0);
begin
ha : HalfAdder port map (a => a(0), b => b(0), s => o(0), c => cSN_LSB(0));
rgN : for index in 1 to (width-1) generate
begin rg : ResultGen port map (a => a(index),
b => b(index),
s => tempS(0)(index),
c => tempC(0)(index));
end generate;
selStage: for stage in 0 to log2_ceil(width) - 1 generate
constant slice : integer := 2**(stage+1);
constant sInTot : integer := 2**(stage);
constant sels : integer := width/slice;
begin
selSel: for index in 0 to (width/slice)-1 generate
constant msb : integer := (slice*(index+1))-1;
constant lsb : integer := (slice*index);
constant sInLSB : integer := msb-sInTot+1;
constant bInMSB : integer := msb-sInTot;
constant bInTot : integer := bInMSB-lsb+1;
begin
selIf0: if index = 0 generate
selB0: SelectorLSB generic map ( num_sum => sInTot - 1)
port map ( cIn => tempC(stage)(msb),
cSel => cSN_LSB(stage),
cOut => cSN_LSB(stage+1),
sumIn => tempS(stage)(msb downto sInLSB),
sumOut => o(msb downto sInLSB));
end generate;
selIfN: if index /= 0 generate
constant csel : integer := msb - sInTot;
begin
selBN: Selector generic map ( num_sum => sInTot - 1, num_buffer => bInTot - 1)
port map ( cIn => tempC(stage)(msb),
cSel => tempC(stage)(csel),
cOut => tempC(stage+1)(msb),
sumIn => tempS(stage)(msb downto sInLSB),
sumOut => tempS(stage+1)(msb downto sInLSB),
bufferIn => tempS(stage)(bInMSB downto lsb),
bufferOut => tempS(stage+1)(bInMSB downto lsb));
end generate;
end generate;
end generate;
cout <= cSN_LSB(log2_ceil(width));
end Behavioral; |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
component prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end component;
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
prg : prgmem
generic map (
INIT_FILE_NAME => "prom.hex",
PRGM_MEM => abits,
MEM_WIDTH => 32
) port map (
clk => clk,
addr => romdata,
data => addr
);
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate --won't really work
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
--will be clocked in prgmem already
--ahbso.hrdata <= romdata;
end if;
end process;
ahbso.hrdata <= romdata;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_0 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 10,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 10,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 16,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 2,
C_AXIS_TKEEP_WIDTH => 2,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_0_arch;
|
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
-- Violation below
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity registerFile_tb is
end registerFile_tb;
architecture behv of registerFile_tb is
component register_file
port (
clk : in std_logic;
data : in std_logic_vector (31 downto 0);
reg_write : in std_logic_vector(4 downto 0);
wr_en : in std_logic;
reg_read1 : in std_logic_vector(4 downto 0);
reg_read0 : in std_logic_vector(4 downto 0);
output1 : out std_logic_vector(31 downto 0);
output0 : out std_logic_vector(31 downto 0)
);
end component;
signal clk : std_logic := '0';
signal data : std_logic_vector (31 downto 0);
signal reg_write : std_logic_vector(4 downto 0);
signal wr_en : std_logic;
signal reg_read1 : std_logic_vector(4 downto 0);
signal reg_read0 : std_logic_vector(4 downto 0);
signal output1 : std_logic_vector(31 downto 0);
signal output0 : std_logic_vector(31 downto 0);
begin
reg_bank: register_file
port map (
clk => clk,
data => data,
reg_write => reg_write,
wr_en => wr_en,
reg_read1 => reg_read1,
reg_read0 => reg_read0,
output1 => output1,
output0 => output0
);
clk <= not clk after 10 ns;
process
begin
reg_read1 <="00";
reg_read0 <="00";
data <= x"EEEEAAAA";
reg_write <= conv_std_logic_vector(9, 5);
wr_en <='1';
wait for 20 ns;
data <= x"BABABABA";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
data <= x"00000000";
reg_write <= "00000";
wr_en <='0';
wait for 20 ns;
data <= x"FFFFBABA";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
data <= x"55555555";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
data <= x"FEEDBEEF";
reg_write <= "00000";
wr_en <='1';
wait for 20 ns;
reg_read1 <="01001";
reg_read0 <="00000";
wr_en <='0';
wait for 20 ns;
reg_read1 <="00000";
reg_read0 <="00000";
wr_en <='0';
wait for 20 ns;
wait;
end process;
end behv;
|
-------------------------------------------------------------------------------------
-- FILE NAME : performance.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - toplevel_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Counts clock cycles and valids
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity performance is
port (
clk_in : in std_logic;
rst_in : in std_logic;
start_in : in std_logic;
in_val : in std_logic;
out_val : in std_logic;
cycle_cnt : out std_logic_vector(63 downto 0);
in_cnt : out std_logic_vector(63 downto 0);
out_cnt : out std_logic_vector(63 downto 0)
);
end performance;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of performance is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type state_m is (T_IDLE, T_COUNT, T_DONE);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal state_reg : state_m;
signal timer_count : std_logic_vector(63 downto 0);
signal input_count : std_logic_vector(63 downto 0);
signal output_count : std_logic_vector(63 downto 0);
signal count_rst : std_logic;
signal valid : std_logic;
signal input_valid : std_logic;
signal output_valid : std_logic;
--***********************************************************************************
begin
--***********************************************************************************
-- output mapping
cycle_cnt <= timer_count;
out_cnt <= output_count;
in_cnt <= input_count;
-- control state machine
process (clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
state_reg <= T_IDLE;
timer_count <= (others=>'0');
count_rst <= '1';
valid <= '0';
input_valid <= '0';
output_valid <= '0';
else
input_valid <= valid and in_val;
output_valid <= valid and out_val;
case state_reg is
when T_IDLE =>
timer_count <= (others=>'0');
count_rst <= '1'; -- don't allow counting
valid <= '0'; -- don't accept data
if start_in = '1' then
state_reg <= T_COUNT;
end if;
when T_COUNT =>
timer_count <= timer_count + 1;
state_reg <= T_COUNT;
count_rst <= '0'; -- allow counting
valid <= '1'; -- accept data
if start_in = '0' then
state_reg <= T_DONE;
end if;
when T_DONE =>
valid <= '0'; -- allow counting (hold)
count_rst <= '0'; -- don't accept data
if start_in = '1' then
state_reg <= T_IDLE;
end if;
when others =>
timer_count <= (others=>'0');
count_rst <= '1';
valid <= '0';
state_reg <= T_IDLE;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------------
-- Input counter process
-------------------------------------------------------------------------------------
process(clk_in, count_rst)
begin
if rising_edge(clk_in) then
if count_rst = '1' then
input_count <= (others=>'0');
else
if input_valid = '1' then
input_count <= input_count + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------
-- Output counter process
-------------------------------------------------------------------------------------
process(clk_in, count_rst)
begin
if rising_edge(clk_in) then
if count_rst = '1' then
output_count <= (others=>'0');
else
if output_valid = '1' then
output_count <= output_count + 1;
end if;
end if;
end if;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity compar_tb is
end entity;
architecture behav of compar_tb is
component compar is
port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
so_a : out std_logic;
so_b : out std_logic
);
end component;
signal a,b : std_logic_vector(3 downto 0);
signal so_a, so_b : std_logic;
for compar_0: compar use entity work.compar;
begin
compar_0: compar port map (a=>a, b=>b, so_a=>so_a, so_b=>so_b);
process
begin
a<="1110";
b<="0111";
wait for 5 ns;
b<="1110";
a<="0000";
wait for 5 ns;
b<="0010";
a<="0111";
wait for 5 ns;
b<="1010";
a<="0111";
wait for 5 ns;
b<="0110";
a<="0110";
wait for 5 ns;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:58:35 12/03/2017
-- Design Name:
-- Module Name: Barra2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Barra2 is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ncwpin : in STD_LOGIC;
callin : in STD_LOGIC_VECTOR (31 downto 0);
ifin : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
wrenmenin : in STD_LOGIC;
pcsourcein : in STD_LOGIC_VECTOR (1 downto 0);
aluopin : in STD_LOGIC_VECTOR (5 downto 0);
a18in : in STD_LOGIC_VECTOR (31 downto 0);
crs1outin : in STD_LOGIC_VECTOR (31 downto 0);
op2outin : in STD_LOGIC_VECTOR (31 downto 0);
PCC : in STD_LOGIC_VECTOR (31 downto 0);
PCCout : out STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
Cuentradain : in STD_LOGIC_VECTOR (1 downto 0);
Cuentradaout : out STD_LOGIC_VECTOR (1 downto 0);
ncwpout : out STD_LOGIC;
callout : out STD_LOGIC_VECTOR (31 downto 0);
ifout : out STD_LOGIC_VECTOR (31 downto 0);
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0);
wrenmen : out STD_LOGIC;
pcsource : out STD_LOGIC_VECTOR (1 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
a18 : out STD_LOGIC_VECTOR (31 downto 0);
crs1out : out STD_LOGIC_VECTOR (31 downto 0);
op2out : out STD_LOGIC_VECTOR (31 downto 0));
end Barra2;
architecture Behavioral of Barra2 is
begin
process(Clk,Reset,ncwpin ,callin ,ifin,rfsourcein ,wrenmenin ,pcsourcein ,
aluopin,a18in ,crs1outin ,op2outin,PCC,RD,Cuentradain )
begin
if reset='1' then
ncwpout <= '0';
callout <= "00000000000000000000000000000000";
ifout<= "00000000000000000000000000000000";
rfsourceout <= "00";
wrenmen <= '0';
pcsource <= "00";
Cuentradaout<= "00";
aluop<= "000000";
a18 <= "00000000000000000000000000000000";
crs1out <= "00000000000000000000000000000000";
op2out<= "00000000000000000000000000000000";
PCCout<= "00000000000000000000000000000000";
RDout <= "000000";
elsif(rising_edge(Clk)) then
ncwpout <= ncwpin;
callout <= callin;
ifout<= ifin;
rfsourceout <= rfsourcein;
wrenmen <= wrenmenin;
pcsource <= pcsourcein;
RDout<= RD;
Cuentradaout<= Cuentradain ;
aluop<=aluopin;
a18 <= a18in;
crs1out <= crs1outin;
op2out<= op2outin;
PCCout<=PCC;
end if;
end process;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:27:45 08/19/2013
-- Design Name:
-- Module Name: servo_controller_wb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_servo is
generic(NB_SERVOS : positive := 2;
wb_size : natural := 16 ; -- Data port size for wishbone
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
failsafe : in std_logic ;
servos : out std_logic_vector(NB_SERVOS-1 downto 0)
);
end wishbone_servo;
architecture Behavioral of wishbone_servo is
component servo_controller is
generic(
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port (clk : in std_logic;
rst : in std_logic;
servo_position : in std_logic_vector (pos_width-1 downto 0);
servo_out : out std_logic);
end component;
constant reset_pulse : std_logic_vector(15 downto 0) := X"8080";
type reg16_array is array (0 to (NB_SERVOS-1)) of std_logic_vector(15 downto 0) ;
signal pos_regs : reg16_array := (others => reset_pulse);
signal failsafe_regs : reg16_array := (others => reset_pulse);
signal servo_pos : reg16_array ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_readdata <= pos_regs(conv_integer(wbs_address)) ;
register_mngmt : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
pos_regs <= (others => reset_pulse) ;
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '0' then
pos_regs(conv_integer(wbs_address(15 downto 1))) <= wbs_writedata;
end if ;
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '1' then
failsafe_regs(conv_integer(wbs_address(15 downto 1))) <= wbs_writedata;
end if ;
end if;
end process register_mngmt;
gen_servo_ctrl : for i in 0 to (NB_SERVOS-1) generate
servo_pos(i) <= pos_regs(i) when failsafe = '0' else
failsafe_regs(i) ;
servo_ctrl : servo_controller
generic map(
pos_width => pos_width,
clock_period => clock_period,
minimum_high_pulse_width => minimum_high_pulse_width,
maximum_high_pulse_width => maximum_high_pulse_width
)
port map(clk => gls_clk,
rst => gls_reset,
servo_position =>servo_pos(i)(pos_width-1 downto 0),
servo_out => servos(i)
);
end generate ;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:27:45 08/19/2013
-- Design Name:
-- Module Name: servo_controller_wb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_servo is
generic(NB_SERVOS : positive := 2;
wb_size : natural := 16 ; -- Data port size for wishbone
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
failsafe : in std_logic ;
servos : out std_logic_vector(NB_SERVOS-1 downto 0)
);
end wishbone_servo;
architecture Behavioral of wishbone_servo is
component servo_controller is
generic(
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port (clk : in std_logic;
rst : in std_logic;
servo_position : in std_logic_vector (pos_width-1 downto 0);
servo_out : out std_logic);
end component;
constant reset_pulse : std_logic_vector(15 downto 0) := X"8080";
type reg16_array is array (0 to (NB_SERVOS-1)) of std_logic_vector(15 downto 0) ;
signal pos_regs : reg16_array := (others => reset_pulse);
signal failsafe_regs : reg16_array := (others => reset_pulse);
signal servo_pos : reg16_array ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_readdata <= pos_regs(conv_integer(wbs_address)) ;
register_mngmt : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
pos_regs <= (others => reset_pulse) ;
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '0' then
pos_regs(conv_integer(wbs_address(15 downto 1))) <= wbs_writedata;
end if ;
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '1' then
failsafe_regs(conv_integer(wbs_address(15 downto 1))) <= wbs_writedata;
end if ;
end if;
end process register_mngmt;
gen_servo_ctrl : for i in 0 to (NB_SERVOS-1) generate
servo_pos(i) <= pos_regs(i) when failsafe = '0' else
failsafe_regs(i) ;
servo_ctrl : servo_controller
generic map(
pos_width => pos_width,
clock_period => clock_period,
minimum_high_pulse_width => minimum_high_pulse_width,
maximum_high_pulse_width => maximum_high_pulse_width
)
port map(clk => gls_clk,
rst => gls_reset,
servo_position =>servo_pos(i)(pos_width-1 downto 0),
servo_out => servos(i)
);
end generate ;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity InstrucDecoder is
generic(
nop : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi1, Hi0, Hi0);
add : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
sub : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi0);
\AND\ : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi0, Hi0);
\OR\ : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi0, Hi1);
\XOR\ : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi1, Hi0);
slt : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0);
\sll\ : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
lw : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi1);
sw : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi1);
jmp : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi1, Hi0);
jr : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi0, Hi0);
bgt : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi1, Hi0, Hi1)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of nop : constant is 1;
attribute mti_svvh_generic_type of add : constant is 1;
attribute mti_svvh_generic_type of sub : constant is 1;
attribute mti_svvh_generic_type of \AND\ : constant is 1;
attribute mti_svvh_generic_type of \OR\ : constant is 1;
attribute mti_svvh_generic_type of \XOR\ : constant is 1;
attribute mti_svvh_generic_type of slt : constant is 1;
attribute mti_svvh_generic_type of \sll\ : constant is 1;
attribute mti_svvh_generic_type of lw : constant is 1;
attribute mti_svvh_generic_type of sw : constant is 1;
attribute mti_svvh_generic_type of jmp : constant is 1;
attribute mti_svvh_generic_type of jr : constant is 1;
attribute mti_svvh_generic_type of bgt : constant is 1;
-- This module cannot be connected to/from
-- VHDL because it has unnamed ports.
end InstrucDecoder;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic;
signal reset : std_logic;
signal sim_finished : boolean := false;
-- simulation parameters ---------------------------------------------------
constant PIX_DEPTH : positive := 8;
constant SAMPLE_EDGE : string := "RISING";
constant MAX_WIDTH : positive := 1920;
constant MAX_HEIGHT : positive := 1080;
constant OUTPUT_WIDTH : positive := 32;
constant FIFO_DEPTH : positive := 32;
constant DEVICE_FAMILY : string := "Cyclone V";
constant DEBAYER_ENABLE : boolean := false;
constant PACKER_ENABLE : boolean := false;
constant DEBAYER_PATTERN : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB;
constant FRAME_WIDTH : positive := 5;
constant FRAME_HEIGHT : positive := 4;
constant FRAME_FRAME_BLANK : positive := 1;
constant FRAME_LINE_BLANK : natural := 1;
constant LINE_LINE_BLANK : positive := 1;
constant LINE_FRAME_BLANK : natural := 1;
constant BUS_BUSY_THRESHOLD : natural range 0 to 100 := 100;
-- cmos_sensor_output_generator --------------------------------------------
signal cmos_sensor_output_generator_addr : std_logic_vector(2 downto 0);
signal cmos_sensor_output_generator_read : std_logic;
signal cmos_sensor_output_generator_write : std_logic;
signal cmos_sensor_output_generator_rddata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_wrdata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_frame_valid : std_logic;
signal cmos_sensor_output_generator_line_valid : std_logic;
signal cmos_sensor_output_generator_data : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- cmos_sensor_input -------------------------------------------------------
signal cmos_sensor_input_ready : std_logic;
signal cmos_sensor_input_valid : std_logic;
signal cmos_sensor_input_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal cmos_sensor_input_addr : std_logic_vector(1 downto 0);
signal cmos_sensor_input_read : std_logic;
signal cmos_sensor_input_write : std_logic;
signal cmos_sensor_input_rddata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_wrdata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_irq : std_logic;
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
cmos_sensor_input_ready_generation : process
variable rand_gen : RandomPType;
variable rint : integer;
begin
rand_gen.InitSeed(rand_gen'instance_name);
rand_gen.SetRandomParm(UNIFORM);
while true loop
if not sim_finished then
wait until falling_edge(clk);
rint := rand_gen.RandInt(0, 100);
if rint < BUS_BUSY_THRESHOLD then
cmos_sensor_input_ready <= '0';
else
cmos_sensor_input_ready <= '1';
end if;
else
wait;
end if;
end loop;
end process cmos_sensor_input_ready_generation;
cmos_sensor_output_generator_inst : entity work.cmos_sensor_output_generator
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => clk,
reset => reset,
addr => cmos_sensor_output_generator_addr,
read => cmos_sensor_output_generator_read,
write => cmos_sensor_output_generator_write,
rddata => cmos_sensor_output_generator_rddata,
wrdata => cmos_sensor_output_generator_wrdata,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data => cmos_sensor_output_generator_data);
cmos_sensor_input_inst : entity work.cmos_sensor_input
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT,
OUTPUT_WIDTH => OUTPUT_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY,
DEBAYER_ENABLE => DEBAYER_ENABLE,
PACKER_ENABLE => PACKER_ENABLE)
port map(clk => clk,
reset => reset,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data_in => cmos_sensor_output_generator_data,
ready => cmos_sensor_input_ready,
valid => cmos_sensor_input_valid,
data_out => cmos_sensor_input_data_out,
addr => cmos_sensor_input_addr,
read => cmos_sensor_input_read,
write => cmos_sensor_input_write,
rddata => cmos_sensor_input_rddata,
wrdata => cmos_sensor_input_wrdata,
irq => cmos_sensor_input_irq);
sim : process
function configuration_valid return boolean is
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE : positive := 1 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE : positive := 2 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE : positive := 3 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE : positive := 6 * PIX_DEPTH;
begin
if not ((1 <= PIX_DEPTH) and (PIX_DEPTH <= 32)) then
assert false
report "PIX_DEPTH must be in range {1:32}"
severity error;
return false;
end if;
if not ((SAMPLE_EDGE = "RISING") or (SAMPLE_EDGE = "FALLING")) then
assert false
report "SAMPLE_EDGE must be {RISING, FALLING}"
severity error;
return false;
end if;
if not ((2 <= MAX_WIDTH) and (MAX_WIDTH <= 65535)) then
assert false
report "MAX_WIDTH must be in range {2:65535}"
severity error;
return false;
end if;
if not ((1 <= MAX_HEIGHT) and (MAX_HEIGHT <= 65535)) then
assert false
report "MAX_HEIGHT must be in range {1:65535}"
severity error;
return false;
end if;
if not ((OUTPUT_WIDTH = 8) or (OUTPUT_WIDTH = 16) or (OUTPUT_WIDTH = 32) or (OUTPUT_WIDTH = 64) or (OUTPUT_WIDTH = 128) or (OUTPUT_WIDTH = 256) or (OUTPUT_WIDTH = 512) or (OUTPUT_WIDTH = 1024)) then
assert false
report "OUTPUT_WIDTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((FIFO_DEPTH = 8) or (FIFO_DEPTH = 16) or (FIFO_DEPTH = 32) or (FIFO_DEPTH = 64) or (FIFO_DEPTH = 128) or (FIFO_DEPTH = 256) or (FIFO_DEPTH = 512) or (FIFO_DEPTH = 1024)) then
assert false
report "FIFO_DEPTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((DEVICE_FAMILY = "Cyclone IV E") or (DEVICE_FAMILY = "Cyclone V")) then
assert false
report "DEVICE_FAMILY must be {Cyclone IV E, Cyclone V}"
severity error;
return false;
end if;
if not DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE)
severity error;
return false;
end if;
end if;
if not ((2 <= FRAME_WIDTH) and (FRAME_WIDTH <= MAX_WIDTH)) then
assert false
report "FRAME_WIDTH must be in range {1:" & integer'image(MAX_WIDTH) & "}"
severity error;
return false;
end if;
if not ((2 <= FRAME_HEIGHT) and (FRAME_HEIGHT <= MAX_HEIGHT)) then
assert false
report "FRAME_HEIGHT must be in range {1:" & integer'image(MAX_HEIGHT) & "}"
severity error;
return false;
end if;
return true;
end function configuration_valid;
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure setup_cmos_sensor_output_generator is
procedure write_register(constant ofst : in std_logic_vector;
constant val : in natural) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(to_unsigned(val, cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(resize(unsigned(val), cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
begin
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST, FRAME_WIDTH);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST, FRAME_HEIGHT);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST, FRAME_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST, FRAME_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST, LINE_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST, LINE_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
end procedure setup_cmos_sensor_output_generator;
procedure sim_cmos_sensor_input is
procedure write_command_register(constant data : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_COMMAND_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST) <= data;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_command_register;
procedure write_config_register(constant irq : in boolean;
constant debayer_pattern : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_CONFIG_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata <= (others => '0');
if irq then
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE;
else
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE;
end if;
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST) <= debayer_pattern;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_config_register;
procedure read_frame_info_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_FRAME_INFO_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_frame_info_register;
procedure read_status_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_status_register;
procedure wait_until_idle is
variable end_loop : boolean := false;
begin
while not end_loop loop
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
if cmos_sensor_input_rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) = CMOS_SENSOR_INPUT_STATUS_STATE_IDLE then
end_loop := true;
end if;
end loop;
end procedure wait_until_idle;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
procedure noIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(false, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
wait_until_idle;
end procedure noIrq;
procedure withIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(true, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
end procedure withIrq;
begin
--noIrq;
withIrq;
end procedure sim_cmos_sensor_input;
begin
if configuration_valid then
async_reset;
setup_cmos_sensor_output_generator;
sim_cmos_sensor_input;
else
end if;
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic;
signal reset : std_logic;
signal sim_finished : boolean := false;
-- simulation parameters ---------------------------------------------------
constant PIX_DEPTH : positive := 8;
constant SAMPLE_EDGE : string := "RISING";
constant MAX_WIDTH : positive := 1920;
constant MAX_HEIGHT : positive := 1080;
constant OUTPUT_WIDTH : positive := 32;
constant FIFO_DEPTH : positive := 32;
constant DEVICE_FAMILY : string := "Cyclone V";
constant DEBAYER_ENABLE : boolean := false;
constant PACKER_ENABLE : boolean := false;
constant DEBAYER_PATTERN : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB;
constant FRAME_WIDTH : positive := 5;
constant FRAME_HEIGHT : positive := 4;
constant FRAME_FRAME_BLANK : positive := 1;
constant FRAME_LINE_BLANK : natural := 1;
constant LINE_LINE_BLANK : positive := 1;
constant LINE_FRAME_BLANK : natural := 1;
constant BUS_BUSY_THRESHOLD : natural range 0 to 100 := 100;
-- cmos_sensor_output_generator --------------------------------------------
signal cmos_sensor_output_generator_addr : std_logic_vector(2 downto 0);
signal cmos_sensor_output_generator_read : std_logic;
signal cmos_sensor_output_generator_write : std_logic;
signal cmos_sensor_output_generator_rddata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_wrdata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_frame_valid : std_logic;
signal cmos_sensor_output_generator_line_valid : std_logic;
signal cmos_sensor_output_generator_data : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- cmos_sensor_input -------------------------------------------------------
signal cmos_sensor_input_ready : std_logic;
signal cmos_sensor_input_valid : std_logic;
signal cmos_sensor_input_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal cmos_sensor_input_addr : std_logic_vector(1 downto 0);
signal cmos_sensor_input_read : std_logic;
signal cmos_sensor_input_write : std_logic;
signal cmos_sensor_input_rddata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_wrdata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_irq : std_logic;
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
cmos_sensor_input_ready_generation : process
variable rand_gen : RandomPType;
variable rint : integer;
begin
rand_gen.InitSeed(rand_gen'instance_name);
rand_gen.SetRandomParm(UNIFORM);
while true loop
if not sim_finished then
wait until falling_edge(clk);
rint := rand_gen.RandInt(0, 100);
if rint < BUS_BUSY_THRESHOLD then
cmos_sensor_input_ready <= '0';
else
cmos_sensor_input_ready <= '1';
end if;
else
wait;
end if;
end loop;
end process cmos_sensor_input_ready_generation;
cmos_sensor_output_generator_inst : entity work.cmos_sensor_output_generator
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => clk,
reset => reset,
addr => cmos_sensor_output_generator_addr,
read => cmos_sensor_output_generator_read,
write => cmos_sensor_output_generator_write,
rddata => cmos_sensor_output_generator_rddata,
wrdata => cmos_sensor_output_generator_wrdata,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data => cmos_sensor_output_generator_data);
cmos_sensor_input_inst : entity work.cmos_sensor_input
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT,
OUTPUT_WIDTH => OUTPUT_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY,
DEBAYER_ENABLE => DEBAYER_ENABLE,
PACKER_ENABLE => PACKER_ENABLE)
port map(clk => clk,
reset => reset,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data_in => cmos_sensor_output_generator_data,
ready => cmos_sensor_input_ready,
valid => cmos_sensor_input_valid,
data_out => cmos_sensor_input_data_out,
addr => cmos_sensor_input_addr,
read => cmos_sensor_input_read,
write => cmos_sensor_input_write,
rddata => cmos_sensor_input_rddata,
wrdata => cmos_sensor_input_wrdata,
irq => cmos_sensor_input_irq);
sim : process
function configuration_valid return boolean is
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE : positive := 1 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE : positive := 2 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE : positive := 3 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE : positive := 6 * PIX_DEPTH;
begin
if not ((1 <= PIX_DEPTH) and (PIX_DEPTH <= 32)) then
assert false
report "PIX_DEPTH must be in range {1:32}"
severity error;
return false;
end if;
if not ((SAMPLE_EDGE = "RISING") or (SAMPLE_EDGE = "FALLING")) then
assert false
report "SAMPLE_EDGE must be {RISING, FALLING}"
severity error;
return false;
end if;
if not ((2 <= MAX_WIDTH) and (MAX_WIDTH <= 65535)) then
assert false
report "MAX_WIDTH must be in range {2:65535}"
severity error;
return false;
end if;
if not ((1 <= MAX_HEIGHT) and (MAX_HEIGHT <= 65535)) then
assert false
report "MAX_HEIGHT must be in range {1:65535}"
severity error;
return false;
end if;
if not ((OUTPUT_WIDTH = 8) or (OUTPUT_WIDTH = 16) or (OUTPUT_WIDTH = 32) or (OUTPUT_WIDTH = 64) or (OUTPUT_WIDTH = 128) or (OUTPUT_WIDTH = 256) or (OUTPUT_WIDTH = 512) or (OUTPUT_WIDTH = 1024)) then
assert false
report "OUTPUT_WIDTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((FIFO_DEPTH = 8) or (FIFO_DEPTH = 16) or (FIFO_DEPTH = 32) or (FIFO_DEPTH = 64) or (FIFO_DEPTH = 128) or (FIFO_DEPTH = 256) or (FIFO_DEPTH = 512) or (FIFO_DEPTH = 1024)) then
assert false
report "FIFO_DEPTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((DEVICE_FAMILY = "Cyclone IV E") or (DEVICE_FAMILY = "Cyclone V")) then
assert false
report "DEVICE_FAMILY must be {Cyclone IV E, Cyclone V}"
severity error;
return false;
end if;
if not DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE)
severity error;
return false;
end if;
end if;
if not ((2 <= FRAME_WIDTH) and (FRAME_WIDTH <= MAX_WIDTH)) then
assert false
report "FRAME_WIDTH must be in range {1:" & integer'image(MAX_WIDTH) & "}"
severity error;
return false;
end if;
if not ((2 <= FRAME_HEIGHT) and (FRAME_HEIGHT <= MAX_HEIGHT)) then
assert false
report "FRAME_HEIGHT must be in range {1:" & integer'image(MAX_HEIGHT) & "}"
severity error;
return false;
end if;
return true;
end function configuration_valid;
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure setup_cmos_sensor_output_generator is
procedure write_register(constant ofst : in std_logic_vector;
constant val : in natural) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(to_unsigned(val, cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(resize(unsigned(val), cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
begin
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST, FRAME_WIDTH);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST, FRAME_HEIGHT);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST, FRAME_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST, FRAME_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST, LINE_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST, LINE_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
end procedure setup_cmos_sensor_output_generator;
procedure sim_cmos_sensor_input is
procedure write_command_register(constant data : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_COMMAND_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST) <= data;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_command_register;
procedure write_config_register(constant irq : in boolean;
constant debayer_pattern : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_CONFIG_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata <= (others => '0');
if irq then
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE;
else
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE;
end if;
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST) <= debayer_pattern;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_config_register;
procedure read_frame_info_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_FRAME_INFO_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_frame_info_register;
procedure read_status_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_status_register;
procedure wait_until_idle is
variable end_loop : boolean := false;
begin
while not end_loop loop
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
if cmos_sensor_input_rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) = CMOS_SENSOR_INPUT_STATUS_STATE_IDLE then
end_loop := true;
end if;
end loop;
end procedure wait_until_idle;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
procedure noIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(false, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
wait_until_idle;
end procedure noIrq;
procedure withIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(true, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
end procedure withIrq;
begin
--noIrq;
withIrq;
end procedure sim_cmos_sensor_input;
begin
if configuration_valid then
async_reset;
setup_cmos_sensor_output_generator;
sim_cmos_sensor_input;
else
end if;
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic;
signal reset : std_logic;
signal sim_finished : boolean := false;
-- simulation parameters ---------------------------------------------------
constant PIX_DEPTH : positive := 8;
constant SAMPLE_EDGE : string := "RISING";
constant MAX_WIDTH : positive := 1920;
constant MAX_HEIGHT : positive := 1080;
constant OUTPUT_WIDTH : positive := 32;
constant FIFO_DEPTH : positive := 32;
constant DEVICE_FAMILY : string := "Cyclone V";
constant DEBAYER_ENABLE : boolean := false;
constant PACKER_ENABLE : boolean := false;
constant DEBAYER_PATTERN : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB;
constant FRAME_WIDTH : positive := 5;
constant FRAME_HEIGHT : positive := 4;
constant FRAME_FRAME_BLANK : positive := 1;
constant FRAME_LINE_BLANK : natural := 1;
constant LINE_LINE_BLANK : positive := 1;
constant LINE_FRAME_BLANK : natural := 1;
constant BUS_BUSY_THRESHOLD : natural range 0 to 100 := 100;
-- cmos_sensor_output_generator --------------------------------------------
signal cmos_sensor_output_generator_addr : std_logic_vector(2 downto 0);
signal cmos_sensor_output_generator_read : std_logic;
signal cmos_sensor_output_generator_write : std_logic;
signal cmos_sensor_output_generator_rddata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_wrdata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_frame_valid : std_logic;
signal cmos_sensor_output_generator_line_valid : std_logic;
signal cmos_sensor_output_generator_data : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- cmos_sensor_input -------------------------------------------------------
signal cmos_sensor_input_ready : std_logic;
signal cmos_sensor_input_valid : std_logic;
signal cmos_sensor_input_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal cmos_sensor_input_addr : std_logic_vector(1 downto 0);
signal cmos_sensor_input_read : std_logic;
signal cmos_sensor_input_write : std_logic;
signal cmos_sensor_input_rddata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_wrdata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_irq : std_logic;
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
cmos_sensor_input_ready_generation : process
variable rand_gen : RandomPType;
variable rint : integer;
begin
rand_gen.InitSeed(rand_gen'instance_name);
rand_gen.SetRandomParm(UNIFORM);
while true loop
if not sim_finished then
wait until falling_edge(clk);
rint := rand_gen.RandInt(0, 100);
if rint < BUS_BUSY_THRESHOLD then
cmos_sensor_input_ready <= '0';
else
cmos_sensor_input_ready <= '1';
end if;
else
wait;
end if;
end loop;
end process cmos_sensor_input_ready_generation;
cmos_sensor_output_generator_inst : entity work.cmos_sensor_output_generator
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => clk,
reset => reset,
addr => cmos_sensor_output_generator_addr,
read => cmos_sensor_output_generator_read,
write => cmos_sensor_output_generator_write,
rddata => cmos_sensor_output_generator_rddata,
wrdata => cmos_sensor_output_generator_wrdata,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data => cmos_sensor_output_generator_data);
cmos_sensor_input_inst : entity work.cmos_sensor_input
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT,
OUTPUT_WIDTH => OUTPUT_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY,
DEBAYER_ENABLE => DEBAYER_ENABLE,
PACKER_ENABLE => PACKER_ENABLE)
port map(clk => clk,
reset => reset,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data_in => cmos_sensor_output_generator_data,
ready => cmos_sensor_input_ready,
valid => cmos_sensor_input_valid,
data_out => cmos_sensor_input_data_out,
addr => cmos_sensor_input_addr,
read => cmos_sensor_input_read,
write => cmos_sensor_input_write,
rddata => cmos_sensor_input_rddata,
wrdata => cmos_sensor_input_wrdata,
irq => cmos_sensor_input_irq);
sim : process
function configuration_valid return boolean is
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE : positive := 1 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE : positive := 2 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE : positive := 3 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE : positive := 6 * PIX_DEPTH;
begin
if not ((1 <= PIX_DEPTH) and (PIX_DEPTH <= 32)) then
assert false
report "PIX_DEPTH must be in range {1:32}"
severity error;
return false;
end if;
if not ((SAMPLE_EDGE = "RISING") or (SAMPLE_EDGE = "FALLING")) then
assert false
report "SAMPLE_EDGE must be {RISING, FALLING}"
severity error;
return false;
end if;
if not ((2 <= MAX_WIDTH) and (MAX_WIDTH <= 65535)) then
assert false
report "MAX_WIDTH must be in range {2:65535}"
severity error;
return false;
end if;
if not ((1 <= MAX_HEIGHT) and (MAX_HEIGHT <= 65535)) then
assert false
report "MAX_HEIGHT must be in range {1:65535}"
severity error;
return false;
end if;
if not ((OUTPUT_WIDTH = 8) or (OUTPUT_WIDTH = 16) or (OUTPUT_WIDTH = 32) or (OUTPUT_WIDTH = 64) or (OUTPUT_WIDTH = 128) or (OUTPUT_WIDTH = 256) or (OUTPUT_WIDTH = 512) or (OUTPUT_WIDTH = 1024)) then
assert false
report "OUTPUT_WIDTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((FIFO_DEPTH = 8) or (FIFO_DEPTH = 16) or (FIFO_DEPTH = 32) or (FIFO_DEPTH = 64) or (FIFO_DEPTH = 128) or (FIFO_DEPTH = 256) or (FIFO_DEPTH = 512) or (FIFO_DEPTH = 1024)) then
assert false
report "FIFO_DEPTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((DEVICE_FAMILY = "Cyclone IV E") or (DEVICE_FAMILY = "Cyclone V")) then
assert false
report "DEVICE_FAMILY must be {Cyclone IV E, Cyclone V}"
severity error;
return false;
end if;
if not DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE)
severity error;
return false;
end if;
end if;
if not ((2 <= FRAME_WIDTH) and (FRAME_WIDTH <= MAX_WIDTH)) then
assert false
report "FRAME_WIDTH must be in range {1:" & integer'image(MAX_WIDTH) & "}"
severity error;
return false;
end if;
if not ((2 <= FRAME_HEIGHT) and (FRAME_HEIGHT <= MAX_HEIGHT)) then
assert false
report "FRAME_HEIGHT must be in range {1:" & integer'image(MAX_HEIGHT) & "}"
severity error;
return false;
end if;
return true;
end function configuration_valid;
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure setup_cmos_sensor_output_generator is
procedure write_register(constant ofst : in std_logic_vector;
constant val : in natural) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(to_unsigned(val, cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(resize(unsigned(val), cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
begin
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST, FRAME_WIDTH);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST, FRAME_HEIGHT);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST, FRAME_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST, FRAME_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST, LINE_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST, LINE_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
end procedure setup_cmos_sensor_output_generator;
procedure sim_cmos_sensor_input is
procedure write_command_register(constant data : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_COMMAND_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST) <= data;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_command_register;
procedure write_config_register(constant irq : in boolean;
constant debayer_pattern : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_CONFIG_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata <= (others => '0');
if irq then
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE;
else
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE;
end if;
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST) <= debayer_pattern;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_config_register;
procedure read_frame_info_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_FRAME_INFO_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_frame_info_register;
procedure read_status_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_status_register;
procedure wait_until_idle is
variable end_loop : boolean := false;
begin
while not end_loop loop
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
if cmos_sensor_input_rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) = CMOS_SENSOR_INPUT_STATUS_STATE_IDLE then
end_loop := true;
end if;
end loop;
end procedure wait_until_idle;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
procedure noIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(false, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
wait_until_idle;
end procedure noIrq;
procedure withIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(true, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
end procedure withIrq;
begin
--noIrq;
withIrq;
end procedure sim_cmos_sensor_input;
begin
if configuration_valid then
async_reset;
setup_cmos_sensor_output_generator;
sim_cmos_sensor_input;
else
end if;
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic;
signal reset : std_logic;
signal sim_finished : boolean := false;
-- simulation parameters ---------------------------------------------------
constant PIX_DEPTH : positive := 8;
constant SAMPLE_EDGE : string := "RISING";
constant MAX_WIDTH : positive := 1920;
constant MAX_HEIGHT : positive := 1080;
constant OUTPUT_WIDTH : positive := 32;
constant FIFO_DEPTH : positive := 32;
constant DEVICE_FAMILY : string := "Cyclone V";
constant DEBAYER_ENABLE : boolean := false;
constant PACKER_ENABLE : boolean := false;
constant DEBAYER_PATTERN : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB;
constant FRAME_WIDTH : positive := 5;
constant FRAME_HEIGHT : positive := 4;
constant FRAME_FRAME_BLANK : positive := 1;
constant FRAME_LINE_BLANK : natural := 1;
constant LINE_LINE_BLANK : positive := 1;
constant LINE_FRAME_BLANK : natural := 1;
constant BUS_BUSY_THRESHOLD : natural range 0 to 100 := 100;
-- cmos_sensor_output_generator --------------------------------------------
signal cmos_sensor_output_generator_addr : std_logic_vector(2 downto 0);
signal cmos_sensor_output_generator_read : std_logic;
signal cmos_sensor_output_generator_write : std_logic;
signal cmos_sensor_output_generator_rddata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_wrdata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_frame_valid : std_logic;
signal cmos_sensor_output_generator_line_valid : std_logic;
signal cmos_sensor_output_generator_data : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- cmos_sensor_input -------------------------------------------------------
signal cmos_sensor_input_ready : std_logic;
signal cmos_sensor_input_valid : std_logic;
signal cmos_sensor_input_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal cmos_sensor_input_addr : std_logic_vector(1 downto 0);
signal cmos_sensor_input_read : std_logic;
signal cmos_sensor_input_write : std_logic;
signal cmos_sensor_input_rddata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_wrdata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_irq : std_logic;
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
cmos_sensor_input_ready_generation : process
variable rand_gen : RandomPType;
variable rint : integer;
begin
rand_gen.InitSeed(rand_gen'instance_name);
rand_gen.SetRandomParm(UNIFORM);
while true loop
if not sim_finished then
wait until falling_edge(clk);
rint := rand_gen.RandInt(0, 100);
if rint < BUS_BUSY_THRESHOLD then
cmos_sensor_input_ready <= '0';
else
cmos_sensor_input_ready <= '1';
end if;
else
wait;
end if;
end loop;
end process cmos_sensor_input_ready_generation;
cmos_sensor_output_generator_inst : entity work.cmos_sensor_output_generator
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => clk,
reset => reset,
addr => cmos_sensor_output_generator_addr,
read => cmos_sensor_output_generator_read,
write => cmos_sensor_output_generator_write,
rddata => cmos_sensor_output_generator_rddata,
wrdata => cmos_sensor_output_generator_wrdata,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data => cmos_sensor_output_generator_data);
cmos_sensor_input_inst : entity work.cmos_sensor_input
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT,
OUTPUT_WIDTH => OUTPUT_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY,
DEBAYER_ENABLE => DEBAYER_ENABLE,
PACKER_ENABLE => PACKER_ENABLE)
port map(clk => clk,
reset => reset,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data_in => cmos_sensor_output_generator_data,
ready => cmos_sensor_input_ready,
valid => cmos_sensor_input_valid,
data_out => cmos_sensor_input_data_out,
addr => cmos_sensor_input_addr,
read => cmos_sensor_input_read,
write => cmos_sensor_input_write,
rddata => cmos_sensor_input_rddata,
wrdata => cmos_sensor_input_wrdata,
irq => cmos_sensor_input_irq);
sim : process
function configuration_valid return boolean is
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE : positive := 1 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE : positive := 2 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE : positive := 3 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE : positive := 6 * PIX_DEPTH;
begin
if not ((1 <= PIX_DEPTH) and (PIX_DEPTH <= 32)) then
assert false
report "PIX_DEPTH must be in range {1:32}"
severity error;
return false;
end if;
if not ((SAMPLE_EDGE = "RISING") or (SAMPLE_EDGE = "FALLING")) then
assert false
report "SAMPLE_EDGE must be {RISING, FALLING}"
severity error;
return false;
end if;
if not ((2 <= MAX_WIDTH) and (MAX_WIDTH <= 65535)) then
assert false
report "MAX_WIDTH must be in range {2:65535}"
severity error;
return false;
end if;
if not ((1 <= MAX_HEIGHT) and (MAX_HEIGHT <= 65535)) then
assert false
report "MAX_HEIGHT must be in range {1:65535}"
severity error;
return false;
end if;
if not ((OUTPUT_WIDTH = 8) or (OUTPUT_WIDTH = 16) or (OUTPUT_WIDTH = 32) or (OUTPUT_WIDTH = 64) or (OUTPUT_WIDTH = 128) or (OUTPUT_WIDTH = 256) or (OUTPUT_WIDTH = 512) or (OUTPUT_WIDTH = 1024)) then
assert false
report "OUTPUT_WIDTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((FIFO_DEPTH = 8) or (FIFO_DEPTH = 16) or (FIFO_DEPTH = 32) or (FIFO_DEPTH = 64) or (FIFO_DEPTH = 128) or (FIFO_DEPTH = 256) or (FIFO_DEPTH = 512) or (FIFO_DEPTH = 1024)) then
assert false
report "FIFO_DEPTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((DEVICE_FAMILY = "Cyclone IV E") or (DEVICE_FAMILY = "Cyclone V")) then
assert false
report "DEVICE_FAMILY must be {Cyclone IV E, Cyclone V}"
severity error;
return false;
end if;
if not DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE)
severity error;
return false;
end if;
end if;
if not ((2 <= FRAME_WIDTH) and (FRAME_WIDTH <= MAX_WIDTH)) then
assert false
report "FRAME_WIDTH must be in range {1:" & integer'image(MAX_WIDTH) & "}"
severity error;
return false;
end if;
if not ((2 <= FRAME_HEIGHT) and (FRAME_HEIGHT <= MAX_HEIGHT)) then
assert false
report "FRAME_HEIGHT must be in range {1:" & integer'image(MAX_HEIGHT) & "}"
severity error;
return false;
end if;
return true;
end function configuration_valid;
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure setup_cmos_sensor_output_generator is
procedure write_register(constant ofst : in std_logic_vector;
constant val : in natural) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(to_unsigned(val, cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(resize(unsigned(val), cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
begin
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST, FRAME_WIDTH);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST, FRAME_HEIGHT);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST, FRAME_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST, FRAME_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST, LINE_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST, LINE_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
end procedure setup_cmos_sensor_output_generator;
procedure sim_cmos_sensor_input is
procedure write_command_register(constant data : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_COMMAND_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST) <= data;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_command_register;
procedure write_config_register(constant irq : in boolean;
constant debayer_pattern : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_CONFIG_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata <= (others => '0');
if irq then
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE;
else
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE;
end if;
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST) <= debayer_pattern;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_config_register;
procedure read_frame_info_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_FRAME_INFO_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_frame_info_register;
procedure read_status_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_status_register;
procedure wait_until_idle is
variable end_loop : boolean := false;
begin
while not end_loop loop
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
if cmos_sensor_input_rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) = CMOS_SENSOR_INPUT_STATUS_STATE_IDLE then
end_loop := true;
end if;
end loop;
end procedure wait_until_idle;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
procedure noIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(false, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
wait_until_idle;
end procedure noIrq;
procedure withIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(true, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
end procedure withIrq;
begin
--noIrq;
withIrq;
end procedure sim_cmos_sensor_input;
begin
if configuration_valid then
async_reset;
setup_cmos_sensor_output_generator;
sim_cmos_sensor_input;
else
end if;
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_input_constants.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_input is
end tb_cmos_sensor_input;
architecture test of tb_cmos_sensor_input is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic;
signal reset : std_logic;
signal sim_finished : boolean := false;
-- simulation parameters ---------------------------------------------------
constant PIX_DEPTH : positive := 8;
constant SAMPLE_EDGE : string := "RISING";
constant MAX_WIDTH : positive := 1920;
constant MAX_HEIGHT : positive := 1080;
constant OUTPUT_WIDTH : positive := 32;
constant FIFO_DEPTH : positive := 32;
constant DEVICE_FAMILY : string := "Cyclone V";
constant DEBAYER_ENABLE : boolean := false;
constant PACKER_ENABLE : boolean := false;
constant DEBAYER_PATTERN : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB;
constant FRAME_WIDTH : positive := 5;
constant FRAME_HEIGHT : positive := 4;
constant FRAME_FRAME_BLANK : positive := 1;
constant FRAME_LINE_BLANK : natural := 1;
constant LINE_LINE_BLANK : positive := 1;
constant LINE_FRAME_BLANK : natural := 1;
constant BUS_BUSY_THRESHOLD : natural range 0 to 100 := 100;
-- cmos_sensor_output_generator --------------------------------------------
signal cmos_sensor_output_generator_addr : std_logic_vector(2 downto 0);
signal cmos_sensor_output_generator_read : std_logic;
signal cmos_sensor_output_generator_write : std_logic;
signal cmos_sensor_output_generator_rddata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_wrdata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_output_generator_frame_valid : std_logic;
signal cmos_sensor_output_generator_line_valid : std_logic;
signal cmos_sensor_output_generator_data : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- cmos_sensor_input -------------------------------------------------------
signal cmos_sensor_input_ready : std_logic;
signal cmos_sensor_input_valid : std_logic;
signal cmos_sensor_input_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal cmos_sensor_input_addr : std_logic_vector(1 downto 0);
signal cmos_sensor_input_read : std_logic;
signal cmos_sensor_input_write : std_logic;
signal cmos_sensor_input_rddata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_wrdata : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal cmos_sensor_input_irq : std_logic;
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
cmos_sensor_input_ready_generation : process
variable rand_gen : RandomPType;
variable rint : integer;
begin
rand_gen.InitSeed(rand_gen'instance_name);
rand_gen.SetRandomParm(UNIFORM);
while true loop
if not sim_finished then
wait until falling_edge(clk);
rint := rand_gen.RandInt(0, 100);
if rint < BUS_BUSY_THRESHOLD then
cmos_sensor_input_ready <= '0';
else
cmos_sensor_input_ready <= '1';
end if;
else
wait;
end if;
end loop;
end process cmos_sensor_input_ready_generation;
cmos_sensor_output_generator_inst : entity work.cmos_sensor_output_generator
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => clk,
reset => reset,
addr => cmos_sensor_output_generator_addr,
read => cmos_sensor_output_generator_read,
write => cmos_sensor_output_generator_write,
rddata => cmos_sensor_output_generator_rddata,
wrdata => cmos_sensor_output_generator_wrdata,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data => cmos_sensor_output_generator_data);
cmos_sensor_input_inst : entity work.cmos_sensor_input
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT,
OUTPUT_WIDTH => OUTPUT_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY,
DEBAYER_ENABLE => DEBAYER_ENABLE,
PACKER_ENABLE => PACKER_ENABLE)
port map(clk => clk,
reset => reset,
frame_valid => cmos_sensor_output_generator_frame_valid,
line_valid => cmos_sensor_output_generator_line_valid,
data_in => cmos_sensor_output_generator_data,
ready => cmos_sensor_input_ready,
valid => cmos_sensor_input_valid,
data_out => cmos_sensor_input_data_out,
addr => cmos_sensor_input_addr,
read => cmos_sensor_input_read,
write => cmos_sensor_input_write,
rddata => cmos_sensor_input_rddata,
wrdata => cmos_sensor_input_wrdata,
irq => cmos_sensor_input_irq);
sim : process
function configuration_valid return boolean is
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE : positive := 1 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE : positive := 2 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE : positive := 3 * PIX_DEPTH;
constant MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE : positive := 6 * PIX_DEPTH;
begin
if not ((1 <= PIX_DEPTH) and (PIX_DEPTH <= 32)) then
assert false
report "PIX_DEPTH must be in range {1:32}"
severity error;
return false;
end if;
if not ((SAMPLE_EDGE = "RISING") or (SAMPLE_EDGE = "FALLING")) then
assert false
report "SAMPLE_EDGE must be {RISING, FALLING}"
severity error;
return false;
end if;
if not ((2 <= MAX_WIDTH) and (MAX_WIDTH <= 65535)) then
assert false
report "MAX_WIDTH must be in range {2:65535}"
severity error;
return false;
end if;
if not ((1 <= MAX_HEIGHT) and (MAX_HEIGHT <= 65535)) then
assert false
report "MAX_HEIGHT must be in range {1:65535}"
severity error;
return false;
end if;
if not ((OUTPUT_WIDTH = 8) or (OUTPUT_WIDTH = 16) or (OUTPUT_WIDTH = 32) or (OUTPUT_WIDTH = 64) or (OUTPUT_WIDTH = 128) or (OUTPUT_WIDTH = 256) or (OUTPUT_WIDTH = 512) or (OUTPUT_WIDTH = 1024)) then
assert false
report "OUTPUT_WIDTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((FIFO_DEPTH = 8) or (FIFO_DEPTH = 16) or (FIFO_DEPTH = 32) or (FIFO_DEPTH = 64) or (FIFO_DEPTH = 128) or (FIFO_DEPTH = 256) or (FIFO_DEPTH = 512) or (FIFO_DEPTH = 1024)) then
assert false
report "FIFO_DEPTH must be {8, 16, 32, 64, 128, 256, 512, 1024}"
severity error;
return false;
end if;
if not ((DEVICE_FAMILY = "Cyclone IV E") or (DEVICE_FAMILY = "Cyclone V")) then
assert false
report "DEVICE_FAMILY must be {Cyclone IV E, Cyclone V}"
severity error;
return false;
end if;
if not DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_DISABLE_PACKER_ENABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_DISABLE)
severity error;
return false;
end if;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
if OUTPUT_WIDTH < MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE then
assert false
report "OUTPUT_WIDTH must be larger or equal to " & integer'image(MIN_OUTPUT_WIDTH_DEBAYER_ENABLE_PACKER_ENABLE)
severity error;
return false;
end if;
end if;
if not ((2 <= FRAME_WIDTH) and (FRAME_WIDTH <= MAX_WIDTH)) then
assert false
report "FRAME_WIDTH must be in range {1:" & integer'image(MAX_WIDTH) & "}"
severity error;
return false;
end if;
if not ((2 <= FRAME_HEIGHT) and (FRAME_HEIGHT <= MAX_HEIGHT)) then
assert false
report "FRAME_HEIGHT must be in range {1:" & integer'image(MAX_HEIGHT) & "}"
severity error;
return false;
end if;
return true;
end function configuration_valid;
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure setup_cmos_sensor_output_generator is
procedure write_register(constant ofst : in std_logic_vector;
constant val : in natural) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(to_unsigned(val, cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= ofst;
cmos_sensor_output_generator_write <= '1';
cmos_sensor_output_generator_wrdata <= std_logic_vector(resize(unsigned(val), cmos_sensor_output_generator_wrdata'length));
wait until falling_edge(clk);
cmos_sensor_output_generator_addr <= (others => '0');
cmos_sensor_output_generator_write <= '0';
cmos_sensor_output_generator_wrdata <= (others => '0');
end procedure write_register;
begin
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST, FRAME_WIDTH);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST, FRAME_HEIGHT);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST, FRAME_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST, FRAME_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST, LINE_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST, LINE_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
end procedure setup_cmos_sensor_output_generator;
procedure sim_cmos_sensor_input is
procedure write_command_register(constant data : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_COMMAND_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST) <= data;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_command_register;
procedure write_config_register(constant irq : in boolean;
constant debayer_pattern : in std_logic_vector) is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_CONFIG_OFST;
cmos_sensor_input_write <= '1';
cmos_sensor_input_wrdata <= (others => '0');
if irq then
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE;
else
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE;
end if;
cmos_sensor_input_wrdata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST) <= debayer_pattern;
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_write <= '0';
cmos_sensor_input_wrdata <= (others => '0');
end procedure write_config_register;
procedure read_frame_info_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_FRAME_INFO_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_frame_info_register;
procedure read_status_register is
begin
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
end procedure read_status_register;
procedure wait_until_idle is
variable end_loop : boolean := false;
begin
while not end_loop loop
wait until falling_edge(clk);
cmos_sensor_input_addr <= CMOS_SENSOR_INPUT_STATUS_OFST;
cmos_sensor_input_read <= '1';
wait until falling_edge(clk);
cmos_sensor_input_addr <= (others => '0');
cmos_sensor_input_read <= '0';
if cmos_sensor_input_rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) = CMOS_SENSOR_INPUT_STATUS_STATE_IDLE then
end_loop := true;
end if;
end loop;
end procedure wait_until_idle;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
procedure noIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(false, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
wait_until_idle;
end procedure noIrq;
procedure withIrq is
begin
write_command_register(CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET);
wait_until_idle;
write_config_register(true, DEBAYER_PATTERN);
wait_until_idle;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
read_frame_info_register;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT);
if cmos_sensor_input_irq = '0' then
wait until cmos_sensor_input_irq = '1';
end if;
write_command_register(CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK);
wait_until_idle;
end procedure withIrq;
begin
--noIrq;
withIrq;
end procedure sim_cmos_sensor_input;
begin
if configuration_valid then
async_reset;
setup_cmos_sensor_output_generator;
sim_cmos_sensor_input;
else
end if;
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of ram_1024_x_18 : label is "86B981F181098179A000871969276712680066C087C9663F68124D3967118779";
attribute INIT_02 of ram_1024_x_18 : label is "6712800287C966C0880148918002815187C966004899A178D301D201478980E8";
attribute INIT_03 of ram_1024_x_18 : label is "822B0D11800287C9680187C966C0680087C95341682687C96600524151396827";
attribute INIT_04 of ram_1024_x_18 : label is "823086B9842186B9831186B9828186B98779A0018002822882324D9082324D98";
attribute INIT_05 of ram_1024_x_18 : label is "690C671468088719690C670F68088719690C670A680887496914670A68086607";
attribute INIT_06 of ram_1024_x_18 : label is "670A681A87C967CA681987496911670D681D87496914670A6818660780028719";
attribute INIT_07 of ram_1024_x_18 : label is "87C96713681B87C96714681A87C96714681987C9670C681C87C9670B681B87C9";
attribute INIT_08 of ram_1024_x_18 : label is "87C9670B681087496914670A681587496914670A680F6607800287C96712681C";
attribute INIT_09 of ram_1024_x_18 : label is "681387C96710681387C9670F681287C9670E681287C9670D681187C9670C6811";
attribute INIT_0A of ram_1024_x_18 : label is "858987C9663F68124769CD014E69800287C96713681487C96712681487C96711";
attribute INIT_0B of ram_1024_x_18 : label is "6812670C8002858987C9663F681247698D014E69800287C96600681247718002";
attribute INIT_0C of ram_1024_x_18 : label is "85F185B186B98109854986B981098549800287C9660068126713800287C96600";
attribute INIT_0D of ram_1024_x_18 : label is "86D33C0086E3DB017B1FDC017CFFDD017DFFA00386B98109861985B186B98109";
attribute INIT_0E of ram_1024_x_18 : label is "6600800287534748870187C98901800287234848880187C98901800286C33D00";
attribute INIT_0F of ram_1024_x_18 : label is "2540A8090401041F053F454144398002878B0D1E8D0187196927680047696D00";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000080024692449045912580A82104018000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "8640000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000";
attribute INITP_01 of ram_1024_x_18 : label is "868138F3D089089222EED00000004FD3F43C84F10F213CF3CF3CF3CF3CFCFF4F";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000007F85";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"86B981F181098179A000871969276712680066C087C9663F68124D3967118779",
INIT_02 => X"6712800287C966C0880148918002815187C966004899A178D301D201478980E8",
INIT_03 => X"822B0D11800287C9680187C966C0680087C95341682687C96600524151396827",
INIT_04 => X"823086B9842186B9831186B9828186B98779A0018002822882324D9082324D98",
INIT_05 => X"690C671468088719690C670F68088719690C670A680887496914670A68086607",
INIT_06 => X"670A681A87C967CA681987496911670D681D87496914670A6818660780028719",
INIT_07 => X"87C96713681B87C96714681A87C96714681987C9670C681C87C9670B681B87C9",
INIT_08 => X"87C9670B681087496914670A681587496914670A680F6607800287C96712681C",
INIT_09 => X"681387C96710681387C9670F681287C9670E681287C9670D681187C9670C6811",
INIT_0A => X"858987C9663F68124769CD014E69800287C96713681487C96712681487C96711",
INIT_0B => X"6812670C8002858987C9663F681247698D014E69800287C96600681247718002",
INIT_0C => X"85F185B186B98109854986B981098549800287C9660068126713800287C96600",
INIT_0D => X"86D33C0086E3DB017B1FDC017CFFDD017DFFA00386B98109861985B186B98109",
INIT_0E => X"6600800287534748870187C98901800287234848880187C98901800286C33D00",
INIT_0F => X"2540A8090401041F053F454144398002878B0D1E8D0187196927680047696D00",
INIT_10 => X"0000000000000000000000000000000080024692449045912580A82104018000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"8640000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000",
INITP_01 => X"868138F3D089089222EED00000004FD3F43C84F10F213CF3CF3CF3CF3CFCFF4F",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000007F85",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
|
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NbcGieBDcw4HyyE8JFDr4tZoSisArNo6vuCRsvQSi+bai5x7H9vokhrFv2jic1+XINN8ys3vThOl
rTiebdQDFbr8PNRN73S7HT2g20UwHumct205MWBYviMn1PsurgkDnkBY1rEh9cdZR8mCvpeIlByf
1+0Vj9xKhw5JYJJLEiMeE39ndsNn4lRjOMIreqDzJRd+NoE+BKXYdnvbJJKq3ZFAw1UjBO9V2fiB
N6Sh4vdG84q3lHzn4AjwXOwRKRNf1KBHCy7bCzAeiuanMQAYfz8s3293zfeCRcJymrSwdvCKjl4Y
RMZnemjh7HolNBop6ZbTsdugBWVyvu3jafGW2gGa08GKtc25n29GVmEMhEhCgQvK+fO13qCji36s
xhk5WJeuoNLaZDrg5RwdARZS4TQcIGhc2cXnpK0ZizAYl37pafIIn6iqHnhG1qogQzMLuxaYmWn2
+l/yyGsDeE0WcJkqH8YyPpgyhbLmxhxcv6IYxavBNvzl+l2GMqkBHmsWEh/zP3vS0ymANeo5Sj52
Jjc63cM4egrDZP7LLbIj7TeohKp4ypiEA2OPt0vNqPuA2JRP88SLxwvcdZBtpybKg2hSl/KQRlBP
/7zm076kVftxsBXHU04OWSNsvzXBxgM4PTgwqvW3fqKYLMTgtGWDrU31VjQhntEaG5H1ER2dtCkB
p78y9axYOdAkeIas4MCABFQQLJZfwz7P6EDm6Tp0HvYMQnYFJXi4Bb66F8X9X0czG5ZRKeRJEFa6
/bKGYp+PBk+yF405KjZTbywdlgK7pvczRAoNWrMwUikAbOkKSmZY9uW7vha/uDLMKVaya+lCED3r
N07sQ3mPaXsYhHVXBR+whA3A1W34blXYRVMzcp9bq/rD2BamaZx6OpiMKkddgvaQawaQCOGXzJWJ
oOH51IzFho57HzLRspdnkijX22vEdMC1um84yAIRouERYDNeEwjKtmaGFnxbKvvsIp/Iy24yCigM
RizNlwZjE4kdLk9pzFdon974n0PoMuWkWZ7j/woN74QmgvdZ4fblpNlfT5uIwKUUM0bWNljryiDQ
yDiYWsfCZOkWZk4YmaaJ5vnx0/zmO8tS0iSkUMOqhm7ne2KwApiAVgPiI8ez2opbSIM8jznFOsWF
m9TDHUOXd3s0ZarxKjKDaFo=
`protect end_protected
|
entity tb_concat01 is
end tb_concat01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_concat01 is
signal a : std_logic_vector(15 downto 0);
begin
dut: entity work.concat01
port map (a);
process
begin
wait for 1 ns;
assert a = x"ab9e" severity failure;
wait;
end process;
end behav;
|
entity FIFO is
generic (
G_GEN1 : std_logic,
G_GEN2 : std_logic_vector(3 downto 0),
G_GEN3 : integer,
G_GEN4 : signed(15 downto 0),
G_GEN5 : unsigned(7 downto 0)
);
port (
I_PORT1 : in integer;
I_PORT2 : in std_logic;
I_PORTA : in t_user2;
I_PORT3 : in std_logic_vector(3 downto 0);
I_PORT4 : in signed(15 downto 0);
I_PORT5 : in unsigned(7 downto 0);
I_PORT6 : in std_ulogic;
I_PORT7 : in t_user1
);
end entity FIFO;
architecture rtl of fifo is
signal my_sig : std_logic;
constant my_con : std_logic_vector(3 downto 0);
procedure my_proc (
init : in std_logic
) is
variable my_sig : std_logic;
constant my_con : std_logic_vector(3 downto 0);
begin
end procedure;
component MY_COMP is
generic (
G_GEN1 : std_logic,
G_GEN2 : std_logic_vector(3 downto 0),
G_GEN3 : integer,
G_GEN4 : signed(15 downto 0),
G_GEN5 : unsigned(7 downto 0)
);
port (
I_PORT1 : in integer;
I_PORT2 : in std_logic;
I_PORTA : in t_user2;
I_PORT3 : in std_logic_vector(3 downto 0);
I_PORT4 : in signed(15 downto 0);
I_PORT5 : in unsigned(7 downto 0);
I_PORT6 : in std_ulogic;
I_PORT7 : in t_user1
);
end component;
begin
end architecture rtl;
--====== UPPERCASE before
entity FIFO is
generic (
G_GEN1 : STD_LOGIC,
G_GEN2 : STD_LOGIC_VECTOR(3 downto 0),
G_GEN3 : INTEGER,
G_GEN4 : SIGNED(15 downto 0),
G_GEN5 : UNSIGNED(7 downto 0)
);
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end entity FIFO;
architecture rtl of fifo is
signal my_sig : STD_LOGIC;
constant my_con : STD_LOGIC_VECTOR(3 downto 0);
procedure my_proc (
init : in STD_LOGIC
) is
variable my_sig : STD_LOGIC;
constant my_con : STD_LOGIC_VECTOR(3 downto 0);
begin
end procedure;
component MY_COMP is
generic (
G_GEN1 : STD_LOGIC,
G_GEN2 : STD_LOGIC_VECTOR(3 downto 0),
G_GEN3 : INTEGER,
G_GEN4 : SIGNED(15 downto 0),
G_GEN5 : UNSIGNED(7 downto 0)
);
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end component;
begin
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
ENTITY fifo_rx_tb IS
END ENTITY;
ARCHITECTURE fifo_rx_arch OF fifo_rx_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fifo_rx_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fifo_rx_synth
fifo_rx_synth_inst:fifo_rx_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 28
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file memory.vhd when simulating
-- the core, memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END memory;
ARCHITECTURE memory_a OF memory IS
-- synthesis translate_off
COMPONENT wrapped_memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 256,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END memory_a;
|
-- $Id: pdp11_sequencer.vhd 1321 2022-11-24 15:06:47Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sequencer - syn
-- Description: pdp11: CPU sequencer
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode
-- 2022-11-21 1320 1.6.19 rename some rsv->ser and cpustat_type trap_->treq_;
-- remove vm_cntl_type.trap_done;
-- BUGFIX: correct ysv flow implementation
-- 2022-11-18 1316 1.6.18 BUGFIX: use is_kstackdst1246 also in dstr flow
-- 2022-10-29 1312 1.6.17 rename s_int_* -> s_vec_*, s_trap_* -> s_abort_*
-- 2022-10-25 1309 1.6.16 rename _gpr -> _gr
-- 2022-10-03 1301 1.6.15 finalize fix for I space mode=1 in s_dstr_def
-- 2022-09-08 1296 1.6.14 BUGFIX: use I space for all mode=1,2,3 if reg=pc
-- 2022-08-13 1279 1.6.13 ssr->mmr rename
-- 2019-08-17 1203 1.6.12 fix for ghdl V0.36 -Whide warnings
-- 2018-10-07 1054 1.6.11 drop ITIMER, use DM_STAT_SE.itimer
-- 2018-10-06 1053 1.6.10 add DM_STAT_SE.(cpbusy,idec,pcload)
-- 2017-04-23 885 1.6.9 not sys_conf_dmscnt: set SNUM from state category;
-- change waitsusp logic; add WAIT to idm_idone
-- 2016-12-27 831 1.6.8 CPUERR now cleared with creset
-- 2016-10-03 812 1.6.7 always define DM_STAT_SE.snum
-- 2016-05-26 768 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- proc_snum conditional (vivado fsm workaround)
-- 2015-08-02 708 1.6.5 BUGFIX: proper trap_mmu and trap_ysv handling
-- 2015-08-01 707 1.6.4 set dm_idone in s_(trap_10|op_trap); add dm_vfetch
-- 2015-07-19 702 1.6.3 add DM_STAT_SE, drop SNUM port
-- 2015-07-10 700 1.6.2 use c_cpurust_hbpt
-- 2015-06-26 695 1.6.1 add SNUM (state number) port
-- 2015-05-10 678 1.6 start/stop/suspend overhaul; reset overhaul
-- 2015-02-07 643 1.5.2 s_op_wait: load R0 in DSRC for DR emulation
-- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit;
-- use DP_STAT.div_quit; set munit_s_div_sr;
-- BUGFIX: s_opg_div_sr: check for late div_quit
-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
-- CNTL.cpdout_we instead of CPDOUT_WE
-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.2.6 BUGFIX: use is_kstackdst1246, stklim for mode=6
-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
-- 2008-12-13 176 1.2.2 BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; prevent stale DSRC
-- 2008-08-22 161 1.2 rename ubf_ -> ibf_; use iblib
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust; cp reset sets now
-- c_cpurust_reset; proper c_cpurust_vfail handling
-- 2008-04-27 140 1.1.8 BUGFIX: halt cpu in case of a vector fetch error
-- use cpursta to encode why cpu halts, remove cpufail
-- 2008-04-27 139 1.1.7 BUGFIX: correct bytop handling for address fetches;
-- BUGFIX: redo mtp flow; add fork_dsta fork and ddst
-- reload in s_opa_mtp_pop_w;
-- 2008-04-19 137 1.1.6 BUGFIX: fix loop state in s_rti_getpc_w
-- 2008-03-30 131 1.1.5 BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+
-- inc/dec by 2 for @(R)+ and @-(R) also for bytop's
-- 2008-03-02 121 1.1.4 remove snoopers; add waitsusp, redo WAIT handling
-- 2008-02-24 119 1.1.3 add lah,rps,wps command; revamp cp memory access
-- change WAIT logic, now also bails out on cp command
-- 2008-01-20 112 1.1.2 rename PRESET->BRESET
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_sequencer is -- CPU sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
INT_ACK : out slbit; -- interrupt acknowledge
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_SE : out dm_stat_se_type -- debug and monitor status - sequencer
);
end pdp11_sequencer;
architecture syn of pdp11_sequencer is
constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
constant cpuerr_ibf_illhlt : integer := 7;
constant cpuerr_ibf_adderr : integer := 6;
constant cpuerr_ibf_nxm : integer := 5;
constant cpuerr_ibf_iobto : integer := 4;
constant cpuerr_ibf_ysv : integer := 3;
constant cpuerr_ibf_rsv : integer := 2;
type state_type is (
s_idle,
s_cp_regread,
s_cp_rps,
s_cp_memr_w,
s_cp_memw_w,
s_ifetch,
s_ifetch_w,
s_idecode,
s_srcr_def,
s_srcr_def_w,
s_srcr_inc,
s_srcr_inc_w,
s_srcr_dec,
s_srcr_dec1,
s_srcr_ind,
s_srcr_ind1_w,
s_srcr_ind2,
s_srcr_ind2_w,
s_dstr_def,
s_dstr_def_w,
s_dstr_inc,
s_dstr_inc_w,
s_dstr_dec,
s_dstr_dec1,
s_dstr_ind,
s_dstr_ind1_w,
s_dstr_ind2,
s_dstr_ind2_w,
s_dstw_def,
s_dstw_def_w,
s_dstw_inc,
s_dstw_inc_w,
s_dstw_incdef_w,
s_dstw_dec,
s_dstw_dec1,
s_dstw_ind,
s_dstw_ind_w,
s_dstw_def246,
s_dsta_inc,
s_dsta_incdef_w,
s_dsta_dec,
s_dsta_dec1,
s_dsta_ind,
s_dsta_ind_w,
s_op_halt,
s_op_wait,
s_op_trap,
s_op_reset,
s_op_rts,
s_op_rts_pop,
s_op_rts_pop_w,
s_op_spl,
s_op_mcc,
s_op_br,
s_op_mark,
s_op_mark1,
s_op_mark_pop,
s_op_mark_pop_w,
s_op_sob,
s_op_sob1,
s_opg_gen,
s_opg_gen_rmw_w,
s_opg_mul,
s_opg_mul1,
s_opg_div,
s_opg_div_cn,
s_opg_div_cr,
s_opg_div_sq,
s_opg_div_sr,
s_opg_div_quit,
s_opg_ash,
s_opg_ash_cn,
s_opg_ashc,
s_opg_ashc_cn,
s_opg_ashc_wl,
s_opa_jsr,
s_opa_jsr1,
s_opa_jsr_push,
s_opa_jsr_push_w,
s_opa_jsr2,
s_opa_jmp,
s_opa_mtp,
s_opa_mtp_pop_w,
s_opa_mtp_reg,
s_opa_mtp_mem,
s_opa_mtp_mem_w,
s_opa_mfp_reg,
s_opa_mfp_mem,
s_opa_mfp_mem_w,
s_opa_mfp_dec,
s_opa_mfp_push,
s_opa_mfp_push_w,
s_abort_4,
s_abort_10,
s_trap_disp,
s_int_ext,
s_vec_getpc,
s_vec_getpc_w,
s_vec_getps,
s_vec_getps_w,
s_vec_getsp,
s_vec_decsp,
s_vec_pushps,
s_vec_pushps_w,
s_vec_pushpc,
s_vec_pushpc_w,
s_rti_getpc,
s_rti_getpc_w,
s_rti_getps,
s_rti_getps_w,
s_rti_newpc,
s_vmerr,
s_cpufail
);
signal R_STATE : state_type := s_idle;-- state register
signal N_STATE : state_type; -- don't init (vivado fix for fsm infer)
attribute fsm_encoding : string;
attribute fsm_encoding of R_STATE : signal is "one_hot";
signal R_STATUS : cpustat_type := cpustat_init;
signal N_STATUS : cpustat_type := cpustat_init;
signal R_CPUERR : cpuerr_type := cpuerr_init;
signal N_CPUERR : cpuerr_type := cpuerr_init;
signal R_IDSTAT : decode_stat_type := decode_stat_init;
signal N_IDSTAT : decode_stat_type := decode_stat_init;
signal R_VMSTAT : vm_stat_type := vm_stat_init;
signal IBSEL_CPUERR : slbit := '0';
signal VM_CNTL_L : vm_cntl_type := vm_cntl_init;
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_cpuerr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_CPUERR
);
proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_CPUERR = '1' then
idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_status: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATUS <= cpustat_init;
R_IDSTAT <= decode_stat_init;
R_VMSTAT <= vm_stat_init;
else
R_STATUS <= N_STATUS;
R_IDSTAT <= N_IDSTAT;
R_VMSTAT <= VM_STAT;
end if;
end if;
end process proc_status;
-- ensure that CPUERR is reset with GRESET and CRESET
proc_cpuerr: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' or R_STATUS.creset = '1' then
R_CPUERR <= cpuerr_init;
else
R_CPUERR <= N_CPUERR;
end if;
end if;
end process proc_cpuerr;
proc_state: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATE <= s_idle;
else
R_STATE <= N_STATE;
end if;
end if;
end process proc_state;
proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,
ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
INT_PRI, INT_VECT, ESUSP_I, HBPT)
variable nstate : state_type;
variable nstatus : cpustat_type := cpustat_init;
variable ncpuerr : cpuerr_type := cpuerr_init;
variable ndpcntl : dpath_cntl_type := dpath_cntl_init;
variable nvmcntl : vm_cntl_type := vm_cntl_init;
variable nidstat : decode_stat_type := decode_stat_init;
variable nmmumoni : mmu_moni_type := mmu_moni_init;
variable imemok : boolean;
variable bytop : slbit := '0'; -- local bytop access flag
variable macc : slbit := '0'; -- local modify access flag
variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector
variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)
variable brcond : slbit := '0'; -- br condition value
variable is_kmode : slbit := '0'; -- cmode is kernel mode
variable is_kstackdst1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
variable int_pending : slbit := '0'; -- an interrupt is pending
variable idm_idle : slbit := '0'; -- idle for dm_stat_se
variable idm_cpbusy : slbit := '0'; -- cpbusy for dm_stat_se
variable idm_idec : slbit := '0'; -- idec for dm_stat_se
variable idm_idone : slbit := '0'; -- idone for dm_stat_se
variable idm_pcload : slbit := '0'; -- pcload for dm_stat_se
variable idm_vfetch : slbit := '0'; -- vfetch for dm_stat_se
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
procedure do_memread_i(pnstate : inout state_type;
pndpcntl : inout dpath_cntl_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type) is
begin
pndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
pnvmcntl.dspace := '0';
pnvmcntl.req := '1';
pndpcntl.gr_pcinc := '1'; -- (pc)++
pnstate := pwstate;
end procedure do_memread_i;
procedure do_memread_d(pnstate : inout state_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type;
pbytop : in slbit := '0';
pmacc : in slbit := '0';
pispace : in slbit := '0';
kstack : in slbit := '0') is
begin
pnvmcntl.dspace := not pispace;
-- bytop := R_IDSTAT.is_bytop and not is_addr;
pnvmcntl.bytop := pbytop;
pnvmcntl.macc := pmacc;
pnvmcntl.kstack := kstack;
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memread_d;
procedure do_memread_srcinc(pnstate : inout state_type;
pndpcntl : inout dpath_cntl_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type;
pnmmumoni : inout mmu_moni_type;
pupdt_sp : in slbit := '0') is
begin
pndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
pndpcntl.ounit_const := "000000010"; -- OUNIT const=2
pndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
pndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
pndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
pndpcntl.dsrc_we := '1'; -- update DSRC
if pupdt_sp = '1' then
pnmmumoni.regmod := '1';
pnmmumoni.isdec := '0';
pndpcntl.gr_adst := c_gr_sp; -- update SP too
pndpcntl.gr_we := '1';
end if;
pndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
pnvmcntl.dspace := '1';
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memread_srcinc;
procedure do_memwrite(pnstate : inout state_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type;
pmacc : in slbit :='0';
pispace : in slbit := '0') is
begin
pnvmcntl.dspace := not pispace;
pnvmcntl.bytop := R_IDSTAT.is_bytop;
pnvmcntl.wacc := '1';
pnvmcntl.macc := pmacc;
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memwrite;
procedure do_memcheck(pnstate : inout state_type;
pnstatus : inout cpustat_type;
pmok : out boolean) is
begin
pnstate := pnstate; -- dummy to add driver (vivado)
pnstatus := pnstatus; -- "
pmok := false;
if VM_STAT.ack = '1' then
pmok := true;
if VM_STAT.trap_mmu = '1' then -- remember trap_mmu, may happen on any
pnstatus.treq_mmu := '1'; -- memory access of an instruction
end if;
if VM_STAT.trap_ysv = '1' then -- remember trap_ysv (on final writes)
if R_STATUS.in_vecysv = '0' then -- trap when not in ysv vector flow
pnstatus.treq_ysv := '1';
end if;
end if;
elsif VM_STAT.err='1' or VM_STAT.fail='1' then
pnstate := s_vmerr;
end if;
end procedure do_memcheck;
procedure do_const_opsize(pndpcntl : inout dpath_cntl_type;
pbytop : in slbit;
pisdef : in slbit;
pregnum : in slv3) is
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
if pbytop='0' or pisdef='1' or
pregnum=c_gr_pc or pregnum=c_gr_sp then
pndpcntl.ounit_const := "000000010";
else
pndpcntl.ounit_const := "000000001";
end if;
end procedure do_const_opsize;
procedure do_fork_dstr(pnstate : inout state_type;
pidstat : in decode_stat_type) is
begin
case pidstat.fork_dstr is
when c_fork_dstr_def => pnstate := s_dstr_def;
when c_fork_dstr_inc => pnstate := s_dstr_inc;
when c_fork_dstr_dec => pnstate := s_dstr_dec;
when c_fork_dstr_ind => pnstate := s_dstr_ind;
when others => pnstate := s_cpufail;
end case;
end procedure do_fork_dstr;
procedure do_fork_opg(pnstate : inout state_type;
pidstat : in decode_stat_type) is
begin
case pidstat.fork_opg is
when c_fork_opg_gen => pnstate := s_opg_gen;
when c_fork_opg_wdef => pnstate := s_dstw_def;
when c_fork_opg_winc => pnstate := s_dstw_inc;
when c_fork_opg_wdec => pnstate := s_dstw_dec;
when c_fork_opg_wind => pnstate := s_dstw_ind;
when c_fork_opg_mul => pnstate := s_opg_mul;
when c_fork_opg_div => pnstate := s_opg_div;
when c_fork_opg_ash => pnstate := s_opg_ash;
when c_fork_opg_ashc => pnstate := s_opg_ashc;
when others => pnstate := s_cpufail;
end case;
end procedure do_fork_opg;
procedure do_fork_opa(pnstate : inout state_type;
pidstat : in decode_stat_type) is
begin
case pidstat.fork_opa is
when c_fork_opa_jmp => pnstate := s_opa_jmp;
when c_fork_opa_jsr => pnstate := s_opa_jsr;
when c_fork_opa_mtp => pnstate := s_opa_mtp_mem;
when c_fork_opa_mfp_reg => pnstate := s_opa_mfp_reg;
when c_fork_opa_mfp_mem => pnstate := s_opa_mfp_mem;
when others => pnstate := s_cpufail;
end case;
end procedure do_fork_opa;
procedure do_fork_next(pnstate : inout state_type;
pnstatus : inout cpustat_type;
pnmmumoni : inout mmu_moni_type) is
begin
pnmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
pnstate := s_idle;
elsif R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or
R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or
PSW.tflag='1' then
pnstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and -- running
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
pnstate := s_ifetch; -- fetch next
else
pnstate := s_idle; -- otherwise idle
end if;
end procedure do_fork_next;
procedure do_fork_next_pref(pnstate : inout state_type;
pnstatus : inout cpustat_type;
pndpcntl : inout dpath_cntl_type;
pnvmcntl : inout vm_cntl_type;
pnmmumoni : inout mmu_moni_type) is
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
pnvmcntl := pnvmcntl; -- "
pnmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
pnstate := s_idle;
elsif R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or
R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or
PSW.tflag='1' then
pnstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and -- running
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
pnvmcntl.req := '1'; -- read next instruction
pndpcntl.gr_pcinc := '1' ; -- inc PC
pnmmumoni.istart := '1'; -- signal istart to MMU
pnstate := s_ifetch_w; -- next: wait for fetched instruction
else
pnstate := s_idle; -- otherwise idle
end if;
end procedure do_fork_next_pref;
procedure do_start_vec(pnstate : inout state_type;
pndpcntl : inout dpath_cntl_type;
pvector : in slv9_2) is
begin
pndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
pndpcntl.dtmp_we := '1';
pndpcntl.ounit_azero := '1'; -- OUNIT A = 0
pndpcntl.ounit_const := pvector & "00"; -- vector
pndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
pndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
pndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
pndpcntl.dsrc_we := '1'; -- DSRC = vector
pnstate := s_vec_getpc;
end procedure do_start_vec;
begin
nstate := R_STATE;
nstatus := R_STATUS;
ncpuerr := R_CPUERR;
nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait
-- itimer pulse logic:
-- if neither running nor suspended --> free run, set itimer = 1
-- otherwise clear to ensure single cycle pulses generated by
-- s_idecode or s_op_wait
if R_STATUS.cpugo='0' and R_STATUS.cpususp='0' then
nstatus.itimer := '1';
else
nstatus.itimer := '0';
end if;
nstatus.creset := '0'; -- ensure single cycle pulse
nstatus.breset := '0'; -- dito
nstatus.intack := '0'; -- dito
nidstat := R_IDSTAT;
if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
ncpuerr := cpuerr_init;
end if;
int_pending := '0';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
int_pending := '1';
end if;
nstatus.intpend := int_pending;
idm_idle := '0';
idm_cpbusy := '0';
idm_idec := '0';
idm_idone := '0';
idm_pcload := '0';
idm_vfetch := '0';
imemok := false;
nmmumoni := mmu_moni_init;
nmmumoni.pc := PC;
macc := '0';
bytop := '0';
brcode := IREG(15) & IREG(10 downto 8);
brcond := '1';
is_kmode := '0';
is_kstackdst1246 := '0';
if PSW.cmode = c_psw_kmode then
is_kmode := '1';
if DSTREG = c_gr_sp and
(DSTMODF="001" or DSTMODF="010" or
DSTMODF="100" or DSTMODF="110") then
is_kstackdst1246 := '1';
end if;
end if;
lvector := (others=>'0');
nvmcntl := vm_cntl_init;
nvmcntl.dspace := '1'; -- DEFAULT
nvmcntl.mode := PSW.cmode; -- DEFAULT
nvmcntl.vecser := R_STATUS.in_vecser; -- DEFAULT
ndpcntl := dpath_cntl_init;
ndpcntl.gr_asrc := SRCREG; -- DEFAULT
ndpcntl.gr_adst := DSTREG; -- DEFAULT
ndpcntl.gr_mode := PSW.cmode; -- DEFAULT
ndpcntl.gr_rset := PSW.rset; -- DEFAULT
ndpcntl.gr_we := '0'; -- DEFAULT
ndpcntl.gr_bytop := '0'; -- DEFAULT
ndpcntl.gr_pcinc := '0'; -- DEFAULT
ndpcntl.psr_ccwe := '0'; -- DEFAULT
ndpcntl.psr_we := '0'; -- DEFAULT
ndpcntl.psr_func := "000"; -- DEFAULT
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '0';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '0';
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '0';
ndpcntl.ounit_asel := c_ounit_asel_ddst;
ndpcntl.ounit_azero := '0'; -- DEFAULT
ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
ndpcntl.ounit_bsel := c_ounit_bsel_const;
ndpcntl.ounit_opsub := '0'; -- DEFAULT
ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
ndpcntl.ireg_we := '0';
ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
ndpcntl.dres_sel := c_dpath_res_ounit;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
nstatus.cmdbusy := '1';
nstatus.cpfunc := CP_CNTL.func;
nstatus.cprnum := CP_CNTL.rnum;
end if;
if R_STATUS.cmdack = '1' then
nstatus.cmdack := '0';
nstatus.cmderr := '0';
nstatus.cmdmerr := '0';
end if;
case R_STATE is
-- idle and command port states ---------------------------------------------
when s_idle => -- ------------------------------------
-- Note: s_idle was entered from suspended WAIT when waitsusp='1'
-- --> all exits must check this and either return to s_op_wait
-- or abort the WAIT and set waitsusp='0'
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST (do mux early)
nstatus.cpustep := '0';
idm_idle := '1'; -- signal sequencer idle
if R_STATUS.cmdbusy = '1' then
idm_cpbusy := '1'; -- signal cp busy
case R_STATUS.cpfunc is
when c_cpfunc_noop => -- noop : no operation -------
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_start => -- start : cpu start ---------
nstatus.cmdack := '1';
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.cpugo := '1'; -- start cpu
nstatus.cpurust := c_cpurust_runs;
nstatus.waitsusp := '0';
end if;
nstate := s_idle;
when c_cpfunc_stop => -- stop : cpu stop -----------
nstatus.cmdack := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_stop;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_step => -- step : cpu step -----------
nstatus.cmdack := '1';
nstatus.cpustep := '1';
nstatus.cpurust := c_cpurust_step;
nstatus.waitsusp := '0';
if int_pending = '1' then
nstatus.intack := '1';
nstatus.intvect := INT_VECT;
nstate := s_int_ext;
else
nstate := s_ifetch;
end if;
when c_cpfunc_creset => -- creset : cpu reset --------
nstatus.cmdack := '1';
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.creset := '1'; -- do cpu reset
nstatus.breset := '1'; -- and bus reset !
nstatus.suspint := '0'; -- clear suspend
nstatus.cpurust := c_cpurust_init;
end if;
nstate := s_idle;
when c_cpfunc_breset => -- breset : bus reset --------
nstatus.cmdack := '1';
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.breset := '1'; -- do bus reset only
end if;
nstate := s_idle;
when c_cpfunc_suspend => -- suspend : cpu suspend -----
nstatus.cmdack := '1';
nstatus.suspint := '1';
nstatus.cpurust := c_cpurust_susp;
nstate := s_idle;
when c_cpfunc_resume => -- resume : cpu resume -------
nstatus.cmdack := '1';
nstatus.suspint := '0';
if R_STATUS.cpugo = '1' then
nstatus.cpurust := c_cpurust_runs;
else
nstatus.cpurust := c_cpurust_stop;
end if;
nstate := s_idle;
when c_cpfunc_rreg => -- rreg : read register ------
ndpcntl.gr_adst := R_STATUS.cprnum;
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_cp_regread;
when c_cpfunc_wreg => -- wreg : write register -----
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.gr_adst := R_STATUS.cprnum;
ndpcntl.gr_we := '1';
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rpsw => -- rpsw : read psw -----------
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
nstate := s_cp_rps;
when c_cpfunc_wpsw => -- wpsw : write psw ----------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
ndpcntl.psr_we := '1'; -- load new PS
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rmem => -- rmem : read memory --------
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memr_w;
when c_cpfunc_wmem => -- wmem : write memory -------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
nvmcntl.wacc := '1'; -- write mem
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memw_w;
when others =>
nstatus.cmdack := '1';
nstatus.cmderr := '1';
nstate := s_idle;
end case;
elsif R_STATUS.waitsusp = '1' then
nstate := s_op_wait; --waitsusp is cleared in s_op_wait
elsif R_STATUS.cpugo = '1' and -- running
R_STATUS.cpususp='0' then -- and not suspended
if int_pending = '1' then -- interrupt pending
nstatus.intack := '1'; -- acknowledle it
nstatus.intvect := INT_VECT; -- latch vector address
nstate := s_int_ext; -- and handle
else
nstate := s_ifetch; -- otherwise fetch intruction
end if;
end if;
when s_cp_regread => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_rps => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_memr_w => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
nstate := s_cp_memr_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.treq_ysv := '0'; -- suppress traps on console
nstatus.treq_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
when s_cp_memw_w => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
nstate := s_cp_memw_w;
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.treq_ysv := '0'; -- suppress traps on console
nstatus.treq_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
-- instruction fetch and decode ---------------------------------------------
when s_ifetch => -- -----------------------------------
nmmumoni.istart := '1'; -- do here; memread_i inc PC !
do_memread_i(nstate, ndpcntl, nvmcntl, s_ifetch_w);
when s_ifetch_w => -- -----------------------------------
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
when s_idecode => -- -----------------------------------
idm_idec := '1'; -- signal instruction started
nstatus.itimer := '1'; -- itimer counts each decode
nidstat := ID_STAT; -- register decode status
if ID_STAT.force_srcsp = '1' then
ndpcntl.gr_asrc := c_gr_sp;
end if;
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nvmcntl.dspace := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
-- The prefetch decision path can be critical (and was on s3).
-- It uses R_STATUS.intpend instead of int_pending, using the status
-- latched at the previous state is OK. It uses R_STATUS.treq_mmu
-- because no MMU trap can occur during this state (only in *_w states).
-- It does not check treq_ysv because pipelined instructions can't
-- trigger ysv traps, in contrast to MMU traps.
if ID_STAT.do_pref_dec='1' and -- prefetch possible
PSW.tflag='0' and -- no tbit traps
R_STATUS.intpend='0' and -- no interrupts
R_STATUS.treq_mmu='0' and -- no MMU trap request
R_STATUS.cpugo='1' and -- CPU on go
R_STATUS.cpususp='0' and -- CPU not suspended
not R_STATUS.cmdbusy='1' -- and no command pending
then -- then go for prefetch
nvmcntl.req := '1';
ndpcntl.gr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
end if;
if ID_STAT.do_fork_op = '1' then
case ID_STAT.fork_op is
when c_fork_op_halt => nstate := s_op_halt;
when c_fork_op_wait => nstate := s_op_wait;
when c_fork_op_rtti => nstate := s_rti_getpc;
when c_fork_op_trap => nstate := s_op_trap;
when c_fork_op_reset=> nstate := s_op_reset;
when c_fork_op_rts => nstate := s_op_rts;
when c_fork_op_spl => nstate := s_op_spl;
when c_fork_op_mcc => nstate := s_op_mcc;
when c_fork_op_br => nstate := s_op_br;
when c_fork_op_mark => nstate := s_op_mark;
when c_fork_op_sob => nstate := s_op_sob;
when c_fork_op_mtp => nstate := s_opa_mtp;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_srcr = '1' then
case ID_STAT.fork_srcr is
when c_fork_srcr_def => nstate := s_srcr_def;
when c_fork_srcr_inc => nstate := s_srcr_inc;
when c_fork_srcr_dec => nstate := s_srcr_dec;
when c_fork_srcr_ind => nstate := s_srcr_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, ID_STAT);
elsif ID_STAT.do_fork_dsta = '1' then
case ID_STAT.fork_dsta is -- 2nd dsta fork in s_opa_mtp_pop_w
when c_fork_dsta_def => do_fork_opa(nstate, ID_STAT);
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_opg = '1' then
do_fork_opg(nstate, ID_STAT);
elsif ID_STAT.is_res = '1' then
nstate := s_abort_10; -- do vector 10 abort;
else
nstate := s_cpufail; -- catch mistakes here...
end if;
-- source read states -------------------------------------------------------
-- flows:
-- 1 (r) s_srcr_def req (r)
-- s_srcr_def_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 2 (r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 3 @(r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 4 -(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 5 @-(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 6 n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 7 @n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- s_srcr_def req @n(r)
-- s_srcr_def_w get @n(r)
-- -> do_fork_dstr or do_fork_opg
when s_srcr_def => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
do_memread_d(nstate, nvmcntl, s_srcr_def_w,
pbytop=>R_IDSTAT.is_bytop,
pispace=>R_IDSTAT.is_srcpcmode1);
when s_srcr_def_w => -- -----------------------------------
nstate := s_srcr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_srcr_inc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w,
pbytop=>bytop, pispace=>R_IDSTAT.is_srcpc);
when s_srcr_inc_w => -- -----------------------------------
nstate := s_srcr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
when s_srcr_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
nstate := s_srcr_dec1;
when s_srcr_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w, pbytop=>bytop);
when s_srcr_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_srcr_ind1_w);
when s_srcr_ind1_w => -- -----------------------------------
nstate := s_srcr_ind1_w;
if R_IDSTAT.is_srcpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.ddst_we := '1'; -- update DDST (to reload PC)
nstate := s_srcr_ind2;
end if;
when s_srcr_ind2 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_ind2_w, pbytop=>bytop);
when s_srcr_ind2_w => -- -----------------------------------
nstate := s_srcr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
-- destination read states --------------------------------------------------
-- flows:
-- 1 (r) s_dstr_def req (r) (rmw if rmw op)
-- s_dstr_def_w get (r)
-- -> do_fork_opg
--
-- 2 (r)+ s_dstr_inc req (r); r+=s (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 3 @(r)+ s_dstr_inc req (r); r+=s
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 4 -(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r) (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 5 @-(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r)
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 6 n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r) (rmw if rmw op)
-- s_dstr_ind2_w get n(r)
-- -> do_fork_opg
--
-- 7 @n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r)
-- s_dstr_ind2_w get n(r)
-- s_dstr_def req @n(r) (rmw if rmw op)
-- s_dstr_def_w get @n(r)
-- -> do_fork_opg
when s_dstr_def => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memread_d(nstate, nvmcntl, s_dstr_def_w,
pbytop=>R_IDSTAT.is_bytop, pmacc=>R_IDSTAT.is_rmwop,
pispace=>R_IDSTAT.is_dstpcmode1,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_def_w => -- -----------------------------------
nstate := s_dstr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opg(nstate, R_IDSTAT);
end if;
when s_dstr_inc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_inc_w => -- -----------------------------------
nstate := s_dstr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_dstr_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstr_dec1;
when s_dstr_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
pbytop=>bytop, pmacc=>macc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
when s_dstr_ind1_w => -- -----------------------------------
nstate := s_dstr_ind1_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstr_ind2;
end if;
when s_dstr_ind2 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
pbytop=>bytop, pmacc=>macc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_ind2_w => -- -----------------------------------
nstate := s_dstr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
-- destination write states -------------------------------------------------
-- flows:
-- 1 (r) s_dstw_def wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 2 (r)+ s_dstw_inc wreq (r) check kstack
-- s_dstw_inc_w ack (r); r+=s
-- -> do_fork_next
--
-- 3 @(r)+ s_dstw_inc rreq (r); r+=s
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 4 -(r) s_dstw_dec r-=s
-- s_dstw_dec1 wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 5 @-(r) s_dstw_dec r-=s
-- s_dstw_dec1 rreq (r)
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 6 n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 wreq n(r) check kstack
-- s_dstw_def_w ack n(r)
-- -> do_fork_next
--
-- 7 @n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 rreq n(r)
-- s_dstw_incdef_w get n(r)
-- s_dstw_def246 wreq @n(r)
-- s_dstw_def_w ack @n(r)
-- -> do_fork_next
when s_dstw_def => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
nvmcntl.kstack := is_kstackdst1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w, pispace=>R_IDSTAT.is_dstpc);
when s_dstw_def_w => -- -----------------------------------
nstate := s_dstw_def_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_dstw_inc => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
if DSTDEF = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
nvmcntl.kstack := is_kstackdst1246;
do_memwrite(nstate, nvmcntl, s_dstw_inc_w, pispace=>R_IDSTAT.is_dstpc);
nstatus.do_grwe := '1';
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
pispace=>R_IDSTAT.is_dstpc);
end if;
when s_dstw_inc_w => -- -----------------------------------
nstate := s_dstw_inc_w;
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
if R_STATUS.do_grwe = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
nmmumoni.trace_prev := '1'; -- mmr freeze of prev state
ndpcntl.gr_we := '1'; -- update DST reg
end if;
nstatus.do_grwe := '0';
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_dstw_incdef_w => -- -----------------------------------
nstate := s_dstw_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_def246;
end if;
when s_dstw_dec => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstw_dec1;
when s_dstw_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
if DSTDEF = '0' then
nvmcntl.kstack := is_kstackdst1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
else
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
end if;
when s_dstw_ind => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstw_ind_w);
when s_dstw_ind_w => -- -----------------------------------
nstate := s_dstw_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_dec1;
end if;
when s_dstw_def246 => -- -----------------------------------
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
-- destination address states -----------------------------------------------
-- flows:
-- 1 (r) -> do_fork_opa
--
-- 2 (r)+ s_dsta_inc r+=2
-- -> do_fork_opa
--
-- 3 @(r)+ s_dsta_inc req (r); r+=s
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 4 -(r) s_dsta_dec r-=s
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 5 @-(r) s_dsta_dec r-=s
-- s_dsta_dec1 req (r)
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 6 n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 7 @n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 req n(r)
-- s_dsta_incdef_w get n(r)
-- -> do_fork_opa
when s_dsta_inc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then
do_fork_opa(nstate, R_IDSTAT);
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w,
pispace=>R_IDSTAT.is_dstpc);
end if;
when s_dsta_incdef_w => -- -----------------------------------
nstate := s_dsta_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opa(nstate, R_IDSTAT);
end if;
when s_dsta_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
nstate := s_dsta_dec1;
when s_dsta_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then -- check here used also by
do_fork_opa(nstate, R_IDSTAT); -- s_dsta_ind flow !!
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w);
end if;
when s_dsta_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_dsta_ind_w);
when s_dsta_ind_w => -- -----------------------------------
nstate := s_dsta_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dsta_dec1;
end if;
-- instruction operate states -----------------------------------------------
when s_op_halt => -- HALT -------------------------------
idm_idone := '1'; -- instruction done
if is_kmode = '1' then -- if in kernel mode execute
nmmumoni.idone := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_halt;
nstate := s_idle;
else -- otherwise trap
ncpuerr.illhlt := '1';
nstate := s_abort_4; -- vector 4 abort like 11/70
end if;
when s_op_wait => -- WAIT ------------------------------
-- Note: wait is the only interruptable instruction. The CPU spins
-- in s_op_wait until an interrupt or a control command is seen.
-- In case of a control command R_STATUS.waitsusp is set and
-- control transfered to s_idle. If the control command returns
-- to s_op_wait, waitsusp is cleared here. This ensures that the
-- idm_idone logic (for dmcmon) sees only one WAIT even if it is
-- interrupted by control commands.
ndpcntl.gr_asrc := "000"; -- load R0 in DSRC for DR emulation
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
nstatus.waitsusp := '0'; -- in case of returning from s_idle
-- signal idone in the first cycle of a WAIT instruction to dmcmon
-- ensures that a WAIT is logged once and only once
idm_idone := not (R_STATUS.waitsusp or R_STATUS.cpuwait);
nstate := s_op_wait; -- spin here
if is_kmode = '0' then -- but act as nop if not in kernel
nstate := s_idle;
elsif int_pending = '1' or -- bail out if pending interrupt
R_STATUS.cpustep='1' then -- or the instruction is only stepped
nstate := s_idle;
elsif R_STATUS.cmdbusy = '1' then -- suspend if a cp command is pending
nstatus.waitsusp := '1';
nstate := s_idle;
else
nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait
nstatus.itimer := '1'; -- itimer will stay 1 during a WAIT
end if;
when s_op_trap => -- traps -----------------------------
idm_idone := '1'; -- instruction done
lvector := "0000" & R_IDSTAT.trap_vec; -- vector
do_start_vec(nstate, ndpcntl, lvector);
when s_op_reset => -- RESET -----------------------------
if is_kmode = '1' then -- if in kernel mode execute
nstatus.breset := '1'; -- issue bus reset
end if;
nstate := s_idle;
when s_op_rts => -- RTS -------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with reg(dst)
idm_pcload := '1'; -- signal flow change
nstate := s_op_rts_pop;
when s_op_rts_pop => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_rts_pop_w,
nmmumoni, pupdt_sp=>'1');
when s_op_rts_pop_w => -- -----------------------------------
nstate := s_op_rts_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gr_adst := DSTREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gr_we := '1'; -- load R with (SP)+
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_op_spl => -- SPL -------------------------------
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wspl;
idm_idone := '1'; -- instruction done
if is_kmode = '1' then -- active only in kernel mode
ndpcntl.psr_we := '1';
nstate := s_ifetch; -- unconditionally fetch next
-- instruction like a 11/70
-- no interrupt recognition !
else
do_fork_next(nstate, nstatus, nmmumoni); -- in non-kernel, noop
end if;
when s_op_mcc => -- CLx/SEx ---------------------------
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wcc;
ndpcntl.psr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_op_br => -- BR --------------------------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
-- note: cc are NZVC
case brcode(3 downto 1) is
when "000" => -- BR
brcond := '1';
when "001" => -- BNE/BEQ: if Z = x
brcond := PSW.cc(2);
when "010" => -- BGE/BLT: if N xor V = x
brcond := PSW.cc(3) xor PSW.cc(1);
when "011" => -- BGT/BLE: if Z or (N xor V) = x
brcond := PSW.cc(2) or (PSW.cc(3) xor PSW.cc(1));
when "100" => -- BPL/BMI: if N = x
brcond := PSW.cc(3);
when "101" => -- BHI/BLOS:if C or Z = x
brcond := PSW.cc(2) or PSW.cc(0);
when "110" => -- BVC/BVS: if V = x
brcond := PSW.cc(1);
when "111" => -- BCC/BCS: if C = x
brcond := PSW.cc(0);
when others => null;
end case;
ndpcntl.gr_adst := c_gr_pc;
idm_idone := '1'; -- instruction done
if brcond = brcode(0) then -- this coding creates redundant code
ndpcntl.gr_we := '1'; -- but synthesis optimizes this way !
idm_pcload := '1'; -- signal flow change
do_fork_next(nstate, nstatus, nmmumoni);
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_op_mark => -- MARK ------------------------------
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
ndpcntl.gr_adst := c_gr_r5; -- fetch r5
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_op_mark1;
when s_op_mark1 => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with r5
idm_pcload := '1'; -- signal flow change
nstate := s_op_mark_pop;
when s_op_mark_pop => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_mark_pop_w,
nmmumoni, pupdt_sp=>'1');
when s_op_mark_pop_w => -- -----------------------------------
nstate := s_op_mark_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gr_adst := c_gr_r5;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gr_we := '1'; -- load R5 with (sp)+
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_op_sob => -- SOB (dec) -------------------------
-- comment fork_next_pref out (blog 2006-10-02) due to synthesis impact
--nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
--ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.dres_sel := R_IDSTAT.res_sel;
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
nstate := s_op_sob1;
else
--do_fork_next_pref(nstate, ndpcntl, nvmcntl, nmmumoni);
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_op_sob1 => -- SOB (br) --------------------------
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1';
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_gen => -- -----------------------------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.gr_bytop := R_IDSTAT.is_bytop;
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
ndpcntl.gr_bytop := '0'; -- no bytop, do sign extend
end if;
ndpcntl.psr_ccwe := '1';
if R_IDSTAT.is_dstw_reg = '1' then
ndpcntl.gr_we := '1';
end if;
if R_IDSTAT.is_rmwop = '1' then
do_memwrite(nstate, nvmcntl, s_opg_gen_rmw_w, pmacc=>'1');
else
idm_idone := '1'; -- instruction done
if R_STATUS.prefdone = '1' then
nstatus.prefdone :='0';
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
else
if R_IDSTAT.is_dstw_pc = '1' then
nstate := s_idle;
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
end if;
end if;
when s_opg_gen_rmw_w => -- -----------------------------------
nstate := s_opg_gen_rmw_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opg_mul => -- MUL (oper) ------------------------
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.gr_adst := SRCREG; -- write high order result
ndpcntl.gr_we := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- capture high order part
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.dtmp_we := '1'; -- capture low order part
nstate := s_opg_mul1;
when s_opg_mul1 => -- MUL (write odd reg) ---------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_div => -- DIV (load dd_low) -----------------
ndpcntl.munit_s_div := '1';
ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
nstate := s_opg_div_cn;
when s_opg_div_cn => -- DIV (1st...16th cycle) ------------
ndpcntl.munit_s_div_cn := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
nstate := s_opg_div_cn;
if DP_STAT.div_quit = '1' then
nstate := s_opg_div_quit;
else
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
end if;
if DP_STAT.shc_tc = '1' then
nstate := s_opg_div_cr;
end if;
when s_opg_div_cr => -- DIV (remainder correction) --------
ndpcntl.munit_s_div_cr := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
nstate := s_opg_div_sq;
when s_opg_div_sq => -- DIV (correct and store quotient) --
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.gr_we := '1';
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
nstate := s_opg_div_sr;
when s_opg_div_sr => -- DIV (store remainder) -------------
ndpcntl.munit_s_div_sr := '1';
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
if DP_STAT.div_quit = '1' then
nstate := s_opg_div_quit;
else
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opg_div_quit => -- DIV (0/ or /0 or V=1 aborts) ------
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_ash => -- ASH (load shc) --------------------
ndpcntl.munit_s_ash := '1';
nstate := s_opg_ash_cn;
when s_opg_ash_cn => -- ASH (shift cycles) ----------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.munit_s_ash_cn := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nstate := s_opg_ash_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_opg_ashc => -- ASHC (load low, load shc) ---------
ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
ndpcntl.munit_s_ashc := '1';
nstate := s_opg_ashc_cn;
when s_opg_ashc_cn => -- ASHC (shift cycles) ---------------
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.munit_s_ashc_cn := '1';
nstate := s_opg_ashc_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
nstate := s_opg_ashc_wl;
end if;
when s_opg_ashc_wl => -- ASHC (write low) ------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
-- dsta mode operations -----------------------------------------------------
when s_opa_jsr => -- -----------------------------------
ndpcntl.gr_asrc := c_gr_sp; -- (for else)
ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_abort_10; -- vector 10 abort like 11/70
else
ndpcntl.dsrc_we := '1';
nstate := s_opa_jsr1;
end if;
when s_opa_jsr1 => -- -----------------------------------
ndpcntl.gr_asrc := SRCREG;
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
ndpcntl.dtmp_we := '1';
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
ndpcntl.dsrc_we := '1'; -- update DDST
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_jsr_push;
when s_opa_jsr_push => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_jsr_push_w;
when s_opa_jsr_push_w => -- -----------------------------------
nstate := s_opa_jsr_push_w;
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gr_we := '1'; -- load R with PC
nstate := s_opa_jsr2;
end if;
when s_opa_jsr2 => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with dsta
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opa_jmp => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_abort_10; -- vector 10 abort like 11/70
else
ndpcntl.gr_we := '1'; -- load PC with dsta
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opa_mtp => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_opa_mtp_pop_w,
nmmumoni, pupdt_sp=>'1');
when s_opa_mtp_pop_w => -- -----------------------------------
nstate := s_opa_mtp_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dtmp_we := '1'; -- load DTMP
if R_IDSTAT.is_dstmode0 = '1' then -- handle register access
nstate := s_opa_mtp_reg;
else
case R_IDSTAT.fork_dsta is -- 2nd dsta fork in s_idecode
when c_fork_dsta_def => nstate := s_opa_mtp_mem;
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
end if;
end if;
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
when s_opa_mtp_reg => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.gr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opa_mtp_mem => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
nvmcntl.mode := PSW.pmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mtp_mem_w;
when s_opa_mtp_mem_w => -- -----------------------------------
nstate := s_opa_mtp_mem_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opa_mfp_reg => -- -----------------------------------
ndpcntl.gr_mode := PSW.pmode; -- fetch reg in pmode
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
when s_opa_mfp_mem => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if PSW.cmode=c_psw_umode and -- if cm=pm=user then
PSW.cmode=c_psw_umode then -- MFPI works like it
nvmcntl.dspace := '1'; -- were MFPD
else
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
end if;
nvmcntl.mode := PSW.pmode;
nvmcntl.req := '1';
nstate := s_opa_mfp_mem_w;
when s_opa_mfp_mem_w => -- -----------------------------------
nstate := s_opa_mfp_mem_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
end if;
when s_opa_mfp_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_mfp_push;
when s_opa_mfp_push => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mfp_push_w;
when s_opa_mfp_push_w => -- -----------------------------------
nstate := s_opa_mfp_push_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
-- trap and interrupt handling states --------------------------------------
when s_abort_4 => -- -----------------------------------
lvector := "0000001"; -- vector (4)
do_start_vec(nstate, ndpcntl, lvector);
when s_abort_10 => -- -----------------------------------
idm_idone := '1'; -- instruction done
lvector := "0000010"; -- vector (10)
do_start_vec(nstate, ndpcntl, lvector);
when s_trap_disp => -- -----------------------------------
if R_STATUS.treq_mmu = '1' then -- mmu trap requested ?
lvector := "0101010"; -- mmu trap: vector (250)
elsif R_STATUS.treq_ysv = '1' then -- ysv trap requested ?
lvector := "0000001"; -- ysv trap: vector (4)
ncpuerr.ysv := '1';
nstatus.in_vecysv := '1'; -- signal start of ysv vector flow
else
lvector := "0000011"; -- trace trap: vector (14)
end if;
nstatus.treq_mmu := '0'; -- clear trap request flags
nstatus.treq_ysv := '0'; --
do_start_vec(nstate, ndpcntl, lvector);
when s_int_ext => -- -----------------------------------
lvector := R_STATUS.intvect; -- external vector
do_start_vec(nstate, ndpcntl, lvector);
-- vector flow states ------------------------------------------------------
when s_vec_getpc => -- -----------------------------------
idm_vfetch := '1'; -- signal vfetch
nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getpc_w, nmmumoni);
when s_vec_getpc_w => -- -----------------------------------
nstate := s_vec_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_vec_getps;
end if;
when s_vec_getps => -- -----------------------------------
nvmcntl.mode := c_psw_kmode; -- fetch PS from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getps_w, nmmumoni);
when s_vec_getps_w => -- -----------------------------------
nstate := s_vec_getps_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.psr_func := c_psr_func_wint; -- interupt mode write
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.psr_we := '1'; -- store new PS
nstate := s_vec_getsp;
end if;
when s_vec_getsp => -- -----------------------------------
ndpcntl.gr_asrc := c_gr_sp;
ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
nstate := s_vec_decsp;
when s_vec_decsp => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP too
nstate := s_vec_pushps;
when s_vec_pushps => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_vec_pushps_w;
when s_vec_pushps_w => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.gr_adst := c_gr_sp;
nstate := s_vec_pushps_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_we := '1'; -- update SP too
nstate := s_vec_pushpc;
end if;
when s_vec_pushpc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_vec_pushpc_w;
when s_vec_pushpc_w => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
nstate := s_vec_pushpc_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
nstatus.in_vecser := '0'; -- signal end of ser flow
nstatus.in_vecysv := '0'; -- signal end of ysv flow
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
do_fork_next(nstate, nstatus, nmmumoni); -- ???
end if;
-- return from trap or interrupt handling states ----------------------------
when s_rti_getpc => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getpc_w,
nmmumoni, pupdt_sp=>'1');
when s_rti_getpc_w => -- -----------------------------------
nstate := s_rti_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_rti_getps;
end if;
when s_rti_getps => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getps_w,
nmmumoni, pupdt_sp=>'1');
when s_rti_getps_w => -- -----------------------------------
nstate := s_rti_getps_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if is_kmode = '1' then -- if in kernel mode
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
else
ndpcntl.psr_func := c_psr_func_wrti; -- otherwise filter
end if;
if imemok then
ndpcntl.psr_we := '1'; -- load new PS
nstate := s_rti_newpc;
end if;
when s_rti_newpc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
do_fork_next(nstate, nstatus, nmmumoni);
end if;
-- exception abort states ---------------------------------------------------
when s_vmerr => -- -----------------------------------
nstate := s_cpufail;
-- setup for R_VMSTAT.err_rsv='1'
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gr_adst := c_gr_sp;
nstatus.treq_mmu := '0'; -- cancel mmu trap request
nstatus.treq_ysv := '0'; -- cancel ysv trap request
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu
nstatus.cpurust := c_cpurust_vfail;
nstate := s_idle;
elsif R_STATUS.in_vecser = '1' then -- double fatal stack error
nstatus.cpugo := '0'; -- give up, HALT cpu
nstatus.cpurust := c_cpurust_recser;
nstate := s_idle;
elsif R_VMSTAT.err = '1' then -- normal vm errors
if R_VMSTAT.err_rsv = '1' then
nstatus.in_vecser := '1'; -- signal start of ser flow
nstatus.in_vecysv := '0'; -- cancel ysv flow
ndpcntl.gr_we := '1';
if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
ncpuerr.adderr := '1';
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
end if;
ncpuerr.rsv := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_odd = '1' then
ncpuerr.adderr := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_mmu = '1' then
lvector := "0101010"; -- vector (250)
do_start_vec(nstate, ndpcntl, lvector);
end if;
end if;
when s_cpufail => -- -----------------------------------
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_sfail;
nstate := s_idle;
when others => -- -----------------------------------
nstate := s_cpufail; --!!! catch undefined states !!!
end case;
if HBPT = '1' then -- handle hardware bpt
nstatus.cpurust := c_cpurust_hbpt;
nstatus.suspint :='1';
end if;
nstatus.suspext := ESUSP_I;
-- handle cpususp transitions
if nstatus.suspint='1' or nstatus.suspext='1' then
nstatus.cpususp := '1';
elsif R_STATUS.suspint='0' and R_STATUS.suspext='0' then
nstatus.cpususp := '0';
end if;
if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test
-- nstatus here !!
nstatus.cmdbusy := '0';
ndpcntl.cpdout_we := '1';
end if;
N_STATE <= nstate;
N_STATUS <= nstatus;
N_CPUERR <= ncpuerr;
N_IDSTAT <= nidstat;
INT_ACK <= R_STATUS.intack;
CRESET <= R_STATUS.creset;
BRESET <= R_STATUS.breset;
ESUSP_O <= R_STATUS.suspint; -- FIXME_code: handle masking later
DP_CNTL <= ndpcntl;
VM_CNTL <= nvmcntl;
VM_CNTL_L <= nvmcntl;
nmmumoni.regnum := ndpcntl.gr_adst;
nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
MMU_MONI <= nmmumoni;
DM_STAT_SE.idle <= idm_idle;
DM_STAT_SE.cpbusy <= idm_cpbusy;
DM_STAT_SE.istart <= nmmumoni.istart;
DM_STAT_SE.idec <= idm_idec;
DM_STAT_SE.idone <= idm_idone;
DM_STAT_SE.itimer <= R_STATUS.itimer;
DM_STAT_SE.pcload <= idm_pcload;
DM_STAT_SE.vfetch <= idm_vfetch;
end process proc_next;
proc_cpstat : process (R_STATUS)
begin
CP_STAT <= cp_stat_init;
CP_STAT.cmdbusy <= R_STATUS.cmdbusy;
CP_STAT.cmdack <= R_STATUS.cmdack;
CP_STAT.cmderr <= R_STATUS.cmderr;
CP_STAT.cmdmerr <= R_STATUS.cmdmerr;
CP_STAT.cpugo <= R_STATUS.cpugo;
CP_STAT.cpustep <= R_STATUS.cpustep;
CP_STAT.cpuwait <= R_STATUS.cpuwait;
CP_STAT.cpususp <= R_STATUS.cpususp;
CP_STAT.cpurust <= R_STATUS.cpurust;
CP_STAT.suspint <= R_STATUS.suspint;
CP_STAT.suspext <= R_STATUS.suspext;
end process proc_cpstat;
-- SNUM creation logic is conditional due to synthesis impact in vivado.
-- SNUM = 'full state number' only available when dmscnt unit enabled.
SNUM1 : if sys_conf_dmscnt generate
begin
proc_snum : process (R_STATE)
variable isnum : slv8 := (others=>'0');
begin
isnum := (others=>'0');
case R_STATE is
-- STATE2SNUM mapper begin
when s_idle => isnum := x"00";
when s_cp_regread => isnum := x"01";
when s_cp_rps => isnum := x"02";
when s_cp_memr_w => isnum := x"03";
when s_cp_memw_w => isnum := x"04";
when s_ifetch => isnum := x"05";
when s_ifetch_w => isnum := x"06";
when s_idecode => isnum := x"07";
when s_srcr_def => isnum := x"08";
when s_srcr_def_w => isnum := x"09";
when s_srcr_inc => isnum := x"0a";
when s_srcr_inc_w => isnum := x"0b";
when s_srcr_dec => isnum := x"0c";
when s_srcr_dec1 => isnum := x"0d";
when s_srcr_ind => isnum := x"0e";
when s_srcr_ind1_w => isnum := x"0f";
when s_srcr_ind2 => isnum := x"10";
when s_srcr_ind2_w => isnum := x"11";
when s_dstr_def => isnum := x"12";
when s_dstr_def_w => isnum := x"13";
when s_dstr_inc => isnum := x"14";
when s_dstr_inc_w => isnum := x"15";
when s_dstr_dec => isnum := x"16";
when s_dstr_dec1 => isnum := x"17";
when s_dstr_ind => isnum := x"18";
when s_dstr_ind1_w => isnum := x"19";
when s_dstr_ind2 => isnum := x"1a";
when s_dstr_ind2_w => isnum := x"1b";
when s_dstw_def => isnum := x"1c";
when s_dstw_def_w => isnum := x"1d";
when s_dstw_inc => isnum := x"1e";
when s_dstw_inc_w => isnum := x"1f";
when s_dstw_incdef_w => isnum := x"20";
when s_dstw_dec => isnum := x"21";
when s_dstw_dec1 => isnum := x"22";
when s_dstw_ind => isnum := x"23";
when s_dstw_ind_w => isnum := x"24";
when s_dstw_def246 => isnum := x"25";
when s_dsta_inc => isnum := x"26";
when s_dsta_incdef_w => isnum := x"27";
when s_dsta_dec => isnum := x"28";
when s_dsta_dec1 => isnum := x"29";
when s_dsta_ind => isnum := x"2a";
when s_dsta_ind_w => isnum := x"2b";
when s_op_halt => isnum := x"2c";
when s_op_wait => isnum := x"2d";
when s_op_trap => isnum := x"2e";
when s_op_reset => isnum := x"2f";
when s_op_rts => isnum := x"30";
when s_op_rts_pop => isnum := x"31";
when s_op_rts_pop_w => isnum := x"32";
when s_op_spl => isnum := x"33";
when s_op_mcc => isnum := x"34";
when s_op_br => isnum := x"35";
when s_op_mark => isnum := x"36";
when s_op_mark1 => isnum := x"37";
when s_op_mark_pop => isnum := x"38";
when s_op_mark_pop_w => isnum := x"39";
when s_op_sob => isnum := x"3a";
when s_op_sob1 => isnum := x"3b";
when s_opg_gen => isnum := x"3c";
when s_opg_gen_rmw_w => isnum := x"3d";
when s_opg_mul => isnum := x"3e";
when s_opg_mul1 => isnum := x"3f";
when s_opg_div => isnum := x"40";
when s_opg_div_cn => isnum := x"41";
when s_opg_div_cr => isnum := x"42";
when s_opg_div_sq => isnum := x"43";
when s_opg_div_sr => isnum := x"44";
when s_opg_div_quit => isnum := x"45";
when s_opg_ash => isnum := x"46";
when s_opg_ash_cn => isnum := x"47";
when s_opg_ashc => isnum := x"48";
when s_opg_ashc_cn => isnum := x"49";
when s_opg_ashc_wl => isnum := x"4a";
when s_opa_jsr => isnum := x"4b";
when s_opa_jsr1 => isnum := x"4c";
when s_opa_jsr_push => isnum := x"4d";
when s_opa_jsr_push_w => isnum := x"4e";
when s_opa_jsr2 => isnum := x"4f";
when s_opa_jmp => isnum := x"50";
when s_opa_mtp => isnum := x"51";
when s_opa_mtp_pop_w => isnum := x"52";
when s_opa_mtp_reg => isnum := x"53";
when s_opa_mtp_mem => isnum := x"54";
when s_opa_mtp_mem_w => isnum := x"55";
when s_opa_mfp_reg => isnum := x"56";
when s_opa_mfp_mem => isnum := x"57";
when s_opa_mfp_mem_w => isnum := x"58";
when s_opa_mfp_dec => isnum := x"59";
when s_opa_mfp_push => isnum := x"5a";
when s_opa_mfp_push_w => isnum := x"5b";
when s_abort_4 => isnum := x"5c";
when s_abort_10 => isnum := x"5d";
when s_trap_disp => isnum := x"5e";
when s_int_ext => isnum := x"5f";
when s_vec_getpc => isnum := x"60";
when s_vec_getpc_w => isnum := x"61";
when s_vec_getps => isnum := x"62";
when s_vec_getps_w => isnum := x"63";
when s_vec_getsp => isnum := x"64";
when s_vec_decsp => isnum := x"65";
when s_vec_pushps => isnum := x"66";
when s_vec_pushps_w => isnum := x"67";
when s_vec_pushpc => isnum := x"68";
when s_vec_pushpc_w => isnum := x"69";
when s_rti_getpc => isnum := x"6a";
when s_rti_getpc_w => isnum := x"6b";
when s_rti_getps => isnum := x"6c";
when s_rti_getps_w => isnum := x"6d";
when s_rti_newpc => isnum := x"6e";
when s_vmerr => isnum := x"6f";
when s_cpufail => isnum := x"70";
-- STATE2SNUM mapper end
when others => isnum := x"ff";
end case;
DM_STAT_SE.snum <= isnum;
end process proc_snum;
end generate SNUM1;
-- if dmscnt not enable setup SNUM based on state categories (currently 4)
-- and a 'wait' indicator determined from monitoring VM_CNTL and VM_STAT
SNUM0 : if not sys_conf_dmscnt generate
signal R_VMWAIT : slbit := '0'; -- vmwait flag
begin
proc_vmwait: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_VMWAIT <= '0';
else
if VM_CNTL_L.req = '1' then
R_VMWAIT <= '1';
elsif VM_STAT.ack = '1' or VM_STAT.err = '1' or VM_STAT.fail='1' then
R_VMWAIT <= '0';
end if;
end if;
end if;
end process proc_vmwait;
proc_snum : process (R_STATE, R_VMWAIT)
variable isnum_con : slbit := '0';
variable isnum_ins : slbit := '0';
variable isnum_vec : slbit := '0';
variable isnum_err : slbit := '0';
begin
isnum_con := '0';
isnum_ins := '0';
isnum_vec := '0';
isnum_err := '0';
case R_STATE is
when s_idle => null;
when s_cp_regread => isnum_con := '1';
when s_cp_rps => isnum_con := '1';
when s_cp_memr_w => isnum_con := '1';
when s_cp_memw_w => isnum_con := '1';
when s_ifetch => isnum_ins := '1';
when s_ifetch_w => isnum_ins := '1';
when s_idecode => isnum_ins := '1';
when s_srcr_def => isnum_ins := '1';
when s_srcr_def_w => isnum_ins := '1';
when s_srcr_inc => isnum_ins := '1';
when s_srcr_inc_w => isnum_ins := '1';
when s_srcr_dec => isnum_ins := '1';
when s_srcr_dec1 => isnum_ins := '1';
when s_srcr_ind => isnum_ins := '1';
when s_srcr_ind1_w => isnum_ins := '1';
when s_srcr_ind2 => isnum_ins := '1';
when s_srcr_ind2_w => isnum_ins := '1';
when s_dstr_def => isnum_ins := '1';
when s_dstr_def_w => isnum_ins := '1';
when s_dstr_inc => isnum_ins := '1';
when s_dstr_inc_w => isnum_ins := '1';
when s_dstr_dec => isnum_ins := '1';
when s_dstr_dec1 => isnum_ins := '1';
when s_dstr_ind => isnum_ins := '1';
when s_dstr_ind1_w => isnum_ins := '1';
when s_dstr_ind2 => isnum_ins := '1';
when s_dstr_ind2_w => isnum_ins := '1';
when s_dstw_def => isnum_ins := '1';
when s_dstw_def_w => isnum_ins := '1';
when s_dstw_inc => isnum_ins := '1';
when s_dstw_inc_w => isnum_ins := '1';
when s_dstw_incdef_w => isnum_ins := '1';
when s_dstw_dec => isnum_ins := '1';
when s_dstw_dec1 => isnum_ins := '1';
when s_dstw_ind => isnum_ins := '1';
when s_dstw_ind_w => isnum_ins := '1';
when s_dstw_def246 => isnum_ins := '1';
when s_dsta_inc => isnum_ins := '1';
when s_dsta_incdef_w => isnum_ins := '1';
when s_dsta_dec => isnum_ins := '1';
when s_dsta_dec1 => isnum_ins := '1';
when s_dsta_ind => isnum_ins := '1';
when s_dsta_ind_w => isnum_ins := '1';
when s_op_halt => isnum_ins := '1';
when s_op_wait => isnum_ins := '1';
when s_op_trap => isnum_ins := '1';
when s_op_reset => isnum_ins := '1';
when s_op_rts => isnum_ins := '1';
when s_op_rts_pop => isnum_ins := '1';
when s_op_rts_pop_w => isnum_ins := '1';
when s_op_spl => isnum_ins := '1';
when s_op_mcc => isnum_ins := '1';
when s_op_br => isnum_ins := '1';
when s_op_mark => isnum_ins := '1';
when s_op_mark1 => isnum_ins := '1';
when s_op_mark_pop => isnum_ins := '1';
when s_op_mark_pop_w => isnum_ins := '1';
when s_op_sob => isnum_ins := '1';
when s_op_sob1 => isnum_ins := '1';
when s_opg_gen => isnum_ins := '1';
when s_opg_gen_rmw_w => isnum_ins := '1';
when s_opg_mul => isnum_ins := '1';
when s_opg_mul1 => isnum_ins := '1';
when s_opg_div => isnum_ins := '1';
when s_opg_div_cn => isnum_ins := '1';
when s_opg_div_cr => isnum_ins := '1';
when s_opg_div_sq => isnum_ins := '1';
when s_opg_div_sr => isnum_ins := '1';
when s_opg_div_quit => isnum_ins := '1';
when s_opg_ash => isnum_ins := '1';
when s_opg_ash_cn => isnum_ins := '1';
when s_opg_ashc => isnum_ins := '1';
when s_opg_ashc_cn => isnum_ins := '1';
when s_opg_ashc_wl => isnum_ins := '1';
when s_opa_jsr => isnum_ins := '1';
when s_opa_jsr1 => isnum_ins := '1';
when s_opa_jsr_push => isnum_ins := '1';
when s_opa_jsr_push_w => isnum_ins := '1';
when s_opa_jsr2 => isnum_ins := '1';
when s_opa_jmp => isnum_ins := '1';
when s_opa_mtp => isnum_ins := '1';
when s_opa_mtp_pop_w => isnum_ins := '1';
when s_opa_mtp_reg => isnum_ins := '1';
when s_opa_mtp_mem => isnum_ins := '1';
when s_opa_mtp_mem_w => isnum_ins := '1';
when s_opa_mfp_reg => isnum_ins := '1';
when s_opa_mfp_mem => isnum_ins := '1';
when s_opa_mfp_mem_w => isnum_ins := '1';
when s_opa_mfp_dec => isnum_ins := '1';
when s_opa_mfp_push => isnum_ins := '1';
when s_opa_mfp_push_w => isnum_ins := '1';
when s_abort_4 => isnum_ins := '1';
when s_abort_10 => isnum_ins := '1';
when s_trap_disp => isnum_ins := '1';
when s_int_ext => isnum_vec := '1';
when s_vec_getpc => isnum_vec := '1';
when s_vec_getpc_w => isnum_vec := '1';
when s_vec_getps => isnum_vec := '1';
when s_vec_getps_w => isnum_vec := '1';
when s_vec_getsp => isnum_vec := '1';
when s_vec_decsp => isnum_vec := '1';
when s_vec_pushps => isnum_vec := '1';
when s_vec_pushps_w => isnum_vec := '1';
when s_vec_pushpc => isnum_vec := '1';
when s_vec_pushpc_w => isnum_vec := '1';
when s_rti_getpc => isnum_vec := '1';
when s_rti_getpc_w => isnum_vec := '1';
when s_rti_getps => isnum_vec := '1';
when s_rti_getps_w => isnum_vec := '1';
when s_rti_newpc => isnum_vec := '1';
when s_vmerr => isnum_err := '1';
when s_cpufail => isnum_err := '1';
when others => null;
end case;
DM_STAT_SE.snum <= (others=>'0');
DM_STAT_SE.snum(c_snum_f_con) <= isnum_con;
DM_STAT_SE.snum(c_snum_f_ins) <= isnum_ins;
DM_STAT_SE.snum(c_snum_f_vec) <= isnum_vec;
DM_STAT_SE.snum(c_snum_f_err) <= isnum_err;
DM_STAT_SE.snum(c_snum_f_vmw) <= R_VMWAIT;
end process proc_snum;
end generate SNUM0;
end syn;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity gcd is
generic (
C_S_AXI_GCD_BUS_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_GCD_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_gcd_bus_AWVALID : IN STD_LOGIC;
s_axi_gcd_bus_AWREADY : OUT STD_LOGIC;
s_axi_gcd_bus_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_WVALID : IN STD_LOGIC;
s_axi_gcd_bus_WREADY : OUT STD_LOGIC;
s_axi_gcd_bus_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_gcd_bus_ARVALID : IN STD_LOGIC;
s_axi_gcd_bus_ARREADY : OUT STD_LOGIC;
s_axi_gcd_bus_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_RVALID : OUT STD_LOGIC;
s_axi_gcd_bus_RREADY : IN STD_LOGIC;
s_axi_gcd_bus_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_gcd_bus_BVALID : OUT STD_LOGIC;
s_axi_gcd_bus_BREADY : IN STD_LOGIC;
s_axi_gcd_bus_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of gcd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"gcd,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.429000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=203,HLS_SYN_LUT=285,HLS_VERSION=2018_2}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (15 downto 0);
signal b : STD_LOGIC_VECTOR (15 downto 0);
signal pResult_ap_vld : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR (15 downto 0);
signal a_read_reg_107 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_72_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_115 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_2_fu_66_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_assign_fu_78_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal a_assign_reg_121 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_fu_84_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_reg_126 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_1_fu_90_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal a_assign_1_fu_96_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal p_s_reg_45 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal result_reg_56 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component gcd_gcd_bus_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
a : OUT STD_LOGIC_VECTOR (15 downto 0);
b : OUT STD_LOGIC_VECTOR (15 downto 0);
pResult : IN STD_LOGIC_VECTOR (15 downto 0);
pResult_ap_vld : IN STD_LOGIC );
end component;
begin
gcd_gcd_bus_s_axi_U : component gcd_gcd_bus_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_GCD_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_GCD_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_gcd_bus_AWVALID,
AWREADY => s_axi_gcd_bus_AWREADY,
AWADDR => s_axi_gcd_bus_AWADDR,
WVALID => s_axi_gcd_bus_WVALID,
WREADY => s_axi_gcd_bus_WREADY,
WDATA => s_axi_gcd_bus_WDATA,
WSTRB => s_axi_gcd_bus_WSTRB,
ARVALID => s_axi_gcd_bus_ARVALID,
ARREADY => s_axi_gcd_bus_ARREADY,
ARADDR => s_axi_gcd_bus_ARADDR,
RVALID => s_axi_gcd_bus_RVALID,
RREADY => s_axi_gcd_bus_RREADY,
RDATA => s_axi_gcd_bus_RDATA,
RRESP => s_axi_gcd_bus_RRESP,
BVALID => s_axi_gcd_bus_BVALID,
BREADY => s_axi_gcd_bus_BREADY,
BRESP => s_axi_gcd_bus_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
a => a,
b => b,
pResult => p_s_reg_45,
pResult_ap_vld => pResult_ap_vld);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
p_s_reg_45_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
p_s_reg_45 <= b_assign_1_fu_90_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_s_reg_45 <= b_read_reg_102;
end if;
end if;
end process;
result_reg_56_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
result_reg_56 <= a_assign_1_fu_96_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
result_reg_56 <= a_read_reg_107;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_2_fu_66_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
a_assign_reg_121 <= a_assign_fu_78_p2;
b_assign_reg_126 <= b_assign_fu_84_p2;
tmp_3_reg_115 <= tmp_3_fu_72_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
a_read_reg_107 <= a;
b_read_reg_102 <= b;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a_assign_1_fu_96_p3 <=
a_assign_reg_121 when (tmp_3_reg_115(0) = '1') else
result_reg_56;
a_assign_fu_78_p2 <= std_logic_vector(unsigned(result_reg_56) - unsigned(p_s_reg_45));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_done_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
b_assign_1_fu_90_p3 <=
p_s_reg_45 when (tmp_3_reg_115(0) = '1') else
b_assign_reg_126;
b_assign_fu_84_p2 <= std_logic_vector(unsigned(p_s_reg_45) - unsigned(result_reg_56));
pResult_ap_vld_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
pResult_ap_vld <= ap_const_logic_1;
else
pResult_ap_vld <= ap_const_logic_0;
end if;
end process;
tmp_2_fu_66_p2 <= "1" when (result_reg_56 = p_s_reg_45) else "0";
tmp_3_fu_72_p2 <= "1" when (signed(result_reg_56) > signed(p_s_reg_45)) else "0";
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity gcd is
generic (
C_S_AXI_GCD_BUS_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_GCD_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_gcd_bus_AWVALID : IN STD_LOGIC;
s_axi_gcd_bus_AWREADY : OUT STD_LOGIC;
s_axi_gcd_bus_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_WVALID : IN STD_LOGIC;
s_axi_gcd_bus_WREADY : OUT STD_LOGIC;
s_axi_gcd_bus_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_gcd_bus_ARVALID : IN STD_LOGIC;
s_axi_gcd_bus_ARREADY : OUT STD_LOGIC;
s_axi_gcd_bus_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_RVALID : OUT STD_LOGIC;
s_axi_gcd_bus_RREADY : IN STD_LOGIC;
s_axi_gcd_bus_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_gcd_bus_BVALID : OUT STD_LOGIC;
s_axi_gcd_bus_BREADY : IN STD_LOGIC;
s_axi_gcd_bus_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of gcd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"gcd,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.429000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=203,HLS_SYN_LUT=285,HLS_VERSION=2018_2}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (15 downto 0);
signal b : STD_LOGIC_VECTOR (15 downto 0);
signal pResult_ap_vld : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR (15 downto 0);
signal a_read_reg_107 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_72_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_115 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_2_fu_66_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_assign_fu_78_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal a_assign_reg_121 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_fu_84_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_reg_126 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_1_fu_90_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal a_assign_1_fu_96_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal p_s_reg_45 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal result_reg_56 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component gcd_gcd_bus_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
a : OUT STD_LOGIC_VECTOR (15 downto 0);
b : OUT STD_LOGIC_VECTOR (15 downto 0);
pResult : IN STD_LOGIC_VECTOR (15 downto 0);
pResult_ap_vld : IN STD_LOGIC );
end component;
begin
gcd_gcd_bus_s_axi_U : component gcd_gcd_bus_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_GCD_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_GCD_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_gcd_bus_AWVALID,
AWREADY => s_axi_gcd_bus_AWREADY,
AWADDR => s_axi_gcd_bus_AWADDR,
WVALID => s_axi_gcd_bus_WVALID,
WREADY => s_axi_gcd_bus_WREADY,
WDATA => s_axi_gcd_bus_WDATA,
WSTRB => s_axi_gcd_bus_WSTRB,
ARVALID => s_axi_gcd_bus_ARVALID,
ARREADY => s_axi_gcd_bus_ARREADY,
ARADDR => s_axi_gcd_bus_ARADDR,
RVALID => s_axi_gcd_bus_RVALID,
RREADY => s_axi_gcd_bus_RREADY,
RDATA => s_axi_gcd_bus_RDATA,
RRESP => s_axi_gcd_bus_RRESP,
BVALID => s_axi_gcd_bus_BVALID,
BREADY => s_axi_gcd_bus_BREADY,
BRESP => s_axi_gcd_bus_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
a => a,
b => b,
pResult => p_s_reg_45,
pResult_ap_vld => pResult_ap_vld);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
p_s_reg_45_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
p_s_reg_45 <= b_assign_1_fu_90_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_s_reg_45 <= b_read_reg_102;
end if;
end if;
end process;
result_reg_56_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
result_reg_56 <= a_assign_1_fu_96_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
result_reg_56 <= a_read_reg_107;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_2_fu_66_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
a_assign_reg_121 <= a_assign_fu_78_p2;
b_assign_reg_126 <= b_assign_fu_84_p2;
tmp_3_reg_115 <= tmp_3_fu_72_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
a_read_reg_107 <= a;
b_read_reg_102 <= b;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a_assign_1_fu_96_p3 <=
a_assign_reg_121 when (tmp_3_reg_115(0) = '1') else
result_reg_56;
a_assign_fu_78_p2 <= std_logic_vector(unsigned(result_reg_56) - unsigned(p_s_reg_45));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_done_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
b_assign_1_fu_90_p3 <=
p_s_reg_45 when (tmp_3_reg_115(0) = '1') else
b_assign_reg_126;
b_assign_fu_84_p2 <= std_logic_vector(unsigned(p_s_reg_45) - unsigned(result_reg_56));
pResult_ap_vld_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
pResult_ap_vld <= ap_const_logic_1;
else
pResult_ap_vld <= ap_const_logic_0;
end if;
end process;
tmp_2_fu_66_p2 <= "1" when (result_reg_56 = p_s_reg_45) else "0";
tmp_3_fu_72_p2 <= "1" when (signed(result_reg_56) > signed(p_s_reg_45)) else "0";
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity gcd is
generic (
C_S_AXI_GCD_BUS_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_GCD_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_gcd_bus_AWVALID : IN STD_LOGIC;
s_axi_gcd_bus_AWREADY : OUT STD_LOGIC;
s_axi_gcd_bus_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_WVALID : IN STD_LOGIC;
s_axi_gcd_bus_WREADY : OUT STD_LOGIC;
s_axi_gcd_bus_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_gcd_bus_ARVALID : IN STD_LOGIC;
s_axi_gcd_bus_ARREADY : OUT STD_LOGIC;
s_axi_gcd_bus_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_RVALID : OUT STD_LOGIC;
s_axi_gcd_bus_RREADY : IN STD_LOGIC;
s_axi_gcd_bus_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_gcd_bus_BVALID : OUT STD_LOGIC;
s_axi_gcd_bus_BREADY : IN STD_LOGIC;
s_axi_gcd_bus_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of gcd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"gcd,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.429000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=203,HLS_SYN_LUT=285,HLS_VERSION=2018_2}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (15 downto 0);
signal b : STD_LOGIC_VECTOR (15 downto 0);
signal pResult_ap_vld : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR (15 downto 0);
signal a_read_reg_107 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_72_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_115 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_2_fu_66_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_assign_fu_78_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal a_assign_reg_121 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_fu_84_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_reg_126 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_1_fu_90_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal a_assign_1_fu_96_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal p_s_reg_45 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal result_reg_56 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component gcd_gcd_bus_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
a : OUT STD_LOGIC_VECTOR (15 downto 0);
b : OUT STD_LOGIC_VECTOR (15 downto 0);
pResult : IN STD_LOGIC_VECTOR (15 downto 0);
pResult_ap_vld : IN STD_LOGIC );
end component;
begin
gcd_gcd_bus_s_axi_U : component gcd_gcd_bus_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_GCD_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_GCD_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_gcd_bus_AWVALID,
AWREADY => s_axi_gcd_bus_AWREADY,
AWADDR => s_axi_gcd_bus_AWADDR,
WVALID => s_axi_gcd_bus_WVALID,
WREADY => s_axi_gcd_bus_WREADY,
WDATA => s_axi_gcd_bus_WDATA,
WSTRB => s_axi_gcd_bus_WSTRB,
ARVALID => s_axi_gcd_bus_ARVALID,
ARREADY => s_axi_gcd_bus_ARREADY,
ARADDR => s_axi_gcd_bus_ARADDR,
RVALID => s_axi_gcd_bus_RVALID,
RREADY => s_axi_gcd_bus_RREADY,
RDATA => s_axi_gcd_bus_RDATA,
RRESP => s_axi_gcd_bus_RRESP,
BVALID => s_axi_gcd_bus_BVALID,
BREADY => s_axi_gcd_bus_BREADY,
BRESP => s_axi_gcd_bus_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
a => a,
b => b,
pResult => p_s_reg_45,
pResult_ap_vld => pResult_ap_vld);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
p_s_reg_45_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
p_s_reg_45 <= b_assign_1_fu_90_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_s_reg_45 <= b_read_reg_102;
end if;
end if;
end process;
result_reg_56_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
result_reg_56 <= a_assign_1_fu_96_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
result_reg_56 <= a_read_reg_107;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_2_fu_66_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
a_assign_reg_121 <= a_assign_fu_78_p2;
b_assign_reg_126 <= b_assign_fu_84_p2;
tmp_3_reg_115 <= tmp_3_fu_72_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
a_read_reg_107 <= a;
b_read_reg_102 <= b;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a_assign_1_fu_96_p3 <=
a_assign_reg_121 when (tmp_3_reg_115(0) = '1') else
result_reg_56;
a_assign_fu_78_p2 <= std_logic_vector(unsigned(result_reg_56) - unsigned(p_s_reg_45));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_done_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
b_assign_1_fu_90_p3 <=
p_s_reg_45 when (tmp_3_reg_115(0) = '1') else
b_assign_reg_126;
b_assign_fu_84_p2 <= std_logic_vector(unsigned(p_s_reg_45) - unsigned(result_reg_56));
pResult_ap_vld_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
pResult_ap_vld <= ap_const_logic_1;
else
pResult_ap_vld <= ap_const_logic_0;
end if;
end process;
tmp_2_fu_66_p2 <= "1" when (result_reg_56 = p_s_reg_45) else "0";
tmp_3_fu_72_p2 <= "1" when (signed(result_reg_56) > signed(p_s_reg_45)) else "0";
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity delta_sigma_2to5 is
generic (
g_width : positive := 12 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of delta_sigma_2to5 is
-- signal input : unsigned(g_width-1 downto 0);
signal input : unsigned(15 downto 0);
signal level : unsigned(1 downto 0);
signal modulated : integer range 0 to 3;
signal count : integer range 0 to 4;
signal out_i : std_logic;
signal mash_enable : std_logic;
signal sine : signed(15 downto 0);
begin
dac_out <= out_i;
--input <= not(dac_in(dac_in'high)) & unsigned(dac_in(dac_in'high-1 downto 0));
input <= not(sine(sine'high)) & unsigned(sine(sine'high-1 downto 0));
level <= to_unsigned(modulated, 2);
i_pilot: entity work.sine_osc
port map (
clock => clock,
enable => mash_enable,
reset => reset,
sine => sine,
cosine => open );
i_mash: entity work.mash
generic map (2, input'length)
port map (
clock => clock,
enable => mash_enable,
reset => reset,
dac_in => input,
dac_out => modulated );
process(clock)
begin
if rising_edge(clock) then
mash_enable <= '0';
case count is
when 0 =>
out_i <= '0';
when 1 =>
if level="11" then
out_i <= '1';
else
out_i <= '0';
end if;
when 2 =>
out_i <= level(1);
when 3 =>
if level="00" then
out_i <= '0';
else
out_i <= '1';
end if;
when 4 =>
mash_enable <= '1';
out_i <= '1';
when others =>
null;
end case;
if count = 4 then
count <= 0;
else
count <= count + 1;
end if;
if reset='1' then
out_i <= not out_i;
count <= 0;
end if;
end if;
end process;
end gideon;
|
-------------------------------------------------------------------------------
--! @file alteraHostInterface.vhd
--
--! @brief toplevel of host interface for Altera FPGA
--
--! @details This toplevel interfaces to Altera specific implementation.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity alteraHostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBasePdo : natural := 16#0B000#;
--! Base address Timesync
gBaseTimeSync : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Timesync)
gBaseRes : natural := 16#0E400#;
--! Host address width
gHostAddrWidth : natural := 16
);
port (
--! Clock Source input
csi_c0_clock : in std_logic;
--! Reset Source input
rsi_r0_reset : in std_logic;
-- Avalon Memory Mapped Slave for Host
--! Avalon-MM slave host address
avs_host_address : in std_logic_vector(gHostAddrWidth-1 downto 2);
--! Avalon-MM slave host byteenable
avs_host_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave host read
avs_host_read : in std_logic;
--! Avalon-MM slave host readdata
avs_host_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave host write
avs_host_write : in std_logic;
--! Avalon-MM slave host writedata
avs_host_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave host waitrequest
avs_host_waitrequest : out std_logic;
-- Avalon Memory Mapped Slave for PCP
--! Avalon-MM slave pcp address
avs_pcp_address : in std_logic_vector(10 downto 2);
--! Avalon-MM slave pcp byteenable
avs_pcp_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave pcp read
avs_pcp_read : in std_logic;
--! Avalon-MM slave pcp readdata
avs_pcp_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp write
avs_pcp_write : in std_logic;
--! Avalon-MM slave pcp writedata
avs_pcp_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp waitrequest
avs_pcp_waitrequest : out std_logic;
-- Avalon Memory Mapped Master for Host via Magic Bridge
--! Avalon-MM master hostBridge address
avm_hostBridge_address : out std_logic_vector(29 downto 0);
--! Avalon-MM master hostBridge byteenable
avm_hostBridge_byteenable : out std_logic_vector(3 downto 0);
--! Avalon-MM master hostBridge read
avm_hostBridge_read : out std_logic;
--! Avalon-MM master hostBridge readdata
avm_hostBridge_readdata : in std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge write
avm_hostBridge_write : out std_logic;
--! Avalon-MM master hostBridge writedata
avm_hostBridge_writedata : out std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge waitrequest
avm_hostBridge_waitrequest : in std_logic;
--! Interrupt receiver
inr_irqSync_irq : in std_logic;
--! Interrupt sender
ins_irqOut_irq : out std_logic;
--! External Sync Source
coe_ExtSync_exsync : in std_logic
);
end alteraHostInterface;
architecture rtl of alteraHostInterface is
--! The bridge translation lut is implemented in memory blocks to save logic resources.
--! If no M9K shall be used, set this constant to 0.
constant cBridgeUseMemBlock : natural := 1;
begin
--! The host interface
theHostInterface: entity work.hostInterface
generic map (
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gBridgeUseMemBlock => cBridgeUseMemBlock,
gBaseDynBuf0 => gBaseDynBuf0,
gBaseDynBuf1 => gBaseDynBuf1,
gBaseErrCntr => gBaseErrCntr,
gBaseTxNmtQ => gBaseTxNmtQ,
gBaseTxGenQ => gBaseTxGenQ,
gBaseTxSynQ => gBaseTxSynQ,
gBaseTxVetQ => gBaseTxVetQ,
gBaseRxVetQ => gBaseRxVetQ,
gBaseK2UQ => gBaseK2UQ,
gBaseU2KQ => gBaseU2KQ,
gBasePdo => gBasePdo,
gBaseTimeSync => gBaseTimeSync,
gBaseRes => gBaseRes,
gHostAddrWidth => gHostAddrWidth
)
port map (
iClk => csi_c0_clock,
iRst => rsi_r0_reset,
iHostAddress => avs_host_address,
iHostByteenable => avs_host_byteenable,
iHostRead => avs_host_read,
oHostReaddata => avs_host_readdata,
iHostWrite => avs_host_write,
iHostWritedata => avs_host_writedata,
oHostWaitrequest => avs_host_waitrequest,
iPcpAddress => avs_pcp_address,
iPcpByteenable => avs_pcp_byteenable,
iPcpRead => avs_pcp_read,
oPcpReaddata => avs_pcp_readdata,
iPcpWrite => avs_pcp_write,
iPcpWritedata => avs_pcp_writedata,
oPcpWaitrequest => avs_pcp_waitrequest,
oHostBridgeAddress => avm_hostBridge_address,
oHostBridgeByteenable => avm_hostBridge_byteenable,
oHostBridgeRead => avm_hostBridge_read,
iHostBridgeReaddata => avm_hostBridge_readdata,
oHostBridgeWrite => avm_hostBridge_write,
oHostBridgeWritedata => avm_hostBridge_writedata,
iHostBridgeWaitrequest => avm_hostBridge_waitrequest,
iIrqIntSync => inr_irqSync_irq,
iIrqExtSync => coe_ExtSync_exsync,
oIrq => ins_irqOut_irq
);
end rtl;
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_i2c;
use bitvis_vip_i2c.i2c_bfm_pkg.all;
use bitvis_vip_i2c.vvc_cmd_pkg.all;
use bitvis_vip_i2c.vvc_methods_pkg.all;
use bitvis_vip_i2c.td_vvc_framework_common_methods_pkg.all;
end context; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.vhdl
-- Design : system_inverter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_inverter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_inverter_0_0 : entity is "system_inverter_0_0,inverter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_inverter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_inverter_0_0 : entity is "inverter,Vivado 2016.4";
end system_inverter_0_0;
architecture STRUCTURE of system_inverter_0_0 is
begin
x_not_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x,
O => x_not
);
end STRUCTURE;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin
proc_label : process
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin end process;
end architecture rtl;
architecture rtl of fifo is
constant avmm_master_null : avmm_master_t := (
(others => '0'),
(others => '0'),
'0',
'0'
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := (
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
constant cons1 : t_type := (1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(G_GENERIC3))
))
);
constant cons1 : t_type := (1 => func1(G_GENERIC1, G_GENERIC2),
2 => func2(func3(func4(
func5(G_GENERIC3))
)));
constant cons1 : t_type :=
(
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := '0';
constant cons2 : t_type := '0' and '1'
and '0' or '1';
constant cons2 : t_type := func1(G_GENERIC1, G_GENERIC_2,
func2(G_GENERIC3));
begin end architecture rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block4
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_10_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_10_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_12_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_12_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_11_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_12_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_12_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block4 IS
-- Signals
SIGNAL dout_10_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_10_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_12_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_12_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL dout_11_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_11_im_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_12_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_12_im_tmp : signed(20 DOWNTO 0); -- sfix21
BEGIN
dout_10_re_signed <= signed(dout_10_re);
din1_re <= resize(dout_10_re_signed, 21);
dout_10_im_signed <= signed(dout_10_im);
din1_im <= resize(dout_10_im_signed, 21);
dout_12_re_signed <= signed(dout_12_re);
din2_re <= resize(dout_12_re_signed, 21);
dout_12_im_signed <= signed(dout_12_im);
din2_im <= resize(dout_12_im_signed, 21);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 22);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_11)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_11 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) - resize(din2_re, 22);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) - resize(din2_im, 22);
END IF;
dout_11_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(20 DOWNTO 0);
dout_11_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(20 DOWNTO 0);
dout_12_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(20 DOWNTO 0);
dout_12_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(20 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re_1 <= std_logic_vector(dout_12_re_tmp);
dout_12_im_1 <= std_logic_vector(dout_12_im_tmp);
END rtl;
|
-- NEED RESULT: ARCH00699: Formal generics with default expression may be left unassociated in an association list passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00699
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00699(ARCH00699)
-- ENT00699_Test_Bench(ARCH00699_Test_Bench)
--
-- REVISION HISTORY:
--
-- 09-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00699 is
generic (
g_integer : integer := 5 ;
g_boolean : boolean := false ;
g_st_arr3 : st_arr3 := c_st_arr3_2 ;
g_st_rec3 : st_rec3 := c_st_rec3_2
) ;
end ENT00699 ;
--
architecture ARCH00699 of ENT00699 is
begin
process
begin
test_report ( "ARCH00699" ,
"Formal generics with default expression may be left"
& " unassociated in an association list",
g_integer = 5 and not g_boolean and
g_st_arr3 = c_st_arr3_2 and g_st_rec3 = c_st_rec3_1) ;
wait ;
end process ;
end ARCH00699 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00699_Test_Bench is
end ENT00699_Test_Bench ;
--
architecture ARCH00699_Test_Bench of ENT00699_Test_Bench is
begin
L1:
block
component UUT
generic (
lg_st_rec3 : st_rec3
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00699 ( ARCH00699 )
generic map (
g_boolean => false ,
g_st_arr3 => c_st_arr3_2 ,
g_st_rec3 => lg_st_rec3
) ;
begin
CIS1 : UUT
generic map ( lg_st_rec3 => c_st_rec3_1 ) ;
end block L1 ;
end ARCH00699_Test_Bench ;
--
|
-------------------------------------------------------------------------------
-- Title : u2p_dut
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: Toplevel for u2p_dut.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity u2p_test is
port (
-- slot side
SLOT_BUFFER_ENn : out std_logic;
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : inout std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : inout std_logic;
SLOT_ROMLn : inout std_logic;
SLOT_IO1n : inout std_logic;
SLOT_IO2n : inout std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : inout std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : inout std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_test is
component nios_dut is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
audio_in_valid : in std_logic := 'X'; -- valid
audio_in_ready : out std_logic; -- ready
audio_out_data : out std_logic_vector(31 downto 0); -- data
audio_out_valid : out std_logic; -- valid
audio_out_ready : in std_logic := 'X'; -- ready
dummy_export : in std_logic := 'X'; -- export
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
jtag_io_input_vector : in std_logic_vector(47 downto 0) := (others => 'X'); -- input_vector
jtag_io_output_vector : out std_logic_vector(7 downto 0); -- output_vector
jtag_test_clocks_clock_1 : in std_logic := 'X'; -- clock_1
jtag_test_clocks_clock_2 : in std_logic := 'X'; -- clock_2
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
pio1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio2_export : in std_logic_vector(19 downto 0) := (others => 'X'); -- export
pio3_export : out std_logic_vector(7 downto 0); -- export
sys_clock_clk : in std_logic := 'X'; -- clk
sys_reset_reset_n : in std_logic := 'X'; -- reset_n
uart_rxd : in std_logic := 'X'; -- rxd
uart_txd : out std_logic; -- txd
uart_cts_n : in std_logic := 'X'; -- cts_n
uart_rts_n : out std_logic -- rts_n
);
end component nios_dut;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(19 downto 0) := (others => '0');
signal sys_count : unsigned(23 downto 0) := (others => '0');
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal is_idle : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
-- misc io
signal audio_in_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_in_valid : std_logic := '0'; -- valid
signal audio_in_ready : std_logic; -- ready
signal audio_out_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_out_valid : std_logic; -- valid
signal audio_out_ready : std_logic := '0'; -- ready
signal audio_speaker : signed(15 downto 0);
signal pll_locked : std_logic;
signal pio1_export : std_logic_vector(31 downto 0) := (others => '0'); -- in_port
signal pio2_export : std_logic_vector(19 downto 0) := (others => '0'); -- in_port
signal pio3_export : std_logic_vector(7 downto 0); -- out_port
signal prim_uart_rxd : std_logic := '1';
signal prim_uart_txd : std_logic := '1';
signal prim_uart_cts_n : std_logic := '1';
signal prim_uart_rts_n : std_logic := '1';
signal io_uart_rxd : std_logic := '1';
signal io_uart_txd : std_logic := '1';
signal slot_test_vector : std_logic_vector(47 downto 0);
signal jtag_write_vector : std_logic_vector(7 downto 0);
signal test_shift : std_logic_vector(47 downto 0);
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if jtag_write_vector(7) = '1' then
por_count <= (others => '0');
por_n <= '0';
elsif por_count = X"FFFFF" then
por_n <= '1';
else
por_count <= por_count + 1;
por_n <= '0';
end if;
end if;
end process;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_count <= sys_count + 1;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => pll_locked );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_dut
port map (
audio_in_data => audio_in_data,
audio_in_valid => audio_in_valid,
audio_in_ready => audio_in_ready,
audio_out_data => audio_out_data,
audio_out_valid => audio_out_valid,
audio_out_ready => audio_out_ready,
dummy_export => '0',
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
jtag_io_input_vector => slot_test_vector,
jtag_io_output_vector => jtag_write_vector,
jtag_test_clocks_clock_1 => RMII_REFCLK,
jtag_test_clocks_clock_2 => ULPI_CLOCK,
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag,
pio1_export => pio1_export,
pio2_export => pio2_export,
pio3_export => pio3_export,
sys_clock_clk => sys_clock,
sys_reset_reset_n => not sys_reset,
uart_rxd => prim_uart_rxd,
uart_txd => prim_uart_txd,
uart_cts_n => prim_uart_cts_n,
uart_rts_n => prim_uart_rts_n
);
UART_TXD <= prim_uart_txd and io_uart_txd;
prim_uart_rxd <= UART_RXD;
io_uart_rxd <= UART_RXD;
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 10,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => '0', --memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => "1111",
board_rev => not BOARD_REVn,
iec_o => open,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_version => X"7F",
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_drive_1541 => false,
g_drive_1541_2 => false,
g_hardware_gcr => false,
g_ram_expansion => false,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => false,
g_command_intf => false,
g_drive_sound => false,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_analyzer => false,
g_profiler => true,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- local bus side
mem_req => mem_req,
mem_resp => mem_resp,
-- Debug UART
UART_TXD => io_uart_txd,
UART_RXD => io_uart_rxd,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Ethernet Interface (RMII)
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
-- Buttons
BUTTON => not BUTTON );
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_divider => 10,
g_left_shift => 0,
g_width => audio_speaker'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_speaker,
dac_out => SPEAKER_DATA );
audio_speaker(15 downto 8) <= signed(audio_out_data(15 downto 8));
audio_speaker( 7 downto 0) <= signed(audio_out_data(23 downto 16));
process(jtag_write_vector, pio3_export, sys_count, pll_locked, por_n)
begin
case jtag_write_vector(6 downto 5) is
when "00" =>
LED_MOTORn <= sys_count(sys_count'high);
LED_DISKn <= pll_locked; -- if pll_locked = 0, led is on
LED_CARTn <= por_n; -- if por_n is 0, led is on
LED_SDACTn <= '0';
when "01" =>
LED_MOTORn <= not jtag_write_vector(0);
LED_DISKn <= not jtag_write_vector(1);
LED_CARTn <= not jtag_write_vector(2);
LED_SDACTn <= not jtag_write_vector(3);
when "10" =>
LED_MOTORn <= not pio3_export(0);
LED_DISKn <= not pio3_export(1);
LED_CARTn <= not pio3_export(2);
LED_SDACTn <= not pio3_export(3);
when others =>
LED_MOTORn <= '1';
LED_DISKn <= '1';
LED_CARTn <= '1';
LED_SDACTn <= '1';
end case;
end process;
ULPI_RESET <= por_n;
b_audio: block
signal stream_out_data : std_logic_vector(23 downto 0);
signal stream_out_tag : std_logic_vector(0 downto 0);
signal stream_out_valid : std_logic;
signal stream_in_data : std_logic_vector(23 downto 0);
signal stream_in_tag : std_logic_vector(0 downto 0);
signal stream_in_ready : std_logic;
signal audio_out_full : std_logic;
begin
i_aout: entity work.async_fifo_ft
generic map (
g_depth_bits => 4,
g_data_width => 25
)
port map(
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => audio_out_valid,
wr_din(24) => audio_out_data(0),
wr_din(23 downto 16) => audio_out_data(15 downto 8),
wr_din(15 downto 8) => audio_out_data(23 downto 16),
wr_din(7 downto 0) => audio_out_data(31 downto 24),
wr_full => audio_out_full,
rd_clock => audio_clock,
rd_reset => audio_reset,
rd_next => stream_in_ready,
rd_dout(24 downto 24) => stream_in_tag,
rd_dout(23 downto 0) => stream_in_data,
rd_valid => open --stream_in_valid
);
audio_out_ready <= not audio_out_full;
i_ain: entity work.synchronizer_gzw
generic map(
g_width => 25,
g_fast => false
)
port map(
tx_clock => audio_clock,
tx_push => stream_out_valid,
tx_data(24 downto 24) => stream_out_tag,
tx_data(23 downto 0) => stream_out_data,
tx_done => open,
rx_clock => sys_clock,
rx_new_data => audio_in_valid,
rx_data(24) => audio_in_data(0),
rx_data(23 downto 16) => audio_in_data(15 downto 8),
rx_data(15 downto 8) => audio_in_data(23 downto 16),
rx_data(7 downto 0) => audio_in_data(31 downto 24)
);
i2s: entity work.i2s_serializer_old
port map (
clock => audio_clock,
reset => audio_reset,
i2s_out => AUDIO_SDO,
i2s_in => AUDIO_SDI,
i2s_bclk => AUDIO_BCLK,
i2s_fs => AUDIO_LRCLK,
stream_out_data => stream_out_data,
stream_out_tag => stream_out_tag,
stream_out_valid => stream_out_valid,
stream_in_data => stream_in_data,
stream_in_tag => stream_in_tag,
stream_in_valid => '1',
stream_in_ready => stream_in_ready );
AUDIO_MCLK <= audio_clock;
end block;
SLOT_BUFFER_ENn <= '0'; -- once configured, we can connect
pio1_export(31 downto 0) <= slot_test_vector(31 downto 0);
pio2_export(15 downto 0) <= slot_test_vector(47 downto 32);
pio2_export(18 downto 16) <= not BUTTON;
slot_test_vector <= CAS_MOTOR &
CAS_SENSE &
CAS_READ &
CAS_WRITE &
IEC_ATN &
IEC_DATA &
IEC_CLOCK &
IEC_RESET &
IEC_SRQ_IN &
SLOT_PHI2 &
SLOT_DOTCLK &
SLOT_RSTn &
SLOT_RWn &
SLOT_BA &
SLOT_DMAn &
SLOT_EXROMn &
SLOT_GAMEn &
SLOT_ROMHn &
SLOT_ROMLn &
SLOT_IO1n &
SLOT_IO2n &
SLOT_IRQn &
SLOT_NMIn &
SLOT_VCC &
SLOT_DATA &
SLOT_ADDR;
process(sys_clock)
begin
if rising_edge(sys_clock) then
if sys_reset = '1' then
test_shift <= (0 => '1', 1 => '1', 2 => '1', others => '0');
else
test_shift <= test_shift(test_shift'high-1 downto 0) & test_shift(test_shift'high);
end if;
end if;
end process;
CAS_MOTOR <= test_shift(47);
CAS_SENSE <= test_shift(46);
CAS_READ <= test_shift(45);
CAS_WRITE <= test_shift(44);
IEC_ATN <= test_shift(43);
IEC_DATA <= test_shift(42);
IEC_CLOCK <= test_shift(41);
IEC_RESET <= test_shift(40);
IEC_SRQ_IN <= test_shift(39);
-- SLOT_PHI2 <= test_shift(38);
-- SLOT_DOTCLK <= test_shift(37);
SLOT_RSTn <= test_shift(36);
SLOT_RWn <= test_shift(35);
-- SLOT_BA <= test_shift(34);
SLOT_DMAn <= test_shift(33);
SLOT_EXROMn <= test_shift(32);
SLOT_GAMEn <= test_shift(31);
SLOT_ROMHn <= test_shift(30);
SLOT_ROMLn <= test_shift(29);
SLOT_IO1n <= test_shift(28);
SLOT_IO2n <= test_shift(27);
SLOT_IRQn <= test_shift(26);
SLOT_NMIn <= test_shift(25);
-- SLOT_VCC <= test_shift(24);
SLOT_DATA <= test_shift(23 downto 16);
SLOT_ADDR <= test_shift(15 downto 0);
end architecture;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00466
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.7 (5)
-- 9.7 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00466_1(ARCH00466_1)
-- ENT00466(ARCH00466)
-- ENT00466_Test_Bench(ARCH00466_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
entity ENT00466_1 is
generic ( G : Integer ) ;
port ( P : in Integer ;
Q : out Integer ) ;
end ENT00466_1 ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00466_1 of ENT00466_1 is
begin
process ( P )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := False ;
else
Q <= transport (P + G) after 0 ns ;
end if ;
end process ;
end ARCH00466_1 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00466 is
generic ( G1_Low, G1_High : t_enum1 ;
G2_Low, G2_High : Integer ) ;
end ENT00466 ;
architecture ARCH00466 of ENT00466 is
component Comp1
generic ( G : Integer ) ;
port ( P : in Integer ;
Q : out Integer ) ;
end component ;
for all : Comp1 use entity WORK.ENT00466_1 ( ARCH00466_1 );
type Arr_enum1 is array (t_enum1 range G1_Low to G1_High)
of Integer ;
signal S_enum1 : Arr_enum1 := Arr_enum1'(others => -1) ;
subtype t_uint is Integer range G2_Low to G2_High ;
type Arr_uint is array (t_uint) of Integer ;
signal S_uint : Arr_uint := Arr_uint'(others => -1) ;
begin
s_enum1(Arr_enum1'Left) <= transport t_enum1'Pos (Arr_enum1'Left) after 0 ns ;
For_Gen1 :
for i in Arr_enum1'Left to t_enum1'Pred (Arr_enum1'Right) generate
L1 : Comp1
generic map ( t_enum1'Pos ( t_enum1'Succ(i)) )
port map ( s_enum1(i), s_enum1(t_enum1'Succ(i)) ) ;
end generate For_Gen1 ;
Check_It1 :
process
variable correct : boolean := True;
variable sum : Integer := 0 ;
begin
wait for 30 ns ;
for i in Arr_enum1'range ( 1 ) loop
sum := sum + t_enum1'Pos (i) ;
correct := correct and (S_enum1(i) = sum) ;
end loop ;
test_report ( "ARCH00466.Check_It1" ,
"Globally static discrete ranges are permited on "&
"generate statements" ,
correct ) ;
wait ;
end process Check_It1 ;
------------
s_uint(Arr_uint'Left) <= transport t_uint'Pos (Arr_uint'Left) after 0 ns ;
For_Gen2 :
for i in Arr_uint'Left to t_uint'Pred (Arr_uint'Right) generate
L2 : Comp1
generic map ( t_uint'Pos ( t_uint'Succ(i)) )
port map ( s_uint(i), s_uint(t_uint'Succ(i)) ) ;
end generate For_Gen2 ;
Check_It2 :
process
variable correct : boolean := True;
variable sum : Integer := 0 ;
begin
wait for 30 ns ;
for i in Arr_uint'range ( 1 ) loop
sum := sum + t_uint'Pos (i) ;
correct := correct and (S_uint(i) = sum) ;
end loop ;
test_report ( "ARCH00466.Check_It2" ,
"Globally static discrete ranges are permited on "&
"generate statements" ,
correct ) ;
wait ;
end process Check_It2 ;
end ARCH00466 ;
entity ENT00466_Test_Bench is
end ENT00466_Test_Bench ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00466_Test_Bench of ENT00466_Test_Bench is
begin
L1:
block
component UUT generic ( G1_Low, G1_High : t_enum1 ;
G2_Low, G2_High : Integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00466 ( ARCH00466 ) ;
begin
CIS1 : UUT generic map ( t_enum1'Low, t_enum1'High,
G2_High => 20,
G2_Low => 10 ) ;
end block L1 ;
end ARCH00466_Test_Bench ;
|
library verilog;
use verilog.vl_types.all;
entity HexDriver is
port(
In0 : in vl_logic_vector(3 downto 0);
Out0 : out vl_logic_vector(6 downto 0)
);
end HexDriver;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 22 -- rom address depth (flash 4 MB)
-- sramwidth : integer := 32; -- ram data width (8/16/32)
-- sramdepth : integer := 20; -- ram address depth
-- srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal data : std_logic_vector(31 downto 24);
signal romsn : std_logic;
signal oen : std_logic;
signal writen : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal error : std_logic;
signal gpio_0 : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal gpio_1 : std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0);
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal dram_ldqm : std_logic;
signal dram_udqm : std_logic;
signal sdclk : std_logic;
signal sw : std_logic_vector(0 to 2);
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal vga_clk : std_ulogic;
signal vga_blank : std_ulogic;
signal vga_sync : std_ulogic;
signal vga_hs : std_ulogic;
signal vga_vs : std_ulogic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(13 downto 0);
signal sd : std_logic_vector(15 downto 0);
begin
clk <= not clk after ct * 1 ns; --50 MHz clk
rst <= dsurst; --reset
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
sw(0) <= '1';
gpio_0(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'H');
gpio_1(CFG_GRGPIO2_WIDTH-1 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, error, address(21 downto 0), data,
sa(11 downto 0), sa(12), sa(13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, dram_ldqm, dram_udqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, romsn, open, open, open, open, open, open, gpio_0, gpio_1,
ps2_clk, ps2_dat, vga_clk, vga_blank, vga_sync, vga_hs, vga_vs, vga_r,
vga_g, vga_b, sw);
sd1 : if (CFG_SDCTRL = 1) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 12, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(11 downto 0),
Ba => sa(13 downto 12), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0'; --reset low
wait for 500 ns;
dsurst <= '1'; --reset high
wait; --evig w8
wait for 5000 ns;
txc(dsutx, 16#55#, txp);
-- txc(dsutx, 16#c0#, txp); --control byte
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); --adress
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); --write data
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY fir_bp_lr IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END fir_bp_lr;
ARCHITECTURE fir_bp_lr_arch OF fir_bp_lr IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_bp_lr_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "fir_bp_lr",
C_COEF_FILE => "fir_bp_lr.mif",
C_COEF_FILE_LINES => 128,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 4,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 255,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "32",
C_OPTIMIZATION => 2046,
C_DATA_PATH_WIDTHS => "16",
C_DATA_IP_PATH_WIDTHS => "16",
C_DATA_PX_PATH_WIDTHS => "16",
C_DATA_WIDTH => 16,
C_COEF_PATH_WIDTHS => "20",
C_COEF_WIDTH => 20,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "39",
C_OUTPUT_WIDTH => 39,
C_OUTPUT_PATH_WIDTHS => "39",
C_ACCUM_OP_PATH_WIDTHS => "39",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 32,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 4,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 41,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 16,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 40,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END fir_bp_lr_arch;
|
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`protect end_protected
|
`protect begin_protected
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`protect data_block
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`protect end_protected
|
`protect begin_protected
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`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leon
-- File: leon.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Complete processor
------------------------------------------------------------------------------
-- modified for ddm 8.02.02 LA
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity leon is
port (
resetn : in std_logic; -- system signals
clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0); -- memory bus
---
datain : in std_logic_vector(31 downto 0); -- 32 bits conversion LA
dataout : out std_logic_vector(31 downto 0);
datasel : out std_logic_vector(3 downto 0);
---
ramsn : out std_logic_vector(3 downto 0);
ramoen : out std_logic_vector(3 downto 0);
rwen : inout std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : inout std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
---
pioo : out std_logic_vector(15 downto 0); -- I/O port 32 bits LA
pioi : in std_logic_vector(15 downto 0);
piod : out std_logic_vector(15 downto 0);
buttons : in std_logic_vector(3 downto 0); -- ddm ports
audioin : in std_logic;
digit0 : out std_logic_vector(6 downto 0);
digit1 : out std_logic_vector(6 downto 0);
audioout : out std_logic;
lr_out : out std_logic;
shift_clk : out std_logic;
mclk : out std_logic;
dispen : out std_logic;
---
wdogn : out std_logic; -- watchdog output
test : in std_logic
);
end;
architecture rtl of leon is
component mcore
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
--
ddmi : in ddm_in_type; -- DDM signals LA
ddmo : out ddm_out_type;
--
test : in std_logic
);
end component;
signal gnd, clko, resetno : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
--
signal ddmi : ddm_in_type; -- DDM signals LA
signal ddmo : ddm_out_type;
--
begin
gnd <= '0';
-- main processor core
mcore0 : mcore
port map (
resetn => resetno, clk => clko,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
-- pcii => pcii, pcio => pcio, test => test
pcii => pcii, pcio => pcio, ddmi => ddmi, ddmo => ddmo, test => test -- DDM LA
);
-- pads
-- clk_pad : inpad port map (clk, clko); -- clock
clko <= clk; -- avoid buffering during synthesis
--original lines
reset_pad : smpad port map (resetn, resetno); -- reset
brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
--DDM lines
inpad4 : inpad port map (audioin, ddmi.audioin);
inpad5 : inpad port map (buttons(0),ddmi.button0);
inpad6 : inpad port map (buttons(1),ddmi.button1);
inpad7 : inpad port map (buttons(2),ddmi.button2);
inpad8 : inpad port map (buttons(3),ddmi.button3);
-- d_pads: for i in 0 to 31 generate -- data bus
-- d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
-- end generate;
dataout <= memo.data; -- databus DDM LA
memi.data <= datain;
datasel <= memo.bdrive;
-- pio_pads : for i in 0 to 15 generate -- parallel I/O port
-- pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
-- end generate;
pioo <= ioo.piol; -- parallel I/O port DDM
ioi.piol <= pioi;
piod <= ioo.piodir;
rwen(0) <= memo.wrn(0);
memi.wrn(0) <= memo.wrn(0);
rwen(1) <= memo.wrn(1);
memi.wrn(1) <= memo.wrn(1);
rwen(2) <= memo.wrn(2);
memi.wrn(2) <= memo.wrn(2);
rwen(3) <= memo.wrn(3);
memi.wrn(3) <= memo.wrn(3);
-- rwen_pads : for i in 0 to 3 generate -- ram write strobe
-- rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
-- end generate;
-- I/O write strobe
-- writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
writen <= memo.writen; -- DDM LA
memi.writen <= memo.writen;
--
a_pads: for i in 0 to 27 generate -- memory address
a_pad : outpad generic map (3) port map (memo.address(i), address(i));
end generate;
ramsn_pads : for i in 0 to 3 generate -- ram oen/rasn
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
end generate;
ramoen_pads : for i in 0 to 3 generate -- ram chip select
eamoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
end generate;
romsn_pads : for i in 0 to 1 generate -- rom chip select
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
end generate;
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
--
outpadb7: outpad port map (ddmo.shift_clk, shift_clk); -- DDM
outpadb8: outpad port map (ddmo.lr_out, lr_out);
outpadb9: outpad port map (ddmo.audioout, audioout);
outpadb10: for i in 0 to 6 generate
outpad101: outpad port map(ddmo.digit0(i), digit0(i));
end generate;
outpadb11: for i in 0 to 6 generate
outpad111: outpad port map(ddmo.digit1(i), digit1(i));
end generate;
outpadb12: outpad port map (ddmo.mclk, mclk);
dispen <= ddmo.dispen;
--
wd : if WDOGEN generate
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
end generate;
end ;
|
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_minisys - syn
-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
--
-- Dependencies: ibdr_sdreg
-- ibd_kw11l
-- ibdr_dl11
-- ibdr_rk11
-- ib_sres_or_4
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
-- to _dl11
-- 2009-05-31 221 1.0.6 add RESET to kw11l;
-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
-- 2008-08-22 161 1.0.4 use iblib, ibdlib
-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11
-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg
-- 2008-01-20 113 1.0.1 RRI_LAM now vector
-- 2008-01-20 112 1.0 Initial version
------------------------------------------------------------------------------
--
-- mini system setup
--
-- ibbase vec pri slot attn device name
--
-- 177546 100 6 4 - KW11-L
-- 177400 220 5 3 4 RK11
-- 177560 060 4 2 1 DL11-RX 1st
-- 064 4 1 ^ DL11-TX 1st
-- 177570 - - - - sdreg
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end ibdr_minisys;
architecture syn of ibdr_minisys is
constant conf_intmap : intmap_array_type :=
(intmap_init, -- line 15
intmap_init, -- line 14
intmap_init, -- line 13
intmap_init, -- line 12
intmap_init, -- line 11
intmap_init, -- line 10
intmap_init, -- line 9
intmap_init, -- line 8
intmap_init, -- line 7
intmap_init, -- line 6
intmap_init, -- line 5
(8#100#,6), -- line 4 KW11-L
(8#220#,5), -- line 3 RK11
(8#060#,4), -- line 2 DL11-RX
(8#064#,4), -- line 1 DL11-TX
intmap_init -- line 0
);
signal RB_LAM_DL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
signal EI_REQ : slv16_1 := (others=>'0');
signal EI_ACK : slv16_1 := (others=>'0');
signal EI_REQ_KW11L : slbit := '0';
signal EI_REQ_DL11RX : slbit := '0';
signal EI_REQ_DL11TX : slbit := '0';
signal EI_REQ_RK11 : slbit := '0';
signal EI_ACK_KW11L : slbit := '0';
signal EI_ACK_DL11RX : slbit := '0';
signal EI_ACK_DL11TX : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
begin
SDREG : ibdr_sdreg
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SDREG,
DISPREG => DISPREG
);
KW11L : ibd_kw11l
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11L,
EI_REQ => EI_REQ_KW11L,
EI_ACK => EI_ACK_KW11L
);
DL11 : ibdr_dl11
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_DL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11,
EI_REQ_RX => EI_REQ_DL11RX,
EI_REQ_TX => EI_REQ_DL11TX,
EI_ACK_RX => EI_ACK_DL11RX,
EI_ACK_TX => EI_ACK_DL11TX
);
RK11 : ibdr_rk11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
EI_ACK => EI_ACK_RK11
);
SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_SDREG,
IB_SRES_2 => IB_SRES_KW11L,
IB_SRES_3 => IB_SRES_DL11,
IB_SRES_4 => IB_SRES_RK11,
IB_SRES_OR => IB_SRES
);
INTMAP : ib_intmap
generic map (
INTMAP => conf_intmap)
port map (
EI_REQ => EI_REQ,
EI_ACKM => EI_ACKM,
EI_ACK => EI_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT
);
EI_REQ(4) <= EI_REQ_KW11L;
EI_REQ(3) <= EI_REQ_RK11;
EI_REQ(2) <= EI_REQ_DL11RX;
EI_REQ(1) <= EI_REQ_DL11TX;
EI_ACK_KW11L <= EI_ACK(4);
EI_ACK_RK11 <= EI_ACK(3);
EI_ACK_DL11RX <= EI_ACK(2);
EI_ACK_DL11TX <= EI_ACK(1);
RB_LAM(1) <= RB_LAM_DL11;
RB_LAM(2) <= '0'; -- for 2nd DL11
RB_LAM(3) <= '0'; -- for DZ11
RB_LAM(4) <= RB_LAM_RK11;
RB_LAM(15 downto 5) <= (others=>'0');
end syn;
|
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_minisys - syn
-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
--
-- Dependencies: ibdr_sdreg
-- ibd_kw11l
-- ibdr_dl11
-- ibdr_rk11
-- ib_sres_or_4
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
-- to _dl11
-- 2009-05-31 221 1.0.6 add RESET to kw11l;
-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
-- 2008-08-22 161 1.0.4 use iblib, ibdlib
-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11
-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg
-- 2008-01-20 113 1.0.1 RRI_LAM now vector
-- 2008-01-20 112 1.0 Initial version
------------------------------------------------------------------------------
--
-- mini system setup
--
-- ibbase vec pri slot attn device name
--
-- 177546 100 6 4 - KW11-L
-- 177400 220 5 3 4 RK11
-- 177560 060 4 2 1 DL11-RX 1st
-- 064 4 1 ^ DL11-TX 1st
-- 177570 - - - - sdreg
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end ibdr_minisys;
architecture syn of ibdr_minisys is
constant conf_intmap : intmap_array_type :=
(intmap_init, -- line 15
intmap_init, -- line 14
intmap_init, -- line 13
intmap_init, -- line 12
intmap_init, -- line 11
intmap_init, -- line 10
intmap_init, -- line 9
intmap_init, -- line 8
intmap_init, -- line 7
intmap_init, -- line 6
intmap_init, -- line 5
(8#100#,6), -- line 4 KW11-L
(8#220#,5), -- line 3 RK11
(8#060#,4), -- line 2 DL11-RX
(8#064#,4), -- line 1 DL11-TX
intmap_init -- line 0
);
signal RB_LAM_DL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
signal EI_REQ : slv16_1 := (others=>'0');
signal EI_ACK : slv16_1 := (others=>'0');
signal EI_REQ_KW11L : slbit := '0';
signal EI_REQ_DL11RX : slbit := '0';
signal EI_REQ_DL11TX : slbit := '0';
signal EI_REQ_RK11 : slbit := '0';
signal EI_ACK_KW11L : slbit := '0';
signal EI_ACK_DL11RX : slbit := '0';
signal EI_ACK_DL11TX : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
begin
SDREG : ibdr_sdreg
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SDREG,
DISPREG => DISPREG
);
KW11L : ibd_kw11l
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11L,
EI_REQ => EI_REQ_KW11L,
EI_ACK => EI_ACK_KW11L
);
DL11 : ibdr_dl11
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_DL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11,
EI_REQ_RX => EI_REQ_DL11RX,
EI_REQ_TX => EI_REQ_DL11TX,
EI_ACK_RX => EI_ACK_DL11RX,
EI_ACK_TX => EI_ACK_DL11TX
);
RK11 : ibdr_rk11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
EI_ACK => EI_ACK_RK11
);
SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_SDREG,
IB_SRES_2 => IB_SRES_KW11L,
IB_SRES_3 => IB_SRES_DL11,
IB_SRES_4 => IB_SRES_RK11,
IB_SRES_OR => IB_SRES
);
INTMAP : ib_intmap
generic map (
INTMAP => conf_intmap)
port map (
EI_REQ => EI_REQ,
EI_ACKM => EI_ACKM,
EI_ACK => EI_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT
);
EI_REQ(4) <= EI_REQ_KW11L;
EI_REQ(3) <= EI_REQ_RK11;
EI_REQ(2) <= EI_REQ_DL11RX;
EI_REQ(1) <= EI_REQ_DL11TX;
EI_ACK_KW11L <= EI_ACK(4);
EI_ACK_RK11 <= EI_ACK(3);
EI_ACK_DL11RX <= EI_ACK(2);
EI_ACK_DL11TX <= EI_ACK(1);
RB_LAM(1) <= RB_LAM_DL11;
RB_LAM(2) <= '0'; -- for 2nd DL11
RB_LAM(3) <= '0'; -- for DZ11
RB_LAM(4) <= RB_LAM_RK11;
RB_LAM(15 downto 5) <= (others=>'0');
end syn;
|
library verilog;
use verilog.vl_types.all;
entity flexible_lvds_tx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_input: string := "ON";
use_new_coreclk_ckt: string := "FALSE";
outclock_multiply_by: integer := 1;
outclock_duty_cycle: integer := 50;
outclock_divide_by: integer := 1;
use_self_generated_outclock: string := "FALSE";
REGISTER_WIDTH : vl_notype;
DOUBLE_DESER : vl_notype;
LOAD_CNTR_MODULUS: vl_notype
);
port(
tx_in : in vl_logic_vector;
tx_fastclk : in vl_logic;
tx_slowclk : in vl_logic;
tx_regclk : in vl_logic;
tx_locked : in vl_logic;
pll_areset : in vl_logic;
pll_outclock : in vl_logic;
tx_out : out vl_logic_vector;
tx_outclock : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of registered_input : constant is 1;
attribute mti_svvh_generic_type of use_new_coreclk_ckt : constant is 1;
attribute mti_svvh_generic_type of outclock_multiply_by : constant is 1;
attribute mti_svvh_generic_type of outclock_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of outclock_divide_by : constant is 1;
attribute mti_svvh_generic_type of use_self_generated_outclock : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of DOUBLE_DESER : constant is 3;
attribute mti_svvh_generic_type of LOAD_CNTR_MODULUS : constant is 3;
end flexible_lvds_tx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic;
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we : out std_logic;
mem_clk : out std_logic
);
end memory_control;
architecture behavioral of memory_control is
signal addr_r, data_r : std_logic_vector(31 downto 0);
begin
--Not much to it, just here so it can be expanded later in need be
mem_clk <= clk;
mem_addr <= addr_r;
mem_write_data <= data_r;
data_out <= mem_read_data;
mem_we <= we;
latch : process (clk, rst) is
begin
if rst = '1' then
addr_r <= (others => '0');
data_r <= (others => '0');
elsif rising_edge(clk) then
addr_r <= address;
data_r <= data_in;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic;
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we : out std_logic;
mem_clk : out std_logic
);
end memory_control;
architecture behavioral of memory_control is
signal addr_r, data_r : std_logic_vector(31 downto 0);
begin
--Not much to it, just here so it can be expanded later in need be
mem_clk <= clk;
mem_addr <= addr_r;
mem_write_data <= data_r;
data_out <= mem_read_data;
mem_we <= we;
latch : process (clk, rst) is
begin
if rst = '1' then
addr_r <= (others => '0');
data_r <= (others => '0');
elsif rising_edge(clk) then
addr_r <= address;
data_r <= data_in;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sserial is
Port ( address : in STD_LOGIC_VECTOR (7 downto 0);
data : inout STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
read : in STD_LOGIC;
write : in STD_LOGIC);
end sserial;
architecture Behavioral of sserial is
begin
processor: entity DumbAss8
port map (
clk => fclk,
reset => '0',
iabus => iabus, -- program address bus
idbus => idbus, -- program data bus
mradd => mradd, -- memory read address
mwadd => mwadd, -- memory write address
mibus => mibus, -- memory data in bus
mobus => mobus, -- memory data out bus
mwrite => mwrite, -- memory write signal
mread => mread -- memory read signal
-- carryflg => -- carry flag
);
programROM : entity sserialrom
port map(
addr => iabus,
clk => fclk,
din => x"0000",
dout => idbus,
we => '0'
);
DataRam : entity sserialram
port map(
addra => mwadd,
addrb => mradd,
clk => fclk,
dina => mobus,
-- douta =>
doutb => mibus_ram,
wea => mwrite
);
makeUARTRs: for i in 0 to UARTs -1 generate
auarrx: entity uartr8
port map (
clk => clklow,
ibus => ibus,
obus => obus,
popfifo => LoadUARTRData(i),
loadbitratel => LoadUARTRBitRatel(i),
loadbitrateh => LoadUARTRBitRateh(i),
readbitratel => ReadUARTRBitratel(i),
readbitrateh => ReadUARTRBitrateh(i),
clrfifo => ClearUARTRFIFO(i),
readfifocount => ReadUARTRFIFOCount(i),
loadmode => LoadUARTRMode(i),
readmode => ReadUARTRMode(i),
fifohasdata => UARTRFIFOHasData(i),
rxmask => UTDrvEn(i), -- for half duplex rx mask
rxdata => UTRData(i)
);
end generate;
makeUARTTXs: for i in 0 to UARTs -1 generate
auartx: entity uartx8
port map (
clk => clklow,
ibus => ibus,
obus => obus,
pushfifo => LoadUARTXData(i),
loadbitratel => LoadUARTXBitRatel(i),
loadbitrateh => LoadUARTXBitRateh(i),
readbitratel => ReadUARTXBitratel(i),
readbitrateh => ReadUARTXBitrateh(i),
clrfifo => ClearUARTXFIFO(i),
readfifocount => ReadUARTXFIFOCount(i),
loadmode => LoadUARTXModeReg(i),
readmode => ReadUARTXModeReg(i),
fifoempty => UARTXFIFOEmpty(i),
txen => '1',
drven => UTDrvEn(i),
txdata => UTXData(i)
);
end generate;
ram_iomux : process (ioradd(11),mibus_ram,mibus_io)
begin
if ioradd(11) = '1' then
mibus <= mibus_ram;
else
mibus <= mibus_io;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_2;
ARCHITECTURE blk_mem_gen_2_arch OF blk_mem_gen_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.9418 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_2_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity top is
generic(
N: integer := 8
);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r : out STD_LOGIC_VECTOR(N-1 downto 0);
IRQ1, IRQ2 : out std_logic
);
end top;
architecture top of top is
component control_unit
port(
clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(8 downto 1);
y : out STD_LOGIC_VECTOR(16 downto 1)
);
end component;
component operational_unit
generic(
N: integer := 8
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(16 downto 1);
d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r:out STD_LOGIC_VECTOR(N-1 downto 0);
x:out STD_LOGIC_vector(8 downto 1);
IRQ1, IRQ2: out std_logic
);
end component;
signal y : std_logic_vector(16 downto 1);
signal x : std_logic_vector(8 downto 1);
signal nclk:std_logic;
begin
nclk<=not clk;
dd1:control_unit port map (clk,reset,x,y);
dd2:operational_unit port map (clk => nclk ,rst => reset,d1 => d1, d2 =>d2, y=>y, x=>x, r =>r, IRQ1 => IRQ1, IRQ2 => IRQ2);
end top; |
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_tdp is
generic(
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 9
);
port(
-- Port A
a_clk : in std_logic;
a_we : in std_logic;
a_en : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
a_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Port B
b_clk : in std_logic;
b_we : in std_logic;
b_en : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
b_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end bram_tdp;
architecture rtl of bram_tdp is
-- Shared memory
type mem_type is array ((2 ** ADDR_WIDTH) - 1 downto 0) of std_logic_vector(DATA_WIDTH - 1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(a_clk)
begin
if (a_clk'event and a_clk = '1') then
if (a_we = '1' and a_en = '1') then
mem(conv_integer(a_addr)) := a_din;
end if;
a_dout <= mem(conv_integer(a_addr));
end if;
end process;
-- Port B
process(b_clk)
begin
if (b_clk'event and b_clk = '1') then
if (b_we = '1' and b_en = '1') then
mem(conv_integer(b_addr)) := b_din;
end if;
b_dout <= mem(conv_integer(b_addr));
end if;
end process;
end rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer := 60;
Cx_rst : integer := 15;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS : in std_logic;
DRTS : in std_logic;
RTS : out std_logic;
CTS : out std_logic;
flit_type : in std_logic_vector(2 downto 0);
destination_address : in std_logic_vector(NoC_size-1 downto 0);
Grant_N_in , Grant_E_in , Grant_W_in , Grant_S_in , Grant_L_in : in std_logic;
Req_N_in , Req_E_in , Req_W_in , Req_S_in , Req_L_in :in std_logic;
shift : in std_logic;
Grant_N_out, Grant_E_out, Grant_W_out, Grant_S_out, Grant_L_out: out std_logic;
Req_N_out , Req_E_out, Req_W_out, Req_S_out, Req_L_out:out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
Xbar_sel: out std_logic_vector(4 downto 0);
error_signal_sync: out std_logic; -- this is the or of all outputs of the shift register
error_signal_async: out std_logic; -- this is the or of all outputs of the checkers
shift_serial_data: out std_logic
);
end router_channel;
architecture behavior of router_channel is
COMPONENT FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
read_pointer_out, write_pointer_out: out std_logic_vector(3 downto 0);
write_en_out :out std_logic;
-- Checker outputs
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
--err_CTS_in,
err_write_en,
err_not_CTS_in,
--err_not_write_en,
err_read_en_mismatch : out std_logic
);
end COMPONENT;
COMPONENT Arbiter
port (reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
err_IDLE_Req_N,
err_Local_Req_N,
err_South_Req_L,
err_West_Req_L,
err_South_Req_N,
err_East_Req_L,
err_West_Req_N,
err_East_Req_N,
err_next_state_onehot,
err_state_in_onehot,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port (reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : out std_logic
);
end COMPONENT;
COMPONENT shift_register is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_parallel: in std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end COMPONENT;
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal empty: std_logic;
signal combined_error_signals: std_logic_vector(58 downto 0);
signal shift_parallel_data: std_logic_vector(58 downto 0);
-- Signals related to Checkers
-- LBDR Checkers signals
signal err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in : std_logic;
-- Arbiter Checkers signals
signal err_state_IDLE_xbar, err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in, err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in, err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in, err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state, err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants, err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot, err_Requests_next_state_IDLE,
err_IDLE_Req_L, err_Local_Req_L, err_North_Req_N, err_IDLE_Req_N, err_Local_Req_N,
err_South_Req_L, err_West_Req_L, err_South_Req_N, err_East_Req_L,
err_West_Req_N, err_East_Req_N, err_next_state_onehot, err_state_in_onehot,
err_state_north_xbar_sel, err_state_east_xbar_sel,
err_state_west_xbar_sel, err_state_south_xbar_sel : std_logic;
-- FIFO Control Part Checkers signals
signal err_write_en_write_pointer, err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment,
err_write_en, err_not_CTS_in, err_read_en_mismatch : std_logic;
begin
-- OR of checker outputs
error_signal_sync <= OR_REDUCE(shift_parallel_data);
error_signal_async <= OR_REDUCE(combined_error_signals);
-- making the shift register input signal
-- please keep this like this, i use this for counting the number of the signals.
combined_error_signals <= err_header_empty_Requests_FF_Requests_in &
err_tail_Requests_in_all_zero &
err_header_tail_Requests_FF_Requests_in &
err_dst_addr_cur_addr_N1 &
err_dst_addr_cur_addr_not_N1 &
err_dst_addr_cur_addr_E1 &
err_dst_addr_cur_addr_not_E1 &
err_dst_addr_cur_addr_W1 &
err_dst_addr_cur_addr_not_W1 &
err_dst_addr_cur_addr_S1 &
err_dst_addr_cur_addr_not_S1 &
err_dst_addr_cur_addr_not_Req_L_in &
err_dst_addr_cur_addr_Req_L_in &
err_header_not_empty_Req_N_in &
err_header_not_empty_Req_E_in &
err_header_not_empty_Req_W_in &
err_header_not_empty_Req_S_in &
err_state_IDLE_xbar &
err_state_not_IDLE_xbar &
err_state_IDLE_RTS_FF_in &
err_state_not_IDLE_RTS_FF_RTS_FF_in &
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in &
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in &
err_RTS_FF_not_DCTS_state_state_in &
err_not_RTS_FF_state_in_next_state &
err_RTS_FF_DCTS_state_in_next_state &
err_not_DCTS_Grants &
err_DCTS_not_RTS_FF_Grants &
err_DCTS_RTS_FF_IDLE_Grants &
err_DCTS_RTS_FF_not_IDLE_Grants_onehot &
err_Requests_next_state_IDLE &
err_IDLE_Req_L &
err_Local_Req_L &
err_North_Req_N &
err_IDLE_Req_N &
err_Local_Req_N &
err_South_Req_L &
err_West_Req_L &
err_South_Req_N &
err_East_Req_L &
err_West_Req_N &
err_East_Req_N &
err_next_state_onehot &
err_state_in_onehot &
err_state_north_xbar_sel &
err_state_east_xbar_sel &
err_state_west_xbar_sel &
err_state_south_xbar_sel &
err_write_en_write_pointer &
err_not_write_en_write_pointer &
err_read_pointer_write_pointer_not_empty &
err_read_pointer_write_pointer_empty &
err_read_pointer_write_pointer_not_full &
err_read_pointer_write_pointer_full &
err_read_pointer_increment &
err_read_pointer_not_increment &
err_write_en &
err_not_CTS_in &
err_read_en_mismatch;
---------------------------------------------------------------------------------------------------------------------------
FIFO_unit: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, DRTS => DRTS,
read_en_N => Grant_N_in, read_en_E =>Grant_E_in, read_en_W =>Grant_W_in, read_en_S =>Grant_S_in, read_en_L =>Grant_L_in,
CTS => CTS, empty_out => empty,
read_pointer_out => read_pointer_out, write_pointer_out => write_pointer_out,
write_en_out => write_en_out,
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_CTS_in => err_not_CTS_in,
err_read_en_mismatch => err_read_en_mismatch
);
------------------------------------------------------------------------------------------------------------------------------
LBDR_unit: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty, flit_type => flit_type, dst_addr=> destination_address,
Req_N=> Req_N_out, Req_E=>Req_E_out, Req_W=>Req_W_out, Req_S=>Req_S_out, Req_L=>Req_L_out,
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in
);
------------------------------------------------------------------------------------------------------------------------------
Arbiter_unit: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_N_in , Req_E => Req_E_in, Req_W => Req_W_in, Req_S => Req_S_in, Req_L => Req_L_in,
DCTS => DCTS, Grant_N => Grant_N_out, Grant_E => Grant_E_out, Grant_W => Grant_W_out, Grant_S => Grant_S_out, Grant_L => Grant_L_out,
Xbar_sel => Xbar_sel,
RTS => RTS,
err_state_IDLE_xbar => err_state_IDLE_xbar ,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar ,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in ,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in ,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in ,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in ,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state ,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state ,
err_not_DCTS_Grants => err_not_DCTS_Grants ,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants ,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants ,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot ,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE ,
err_IDLE_Req_L => err_IDLE_Req_L ,
err_Local_Req_L => err_Local_Req_L ,
err_North_Req_N => err_North_Req_N ,
err_IDLE_Req_N => err_IDLE_Req_N ,
err_Local_Req_N => err_Local_Req_N ,
err_South_Req_L => err_South_Req_L ,
err_West_Req_L => err_West_Req_L ,
err_South_Req_N => err_South_Req_N ,
err_East_Req_L => err_East_Req_L ,
err_West_Req_N => err_West_Req_N ,
err_East_Req_N => err_East_Req_N ,
err_next_state_onehot => err_next_state_onehot ,
err_state_in_onehot => err_state_in_onehot ,
err_state_north_xbar_sel => err_state_north_xbar_sel ,
err_state_east_xbar_sel => err_state_east_xbar_sel ,
err_state_west_xbar_sel => err_state_west_xbar_sel ,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
checker_shifter: shift_register generic map (REG_WIDTH => 59)
port map (
clk => clk, reset => reset,
shift => shift,
data_in => combined_error_signals,
data_out_parallel => shift_parallel_data,
data_out_serial => shift_serial_data
);
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_05 is
end entity tb_05_05;
library ieee; use ieee.std_logic_1164.all;
architecture test of tb_05_05 is
signal a, b : std_ulogic := '0';
signal y : std_ulogic;
begin
dut : entity work.and2(detailed_delay)
port map ( a => a, b => b, y => y );
stimulus : process is
begin
wait for 10 ns;
a <= '1'; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= '1', '0' after 250 ps; wait for 10 ns;
b <= '1', '0' after 350 ps; wait for 10 ns;
b <= '1', '0' after 450 ps; wait for 10 ns;
b <= '1', '0' after 550 ps; wait for 10 ns;
b <= '1', '0' after 650 ps; wait for 10 ns;
b <= '1', '0' after 750 ps; wait for 10 ns;
b <= '1', '0' after 850 ps; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0', '1' after 250 ps; wait for 10 ns;
b <= '0', '1' after 350 ps; wait for 10 ns;
b <= '0', '1' after 450 ps; wait for 10 ns;
b <= 'X'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= 'X', '0' after 250 ps; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_05 is
end entity tb_05_05;
library ieee; use ieee.std_logic_1164.all;
architecture test of tb_05_05 is
signal a, b : std_ulogic := '0';
signal y : std_ulogic;
begin
dut : entity work.and2(detailed_delay)
port map ( a => a, b => b, y => y );
stimulus : process is
begin
wait for 10 ns;
a <= '1'; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= '1', '0' after 250 ps; wait for 10 ns;
b <= '1', '0' after 350 ps; wait for 10 ns;
b <= '1', '0' after 450 ps; wait for 10 ns;
b <= '1', '0' after 550 ps; wait for 10 ns;
b <= '1', '0' after 650 ps; wait for 10 ns;
b <= '1', '0' after 750 ps; wait for 10 ns;
b <= '1', '0' after 850 ps; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0', '1' after 250 ps; wait for 10 ns;
b <= '0', '1' after 350 ps; wait for 10 ns;
b <= '0', '1' after 450 ps; wait for 10 ns;
b <= 'X'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= 'X', '0' after 250 ps; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_05 is
end entity tb_05_05;
library ieee; use ieee.std_logic_1164.all;
architecture test of tb_05_05 is
signal a, b : std_ulogic := '0';
signal y : std_ulogic;
begin
dut : entity work.and2(detailed_delay)
port map ( a => a, b => b, y => y );
stimulus : process is
begin
wait for 10 ns;
a <= '1'; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= '1', '0' after 250 ps; wait for 10 ns;
b <= '1', '0' after 350 ps; wait for 10 ns;
b <= '1', '0' after 450 ps; wait for 10 ns;
b <= '1', '0' after 550 ps; wait for 10 ns;
b <= '1', '0' after 650 ps; wait for 10 ns;
b <= '1', '0' after 750 ps; wait for 10 ns;
b <= '1', '0' after 850 ps; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0', '1' after 250 ps; wait for 10 ns;
b <= '0', '1' after 350 ps; wait for 10 ns;
b <= '0', '1' after 450 ps; wait for 10 ns;
b <= 'X'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= 'X', '0' after 250 ps; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_SVT : integer := CONFIG_IU_SVT;
constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
constant CFG_PWD : integer := CONFIG_PWD*2;
constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
constant CFG_ISETS : integer := CFG_IU_ISETS;
constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
constant CFG_ILINE : integer := CFG_ILINE_SZ;
constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
constant CFG_DSETS : integer := CFG_IU_DSETS;
constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
constant CFG_DLINE : integer := CFG_DLINE_SZ;
constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
constant CFG_MMUEN : integer := CONFIG_MMUEN;
constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
constant CFG_ITBSZ : integer := CFG_DSU_ITB;
constant CFG_ATBSZ : integer := CFG_DSU_ATB;
constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
|
-- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_SVT : integer := CONFIG_IU_SVT;
constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
constant CFG_PWD : integer := CONFIG_PWD*2;
constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
constant CFG_ISETS : integer := CFG_IU_ISETS;
constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
constant CFG_ILINE : integer := CFG_ILINE_SZ;
constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
constant CFG_DSETS : integer := CFG_IU_DSETS;
constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
constant CFG_DLINE : integer := CFG_DLINE_SZ;
constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
constant CFG_MMUEN : integer := CONFIG_MMUEN;
constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
constant CFG_ITBSZ : integer := CFG_DSU_ITB;
constant CFG_ATBSZ : integer := CFG_DSU_ATB;
constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
|
-- $Id: s7_cmt_sfs_2_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs_2 - syn
-- Description: Series-7 CMT for dual frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-18 1072 1.0 Initial version (derived from s7_cmt_sfs_3_unisim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s7_cmt_sfs_2 is -- 7-Series CMT for dual freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT0_DIVIDE : positive := 1; -- output divide
OUT1_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKOUT0 : out slbit; -- clock output 0
CLKOUT1 : out slbit; -- clock output 1
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs_2;
architecture syn of s7_cmt_sfs_2 is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "MMCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
OUT0_DIVIDE=1 and OUT1_DIVIDE=1 generate
CLKOUT0 <= CLKIN;
CLKOUT1 <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not (VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
OUT0_DIVIDE=1 and OUT1_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKFBOUT_BUF : slbit;
signal CLKOUT0_PLL : slbit;
signal CLKOUT1_PLL : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
signal CLKOUT6_UNUSED : slbit;
pure function bool2string (val : boolean) return string is
begin
if val then
return "TRUE";
else
return "FALSE";
end if;
end function bool2string;
begin
PLL : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT0_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => CLKIN_PERIOD,
REF_JITTER1 => CLKIN_JITTER,
STARTUP_WAIT => bool2string(STARTUP_WAIT))
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0_PLL,
CLKOUT1 => CLKOUT1_PLL,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT_BUF,
CLKIN1 => CLKIN,
LOCKED => LOCKED,
PWRDWN => '0',
RST => '0'
);
BUFG_CLKFB : BUFG
port map (
I => CLKFBOUT,
O => CLKFBOUT_BUF
);
BUFG_CLKOUT0 : BUFG
port map (
I => CLKOUT0_PLL,
O => CLKOUT0
);
BUFG_CLKOUT1 : BUFG
port map (
I => CLKOUT1_PLL,
O => CLKOUT1
);
end generate USEPLL;
USEMMCM: if GEN_TYPE = "MMCM" and
not (VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
OUT0_DIVIDE=1 and OUT1_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKFBOUT_BUF : slbit;
signal CLKFBOUTB_UNUSED : slbit;
signal CLKOUT0_MMCM : slbit;
signal CLKOUT0B_UNUSED : slbit;
signal CLKOUT1_MMCM : slbit;
signal CLKOUT1B_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT2B_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT3B_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
signal CLKOUT6_UNUSED : slbit;
begin
MMCM : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT_F => real(VCO_MULTIPLY),
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE_F => real(OUT0_DIVIDE),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => CLKIN_PERIOD,
REF_JITTER1 => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKFBOUT => CLKFBOUT,
CLKFBOUTB => CLKFBOUTB_UNUSED,
CLKOUT0 => CLKOUT0_MMCM,
CLKOUT0B => CLKOUT0B_UNUSED,
CLKOUT1 => CLKOUT1_MMCM,
CLKOUT1B => CLKOUT1B_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT2B => CLKOUT2B_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT3B => CLKOUT3B_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT_BUF,
CLKIN1 => CLKIN,
LOCKED => LOCKED,
PWRDWN => '0',
RST => '0'
);
BUFG_CLKFB : BUFG
port map (
I => CLKFBOUT,
O => CLKFBOUT_BUF
);
BUFG_CLKOUT0 : BUFG
port map (
I => CLKOUT0_MMCM,
O => CLKOUT0
);
BUFG_CLKOUT1 : BUFG
port map (
I => CLKOUT1_MMCM,
O => CLKOUT1
);
end generate USEMMCM;
end syn;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XDM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XDM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XDM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;
|
--!
--! Simple PWM generator
--!
--! PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--!
--! Example:
--! clk = 50 MHz
--! clk_en = constant '1' (no prescaler)
--! width = 8 => value = 0..255
--!
--! => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
--!
--! Value (for width = 8):
--! 0 => output constant low
--! 1 => 254 cycle low, 1 cycle high
--! 127 => 50% (128 cycles low, 127 cycles high)
--! 128 => 50% (127 cycles low, 128 cycles high)
--! 254 => 1 cycle low, 254 cycles high
--! 255 => output constant high
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm is
generic (
WIDTH : natural := 12); --! Number of bits used for the PWM (12bit => 0..4095)
port (
clk_en_p : in std_logic; --! clock enable
value_p : in std_logic_vector (width - 1 downto 0);
output_p : out std_logic;
reset : in std_logic; --! High active, Restarts the PWM period
clk : in std_logic
);
end pwm;
-- ----------------------------------------------------------------------------
architecture simple of pwm is
signal count : integer range 0 to ((2 ** WIDTH) - 2) := 0;
signal value_buf : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
-- Counter
process
begin
wait until rising_edge(clk);
if reset = '1' then
-- Load new value and reset counter => restart periode
count <= 0;
value_buf <= value_p;
elsif clk_en_p = '1' then
-- counter
if count < ((2 ** WIDTH) - 2) then
count <= count + 1;
else
count <= 0;
-- Load new value from the shadow register (not active before
-- the next clock cycle)
value_buf <= value_p;
end if;
end if;
end process;
-- Generate Output
process
begin
wait until rising_edge(clk);
if reset = '1' then
output_p <= '0';
else
-- comparator for the output
if count >= to_integer(unsigned(value_buf)) then
output_p <= '0';
else
output_p <= '1';
end if;
end if;
end process;
end simple;
|
--!
--! Simple PWM generator
--!
--! PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--!
--! Example:
--! clk = 50 MHz
--! clk_en = constant '1' (no prescaler)
--! width = 8 => value = 0..255
--!
--! => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
--!
--! Value (for width = 8):
--! 0 => output constant low
--! 1 => 254 cycle low, 1 cycle high
--! 127 => 50% (128 cycles low, 127 cycles high)
--! 128 => 50% (127 cycles low, 128 cycles high)
--! 254 => 1 cycle low, 254 cycles high
--! 255 => output constant high
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm is
generic (
WIDTH : natural := 12); --! Number of bits used for the PWM (12bit => 0..4095)
port (
clk_en_p : in std_logic; --! clock enable
value_p : in std_logic_vector (width - 1 downto 0);
output_p : out std_logic;
reset : in std_logic; --! High active, Restarts the PWM period
clk : in std_logic
);
end pwm;
-- ----------------------------------------------------------------------------
architecture simple of pwm is
signal count : integer range 0 to ((2 ** WIDTH) - 2) := 0;
signal value_buf : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
-- Counter
process
begin
wait until rising_edge(clk);
if reset = '1' then
-- Load new value and reset counter => restart periode
count <= 0;
value_buf <= value_p;
elsif clk_en_p = '1' then
-- counter
if count < ((2 ** WIDTH) - 2) then
count <= count + 1;
else
count <= 0;
-- Load new value from the shadow register (not active before
-- the next clock cycle)
value_buf <= value_p;
end if;
end if;
end process;
-- Generate Output
process
begin
wait until rising_edge(clk);
if reset = '1' then
output_p <= '0';
else
-- comparator for the output
if count >= to_integer(unsigned(value_buf)) then
output_p <= '0';
else
output_p <= '1';
end if;
end if;
end process;
end simple;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--- 0 1 2 | Q W E
--- 3 4 5 | A S D
--- 6 7 8 | Z X C
entity board_dec is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
char : in std_logic_vector(6 downto 0);
single_0 : out std_logic;
single_1 : out std_logic;
single_2 : out std_logic;
single_3 : out std_logic;
single_4 : out std_logic;
single_5 : out std_logic;
single_6 : out std_logic;
single_7 : out std_logic;
single_8 : out std_logic
);
end board_dec;
architecture board_decode_arch of board_dec is
-- Define ASCIIg
constant Q : std_logic_vector(6 downto 0) := "1010001";
constant W : std_logic_vector(6 downto 0) := "1010111";
constant E : std_logic_vector(6 downto 0) := "1000101";
constant A : std_logic_vector(6 downto 0) := "1000001";
constant S : std_logic_vector(6 downto 0) := "1010011";
constant D : std_logic_vector(6 downto 0) := "1000100";
constant Z : std_logic_vector(6 downto 0) := "1011010";
constant X : std_logic_vector(6 downto 0) := "1011000";
constant C : std_logic_vector(6 downto 0) := "1000011";
begin
process (clock, reset, enable, char)
begin
if reset = '1' then
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
elsif clock'event and clock = '1' then
case char is
when Q =>
single_0 <= '1';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when W =>
single_0 <= '0';
single_1 <= '1';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when E =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '1';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when A =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '1';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when S =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '1';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when D =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '1';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when Z =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '1';
single_7 <= '0';
single_8 <= '0';
when X =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '1';
single_8 <= '0';
when C =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '1';
when others =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
end case;
end if;
end process;
end board_decode_arch; |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_duo.vhf
-- /___/ /\ Timestamp : 28/07/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronFpga_duo
--Device: Spartan6 LX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity ElectronFpga_duo is
port (
clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERST : in std_logic;
red : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audioL : out std_logic;
audioR : out std_logic;
casIn : in std_logic;
casOut : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
SRAM_nOE : out std_logic;
SRAM_nWE : out std_logic;
SRAM_nCS : out std_logic;
SRAM_A : out std_logic_vector (20 downto 0);
SRAM_D : inout std_logic_vector (7 downto 0);
ARDUINO_RESET : out std_logic;
SW1 : in std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO pin
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
DIP : in std_logic_vector(1 downto 0);
test : out std_logic_vector(7 downto 0);
avr_RxD : in std_logic;
avr_TxD : out std_logic
);
end;
architecture behavioral of ElectronFpga_duo is
signal clock_16 : std_logic;
signal clock_24 : std_logic;
signal clock_32 : std_logic;
signal clock_33 : std_logic;
signal clock_40 : std_logic;
signal hard_reset_n : std_logic;
signal powerup_reset_n : std_logic;
signal reset_counter : std_logic_vector (9 downto 0);
signal RAM_A : std_logic_vector (18 downto 0);
signal RAM_Din : std_logic_vector (7 downto 0);
signal RAM_Dout : std_logic_vector (7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- start address of user data in FLASH as obtained from bitmerge.py
-- this is safely beyond the end of the bitstream
constant user_address : std_logic_vector(23 downto 0) := x"060000";
-- lenth of user data in FLASH = 256KB (16x 16K ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"040000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
inst_pll1: entity work.pll1 port map(
-- 32 MHz input clock
CLKIN_IN => clk_32M00,
-- the main system clock, and also the video clock in sRGB mode
CLK0_OUT => clock_16,
-- used as a 24.00MHz for the SAA5050 in Mode 7
CLK1_OUT => clock_24,
-- used as a output clock MIST scan doubler for the SAA5050 in Mode 7
CLK2_OUT => clock_32,
-- used as a video clock when the ULA is in 60Hz VGA Mode
CLK3_OUT => clock_40
);
inst_dcm1 : entity work.dcm1 port map(
CLKIN_IN => clk_32M00,
-- used as a video clock when the ULA is in 50Hz VGA Mode
CLKFX_OUT => clock_33
);
electron_core : entity work.ElectronFpga_core
generic map (
IncludeICEDebugger => true,
IncludeABRRegs => true,
IncludeJafaMode7 => true
)
port map (
clk_16M00 => clock_16,
clk_24M00 => clock_24,
clk_32M00 => clock_32,
clk_33M33 => clock_33,
clk_40M00 => clock_40,
hard_reset_n => hard_reset_n,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
video_red => red,
video_green => green,
video_blue => blue,
video_vsync => vsync,
video_hsync => hsync,
audio_l => audioL,
audio_r => audioR,
ext_nOE => RAM_nOE,
ext_nWE => RAM_nWE,
ext_nCS => RAM_nCS,
ext_A => RAM_A,
ext_Dout => RAM_Dout,
ext_Din => RAM_Din,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
caps_led => LED1,
motor_led => LED2,
cassette_in => casIn,
cassette_out => casOut,
vid_mode => DIP,
test => test,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
cpu_addr => open
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- Generate a reliable power up reset, as ERST on the Papilio doesn't do this
reset_gen : process(clock_32)
begin
if rising_edge(clock_32) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= not ERST and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- Papilio Duo Misc
--------------------------------------------------------
-- Follow convention for keeping Arduino reset
ARDUINO_RESET <= SW1;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
user_address => user_address,
user_length => user_length
)
port map(
clock => clock_16,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => SRAM_nOE,
SRAM_nWE => SRAM_nWE,
SRAM_nCS => SRAM_nCS,
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc849.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00849pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00849pkg_b;
package body c01s03b01x00p12n01i00849pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00849pkg_b;
use work.c01s03b01x00p12n01i00849pkg_b.all;
package c01s03b01x00p12n01i00849pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00849pkg_a;
use work.c01s03b01x00p12n01i00849pkg_a.all;
use work.c01s03b01x00p12n01i00849pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00849pkg_a.all;
use work.c01s03b01x00p12n01i00849pkg_b.all;
ENTITY c01s03b01x00p12n01i00849ent IS
END c01s03b01x00p12n01i00849ent;
ARCHITECTURE c01s03b01x00p12n01i00849arch OF c01s03b01x00p12n01i00849ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00849"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00849 - Block configuration apply to implicit blocks generated by that generate statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00849arch;
configuration c01s03b01x00p12n01i00849cfg of c01s03b01x00p12n01i00849ent is
for c01s03b01x00p12n01i00849arch
for K
for T5:test use configuration work.testbench;
end for;
for G
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc849.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00849pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00849pkg_b;
package body c01s03b01x00p12n01i00849pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00849pkg_b;
use work.c01s03b01x00p12n01i00849pkg_b.all;
package c01s03b01x00p12n01i00849pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00849pkg_a;
use work.c01s03b01x00p12n01i00849pkg_a.all;
use work.c01s03b01x00p12n01i00849pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00849pkg_a.all;
use work.c01s03b01x00p12n01i00849pkg_b.all;
ENTITY c01s03b01x00p12n01i00849ent IS
END c01s03b01x00p12n01i00849ent;
ARCHITECTURE c01s03b01x00p12n01i00849arch OF c01s03b01x00p12n01i00849ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00849"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00849 - Block configuration apply to implicit blocks generated by that generate statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00849arch;
configuration c01s03b01x00p12n01i00849cfg of c01s03b01x00p12n01i00849ent is
for c01s03b01x00p12n01i00849arch
for K
for T5:test use configuration work.testbench;
end for;
for G
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc849.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00849pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00849pkg_b;
package body c01s03b01x00p12n01i00849pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00849pkg_b;
use work.c01s03b01x00p12n01i00849pkg_b.all;
package c01s03b01x00p12n01i00849pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00849pkg_a;
use work.c01s03b01x00p12n01i00849pkg_a.all;
use work.c01s03b01x00p12n01i00849pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00849pkg_a.all;
use work.c01s03b01x00p12n01i00849pkg_b.all;
ENTITY c01s03b01x00p12n01i00849ent IS
END c01s03b01x00p12n01i00849ent;
ARCHITECTURE c01s03b01x00p12n01i00849arch OF c01s03b01x00p12n01i00849ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00849"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00849 - Block configuration apply to implicit blocks generated by that generate statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00849arch;
configuration c01s03b01x00p12n01i00849cfg of c01s03b01x00p12n01i00849ent is
for c01s03b01x00p12n01i00849arch
for K
for T5:test use configuration work.testbench;
end for;
for G
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc576.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:35 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00576ent IS
END c03s04b01x00p01n01i00576ent;
ARCHITECTURE c03s04b01x00p01n01i00576arch OF c03s04b01x00p01n01i00576ent IS
type natural_file is file of natural;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_file open read_mode is "iofile.18";
variable v : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00576"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00576 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00576arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc576.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:35 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00576ent IS
END c03s04b01x00p01n01i00576ent;
ARCHITECTURE c03s04b01x00p01n01i00576arch OF c03s04b01x00p01n01i00576ent IS
type natural_file is file of natural;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_file open read_mode is "iofile.18";
variable v : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00576"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00576 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00576arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc576.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:35 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00576ent IS
END c03s04b01x00p01n01i00576ent;
ARCHITECTURE c03s04b01x00p01n01i00576arch OF c03s04b01x00p01n01i00576ent IS
type natural_file is file of natural;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_file open read_mode is "iofile.18";
variable v : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00576"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00576 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00576arch;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_ibea_entity;
ARCHITECTURE ewf_ibea_description OF ewf_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
WHEN "00000011" =>
register3 := register2 + 5;
register4 := input2 + 6;
WHEN "00000100" =>
register3 := register4 + register3;
WHEN "00000101" =>
register5 := register3 * 8;
WHEN "00000110" =>
register6 := register3 * 10;
register5 := register2 + register5;
WHEN "00000111" =>
register3 := register3 + register5;
register2 := register2 + register5;
WHEN "00001000" =>
register6 := register4 + register6;
register2 := register2 * 12;
WHEN "00001001" =>
register4 := register4 + register6;
output1 <= register6 + register3;
WHEN "00001010" =>
register3 := register4 * 15;
register2 := register1 + register2;
WHEN "00001011" =>
register1 := register1 + register2;
WHEN "00001100" =>
register1 := register1 * 17;
register4 := register5 + register2;
WHEN "00001101" =>
register1 := register1 + 19;
WHEN "00001110" =>
output2 <= register2 + register1;
register1 := register4 + 22;
WHEN "00001111" =>
register2 := register1 * 24;
WHEN "00010000" =>
register2 := register2 + 26;
WHEN "00010001" =>
output3 <= register1 + register2;
register1 := register3 + 29;
WHEN "00010010" =>
register2 := register6 + register1;
WHEN "00010011" =>
register2 := register2 + 31;
WHEN "00010100" =>
register3 := register2 * 33;
register4 := register1 + 35;
WHEN "00010101" =>
register3 := register3 + 37;
register4 := register4 * 39;
WHEN "00010110" =>
output4 <= register2 + register3;
output5 <= register1 + register4;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_ibea_description; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:33:05 07/07/2015
-- Design Name:
-- Module Name: OFDM_ESTyEQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY OFDM_ESTyEQ IS PORT (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
end_all : out STD_LOGIC);
end OFDM_ESTyEQ;
architecture Behavioral of OFDM_ESTyEQ is
COMPONENT DPRAM_10 IS PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0));
END COMPONENT;
COMPONENT DPRAM_12 PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END COMPONENT;
COMPONENT SPRAM_12
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT ESTIMADOR PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
start : IN STD_LOGIC;
fin : OUT STD_LOGIC;
addr_y : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
addr_h : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
y_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
h_data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
write_h : OUT STD_LOGIC_VECTOR(0 DOWNTO 0));
END COMPONENT;
COMPONENT ECUALIZADOR PORT(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
fin : out STD_LOGIC;
y_data : in STD_LOGIC_VECTOR (19 downto 0);
h_data : in STD_LOGIC_VECTOR (23 downto 0);
y_est_data : out STD_LOGIC_VECTOR (23 downto 0);
y_addr : out STD_LOGIC_VECTOR (10 downto 0);
h_addr : out STD_LOGIC_VECTOR (10 downto 0);
y_est_addr : out STD_LOGIC_VECTOR (10 downto 0);
write_y_est : out STD_LOGIC_VECTOR (0 downto 0));
end COMPONENT;
SIGNAL fin : STD_LOGIC;
SIGNAL addr_y_a,addr_y_b,addr_h_a,addr_h_b,addr_y_est : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL h_in,h_out,y_est_data : STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL y_data_a,y_data_b : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL write_h,write_y_est : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL y_est_out :STD_LOGIC_VECTOR(23 DOWNTO 0);
BEGIN
est: ESTIMADOR
port map(
clk => clk,
rst => rst,
start => start,
fin => fin,
addr_y => addr_y_a,
addr_h => addr_h_a,
y_data => y_data_a,
h_data => h_in,
write_h => write_h
);
eq: ECUALIZADOR
PORT MAP(
clk => clk,
rst => rst,
start => fin,
fin => end_all,
y_data => y_data_b,
h_data => h_out,
y_est_data => y_est_data,
y_addr => addr_y_b,
h_addr => addr_h_b,
y_est_addr => addr_y_est,
write_y_est => write_y_est
);
y_mem : DPRAM_10
PORT MAP(
clka => clk,
wea => "0",
addra => addr_y_a,
dina => y_data_a,
clkb=> clk,
addrb => addr_y_b,
doutb => y_data_b
);
h_mem : DPRAM_12
PORT MAP (
clka => clk,
wea => write_h,
addra => addr_h_a,
dina => h_in,
clkb => clk,
addrb => addr_h_b,
doutb => h_out
);
y_est_mem : SPRAM_12
PORT MAP (
clka => clk,
wea => write_y_est,
addra => addr_y_est,
dina => y_est_data,
douta => y_est_out
);
end Behavioral;
|
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY pala IS
GENERIC (
DEFAULT_POS_X : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 10)
);
PORT (
-- Puertos para dibujado
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Botones de control
btn_up : IN STD_LOGIC;
btn_down : IN STD_LOGIC;
-- Control de rebotes de bola
bola_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rebote : OUT STD_LOGIC
);
END pala;
ARCHITECTURE funcional OF pala IS
-- Constantes de la pantalla
CONSTANT PANTALLA_ANCHO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(640, 10);
CONSTANT PANTALLA_ALTO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(480, 10);
-- Constantes de tamaño y movimiento
CONSTANT SIZE_X : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(10, 10);
CONSTANT SIZE_Y : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(50, 10);
CONSTANT VELO_POSI : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(4, 10);
CONSTANT VELO_NEGA : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(-4, 10);
-- Variables de movimiento
CONSTANT POS_X : STD_LOGIC_VECTOR(9 DOWNTO 0) := DEFAULT_POS_X;
SIGNAL pos_y : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(240, 10);
SIGNAL velo_y : STD_LOGIC_VECTOR(9 DOWNTO 0);
-- Variables de dibujo
SIGNAL red_data : STD_LOGIC;
SIGNAL green_data : STD_LOGIC;
SIGNAL blue_data : STD_LOGIC;
BEGIN
Red <= red_data;
Green <= green_data;
Blue <= blue_data;
--------------------------------
-- Proceso para determinar si --
-- se ha de pintar la pala. --
--------------------------------
PintaPala: PROCESS (pos_y, pixel_column, pixel_row)
BEGIN
-- Comprueba que el pixel a pintar es de la pala
IF (pixel_column + SIZE_X >= POS_X) AND (pixel_column <= POS_X + SIZE_X) AND
(pixel_row + SIZE_Y >= pos_y) AND (pixel_row <= pos_y + SIZE_Y) THEN
red_data <= '1';
green_data <= '0';
blue_data <= '0';
ELSE
red_data <= '0';
green_data <= '0';
blue_data <= '0';
END IF;
END process PintaPala;
--------------------------------
-- Proceso para mover la --
-- pala. --
--------------------------------
MuevePala: PROCESS (vert_sync)
BEGIN
-- Mover la pala cada vert_sync
IF vert_sync'EVENT AND vert_sync = '1' THEN
-- Detectar los bordes superior e inferior de la pantalla
IF pos_y <= SIZE_Y and btn_up = '1' THEN
velo_y <= CONV_STD_LOGIC_VECTOR(0, 10);
ELSIF (pos_y >= PANTALLA_ALTO - SIZE_Y) and btn_down = '1' THEN
velo_y <= CONV_STD_LOGIC_VECTOR(0, 10);
-- Detecta si se ha pulsado una tecla
ELSIF btn_up = '0' THEN
velo_y <= VELO_POSI;
ELSIF btn_down = '0' THEN
velo_y <= VELO_NEGA;
ELSE
velo_y <= CONV_STD_LOGIC_VECTOR(0, 10);
END IF;
-- Calcular la siguiente posicion de la bola
pos_y <= pos_y + velo_y;
END IF;
END PROCESS MuevePala;
ReboteBola: PROCESS (bola_x, bola_y, bola_size_x, bola_size_y, pos_y)
BEGIN
IF (bola_x <= POS_X + SIZE_X + bola_size_x) and
(bola_x + SIZE_X >= POS_X + bola_size_x) and
(bola_y <= pos_y + SIZE_Y + bola_size_y) and
(pos_y <= bola_y + bola_size_y + SIZE_Y) THEN
rebote <= '1';
ELSIF (bola_x + bola_size_x + SIZE_X >= POS_X) and
(bola_x + bola_size_x <= POS_X + SIZE_X) and
(bola_y <= pos_y + SIZE_Y + bola_size_y) and
(pos_y <= bola_y + bola_size_y + SIZE_Y) THEN
rebote <= '1';
ELSE
rebote <= '0';
END IF;
END PROCESS ReboteBola;
END funcional; |
-- NEED RESULT: *** An assertion follows with severity level FAILURE
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00325
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00325)
-- ENT00325_Test_Bench(ARCH00325_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match the comment messages output.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00325 of E00000 is
signal Dummy : Boolean := false;
begin
P1 :
process ( Dummy )
begin
print ("*** An assertion follows with severity level FAILURE") ;
end process P1 ;
assert Dummy
report "An assertion with severity FAILURE"
severity Severity_Level'High ;
end ARCH00325 ;
entity ENT00325_Test_Bench is
end ENT00325_Test_Bench ;
architecture ARCH00325_Test_Bench of ENT00325_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00325 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00325_Test_Bench ;
|
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1987
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <REFERENCES>
--!
--! \copyright <COPYRIGHT_OR_LICENSE>
--!
--! Revision history:
--!
--! \version <VERSION>
--! \date <YYYY-MM-DD>
--! \author <AUTHOR_NAME>
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package template_package is
end template_package;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package body template_package is
end template_package;
|
library verilog;
use verilog.vl_types.all;
entity altmult_accum is
generic(
width_a : integer := 2;
width_b : integer := 2;
width_c : integer := 22;
width_result : integer := 5;
number_of_multipliers: integer := 1;
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
multiplier1_direction: string := "UNUSED";
multiplier3_direction: string := "UNUSED";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg: string := "CLOCK0";
addnsub_pipeline_aclr: string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr: string := "ACLR3";
accum_sload_pipeline_reg: string := "CLOCK0";
accum_sload_pipeline_aclr: string := "ACLR3";
representation_a: string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a: string := "CLOCK0";
sign_pipeline_aclr_a: string := "ACLR3";
port_signb : string := "PORT_CONNECTIVITY";
representation_b: string := "UNSIGNED";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b: string := "CLOCK0";
sign_pipeline_aclr_b: string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR3";
lpm_type : string := "altmult_accum";
lpm_hint : string := "UNUSED";
extra_multiplier_latency: integer := 0;
extra_accumulator_latency: integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
intended_device_family: string := "Stratix";
accum_round_aclr: string := "ACLR3";
accum_round_pipeline_aclr: string := "ACLR3";
accum_round_pipeline_reg: string := "CLOCK0";
accum_round_reg : string := "CLOCK0";
accum_saturation_aclr: string := "ACLR3";
accum_saturation_pipeline_aclr: string := "ACLR3";
accum_saturation_pipeline_reg: string := "CLOCK0";
accum_saturation_reg: string := "CLOCK0";
accum_sload_upper_data_aclr: string := "ACLR3";
accum_sload_upper_data_pipeline_aclr: string := "ACLR3";
accum_sload_upper_data_pipeline_reg: string := "CLOCK0";
accum_sload_upper_data_reg: string := "CLOCK0";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr: string := "ACLR3";
mult_saturation_reg: string := "CLOCK0";
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
width_upper_data: integer := 1;
multiplier_rounding: string := "NO";
multiplier_saturation: string := "NO";
accumulator_rounding: string := "NO";
accumulator_saturation: string := "NO";
port_mult_is_saturated: string := "UNUSED";
port_accum_is_saturated: string := "UNUSED";
int_width_a : vl_notype;
int_width_b : vl_notype;
int_width_result: vl_notype;
int_extra_width : vl_notype;
diff_width_a : vl_notype;
diff_width_b : vl_notype;
sat_for_ini : vl_notype;
mult_round_for_ini: vl_notype;
bits_to_round : vl_notype;
sload_for_limit : vl_notype;
accum_sat_for_limit: vl_notype;
int_width_extra_bit: vl_notype;
preadder_mode : string := "SIMPLE";
loadconst_value : integer := 0;
width_coef : integer := 0;
loadconst_control_register: string := "CLOCK0";
loadconst_control_aclr: string := "ACLR0";
coefsel0_register: string := "CLOCK0";
coefsel1_register: string := "CLOCK0";
coefsel2_register: string := "CLOCK0";
coefsel3_register: string := "CLOCK0";
coefsel0_aclr : string := "ACLR0";
coefsel1_aclr : string := "ACLR0";
coefsel2_aclr : string := "ACLR0";
coefsel3_aclr : string := "ACLR0";
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
datac : in vl_logic_vector;
scanina : in vl_logic_vector;
scaninb : in vl_logic_vector;
sourcea : in vl_logic;
sourceb : in vl_logic;
accum_sload_upper_data: in vl_logic_vector;
addnsub : in vl_logic;
accum_sload : in vl_logic;
signa : in vl_logic;
signb : in vl_logic;
clock0 : in vl_logic;
clock1 : in vl_logic;
clock2 : in vl_logic;
clock3 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
aclr0 : in vl_logic;
aclr1 : in vl_logic;
aclr2 : in vl_logic;
aclr3 : in vl_logic;
result : out vl_logic_vector;
overflow : out vl_logic;
scanouta : out vl_logic_vector;
scanoutb : out vl_logic_vector;
mult_round : in vl_logic;
mult_saturation : in vl_logic;
accum_round : in vl_logic;
accum_saturation: in vl_logic;
mult_is_saturated: out vl_logic;
accum_is_saturated: out vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of width_c : constant is 1;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of input_reg_a : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a : constant is 1;
attribute mti_svvh_generic_type of multiplier1_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier3_direction : constant is 1;
attribute mti_svvh_generic_type of input_reg_b : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b : constant is 1;
attribute mti_svvh_generic_type of port_addnsub : constant is 1;
attribute mti_svvh_generic_type of addnsub_reg : constant is 1;
attribute mti_svvh_generic_type of addnsub_aclr : constant is 1;
attribute mti_svvh_generic_type of addnsub_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of addnsub_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of accum_sload_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of representation_a : constant is 1;
attribute mti_svvh_generic_type of port_signa : constant is 1;
attribute mti_svvh_generic_type of sign_reg_a : constant is 1;
attribute mti_svvh_generic_type of sign_aclr_a : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_reg_a : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_aclr_a : constant is 1;
attribute mti_svvh_generic_type of port_signb : constant is 1;
attribute mti_svvh_generic_type of representation_b : constant is 1;
attribute mti_svvh_generic_type of sign_reg_b : constant is 1;
attribute mti_svvh_generic_type of sign_aclr_b : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_reg_b : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_aclr_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_reg : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr : constant is 1;
attribute mti_svvh_generic_type of output_reg : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of extra_multiplier_latency : constant is 1;
attribute mti_svvh_generic_type of extra_accumulator_latency : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of accum_round_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_round_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_round_reg : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_reg : constant is 1;
attribute mti_svvh_generic_type of mult_round_aclr : constant is 1;
attribute mti_svvh_generic_type of mult_round_reg : constant is 1;
attribute mti_svvh_generic_type of mult_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of mult_saturation_reg : constant is 1;
attribute mti_svvh_generic_type of input_source_a : constant is 1;
attribute mti_svvh_generic_type of input_source_b : constant is 1;
attribute mti_svvh_generic_type of width_upper_data : constant is 1;
attribute mti_svvh_generic_type of multiplier_rounding : constant is 1;
attribute mti_svvh_generic_type of multiplier_saturation : constant is 1;
attribute mti_svvh_generic_type of accumulator_rounding : constant is 1;
attribute mti_svvh_generic_type of accumulator_saturation : constant is 1;
attribute mti_svvh_generic_type of port_mult_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_accum_is_saturated : constant is 1;
attribute mti_svvh_generic_type of int_width_a : constant is 3;
attribute mti_svvh_generic_type of int_width_b : constant is 3;
attribute mti_svvh_generic_type of int_width_result : constant is 3;
attribute mti_svvh_generic_type of int_extra_width : constant is 3;
attribute mti_svvh_generic_type of diff_width_a : constant is 3;
attribute mti_svvh_generic_type of diff_width_b : constant is 3;
attribute mti_svvh_generic_type of sat_for_ini : constant is 3;
attribute mti_svvh_generic_type of mult_round_for_ini : constant is 3;
attribute mti_svvh_generic_type of bits_to_round : constant is 3;
attribute mti_svvh_generic_type of sload_for_limit : constant is 3;
attribute mti_svvh_generic_type of accum_sat_for_limit : constant is 3;
attribute mti_svvh_generic_type of int_width_extra_bit : constant is 3;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_register : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel0_register : constant is 1;
attribute mti_svvh_generic_type of coefsel1_register : constant is 1;
attribute mti_svvh_generic_type of coefsel2_register : constant is 1;
attribute mti_svvh_generic_type of coefsel3_register : constant is 1;
attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of coef0_0 : constant is 1;
attribute mti_svvh_generic_type of coef0_1 : constant is 1;
attribute mti_svvh_generic_type of coef0_2 : constant is 1;
attribute mti_svvh_generic_type of coef0_3 : constant is 1;
attribute mti_svvh_generic_type of coef0_4 : constant is 1;
attribute mti_svvh_generic_type of coef0_5 : constant is 1;
attribute mti_svvh_generic_type of coef0_6 : constant is 1;
attribute mti_svvh_generic_type of coef0_7 : constant is 1;
attribute mti_svvh_generic_type of coef1_0 : constant is 1;
attribute mti_svvh_generic_type of coef1_1 : constant is 1;
attribute mti_svvh_generic_type of coef1_2 : constant is 1;
attribute mti_svvh_generic_type of coef1_3 : constant is 1;
attribute mti_svvh_generic_type of coef1_4 : constant is 1;
attribute mti_svvh_generic_type of coef1_5 : constant is 1;
attribute mti_svvh_generic_type of coef1_6 : constant is 1;
attribute mti_svvh_generic_type of coef1_7 : constant is 1;
attribute mti_svvh_generic_type of coef2_0 : constant is 1;
attribute mti_svvh_generic_type of coef2_1 : constant is 1;
attribute mti_svvh_generic_type of coef2_2 : constant is 1;
attribute mti_svvh_generic_type of coef2_3 : constant is 1;
attribute mti_svvh_generic_type of coef2_4 : constant is 1;
attribute mti_svvh_generic_type of coef2_5 : constant is 1;
attribute mti_svvh_generic_type of coef2_6 : constant is 1;
attribute mti_svvh_generic_type of coef2_7 : constant is 1;
attribute mti_svvh_generic_type of coef3_0 : constant is 1;
attribute mti_svvh_generic_type of coef3_1 : constant is 1;
attribute mti_svvh_generic_type of coef3_2 : constant is 1;
attribute mti_svvh_generic_type of coef3_3 : constant is 1;
attribute mti_svvh_generic_type of coef3_4 : constant is 1;
attribute mti_svvh_generic_type of coef3_5 : constant is 1;
attribute mti_svvh_generic_type of coef3_6 : constant is 1;
attribute mti_svvh_generic_type of coef3_7 : constant is 1;
end altmult_accum;
|
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08B.vhd
-- Creation Date: 21:55:54 27/01/2010
-- Description:
-- Q Register and Storage Protection
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Gates_package.all;
use work.PH;
entity QReg_STP is
Port (
-- Inputs
SA_REG : in STD_LOGIC_VECTOR (0 to 7); -- Stack address, F0-FF are MS storage keys, 00-EF are CCW storage keys
Z_BUS : in STD_LOGIC_VECTOR (0 to 8); -- Z bus used to write to Q reg
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : in STD_LOGIC; -- Selector channel cycle inputs
N_SEL_SHARE_HOLD : in STD_LOGIC; -- Selector channel share cycle
MAIN_STG : in STD_LOGIC; -- Main Storage usage
H_REG_5_PWR : in STD_LOGIC; -- Priority Reg from 04C
FORCE_M_REG_123 : in STD_LOGIC; -- When setting M reg for LS, from 04D
GT_LOCAL_STORAGE : in STD_LOGIC; -- Local Storage usage
GT_T_REG_TO_MN, GT_CK_TO_MN : in STD_LOGIC; -- These operations inhibit storage protect when used with LS
MAIN_STG_CP_1 : in STD_LOGIC; -- Main Storage clock pulse
N_MEM_SELECT : in STD_LOGIC;
N_STACK_MEMORY_SELECT : in STD_LOGIC; -- Indicates that Stack memory should be read/written
STACK_RD_WR_CONTROL : in STD_LOGIC; -- T to indicate Stack is being Read, F to indicate Write
E_SW_SEL_Q : in STD_LOGIC; -- E switch Q Reg selection
MAN_STORE_PWR : in STD_LOGIC; -- Manual Store switch for setting Q Reg
T4 : in STD_LOGIC; -- Main clock phase
MACH_RST_2B : in STD_LOGIC; -- Main system reset
Z_BUS_LO_DIG_PARITY : in STD_LOGIC; -- Parity of Z bus bits 4-7
CD_REG : in STD_LOGIC_VECTOR (0 to 3); -- ALU destination - 0011 specifies Q Reg
CLOCK_OFF : in STD_LOGIC; -- CPU clock stop
GK, HK : in STD_LOGIC_VECTOR (0 to 3); -- Storage key from SX1, SX2
CLK : in STD_LOGIC; -- 50MHz FPGA clock
-- Outputs
Q_REG_BUS : out STD_LOGIC_VECTOR (0 to 8); -- Q Reg output
SEL_CPU_BUMP : out STD_LOGIC; -- Select usage of Aux Storage
STACK_PC : out STD_LOGIC; -- Stack data Parity Check error
MPX_CP : out STD_LOGIC; -- MPX clock pulse
MAIN_STG_CP : out STD_LOGIC; -- MS clock pulse
PROTECT_LOC_CPU_OR_MPX : out STD_LOGIC; -- Storage Protection check from CPU or MPX
PROTECT_LOC_SEL_CHNL : out STD_LOGIC -- Storage Protection check from SX1 or SX2
);
end QReg_STP;
architecture FMD of QReg_STP is
signal Q_REG : STD_LOGIC_VECTOR(0 to 8);
signal INH_STG_PROT : STD_LOGIC;
signal sSTACK_PC : STD_LOGIC;
signal UseQ : STD_LOGIC;
signal SET_Q_HI, SET_Q_LO : STD_LOGIC;
subtype stackData is STD_LOGIC_VECTOR(4 to 8);
type stack is array(0 to 255) of stackData;
signal STP_STACK : stack;
signal STACK_DATA : stackData;
signal Q0_GK0_HK0, Q1_GK1_HK1, Q2_GK2_HK2, Q3_GK3_HK3 : STD_LOGIC;
signal STP : STD_LOGIC;
signal HDWR_STG_KEYS_MAT : STD_LOGIC;
signal CD0011 : STD_LOGIC;
signal STACK_DATA_STROBE, READ_GATE, WRITE_GATE, INHIBIT_TIMING : STD_LOGIC;
type delay is array(0 to 24) of std_logic;
signal delayLine : delay := (others=>'0');
signal setLatch, resetLatch : std_logic;
signal latch : std_logic;
signal INH_STG_PROT_PH_D : std_logic;
signal Q47P_D : std_logic_vector(4 to 8);
begin
Q0_GK0_HK0 <= (HK(0) and SX2_SHARE_CYCLE) or (GK(0) and SX1_SHARE_CYCLE) or (Q_REG(0) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q1_GK1_HK1 <= (HK(1) and SX2_SHARE_CYCLE) or (GK(1) and SX1_SHARE_CYCLE) or (Q_REG(1) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q2_GK2_HK2 <= (HK(2) and SX2_SHARE_CYCLE) or (GK(2) and SX1_SHARE_CYCLE) or (Q_REG(2) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q3_GK3_HK3 <= (HK(3) and SX2_SHARE_CYCLE) or (GK(3) and SX1_SHARE_CYCLE) or (Q_REG(3) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
STP <= not INH_STG_PROT and MAIN_STG and (Q0_GK0_HK0 or Q1_GK1_HK1 or Q2_GK2_HK2 or Q3_GK3_HK3); -- BE3F4
HDWR_STG_KEYS_MAT <= (Q0_GK0_HK0 xnor Q_REG(0)) and (Q1_GK1_HK1 xnor Q_REG(1)) and (Q2_GK2_HK2 xnor Q_REG(2)) and (Q3_GK3_HK3 xnor Q_REG(3)); -- BE3F3
PROTECT_LOC_CPU_OR_MPX <= (not H_REG_5_PWR) and STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
PROTECT_LOC_SEL_CHNL <= STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
INH_STG_PROT_PH_D <= GT_T_REG_TO_MN or GT_CK_TO_MN;
INH_STG_PROT_PH: entity PH port map(INH_STG_PROT_PH_D,GT_LOCAL_STORAGE,INH_STG_PROT); -- AA1F4
SEL_CPU_BUMP_PH: entity PH port map(FORCE_M_REG_123,GT_LOCAL_STORAGE,SEL_CPU_BUMP); -- AA1F4
STACK_PC <= sSTACK_PC;
MPX_CP <= not MAIN_STG_CP_1; -- BE3D3 BE3G4
MAIN_STG_CP <= MAIN_STG_CP_1; -- BE3G4
CD0011 <= '1' when CD_REG="0011" else '0';
UseQ <= (CD0011 and (N_SEL_SHARE_HOLD or (not CLOCK_OFF))) or (CLOCK_OFF and N_MEM_SELECT and N_SEL_SHARE_HOLD); -- BE3J3 BE3G4 BE3J3
SET_Q_HI <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ); -- BE3J4
SET_Q_LO <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ) or (STACK_RD_WR_CONTROL and STACK_DATA_STROBE); -- BE3J4
Q03: PHV4 port map(Z_BUS(0 to 3),SET_Q_HI,Q_REG(0 to 3)); -- BE3H2
Q47P_D <= ((Z_BUS(4 to 7) & Z_BUS_LO_DIG_PARITY) and (4 to 8 => UseQ)) or (STACK_DATA(4 to 8) and not (4 to 8 => UseQ));
Q47P: PHV5 port map(Q47P_D, SET_Q_LO, Q_REG(4 to 8));
Q_REG_BUS <= Q_REG;
sSTACK_PC <= EvenParity(Q_REG(4 to 7));
STP_FL: process(clk)
begin
if rising_edge(clk) then
setLatch <= not N_STACK_MEMORY_SELECT;
delayLine <= setLatch & delayLine(0 to 23);
STACK_DATA_STROBE <= delayLine(7); -- 140ns
resetLatch <= not delayLine(24);
if (setLatch='1') then latch <= '1'; end if;
if (resetLatch='1') then latch <= '0'; end if;
READ_GATE <= latch and STACK_RD_WR_CONTROL;
WRITE_GATE <= latch and not STACK_RD_WR_CONTROL;
INHIBIT_TIMING <= latch and not READ_GATE;
if WRITE_GATE='1' then
STP_STACK(Conv_Integer(SA_REG)) <= Q_REG(4 to 8);
elsif READ_GATE='1' then
STACK_DATA <= STP_STACK(Conv_Integer(SA_REG));
end if;
end if;
end process;
end FMD;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for clkgen
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: clkgen-e.vhd,v 1.2 2005/04/14 06:52:59 wig Exp $
-- $Date: 2005/04/14 06:52:59 $
-- $Log: clkgen-e.vhd,v $
-- Revision 1.2 2005/04/14 06:52:59 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity clkgen
--
entity clkgen is
-- Generics:
-- No Generated Generics for Entity clkgen
-- Generated Port Declaration:
-- No Generated Port for Entity clkgen
end clkgen;
--
-- End of Generated Entity clkgen
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1627.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01627ent IS
END c08s12b00x00p03n01i01627ent;
ARCHITECTURE c08s12b00x00p03n01i01627arch OF c08s12b00x00p03n01i01627ent IS
BEGIN
TESTING: PROCESS
BEGIN
return true; -- illegal in a process statement
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01627 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01627arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1627.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01627ent IS
END c08s12b00x00p03n01i01627ent;
ARCHITECTURE c08s12b00x00p03n01i01627arch OF c08s12b00x00p03n01i01627ent IS
BEGIN
TESTING: PROCESS
BEGIN
return true; -- illegal in a process statement
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01627 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01627arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1627.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01627ent IS
END c08s12b00x00p03n01i01627ent;
ARCHITECTURE c08s12b00x00p03n01i01627arch OF c08s12b00x00p03n01i01627ent IS
BEGIN
TESTING: PROCESS
BEGIN
return true; -- illegal in a process statement
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01627 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01627arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity assert5 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
clk : std_logic;
rst : std_logic;
res : out std_logic);
end;
architecture behav of assert5 is
begin
process (clk, rst)
begin
if rst = '1' then
res <= '0';
elsif rising_edge(clk) and en = '1' then
assert v /= x"05";
res <= v(0) xor v(1);
end if;
end process;
end behav;
|
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