content stringlengths 1 1.04M ⌀ |
|---|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from dummy_ctrl_regs_wb_slave.wb
-- Created : Fri May 13 11:28:38 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dummy_ctrl_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_ctrl_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Ports for PASS_THROUGH field: 'IRQ' in reg: 'DUMMY_1'
dummy_reg_1_o : out std_logic_vector(31 downto 0);
dummy_reg_1_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_reg_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_reg_3_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for LED control' in reg: 'DUMMY_LED'
dummy_reg_led_o : out std_logic_vector(31 downto 0)
);
end dummy_ctrl_regs_wb_slave;
architecture syn of dummy_ctrl_regs_wb_slave is
signal dummy_reg_2_int : std_logic_vector(31 downto 0);
signal dummy_reg_3_int : std_logic_vector(31 downto 0);
signal dummy_reg_led_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dummy_reg_1_wr_o <= '0';
dummy_reg_2_int <= "00000000000000000000000000000000";
dummy_reg_3_int <= "00000000000000000000000000000000";
dummy_reg_led_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dummy_reg_1_wr_o <= '0';
ack_in_progress <= '0';
else
dummy_reg_1_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
dummy_reg_1_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
dummy_reg_2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_2_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
dummy_reg_3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_3_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
dummy_reg_led_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_led_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- IRQ
-- pass-through field: IRQ in register: DUMMY_1
dummy_reg_1_o <= wrdata_reg(31 downto 0);
-- Dummy register 2
dummy_reg_2_o <= dummy_reg_2_int;
-- Dummy register 3
dummy_reg_3_o <= dummy_reg_3_int;
-- Dummy register for LED control
dummy_reg_led_o <= dummy_reg_led_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3 IS
-- Signals
SIGNAL twdlXdin_1_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_1_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_3_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_3_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_1_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_1_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_1_re_signed <= signed(twdlXdin_1_re);
twdlXdin_1_im_signed <= signed(twdlXdin_1_im);
twdlXdin_3_re_signed <= signed(twdlXdin_3_re);
twdlXdin_3_im_signed <= signed(twdlXdin_3_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_1_re_signed,
twdlXdin_1_im_signed, twdlXdin_3_re_signed, twdlXdin_3_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_1_re_signed, 18) + resize(twdlXdin_3_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_1_re_signed, 18) - resize(twdlXdin_3_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_1_im_signed, 18) + resize(twdlXdin_3_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_1_im_signed, 18) - resize(twdlXdin_3_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_1_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_1_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_2_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_2_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_1_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_1_re <= std_logic_vector(dout_1_re_tmp);
dout_1_im <= std_logic_vector(dout_1_im_tmp);
dout_2_re <= std_logic_vector(dout_2_re_tmp);
dout_2_im <= std_logic_vector(dout_2_im_tmp);
END rtl;
|
-------------------------------------------------------------------------------
-- system_ac0_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_ac0_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 14);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 479);
M_UABus : in std_logic_vector(0 to 479);
M_BE : in std_logic_vector(0 to 119);
M_RNW : in std_logic_vector(0 to 14);
M_abort : in std_logic_vector(0 to 14);
M_busLock : in std_logic_vector(0 to 14);
M_TAttribute : in std_logic_vector(0 to 239);
M_lockErr : in std_logic_vector(0 to 14);
M_MSize : in std_logic_vector(0 to 29);
M_priority : in std_logic_vector(0 to 29);
M_rdBurst : in std_logic_vector(0 to 14);
M_request : in std_logic_vector(0 to 14);
M_size : in std_logic_vector(0 to 59);
M_type : in std_logic_vector(0 to 44);
M_wrBurst : in std_logic_vector(0 to 14);
M_wrDBus : in std_logic_vector(0 to 959);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 14);
Sl_MWrErr : in std_logic_vector(0 to 14);
Sl_MBusy : in std_logic_vector(0 to 14);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 63);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 14);
PLB_MIRQ : out std_logic_vector(0 to 14);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 14);
PLB_MTimeout : out std_logic_vector(0 to 14);
PLB_MBusy : out std_logic_vector(0 to 14);
PLB_MRdErr : out std_logic_vector(0 to 14);
PLB_MWrErr : out std_logic_vector(0 to 14);
PLB_MRdBTerm : out std_logic_vector(0 to 14);
PLB_MRdDAck : out std_logic_vector(0 to 14);
PLB_MRdDBus : out std_logic_vector(0 to 959);
PLB_MRdWdAddr : out std_logic_vector(0 to 59);
PLB_MRearbitrate : out std_logic_vector(0 to 14);
PLB_MWrBTerm : out std_logic_vector(0 to 14);
PLB_MWrDAck : out std_logic_vector(0 to 14);
PLB_MSSize : out std_logic_vector(0 to 29);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 3);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 14);
PLB_SMWrErr : out std_logic_vector(0 to 14);
PLB_SMBusy : out std_logic_vector(0 to 14);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end system_ac0_plb_wrapper;
architecture STRUCTURE of system_ac0_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
ac0_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 15,
C_PLBV46_NUM_SLAVES => 1,
C_PLBV46_MID_WIDTH => 4,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:53 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl
-- Design : system_auto_us_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_mi_word_q : out STD_LOGIC;
\M_AXI_RDATA_I_reg[0]_0\ : out STD_LOGIC;
first_word : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
use_wrap_buffer : out STD_LOGIC;
wrap_buffer_available : out STD_LOGIC;
\pre_next_word_1_reg[3]_0\ : out STD_LOGIC;
\current_word_1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\pre_next_word_1_reg[3]_1\ : out STD_LOGIC;
wrap_buffer_available_reg_0 : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
first_word_reg_0 : out STD_LOGIC;
first_word_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
first_word_reg_2 : out STD_LOGIC;
\USE_RTL_ADDR.addr_q_reg[4]\ : out STD_LOGIC;
\m_payload_i_reg[130]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 130 downto 0 );
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_rready : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
\current_word_1_reg[0]_0\ : in STD_LOGIC;
\current_word_1_reg[1]_0\ : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
\m_payload_i_reg[1]\ : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[7]\ : in STD_LOGIC;
\m_payload_i_reg[8]\ : in STD_LOGIC;
\m_payload_i_reg[9]\ : in STD_LOGIC;
\m_payload_i_reg[10]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC;
\m_payload_i_reg[12]\ : in STD_LOGIC;
\m_payload_i_reg[13]\ : in STD_LOGIC;
\m_payload_i_reg[14]\ : in STD_LOGIC;
\m_payload_i_reg[15]\ : in STD_LOGIC;
\m_payload_i_reg[16]\ : in STD_LOGIC;
\m_payload_i_reg[17]\ : in STD_LOGIC;
\m_payload_i_reg[18]\ : in STD_LOGIC;
\m_payload_i_reg[19]\ : in STD_LOGIC;
\m_payload_i_reg[20]\ : in STD_LOGIC;
\m_payload_i_reg[21]\ : in STD_LOGIC;
\m_payload_i_reg[22]\ : in STD_LOGIC;
\m_payload_i_reg[23]\ : in STD_LOGIC;
\m_payload_i_reg[24]\ : in STD_LOGIC;
\m_payload_i_reg[25]\ : in STD_LOGIC;
\m_payload_i_reg[26]\ : in STD_LOGIC;
\m_payload_i_reg[27]\ : in STD_LOGIC;
\m_payload_i_reg[28]\ : in STD_LOGIC;
\m_payload_i_reg[29]\ : in STD_LOGIC;
\m_payload_i_reg[30]\ : in STD_LOGIC;
\m_payload_i_reg[31]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
use_wrap_buffer_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
signal \^m_axi_rdata_i_reg[0]_0\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[0]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[100]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[101]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[102]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[103]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[104]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[105]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[106]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[107]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[108]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[109]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[10]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[110]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[111]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[112]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[113]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[114]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[115]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[116]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[117]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[118]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[119]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[11]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[120]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[121]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[122]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[123]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[124]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[125]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[126]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[127]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[12]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[13]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[14]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[15]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[16]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[17]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[18]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[19]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[1]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[20]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[21]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[22]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[23]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[24]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[25]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[26]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[27]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[28]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[29]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[2]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[30]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[31]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[32]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[33]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[34]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[35]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[36]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[37]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[38]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[39]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[3]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[40]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[41]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[42]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[43]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[44]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[45]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[46]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[47]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[48]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[49]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[4]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[50]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[51]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[52]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[53]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[54]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[55]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[56]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[57]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[58]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[59]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[5]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[60]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[61]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[62]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[63]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[64]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[65]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[66]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[67]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[68]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[69]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[6]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[70]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[71]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[72]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[73]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[74]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[75]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[76]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[77]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[78]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[79]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[7]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[80]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[81]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[82]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[83]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[84]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[85]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[86]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[87]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[88]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[89]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[8]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[90]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[91]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[92]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[93]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[94]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[95]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[96]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[97]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[98]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[99]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[9]\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^current_word_1_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal \^first_word_reg_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \m_payload_i[130]_i_7_n_0\ : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \s_axi_rdata[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[12]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[24]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[25]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[26]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[27]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[28]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[29]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_7_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_8_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_9_n_0 : STD_LOGIC;
signal \^use_wrap_buffer\ : STD_LOGIC;
signal use_wrap_buffer_i_1_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_2_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_3_n_0 : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal wrap_buffer_available_i_1_n_0 : STD_LOGIC;
signal wrap_buffer_available_i_2_n_0 : STD_LOGIC;
signal \^wrap_buffer_available_reg_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_5\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[0]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[4]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_7\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_4 : label is "soft_lutpair66";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair67";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_6 : label is "soft_lutpair71";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_7 : label is "soft_lutpair68";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_8 : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of use_wrap_buffer_i_2 : label is "soft_lutpair70";
attribute SOFT_HLUTNM of use_wrap_buffer_i_3 : label is "soft_lutpair70";
attribute SOFT_HLUTNM of wrap_buffer_available_i_2 : label is "soft_lutpair72";
begin
\M_AXI_RDATA_I_reg[0]_0\ <= \^m_axi_rdata_i_reg[0]_0\;
\current_word_1_reg[3]_0\(3 downto 0) <= \^current_word_1_reg[3]_0\(3 downto 0);
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
first_word_reg_1(3 downto 0) <= \^first_word_reg_1\(3 downto 0);
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer <= \^use_wrap_buffer\;
wrap_buffer_available <= \^wrap_buffer_available\;
wrap_buffer_available_reg_0 <= \^wrap_buffer_available_reg_0\;
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(0),
Q => \M_AXI_RDATA_I_reg_n_0_[0]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(100),
Q => \M_AXI_RDATA_I_reg_n_0_[100]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(101),
Q => \M_AXI_RDATA_I_reg_n_0_[101]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(102),
Q => \M_AXI_RDATA_I_reg_n_0_[102]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(103),
Q => \M_AXI_RDATA_I_reg_n_0_[103]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(104),
Q => \M_AXI_RDATA_I_reg_n_0_[104]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(105),
Q => \M_AXI_RDATA_I_reg_n_0_[105]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(106),
Q => \M_AXI_RDATA_I_reg_n_0_[106]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(107),
Q => \M_AXI_RDATA_I_reg_n_0_[107]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(108),
Q => \M_AXI_RDATA_I_reg_n_0_[108]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(109),
Q => \M_AXI_RDATA_I_reg_n_0_[109]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(10),
Q => \M_AXI_RDATA_I_reg_n_0_[10]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(110),
Q => \M_AXI_RDATA_I_reg_n_0_[110]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(111),
Q => \M_AXI_RDATA_I_reg_n_0_[111]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(112),
Q => \M_AXI_RDATA_I_reg_n_0_[112]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(113),
Q => \M_AXI_RDATA_I_reg_n_0_[113]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(114),
Q => \M_AXI_RDATA_I_reg_n_0_[114]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(115),
Q => \M_AXI_RDATA_I_reg_n_0_[115]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(116),
Q => \M_AXI_RDATA_I_reg_n_0_[116]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(117),
Q => \M_AXI_RDATA_I_reg_n_0_[117]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(118),
Q => \M_AXI_RDATA_I_reg_n_0_[118]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(119),
Q => \M_AXI_RDATA_I_reg_n_0_[119]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(11),
Q => \M_AXI_RDATA_I_reg_n_0_[11]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(120),
Q => \M_AXI_RDATA_I_reg_n_0_[120]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(121),
Q => \M_AXI_RDATA_I_reg_n_0_[121]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(122),
Q => \M_AXI_RDATA_I_reg_n_0_[122]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(123),
Q => \M_AXI_RDATA_I_reg_n_0_[123]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(124),
Q => \M_AXI_RDATA_I_reg_n_0_[124]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(125),
Q => \M_AXI_RDATA_I_reg_n_0_[125]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(126),
Q => \M_AXI_RDATA_I_reg_n_0_[126]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(127),
Q => \M_AXI_RDATA_I_reg_n_0_[127]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(12),
Q => \M_AXI_RDATA_I_reg_n_0_[12]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(13),
Q => \M_AXI_RDATA_I_reg_n_0_[13]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(14),
Q => \M_AXI_RDATA_I_reg_n_0_[14]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(15),
Q => \M_AXI_RDATA_I_reg_n_0_[15]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(16),
Q => \M_AXI_RDATA_I_reg_n_0_[16]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(17),
Q => \M_AXI_RDATA_I_reg_n_0_[17]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(18),
Q => \M_AXI_RDATA_I_reg_n_0_[18]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(19),
Q => \M_AXI_RDATA_I_reg_n_0_[19]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(1),
Q => \M_AXI_RDATA_I_reg_n_0_[1]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(20),
Q => \M_AXI_RDATA_I_reg_n_0_[20]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(21),
Q => \M_AXI_RDATA_I_reg_n_0_[21]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(22),
Q => \M_AXI_RDATA_I_reg_n_0_[22]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(23),
Q => \M_AXI_RDATA_I_reg_n_0_[23]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(24),
Q => \M_AXI_RDATA_I_reg_n_0_[24]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(25),
Q => \M_AXI_RDATA_I_reg_n_0_[25]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(26),
Q => \M_AXI_RDATA_I_reg_n_0_[26]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(27),
Q => \M_AXI_RDATA_I_reg_n_0_[27]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(28),
Q => \M_AXI_RDATA_I_reg_n_0_[28]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(29),
Q => \M_AXI_RDATA_I_reg_n_0_[29]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(2),
Q => \M_AXI_RDATA_I_reg_n_0_[2]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(30),
Q => \M_AXI_RDATA_I_reg_n_0_[30]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(31),
Q => \M_AXI_RDATA_I_reg_n_0_[31]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(32),
Q => \M_AXI_RDATA_I_reg_n_0_[32]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(33),
Q => \M_AXI_RDATA_I_reg_n_0_[33]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(34),
Q => \M_AXI_RDATA_I_reg_n_0_[34]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(35),
Q => \M_AXI_RDATA_I_reg_n_0_[35]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(36),
Q => \M_AXI_RDATA_I_reg_n_0_[36]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(37),
Q => \M_AXI_RDATA_I_reg_n_0_[37]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(38),
Q => \M_AXI_RDATA_I_reg_n_0_[38]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(39),
Q => \M_AXI_RDATA_I_reg_n_0_[39]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(3),
Q => \M_AXI_RDATA_I_reg_n_0_[3]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(40),
Q => \M_AXI_RDATA_I_reg_n_0_[40]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(41),
Q => \M_AXI_RDATA_I_reg_n_0_[41]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(42),
Q => \M_AXI_RDATA_I_reg_n_0_[42]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(43),
Q => \M_AXI_RDATA_I_reg_n_0_[43]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(44),
Q => \M_AXI_RDATA_I_reg_n_0_[44]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(45),
Q => \M_AXI_RDATA_I_reg_n_0_[45]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(46),
Q => \M_AXI_RDATA_I_reg_n_0_[46]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(47),
Q => \M_AXI_RDATA_I_reg_n_0_[47]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(48),
Q => \M_AXI_RDATA_I_reg_n_0_[48]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(49),
Q => \M_AXI_RDATA_I_reg_n_0_[49]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(4),
Q => \M_AXI_RDATA_I_reg_n_0_[4]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(50),
Q => \M_AXI_RDATA_I_reg_n_0_[50]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(51),
Q => \M_AXI_RDATA_I_reg_n_0_[51]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(52),
Q => \M_AXI_RDATA_I_reg_n_0_[52]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(53),
Q => \M_AXI_RDATA_I_reg_n_0_[53]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(54),
Q => \M_AXI_RDATA_I_reg_n_0_[54]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(55),
Q => \M_AXI_RDATA_I_reg_n_0_[55]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(56),
Q => \M_AXI_RDATA_I_reg_n_0_[56]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(57),
Q => \M_AXI_RDATA_I_reg_n_0_[57]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(58),
Q => \M_AXI_RDATA_I_reg_n_0_[58]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(59),
Q => \M_AXI_RDATA_I_reg_n_0_[59]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(5),
Q => \M_AXI_RDATA_I_reg_n_0_[5]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(60),
Q => \M_AXI_RDATA_I_reg_n_0_[60]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(61),
Q => \M_AXI_RDATA_I_reg_n_0_[61]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(62),
Q => \M_AXI_RDATA_I_reg_n_0_[62]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(63),
Q => \M_AXI_RDATA_I_reg_n_0_[63]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(64),
Q => \M_AXI_RDATA_I_reg_n_0_[64]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(65),
Q => \M_AXI_RDATA_I_reg_n_0_[65]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(66),
Q => \M_AXI_RDATA_I_reg_n_0_[66]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(67),
Q => \M_AXI_RDATA_I_reg_n_0_[67]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(68),
Q => \M_AXI_RDATA_I_reg_n_0_[68]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(69),
Q => \M_AXI_RDATA_I_reg_n_0_[69]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(6),
Q => \M_AXI_RDATA_I_reg_n_0_[6]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(70),
Q => \M_AXI_RDATA_I_reg_n_0_[70]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(71),
Q => \M_AXI_RDATA_I_reg_n_0_[71]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(72),
Q => \M_AXI_RDATA_I_reg_n_0_[72]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(73),
Q => \M_AXI_RDATA_I_reg_n_0_[73]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(74),
Q => \M_AXI_RDATA_I_reg_n_0_[74]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(75),
Q => \M_AXI_RDATA_I_reg_n_0_[75]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(76),
Q => \M_AXI_RDATA_I_reg_n_0_[76]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(77),
Q => \M_AXI_RDATA_I_reg_n_0_[77]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(78),
Q => \M_AXI_RDATA_I_reg_n_0_[78]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(79),
Q => \M_AXI_RDATA_I_reg_n_0_[79]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(7),
Q => \M_AXI_RDATA_I_reg_n_0_[7]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(80),
Q => \M_AXI_RDATA_I_reg_n_0_[80]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(81),
Q => \M_AXI_RDATA_I_reg_n_0_[81]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(82),
Q => \M_AXI_RDATA_I_reg_n_0_[82]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(83),
Q => \M_AXI_RDATA_I_reg_n_0_[83]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(84),
Q => \M_AXI_RDATA_I_reg_n_0_[84]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(85),
Q => \M_AXI_RDATA_I_reg_n_0_[85]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(86),
Q => \M_AXI_RDATA_I_reg_n_0_[86]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(87),
Q => \M_AXI_RDATA_I_reg_n_0_[87]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(88),
Q => \M_AXI_RDATA_I_reg_n_0_[88]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(89),
Q => \M_AXI_RDATA_I_reg_n_0_[89]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(8),
Q => \M_AXI_RDATA_I_reg_n_0_[8]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(90),
Q => \M_AXI_RDATA_I_reg_n_0_[90]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(91),
Q => \M_AXI_RDATA_I_reg_n_0_[91]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(92),
Q => \M_AXI_RDATA_I_reg_n_0_[92]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(93),
Q => \M_AXI_RDATA_I_reg_n_0_[93]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(94),
Q => \M_AXI_RDATA_I_reg_n_0_[94]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(95),
Q => \M_AXI_RDATA_I_reg_n_0_[95]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(96),
Q => \M_AXI_RDATA_I_reg_n_0_[96]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(97),
Q => \M_AXI_RDATA_I_reg_n_0_[97]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(98),
Q => \M_AXI_RDATA_I_reg_n_0_[98]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(99),
Q => \M_AXI_RDATA_I_reg_n_0_[99]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(9),
Q => \M_AXI_RDATA_I_reg_n_0_[9]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_ADDR.addr_q[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAAE"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => s_axi_rlast_INST_0_i_4_n_0,
I2 => \m_payload_i[130]_i_7_n_0\,
I3 => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\,
I4 => s_axi_rlast_INST_0_i_9_n_0,
I5 => \^wrap_buffer_available\,
O => \USE_RTL_ADDR.addr_q_reg[4]\
);
\USE_RTL_ADDR.addr_q[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
O => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => m_valid_i_reg,
D => Q(130),
Q => \^first_mi_word_q\,
S => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => \^first_mi_word_q\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => s_axi_rlast_INST_0_i_4_n_0,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \^first_mi_word_q\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B847"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCAACCAAC3AAC355"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I5 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBBFCB8FFFFFFFF"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I5 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0151"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \^first_mi_word_q\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(0),
Q => \^first_word_reg_1\(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(1),
Q => \^first_word_reg_1\(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(2),
Q => \^first_word_reg_1\(2),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(3),
Q => \^first_word_reg_1\(3),
R => \^m_axi_rdata_i_reg[0]_0\
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => p_15_in,
D => \^s_axi_rlast\,
Q => \^first_word\,
S => \^m_axi_rdata_i_reg[0]_0\
);
\m_payload_i[130]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => s_axi_rlast_INST_0_i_9_n_0,
I2 => s_axi_rlast_INST_0_i_8_n_0,
I3 => s_axi_rlast_INST_0_i_7_n_0,
I4 => \m_payload_i[130]_i_7_n_0\,
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => \m_payload_i_reg[130]\
);
\m_payload_i[130]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
O => \m_payload_i[130]_i_7_n_0\
);
\pre_next_word_1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A888"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => mr_rvalid,
I3 => rd_cmd_valid,
O => p_15_in
);
\pre_next_word_1[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^current_word_1_reg[3]_0\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(8),
O => \pre_next_word_1_reg[3]_1\
);
\pre_next_word_1[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^current_word_1_reg[3]_0\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(9),
O => \pre_next_word_1_reg[3]_0\
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(0),
Q => \^current_word_1_reg[3]_0\(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(1),
Q => \^current_word_1_reg[3]_0\(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(2),
Q => \^current_word_1_reg[3]_0\(2),
R => \^m_axi_rdata_i_reg[0]_0\
);
\pre_next_word_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(3),
Q => \^current_word_1_reg[3]_0\(3),
R => \^m_axi_rdata_i_reg[0]_0\
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(128),
Q => rresp_wrap_buffer(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(129),
Q => rresp_wrap_buffer(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[0]\,
I1 => \s_axi_rdata[0]_INST_0_i_2_n_0\,
O => s_axi_rdata(0),
S => \^use_wrap_buffer\
);
\s_axi_rdata[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[0]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[64]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[32]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[96]\,
O => \s_axi_rdata[0]_INST_0_i_2_n_0\
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[10]\,
I1 => \s_axi_rdata[10]_INST_0_i_2_n_0\,
O => s_axi_rdata(10),
S => \^use_wrap_buffer\
);
\s_axi_rdata[10]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[10]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[74]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[42]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[106]\,
O => \s_axi_rdata[10]_INST_0_i_2_n_0\
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[11]\,
I1 => \s_axi_rdata[11]_INST_0_i_2_n_0\,
O => s_axi_rdata(11),
S => \^use_wrap_buffer\
);
\s_axi_rdata[11]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[11]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[75]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[43]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[107]\,
O => \s_axi_rdata[11]_INST_0_i_2_n_0\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \s_axi_rdata[12]_INST_0_i_2_n_0\,
O => s_axi_rdata(12),
S => \^use_wrap_buffer\
);
\s_axi_rdata[12]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[12]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[76]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[44]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[108]\,
O => \s_axi_rdata[12]_INST_0_i_2_n_0\
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[13]\,
I1 => \s_axi_rdata[13]_INST_0_i_2_n_0\,
O => s_axi_rdata(13),
S => \^use_wrap_buffer\
);
\s_axi_rdata[13]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[13]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[77]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[45]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[109]\,
O => \s_axi_rdata[13]_INST_0_i_2_n_0\
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[14]\,
I1 => \s_axi_rdata[14]_INST_0_i_2_n_0\,
O => s_axi_rdata(14),
S => \^use_wrap_buffer\
);
\s_axi_rdata[14]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[14]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[78]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[46]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[110]\,
O => \s_axi_rdata[14]_INST_0_i_2_n_0\
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[15]\,
I1 => \s_axi_rdata[15]_INST_0_i_2_n_0\,
O => s_axi_rdata(15),
S => \^use_wrap_buffer\
);
\s_axi_rdata[15]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[15]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[79]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[47]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[111]\,
O => \s_axi_rdata[15]_INST_0_i_2_n_0\
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[16]\,
I1 => \s_axi_rdata[16]_INST_0_i_2_n_0\,
O => s_axi_rdata(16),
S => \^use_wrap_buffer\
);
\s_axi_rdata[16]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[16]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[80]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[48]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[112]\,
O => \s_axi_rdata[16]_INST_0_i_2_n_0\
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[17]\,
I1 => \s_axi_rdata[17]_INST_0_i_2_n_0\,
O => s_axi_rdata(17),
S => \^use_wrap_buffer\
);
\s_axi_rdata[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[17]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[81]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[49]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[113]\,
O => \s_axi_rdata[17]_INST_0_i_2_n_0\
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[18]\,
I1 => \s_axi_rdata[18]_INST_0_i_2_n_0\,
O => s_axi_rdata(18),
S => \^use_wrap_buffer\
);
\s_axi_rdata[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[18]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[82]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[50]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[114]\,
O => \s_axi_rdata[18]_INST_0_i_2_n_0\
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[19]\,
I1 => \s_axi_rdata[19]_INST_0_i_2_n_0\,
O => s_axi_rdata(19),
S => \^use_wrap_buffer\
);
\s_axi_rdata[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[19]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[83]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[51]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[115]\,
O => \s_axi_rdata[19]_INST_0_i_2_n_0\
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[1]\,
I1 => \s_axi_rdata[1]_INST_0_i_2_n_0\,
O => s_axi_rdata(1),
S => \^use_wrap_buffer\
);
\s_axi_rdata[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[1]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[65]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[33]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[97]\,
O => \s_axi_rdata[1]_INST_0_i_2_n_0\
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[20]\,
I1 => \s_axi_rdata[20]_INST_0_i_2_n_0\,
O => s_axi_rdata(20),
S => \^use_wrap_buffer\
);
\s_axi_rdata[20]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[20]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[84]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[52]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[116]\,
O => \s_axi_rdata[20]_INST_0_i_2_n_0\
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[21]\,
I1 => \s_axi_rdata[21]_INST_0_i_2_n_0\,
O => s_axi_rdata(21),
S => \^use_wrap_buffer\
);
\s_axi_rdata[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[21]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[85]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[53]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[117]\,
O => \s_axi_rdata[21]_INST_0_i_2_n_0\
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[22]\,
I1 => \s_axi_rdata[22]_INST_0_i_2_n_0\,
O => s_axi_rdata(22),
S => \^use_wrap_buffer\
);
\s_axi_rdata[22]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[22]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[86]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[54]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[118]\,
O => \s_axi_rdata[22]_INST_0_i_2_n_0\
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[23]\,
I1 => \s_axi_rdata[23]_INST_0_i_2_n_0\,
O => s_axi_rdata(23),
S => \^use_wrap_buffer\
);
\s_axi_rdata[23]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[23]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[87]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[55]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[119]\,
O => \s_axi_rdata[23]_INST_0_i_2_n_0\
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[24]\,
I1 => \s_axi_rdata[24]_INST_0_i_2_n_0\,
O => s_axi_rdata(24),
S => \^use_wrap_buffer\
);
\s_axi_rdata[24]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[24]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[88]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[56]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[120]\,
O => \s_axi_rdata[24]_INST_0_i_2_n_0\
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[25]\,
I1 => \s_axi_rdata[25]_INST_0_i_2_n_0\,
O => s_axi_rdata(25),
S => \^use_wrap_buffer\
);
\s_axi_rdata[25]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[25]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[89]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[57]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[121]\,
O => \s_axi_rdata[25]_INST_0_i_2_n_0\
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[26]\,
I1 => \s_axi_rdata[26]_INST_0_i_2_n_0\,
O => s_axi_rdata(26),
S => \^use_wrap_buffer\
);
\s_axi_rdata[26]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[26]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[90]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[58]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[122]\,
O => \s_axi_rdata[26]_INST_0_i_2_n_0\
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[27]\,
I1 => \s_axi_rdata[27]_INST_0_i_2_n_0\,
O => s_axi_rdata(27),
S => \^use_wrap_buffer\
);
\s_axi_rdata[27]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[27]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[91]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[59]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[123]\,
O => \s_axi_rdata[27]_INST_0_i_2_n_0\
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[28]\,
I1 => \s_axi_rdata[28]_INST_0_i_2_n_0\,
O => s_axi_rdata(28),
S => \^use_wrap_buffer\
);
\s_axi_rdata[28]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[28]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[92]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[60]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[124]\,
O => \s_axi_rdata[28]_INST_0_i_2_n_0\
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[29]\,
I1 => \s_axi_rdata[29]_INST_0_i_2_n_0\,
O => s_axi_rdata(29),
S => \^use_wrap_buffer\
);
\s_axi_rdata[29]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[29]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[93]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[61]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[125]\,
O => \s_axi_rdata[29]_INST_0_i_2_n_0\
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[2]\,
I1 => \s_axi_rdata[2]_INST_0_i_2_n_0\,
O => s_axi_rdata(2),
S => \^use_wrap_buffer\
);
\s_axi_rdata[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[2]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[66]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[34]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[98]\,
O => \s_axi_rdata[2]_INST_0_i_2_n_0\
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[30]\,
I1 => \s_axi_rdata[30]_INST_0_i_2_n_0\,
O => s_axi_rdata(30),
S => \^use_wrap_buffer\
);
\s_axi_rdata[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[30]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[94]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[62]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[126]\,
O => \s_axi_rdata[30]_INST_0_i_2_n_0\
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[31]\,
I1 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
O => s_axi_rdata(31),
S => \^use_wrap_buffer\
);
\s_axi_rdata[31]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[31]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[95]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[63]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[127]\,
O => \s_axi_rdata[31]_INST_0_i_2_n_0\
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \s_axi_rdata[3]_INST_0_i_2_n_0\,
O => s_axi_rdata(3),
S => \^use_wrap_buffer\
);
\s_axi_rdata[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[3]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[67]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[35]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[99]\,
O => \s_axi_rdata[3]_INST_0_i_2_n_0\
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[4]\,
I1 => \s_axi_rdata[4]_INST_0_i_2_n_0\,
O => s_axi_rdata(4),
S => \^use_wrap_buffer\
);
\s_axi_rdata[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[4]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[68]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[36]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[100]\,
O => \s_axi_rdata[4]_INST_0_i_2_n_0\
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[5]\,
I1 => \s_axi_rdata[5]_INST_0_i_2_n_0\,
O => s_axi_rdata(5),
S => \^use_wrap_buffer\
);
\s_axi_rdata[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[5]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[69]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[37]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[101]\,
O => \s_axi_rdata[5]_INST_0_i_2_n_0\
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \s_axi_rdata[6]_INST_0_i_2_n_0\,
O => s_axi_rdata(6),
S => \^use_wrap_buffer\
);
\s_axi_rdata[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[6]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[70]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[38]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[102]\,
O => \s_axi_rdata[6]_INST_0_i_2_n_0\
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[7]\,
I1 => \s_axi_rdata[7]_INST_0_i_2_n_0\,
O => s_axi_rdata(7),
S => \^use_wrap_buffer\
);
\s_axi_rdata[7]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[7]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[71]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[39]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[103]\,
O => \s_axi_rdata[7]_INST_0_i_2_n_0\
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[8]\,
I1 => \s_axi_rdata[8]_INST_0_i_2_n_0\,
O => s_axi_rdata(8),
S => \^use_wrap_buffer\
);
\s_axi_rdata[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[8]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[72]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[40]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[104]\,
O => \s_axi_rdata[8]_INST_0_i_2_n_0\
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[9]\,
I1 => \s_axi_rdata[9]_INST_0_i_2_n_0\,
O => s_axi_rdata(9),
S => \^use_wrap_buffer\
);
\s_axi_rdata[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[9]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[73]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[41]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[105]\,
O => \s_axi_rdata[9]_INST_0_i_2_n_0\
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F1"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \^wrap_buffer_available_reg_0\,
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[0]_0\,
I4 => \current_word_1_reg[1]_0\,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => s_axi_rlast_INST_0_i_4_n_0,
I1 => s_axi_rlast_INST_0_i_5_n_0,
I2 => s_axi_rlast_INST_0_i_6_n_0,
I3 => s_axi_rlast_INST_0_i_7_n_0,
I4 => s_axi_rlast_INST_0_i_8_n_0,
I5 => s_axi_rlast_INST_0_i_9_n_0,
O => \^wrap_buffer_available_reg_0\
);
s_axi_rlast_INST_0_i_11: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^first_word_reg_1\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(10),
O => first_word_reg_2
);
s_axi_rlast_INST_0_i_12: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^first_word_reg_1\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(11),
O => first_word_reg_0
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
O => s_axi_rlast_INST_0_i_6_n_0
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => s_axi_rlast_INST_0_i_7_n_0
);
s_axi_rlast_INST_0_i_8: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => s_axi_rlast_INST_0_i_8_n_0
);
s_axi_rlast_INST_0_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6),
O => s_axi_rlast_INST_0_i_9_n_0
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => Q(128),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => Q(129),
O => s_axi_rresp(1)
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBFBBBBB00F00000"
)
port map (
I0 => use_wrap_buffer_i_2_n_0,
I1 => \^s_axi_rlast\,
I2 => use_wrap_buffer_reg_0,
I3 => use_wrap_buffer_i_3_n_0,
I4 => \^wrap_buffer_available\,
I5 => \^use_wrap_buffer\,
O => use_wrap_buffer_i_1_n_0
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"57FF"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => mr_rvalid,
I3 => rd_cmd_valid,
O => use_wrap_buffer_i_2_n_0
);
use_wrap_buffer_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"AABF"
)
port map (
I0 => \^wrap_buffer_available_reg_0\,
I1 => rd_cmd_valid,
I2 => mr_rvalid,
I3 => \^use_wrap_buffer\,
O => use_wrap_buffer_i_3_n_0
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => use_wrap_buffer_i_1_n_0,
Q => \^use_wrap_buffer\,
R => \^m_axi_rdata_i_reg[0]_0\
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFAA00"
)
port map (
I0 => E(0),
I1 => \^wrap_buffer_available_reg_0\,
I2 => wrap_buffer_available_i_2_n_0,
I3 => use_wrap_buffer_reg_0,
I4 => \^wrap_buffer_available\,
O => wrap_buffer_available_i_1_n_0
);
wrap_buffer_available_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => mr_rvalid,
I2 => rd_cmd_valid,
O => wrap_buffer_available_i_2_n_0
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => wrap_buffer_available_i_1_n_0,
Q => \^wrap_buffer_available\,
R => \^m_axi_rdata_i_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
port (
\aresetn_d_reg[1]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[50]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 43 downto 0 );
signal \USE_READ.read_addr_inst/mi_word_intra_len__10\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\ : STD_LOGIC;
signal \^aresetn_d_reg[1]_0\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arsize[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arsize[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 3 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
signal upsized_length : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_axi_araddr[0]_INST_0_i_1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_axi_araddr[3]_INST_0_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_4\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_7\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_7\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_8\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_arlen[2]_INST_0_i_2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_4\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_arlen[5]_INST_0_i_2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_axi_arlen[6]_INST_0_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_axi_arlen[6]_INST_0_i_3\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_axi_arsize[0]_INST_0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_axi_arsize[1]_INST_0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_axi_arsize[1]_INST_0_i_2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_axi_arsize[2]_INST_0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_arsize[2]_INST_0_i_2\ : label is "soft_lutpair99";
begin
Q(43 downto 0) <= \^q\(43 downto 0);
\aresetn_d_reg[1]_0\ <= \^aresetn_d_reg[1]_0\;
\in\(32 downto 0) <= \^in\(32 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFDFFFDF"
)
port map (
I0 => CO(0),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF11011000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000FAC000000AC"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(2),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBFBBBBBB"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000CA"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(2),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => sr_araddr(2),
I4 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => sr_araddr(3),
I4 => \m_axi_araddr[3]_INST_0_i_1_n_0\,
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1101115544444400"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => CO(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(0),
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4888884848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\,
I5 => sr_araddr(0),
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF11011111"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arburst(1),
I3 => sr_arburst(0),
I4 => CO(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000CA"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA55155555AA2AA"
)
port map (
I0 => sr_araddr(2),
I1 => CO(0),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\,
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBAAAAAAAAAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\,
I1 => CO(0),
I2 => sr_arburst(1),
I3 => sr_arburst(0),
I4 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0E02020200000000"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => sr_arsize(0),
I2 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I3 => s_axi_arlen_ii(0),
I4 => sr_araddr(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000D0000FFF20000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\,
I4 => \^in\(14),
I5 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\,
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000800080808000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => sr_araddr(0),
I2 => sr_araddr(1),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => CO(0),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0000080800000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \^in\(9),
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I5 => sr_araddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEAEEEAAAAAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\,
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => CO(0),
I5 => sr_araddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555575AAAAAA8A"
)
port map (
I0 => sr_araddr(3),
I1 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
I2 => CO(0),
I3 => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
I5 => \USE_READ.read_addr_inst/mi_word_intra_len__10\(3),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"54000000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"3330303030200000"
)
port map (
I0 => sr_arsize(0),
I1 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000010000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
O => \USE_READ.read_addr_inst/mi_word_intra_len__10\(3)
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFDF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA02000000A8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
I5 => sr_araddr(1),
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"802A2A80"
)
port map (
I0 => \^in\(13),
I1 => sr_araddr(1),
I2 => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0\,
I3 => \^in\(10),
I4 => sr_araddr(2),
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0302"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => sr_arsize(0),
O => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4844444484888888"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
I1 => \^in\(14),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => sr_araddr(3),
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000F000C00080"
)
port map (
I0 => sr_araddr(0),
I1 => sr_araddr(1),
I2 => sr_araddr(2),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545555500000000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => CO(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(0),
O => \^in\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00CA00000000"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => sr_araddr(1),
O => \^in\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^in\(13),
I1 => sr_araddr(2),
O => \^in\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\,
I2 => CO(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(3),
O => \^in\(28)
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\,
I1 => \^q\(32),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
O => \^in\(29)
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sr_araddr(3),
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
O => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => \^q\(32),
I4 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
O => \^in\(30)
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I1 => \^q\(32),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
O => \^in\(31)
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^in\(32)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^in\(8)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => '1',
Q => \^aresetn_d_reg[1]_0\,
R => s_axi_aresetn
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \^aresetn_d_reg[1]_0\,
Q => \^s_ready_i_reg_0\,
R => s_axi_aresetn
);
cmd_packed_wrap_i1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3)
);
cmd_packed_wrap_i1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2)
);
cmd_packed_wrap_i1_carry_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FAFAFA88"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arsize(0),
I2 => s_axi_arlen_ii(2),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1)
);
cmd_packed_wrap_i1_carry_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"EAEAEA00"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0)
);
cmd_packed_wrap_i1_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(7),
I1 => s_axi_arlen_ii(6),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3)
);
cmd_packed_wrap_i1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2)
);
cmd_packed_wrap_i1_carry_i_7: unisim.vcomponents.LUT5
generic map(
INIT => X"010010EE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1)
);
cmd_packed_wrap_i1_carry_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"11181188"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => CO(0),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000EF000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I3 => CO(0),
I4 => sr_araddr(1),
I5 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(0),
I2 => s_axi_arlen_ii(1),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => CO(0),
I2 => sr_araddr(2),
I3 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF530FFFFF53F"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \m_axi_araddr[3]_INST_0_i_1_n_0\,
I1 => CO(0),
I2 => sr_araddr(3),
I3 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(3)
);
\m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F3F3F3F5F5F0FF"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(3),
I4 => sr_arsize(0),
I5 => sr_arsize(1),
O => \m_axi_araddr[3]_INST_0_i_1_n_0\
);
\m_axi_araddr[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBBBF"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => CO(0),
I4 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
O => \m_axi_araddr[3]_INST_0_i_2_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8000"
)
port map (
I0 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I1 => \^q\(32),
I2 => sr_arburst(1),
I3 => CO(0),
I4 => sr_arburst(0),
O => m_axi_arburst(0)
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F0B0"
)
port map (
I0 => sr_arburst(0),
I1 => CO(0),
I2 => sr_arburst(1),
I3 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
O => m_axi_arburst(1)
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555566665666"
)
port map (
I0 => upsized_length(0),
I1 => \m_axi_arlen[0]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => \m_axi_arlen[0]_INST_0_i_5_n_0\,
O => \^in\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABBAAABAABAAAAA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_6_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => sr_arsize(0),
I3 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I4 => s_axi_arlen_ii(3),
I5 => s_axi_arlen_ii(4),
O => upsized_length(0)
);
\m_axi_arlen[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_10_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => sr_arburst(1),
I1 => \^q\(32),
I2 => sr_arburst(0),
I3 => sr_araddr(3),
I4 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I5 => \m_axi_arlen[4]_INST_0_i_6_n_0\,
O => \m_axi_arlen[0]_INST_0_i_2_n_0\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAEAAA"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(1),
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => sr_arburst(0),
I1 => \^q\(32),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(3),
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[0]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEEECCCCEEEECCCC"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => \m_axi_arlen[0]_INST_0_i_8_n_0\,
I2 => \m_axi_arlen[0]_INST_0_i_9_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => sr_araddr(0),
O => \m_axi_arlen[0]_INST_0_i_5_n_0\
);
\m_axi_arlen[0]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888B888888888"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_6_n_0\
);
\m_axi_arlen[0]_INST_0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_7_n_0\
);
\m_axi_arlen[0]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888800080000000"
)
port map (
I0 => \^in\(10),
I1 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(2),
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[0]_INST_0_i_8_n_0\
);
\m_axi_arlen[0]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F00000088000000"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_10_n_0\,
I1 => sr_araddr(2),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_9_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000100010001FFFE"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
O => \^in\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444040404040"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => sr_araddr(3),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0E00000000000000"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000008800C8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_arlen[1]_INST_0_i_9_n_0\,
I2 => sr_araddr(2),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00000008000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => sr_arburst(1),
I3 => \^q\(32),
I4 => sr_arburst(0),
I5 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000002000200"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA00"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808000"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_araddr(1),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => sr_araddr(3),
I2 => s_axi_arlen_ii(4),
I3 => sr_arburst(0),
I4 => \^q\(32),
I5 => sr_arburst(1),
O => \m_axi_arlen[1]_INST_0_i_9_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555AA6A6A"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(5),
I2 => \^in\(9),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[2]_INST_0_i_3_n_0\,
O => \^in\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFC888C888C888"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I2 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[2]_INST_0_i_4_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
O => \^in\(9)
);
\m_axi_arlen[2]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_3_n_0\
);
\m_axi_arlen[2]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => sr_arburst(1),
I1 => \^q\(32),
I2 => sr_arburst(0),
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => s_axi_arlen_ii(5),
O => \m_axi_arlen[2]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00551555FFAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I5 => upsized_length(3),
O => \^in\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010100010000000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
I3 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBEAEAEA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \^in\(9),
I4 => s_axi_arlen_ii(6),
O => upsized_length(3)
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => \^q\(32),
I2 => sr_arburst(0),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"E8A0"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => sr_araddr(1),
I2 => sr_araddr(2),
I3 => s_axi_arlen_ii(0),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00007FFFFFFF8000"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
I4 => \m_axi_arlen[4]_INST_0_i_4_n_0\,
I5 => upsized_length(4),
O => \^in\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => sr_arburst(0),
I3 => \^q\(32),
I4 => sr_arburst(1),
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[4]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[4]_INST_0_i_6_n_0\,
O => \m_axi_arlen[4]_INST_0_i_3_n_0\
);
\m_axi_arlen[4]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EA000000"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(5),
I4 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[4]_INST_0_i_4_n_0\
);
\m_axi_arlen[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F888F888"
)
port map (
I0 => \^in\(10),
I1 => s_axi_arlen_ii(6),
I2 => \^in\(9),
I3 => s_axi_arlen_ii(7),
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => upsized_length(4)
);
\m_axi_arlen[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCE8E8C0E8E8C0C0"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => sr_araddr(0),
I4 => sr_araddr(1),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[4]_INST_0_i_6_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"596A6A6A"
)
port map (
I0 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \^in\(10),
I4 => s_axi_arlen_ii(7),
O => \^in\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000000000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
O => \^in\(10)
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => s_axi_arlen_ii(7),
I4 => s_axi_arlen_ii(6),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \^in\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888800080000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \^in\(10),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(2),
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => \^q\(32),
I3 => sr_arburst(0),
I4 => s_axi_arlen_ii(4),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(32),
O => \m_axi_arlen[6]_INST_0_i_3_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5700"
)
port map (
I0 => \^q\(32),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(7),
O => \^in\(7)
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
I3 => sr_arsize(0),
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
I3 => sr_arsize(1),
O => m_axi_arsize(1)
);
\m_axi_arsize[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000002FFFFFFFF"
)
port map (
I0 => \m_axi_arsize[1]_INST_0_i_2_n_0\,
I1 => \m_axi_arsize[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arsize[2]_INST_0_i_3_n_0\,
I5 => \^q\(32),
O => \m_axi_arsize[1]_INST_0_i_1_n_0\
);
\m_axi_arsize[1]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arsize[1]_INST_0_i_2_n_0\
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFE000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(32),
I3 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I4 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_axi_arsize[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arsize[2]_INST_0_i_2_n_0\,
I5 => \m_axi_arsize[2]_INST_0_i_3_n_0\,
O => \m_axi_arsize[2]_INST_0_i_1_n_0\
);
\m_axi_arsize[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
O => \m_axi_arsize[2]_INST_0_i_2_n_0\
);
\m_axi_arsize[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
O => \m_axi_arsize[2]_INST_0_i_3_n_0\
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => sr_araddr(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^q\(5),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B100"
)
port map (
I0 => \^s_axi_arready\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DD5F0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^sr_arvalid\,
I4 => \^aresetn_d_reg[1]_0\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
sub_sized_wrap0_carry_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00010111"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => DI(1)
);
sub_sized_wrap0_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00070077"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
O => DI(0)
);
sub_sized_wrap0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(7),
I1 => s_axi_arlen_ii(6),
O => S(3)
);
sub_sized_wrap0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(4),
O => S(2)
);
sub_sized_wrap0_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"010010EE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => S(1)
);
sub_sized_wrap0_carry_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"11181188"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
\s_axi_rdata[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 130 downto 0 );
\s_axi_rdata[1]\ : out STD_LOGIC;
\s_axi_rdata[2]\ : out STD_LOGIC;
\s_axi_rdata[3]\ : out STD_LOGIC;
\s_axi_rdata[4]\ : out STD_LOGIC;
\s_axi_rdata[5]\ : out STD_LOGIC;
\s_axi_rdata[6]\ : out STD_LOGIC;
\s_axi_rdata[7]\ : out STD_LOGIC;
\s_axi_rdata[8]\ : out STD_LOGIC;
\s_axi_rdata[9]\ : out STD_LOGIC;
\s_axi_rdata[10]\ : out STD_LOGIC;
\s_axi_rdata[11]\ : out STD_LOGIC;
\s_axi_rdata[12]\ : out STD_LOGIC;
\s_axi_rdata[13]\ : out STD_LOGIC;
\s_axi_rdata[14]\ : out STD_LOGIC;
\s_axi_rdata[15]\ : out STD_LOGIC;
\s_axi_rdata[16]\ : out STD_LOGIC;
\s_axi_rdata[17]\ : out STD_LOGIC;
\s_axi_rdata[18]\ : out STD_LOGIC;
\s_axi_rdata[19]\ : out STD_LOGIC;
\s_axi_rdata[20]\ : out STD_LOGIC;
\s_axi_rdata[21]\ : out STD_LOGIC;
\s_axi_rdata[22]\ : out STD_LOGIC;
\s_axi_rdata[23]\ : out STD_LOGIC;
\s_axi_rdata[24]\ : out STD_LOGIC;
\s_axi_rdata[25]\ : out STD_LOGIC;
\s_axi_rdata[26]\ : out STD_LOGIC;
\s_axi_rdata[27]\ : out STD_LOGIC;
\s_axi_rdata[28]\ : out STD_LOGIC;
\s_axi_rdata[29]\ : out STD_LOGIC;
\s_axi_rdata[30]\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rvalid : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^q\ : STD_LOGIC_VECTOR ( 130 downto 0 );
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 130 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[100]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[101]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[102]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[103]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[104]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[105]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[106]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[107]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[108]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[109]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[110]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[111]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[112]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[113]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[114]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[115]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[116]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[117]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[118]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[119]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[120]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[121]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[122]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[123]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[124]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[125]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[126]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[127]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[128]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[129]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[130]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[67]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[68]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[69]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[70]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[71]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[72]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[73]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[74]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[75]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[76]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[77]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[78]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[79]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[80]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[81]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[82]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[83]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[84]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[85]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[86]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[87]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[88]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[89]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[90]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[91]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[92]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[93]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[94]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[95]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[96]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[97]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[98]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[99]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[100]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[101]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[102]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[103]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[104]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[105]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[106]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[107]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[108]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[109]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[110]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[111]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[112]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[113]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[114]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[115]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[116]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[117]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[118]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[119]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[120]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[121]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[122]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[123]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[124]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[125]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[126]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[127]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[128]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[129]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[67]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[68]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[69]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[70]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[71]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[72]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[73]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[74]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[75]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[76]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[77]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[78]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[79]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[80]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[81]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[82]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[83]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[84]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[85]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[86]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[87]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[88]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[89]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[90]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[91]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[92]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[93]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[94]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[95]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[96]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[97]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[98]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[99]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_valid_i_i_1__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair0";
begin
Q(130 downto 0) <= \^q\(130 downto 0);
m_axi_rready <= \^m_axi_rready\;
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[100]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(100),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[100]\,
O => skid_buffer(100)
);
\m_payload_i[101]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(101),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[101]\,
O => skid_buffer(101)
);
\m_payload_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(102),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[102]\,
O => skid_buffer(102)
);
\m_payload_i[103]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(103),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[103]\,
O => skid_buffer(103)
);
\m_payload_i[104]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(104),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[104]\,
O => skid_buffer(104)
);
\m_payload_i[105]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(105),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[105]\,
O => skid_buffer(105)
);
\m_payload_i[106]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(106),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[106]\,
O => skid_buffer(106)
);
\m_payload_i[107]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(107),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[107]\,
O => skid_buffer(107)
);
\m_payload_i[108]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(108),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[108]\,
O => skid_buffer(108)
);
\m_payload_i[109]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(109),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[109]\,
O => skid_buffer(109)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[110]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(110),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[110]\,
O => skid_buffer(110)
);
\m_payload_i[111]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(111),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[111]\,
O => skid_buffer(111)
);
\m_payload_i[112]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(112),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[112]\,
O => skid_buffer(112)
);
\m_payload_i[113]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(113),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[113]\,
O => skid_buffer(113)
);
\m_payload_i[114]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(114),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[114]\,
O => skid_buffer(114)
);
\m_payload_i[115]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(115),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[115]\,
O => skid_buffer(115)
);
\m_payload_i[116]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(116),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[116]\,
O => skid_buffer(116)
);
\m_payload_i[117]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(117),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[117]\,
O => skid_buffer(117)
);
\m_payload_i[118]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(118),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[118]\,
O => skid_buffer(118)
);
\m_payload_i[119]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(119),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[119]\,
O => skid_buffer(119)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[120]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(120),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[120]\,
O => skid_buffer(120)
);
\m_payload_i[121]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(121),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[121]\,
O => skid_buffer(121)
);
\m_payload_i[122]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(122),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[122]\,
O => skid_buffer(122)
);
\m_payload_i[123]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(123),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[123]\,
O => skid_buffer(123)
);
\m_payload_i[124]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(124),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[124]\,
O => skid_buffer(124)
);
\m_payload_i[125]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(125),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[125]\,
O => skid_buffer(125)
);
\m_payload_i[126]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(126),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[126]\,
O => skid_buffer(126)
);
\m_payload_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(127),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[127]\,
O => skid_buffer(127)
);
\m_payload_i[128]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[128]\,
O => skid_buffer(128)
);
\m_payload_i[129]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[129]\,
O => skid_buffer(129)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[130]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[130]\,
O => skid_buffer(130)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(64),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(65),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(66),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[67]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(67),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[67]\,
O => skid_buffer(67)
);
\m_payload_i[68]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(68),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[68]\,
O => skid_buffer(68)
);
\m_payload_i[69]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(69),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[69]\,
O => skid_buffer(69)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[70]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(70),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[70]\,
O => skid_buffer(70)
);
\m_payload_i[71]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(71),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[71]\,
O => skid_buffer(71)
);
\m_payload_i[72]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(72),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[72]\,
O => skid_buffer(72)
);
\m_payload_i[73]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(73),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[73]\,
O => skid_buffer(73)
);
\m_payload_i[74]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(74),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[74]\,
O => skid_buffer(74)
);
\m_payload_i[75]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(75),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[75]\,
O => skid_buffer(75)
);
\m_payload_i[76]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(76),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[76]\,
O => skid_buffer(76)
);
\m_payload_i[77]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(77),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[77]\,
O => skid_buffer(77)
);
\m_payload_i[78]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(78),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[78]\,
O => skid_buffer(78)
);
\m_payload_i[79]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(79),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[79]\,
O => skid_buffer(79)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[80]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(80),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[80]\,
O => skid_buffer(80)
);
\m_payload_i[81]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(81),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[81]\,
O => skid_buffer(81)
);
\m_payload_i[82]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(82),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[82]\,
O => skid_buffer(82)
);
\m_payload_i[83]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(83),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[83]\,
O => skid_buffer(83)
);
\m_payload_i[84]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(84),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[84]\,
O => skid_buffer(84)
);
\m_payload_i[85]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(85),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[85]\,
O => skid_buffer(85)
);
\m_payload_i[86]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(86),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[86]\,
O => skid_buffer(86)
);
\m_payload_i[87]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(87),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[87]\,
O => skid_buffer(87)
);
\m_payload_i[88]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(88),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[88]\,
O => skid_buffer(88)
);
\m_payload_i[89]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(89),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[89]\,
O => skid_buffer(89)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[90]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(90),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[90]\,
O => skid_buffer(90)
);
\m_payload_i[91]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(91),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[91]\,
O => skid_buffer(91)
);
\m_payload_i[92]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(92),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[92]\,
O => skid_buffer(92)
);
\m_payload_i[93]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(93),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[93]\,
O => skid_buffer(93)
);
\m_payload_i[94]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(94),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[94]\,
O => skid_buffer(94)
);
\m_payload_i[95]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(95),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[95]\,
O => skid_buffer(95)
);
\m_payload_i[96]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(96),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[96]\,
O => skid_buffer(96)
);
\m_payload_i[97]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(97),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[97]\,
O => skid_buffer(97)
);
\m_payload_i[98]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(98),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[98]\,
O => skid_buffer(98)
);
\m_payload_i[99]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(99),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[99]\,
O => skid_buffer(99)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(100),
Q => \^q\(100),
R => '0'
);
\m_payload_i_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(101),
Q => \^q\(101),
R => '0'
);
\m_payload_i_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(102),
Q => \^q\(102),
R => '0'
);
\m_payload_i_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(103),
Q => \^q\(103),
R => '0'
);
\m_payload_i_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(104),
Q => \^q\(104),
R => '0'
);
\m_payload_i_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(105),
Q => \^q\(105),
R => '0'
);
\m_payload_i_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(106),
Q => \^q\(106),
R => '0'
);
\m_payload_i_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(107),
Q => \^q\(107),
R => '0'
);
\m_payload_i_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(108),
Q => \^q\(108),
R => '0'
);
\m_payload_i_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(109),
Q => \^q\(109),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(110),
Q => \^q\(110),
R => '0'
);
\m_payload_i_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(111),
Q => \^q\(111),
R => '0'
);
\m_payload_i_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(112),
Q => \^q\(112),
R => '0'
);
\m_payload_i_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(113),
Q => \^q\(113),
R => '0'
);
\m_payload_i_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(114),
Q => \^q\(114),
R => '0'
);
\m_payload_i_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(115),
Q => \^q\(115),
R => '0'
);
\m_payload_i_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(116),
Q => \^q\(116),
R => '0'
);
\m_payload_i_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(117),
Q => \^q\(117),
R => '0'
);
\m_payload_i_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(118),
Q => \^q\(118),
R => '0'
);
\m_payload_i_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(119),
Q => \^q\(119),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(120),
Q => \^q\(120),
R => '0'
);
\m_payload_i_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(121),
Q => \^q\(121),
R => '0'
);
\m_payload_i_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(122),
Q => \^q\(122),
R => '0'
);
\m_payload_i_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(123),
Q => \^q\(123),
R => '0'
);
\m_payload_i_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(124),
Q => \^q\(124),
R => '0'
);
\m_payload_i_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(125),
Q => \^q\(125),
R => '0'
);
\m_payload_i_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(126),
Q => \^q\(126),
R => '0'
);
\m_payload_i_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(127),
Q => \^q\(127),
R => '0'
);
\m_payload_i_reg[128]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(128),
Q => \^q\(128),
R => '0'
);
\m_payload_i_reg[129]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(129),
Q => \^q\(129),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[130]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(130),
Q => \^q\(130),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(37),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(40),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(41),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(42),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(43),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(65),
Q => \^q\(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(66),
Q => \^q\(66),
R => '0'
);
\m_payload_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(67),
Q => \^q\(67),
R => '0'
);
\m_payload_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(68),
Q => \^q\(68),
R => '0'
);
\m_payload_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(69),
Q => \^q\(69),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(70),
Q => \^q\(70),
R => '0'
);
\m_payload_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(71),
Q => \^q\(71),
R => '0'
);
\m_payload_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(72),
Q => \^q\(72),
R => '0'
);
\m_payload_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(73),
Q => \^q\(73),
R => '0'
);
\m_payload_i_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(74),
Q => \^q\(74),
R => '0'
);
\m_payload_i_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(75),
Q => \^q\(75),
R => '0'
);
\m_payload_i_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(76),
Q => \^q\(76),
R => '0'
);
\m_payload_i_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(77),
Q => \^q\(77),
R => '0'
);
\m_payload_i_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(78),
Q => \^q\(78),
R => '0'
);
\m_payload_i_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(79),
Q => \^q\(79),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(80),
Q => \^q\(80),
R => '0'
);
\m_payload_i_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(81),
Q => \^q\(81),
R => '0'
);
\m_payload_i_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(82),
Q => \^q\(82),
R => '0'
);
\m_payload_i_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(83),
Q => \^q\(83),
R => '0'
);
\m_payload_i_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(84),
Q => \^q\(84),
R => '0'
);
\m_payload_i_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(85),
Q => \^q\(85),
R => '0'
);
\m_payload_i_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(86),
Q => \^q\(86),
R => '0'
);
\m_payload_i_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(87),
Q => \^q\(87),
R => '0'
);
\m_payload_i_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(88),
Q => \^q\(88),
R => '0'
);
\m_payload_i_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(89),
Q => \^q\(89),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(90),
Q => \^q\(90),
R => '0'
);
\m_payload_i_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(91),
Q => \^q\(91),
R => '0'
);
\m_payload_i_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(92),
Q => \^q\(92),
R => '0'
);
\m_payload_i_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(93),
Q => \^q\(93),
R => '0'
);
\m_payload_i_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(94),
Q => \^q\(94),
R => '0'
);
\m_payload_i_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(95),
Q => \^q\(95),
R => '0'
);
\m_payload_i_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(96),
Q => \^q\(96),
R => '0'
);
\m_payload_i_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(97),
Q => \^q\(97),
R => '0'
);
\m_payload_i_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(98),
Q => \^q\(98),
R => '0'
);
\m_payload_i_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(99),
Q => \^q\(99),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF00"
)
port map (
I0 => \^m_axi_rready\,
I1 => m_axi_rvalid,
I2 => E(0),
I3 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => mr_rvalid,
R => '0'
);
\s_axi_rdata[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(0),
I1 => \^q\(64),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(32),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(96),
O => \s_axi_rdata[0]\
);
\s_axi_rdata[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(10),
I1 => \^q\(74),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(42),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(106),
O => \s_axi_rdata[10]\
);
\s_axi_rdata[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(11),
I1 => \^q\(75),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(43),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(107),
O => \s_axi_rdata[11]\
);
\s_axi_rdata[12]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(12),
I1 => \^q\(76),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(44),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(108),
O => \s_axi_rdata[12]\
);
\s_axi_rdata[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(13),
I1 => \^q\(77),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(45),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(109),
O => \s_axi_rdata[13]\
);
\s_axi_rdata[14]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(14),
I1 => \^q\(78),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(46),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(110),
O => \s_axi_rdata[14]\
);
\s_axi_rdata[15]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(15),
I1 => \^q\(79),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(47),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(111),
O => \s_axi_rdata[15]\
);
\s_axi_rdata[16]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(16),
I1 => \^q\(80),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(48),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(112),
O => \s_axi_rdata[16]\
);
\s_axi_rdata[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(17),
I1 => \^q\(81),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(49),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(113),
O => \s_axi_rdata[17]\
);
\s_axi_rdata[18]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(18),
I1 => \^q\(82),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(50),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(114),
O => \s_axi_rdata[18]\
);
\s_axi_rdata[19]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(19),
I1 => \^q\(83),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(51),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(115),
O => \s_axi_rdata[19]\
);
\s_axi_rdata[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(1),
I1 => \^q\(65),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(33),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(97),
O => \s_axi_rdata[1]\
);
\s_axi_rdata[20]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(20),
I1 => \^q\(84),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(52),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(116),
O => \s_axi_rdata[20]\
);
\s_axi_rdata[21]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(21),
I1 => \^q\(85),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(53),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(117),
O => \s_axi_rdata[21]\
);
\s_axi_rdata[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(22),
I1 => \^q\(86),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(54),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(118),
O => \s_axi_rdata[22]\
);
\s_axi_rdata[23]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(23),
I1 => \^q\(87),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(55),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(119),
O => \s_axi_rdata[23]\
);
\s_axi_rdata[24]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(24),
I1 => \^q\(88),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(56),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(120),
O => \s_axi_rdata[24]\
);
\s_axi_rdata[25]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(25),
I1 => \^q\(89),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(57),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(121),
O => \s_axi_rdata[25]\
);
\s_axi_rdata[26]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(26),
I1 => \^q\(90),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(58),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(122),
O => \s_axi_rdata[26]\
);
\s_axi_rdata[27]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(27),
I1 => \^q\(91),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(59),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(123),
O => \s_axi_rdata[27]\
);
\s_axi_rdata[28]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(28),
I1 => \^q\(92),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(60),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(124),
O => \s_axi_rdata[28]\
);
\s_axi_rdata[29]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(29),
I1 => \^q\(93),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(61),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(125),
O => \s_axi_rdata[29]\
);
\s_axi_rdata[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(2),
I1 => \^q\(66),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(34),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(98),
O => \s_axi_rdata[2]\
);
\s_axi_rdata[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(30),
I1 => \^q\(94),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(62),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(126),
O => \s_axi_rdata[30]\
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(31),
I1 => \^q\(95),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(63),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(127),
O => \s_axi_rdata[31]\
);
\s_axi_rdata[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(67),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(35),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(99),
O => \s_axi_rdata[3]\
);
\s_axi_rdata[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(68),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(36),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(100),
O => \s_axi_rdata[4]\
);
\s_axi_rdata[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(5),
I1 => \^q\(69),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(37),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(101),
O => \s_axi_rdata[5]\
);
\s_axi_rdata[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(70),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(38),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(102),
O => \s_axi_rdata[6]\
);
\s_axi_rdata[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(7),
I1 => \^q\(71),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(39),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(103),
O => \s_axi_rdata[7]\
);
\s_axi_rdata[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(8),
I1 => \^q\(72),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(40),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(104),
O => \s_axi_rdata[8]\
);
\s_axi_rdata[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(9),
I1 => \^q\(73),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(41),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(105),
O => \s_axi_rdata[9]\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F200"
)
port map (
I0 => \^m_axi_rready\,
I1 => m_axi_rvalid,
I2 => E(0),
I3 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(100),
Q => \skid_buffer_reg_n_0_[100]\,
R => '0'
);
\skid_buffer_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(101),
Q => \skid_buffer_reg_n_0_[101]\,
R => '0'
);
\skid_buffer_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(102),
Q => \skid_buffer_reg_n_0_[102]\,
R => '0'
);
\skid_buffer_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(103),
Q => \skid_buffer_reg_n_0_[103]\,
R => '0'
);
\skid_buffer_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(104),
Q => \skid_buffer_reg_n_0_[104]\,
R => '0'
);
\skid_buffer_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(105),
Q => \skid_buffer_reg_n_0_[105]\,
R => '0'
);
\skid_buffer_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(106),
Q => \skid_buffer_reg_n_0_[106]\,
R => '0'
);
\skid_buffer_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(107),
Q => \skid_buffer_reg_n_0_[107]\,
R => '0'
);
\skid_buffer_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(108),
Q => \skid_buffer_reg_n_0_[108]\,
R => '0'
);
\skid_buffer_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(109),
Q => \skid_buffer_reg_n_0_[109]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(110),
Q => \skid_buffer_reg_n_0_[110]\,
R => '0'
);
\skid_buffer_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(111),
Q => \skid_buffer_reg_n_0_[111]\,
R => '0'
);
\skid_buffer_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(112),
Q => \skid_buffer_reg_n_0_[112]\,
R => '0'
);
\skid_buffer_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(113),
Q => \skid_buffer_reg_n_0_[113]\,
R => '0'
);
\skid_buffer_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(114),
Q => \skid_buffer_reg_n_0_[114]\,
R => '0'
);
\skid_buffer_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(115),
Q => \skid_buffer_reg_n_0_[115]\,
R => '0'
);
\skid_buffer_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(116),
Q => \skid_buffer_reg_n_0_[116]\,
R => '0'
);
\skid_buffer_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(117),
Q => \skid_buffer_reg_n_0_[117]\,
R => '0'
);
\skid_buffer_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(118),
Q => \skid_buffer_reg_n_0_[118]\,
R => '0'
);
\skid_buffer_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(119),
Q => \skid_buffer_reg_n_0_[119]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(120),
Q => \skid_buffer_reg_n_0_[120]\,
R => '0'
);
\skid_buffer_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(121),
Q => \skid_buffer_reg_n_0_[121]\,
R => '0'
);
\skid_buffer_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(122),
Q => \skid_buffer_reg_n_0_[122]\,
R => '0'
);
\skid_buffer_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(123),
Q => \skid_buffer_reg_n_0_[123]\,
R => '0'
);
\skid_buffer_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(124),
Q => \skid_buffer_reg_n_0_[124]\,
R => '0'
);
\skid_buffer_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(125),
Q => \skid_buffer_reg_n_0_[125]\,
R => '0'
);
\skid_buffer_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(126),
Q => \skid_buffer_reg_n_0_[126]\,
R => '0'
);
\skid_buffer_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(127),
Q => \skid_buffer_reg_n_0_[127]\,
R => '0'
);
\skid_buffer_reg[128]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[128]\,
R => '0'
);
\skid_buffer_reg[129]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[129]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[130]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[130]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(64),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(65),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(66),
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(67),
Q => \skid_buffer_reg_n_0_[67]\,
R => '0'
);
\skid_buffer_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(68),
Q => \skid_buffer_reg_n_0_[68]\,
R => '0'
);
\skid_buffer_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(69),
Q => \skid_buffer_reg_n_0_[69]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(70),
Q => \skid_buffer_reg_n_0_[70]\,
R => '0'
);
\skid_buffer_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(71),
Q => \skid_buffer_reg_n_0_[71]\,
R => '0'
);
\skid_buffer_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(72),
Q => \skid_buffer_reg_n_0_[72]\,
R => '0'
);
\skid_buffer_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(73),
Q => \skid_buffer_reg_n_0_[73]\,
R => '0'
);
\skid_buffer_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(74),
Q => \skid_buffer_reg_n_0_[74]\,
R => '0'
);
\skid_buffer_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(75),
Q => \skid_buffer_reg_n_0_[75]\,
R => '0'
);
\skid_buffer_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(76),
Q => \skid_buffer_reg_n_0_[76]\,
R => '0'
);
\skid_buffer_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(77),
Q => \skid_buffer_reg_n_0_[77]\,
R => '0'
);
\skid_buffer_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(78),
Q => \skid_buffer_reg_n_0_[78]\,
R => '0'
);
\skid_buffer_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(79),
Q => \skid_buffer_reg_n_0_[79]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(80),
Q => \skid_buffer_reg_n_0_[80]\,
R => '0'
);
\skid_buffer_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(81),
Q => \skid_buffer_reg_n_0_[81]\,
R => '0'
);
\skid_buffer_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(82),
Q => \skid_buffer_reg_n_0_[82]\,
R => '0'
);
\skid_buffer_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(83),
Q => \skid_buffer_reg_n_0_[83]\,
R => '0'
);
\skid_buffer_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(84),
Q => \skid_buffer_reg_n_0_[84]\,
R => '0'
);
\skid_buffer_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(85),
Q => \skid_buffer_reg_n_0_[85]\,
R => '0'
);
\skid_buffer_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(86),
Q => \skid_buffer_reg_n_0_[86]\,
R => '0'
);
\skid_buffer_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(87),
Q => \skid_buffer_reg_n_0_[87]\,
R => '0'
);
\skid_buffer_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(88),
Q => \skid_buffer_reg_n_0_[88]\,
R => '0'
);
\skid_buffer_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(89),
Q => \skid_buffer_reg_n_0_[89]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(90),
Q => \skid_buffer_reg_n_0_[90]\,
R => '0'
);
\skid_buffer_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(91),
Q => \skid_buffer_reg_n_0_[91]\,
R => '0'
);
\skid_buffer_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(92),
Q => \skid_buffer_reg_n_0_[92]\,
R => '0'
);
\skid_buffer_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(93),
Q => \skid_buffer_reg_n_0_[93]\,
R => '0'
);
\skid_buffer_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(94),
Q => \skid_buffer_reg_n_0_[94]\,
R => '0'
);
\skid_buffer_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(95),
Q => \skid_buffer_reg_n_0_[95]\,
R => '0'
);
\skid_buffer_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(96),
Q => \skid_buffer_reg_n_0_[96]\,
R => '0'
);
\skid_buffer_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(97),
Q => \skid_buffer_reg_n_0_[97]\,
R => '0'
);
\skid_buffer_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(98),
Q => \skid_buffer_reg_n_0_[98]\,
R => '0'
);
\skid_buffer_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(99),
Q => \skid_buffer_reg_n_0_[99]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
port (
\M_AXI_RDATA_I_reg[127]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
first_word_reg : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\s_axi_rdata[31]_0\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[127]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[3]_0\ : in STD_LOGIC;
\current_word_1_reg[2]\ : in STD_LOGIC;
\current_word_1_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
signal \^m_axi_rdata_i_reg[127]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[7]_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^current_word_1_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal \^first_word_reg\ : STD_LOGIC;
signal \^first_word_reg_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_6_n_0\ : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[3]_i_4_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal s_axi_rlast_INST_0_i_10_n_0 : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \M_AXI_RDATA_I[127]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair76";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][14]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][30]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][31]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][32]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][33]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][34]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \current_word_1[0]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_3\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_10 : label is "soft_lutpair74";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair77";
attribute SOFT_HLUTNM of s_ready_i_i_2 : label is "soft_lutpair79";
begin
\M_AXI_RDATA_I_reg[127]\ <= \^m_axi_rdata_i_reg[127]\;
Q(12 downto 0) <= \^q\(12 downto 0);
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ <= \^use_rtl_length.length_counter_q_reg[7]_0\;
\current_word_1_reg[3]\(3 downto 0) <= \^current_word_1_reg[3]\(3 downto 0);
first_word_reg <= \^first_word_reg\;
first_word_reg_0 <= \^first_word_reg_0\;
\M_AXI_RDATA_I[127]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => mr_rvalid,
I1 => \^m_axi_rdata_i_reg[127]\,
I2 => first_mi_word_q,
I3 => use_wrap_buffer,
I4 => rd_cmd_packed_wrap,
O => \M_AXI_RDATA_I_reg[127]_0\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00005501FFFFFFFF"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\,
I1 => wrap_buffer_available,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
I3 => use_wrap_buffer,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\,
I5 => \^m_axi_rdata_i_reg[127]\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"07FF"
)
port map (
I0 => \^m_axi_rdata_i_reg[127]\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
I3 => s_axi_rready,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF9F9FF"
)
port map (
I0 => cmd_last_word(3),
I1 => \current_word_1_reg[3]_0\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0\,
I3 => cmd_last_word(2),
I4 => \current_word_1_reg[2]\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(1),
I1 => rd_cmd_first_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \current_word_1_reg[3]_1\(1),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(0),
I1 => rd_cmd_first_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \current_word_1_reg[3]_1\(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q => rd_cmd_mask(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => rd_cmd_offset(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => cmd_last_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => cmd_last_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => cmd_last_word(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_next_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => \^q\(8),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(9),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(10),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q => \^q\(11),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q => rd_cmd_packed_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q => rd_cmd_modified,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q => \^q\(12),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => data_Exists_I,
Q => \^m_axi_rdata_i_reg[127]\,
R => SR(0)
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA9A55555565"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => buffer_Full_q,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BF40F40B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFF2000FFBA0045"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I2 => valid_Write,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080800C8080"
)
port map (
I0 => data_Exists_I_i_2_n_0,
I1 => data_Exists_I,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888808888"
)
port map (
I0 => valid_Write,
I1 => \^m_axi_rdata_i_reg[127]\,
I2 => \^first_word_reg\,
I3 => \^first_word_reg_0\,
I4 => use_wrap_buffer_reg,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => SR(0)
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(28),
Q => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(29),
Q => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(30),
Q => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(31),
Q => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(32),
Q => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[7]_0\,
I1 => mr_rvalid,
O => \USE_RTL_LENGTH.length_counter_q_reg[7]\
);
\USE_RTL_LENGTH.first_mi_word_q_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0001"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\,
I1 => use_wrap_buffer,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
I3 => wrap_buffer_available,
I4 => \m_payload_i[130]_i_4_n_0\,
I5 => \m_payload_i[130]_i_3_n_0\,
O => \^use_rtl_length.length_counter_q_reg[7]_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00040000"
)
port map (
I0 => cmd_push_block,
I1 => sr_arvalid,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FFFFF"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => SR(0)
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => m_axi_arready,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(0),
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(0),
O => \^current_word_1_reg[3]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(1),
I1 => rd_cmd_next_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(1),
O => \^current_word_1_reg[3]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \^q\(8),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(2),
O => \^current_word_1_reg[3]\(2)
);
\current_word_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(3),
I1 => \^q\(9),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(3),
O => \^current_word_1_reg[3]\(3)
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"C4C4C4C4C4CFC4C4"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I1 => data_Exists_I,
I2 => data_Exists_I_i_2_n_0,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => SR(0)
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_arvalid
);
\m_payload_i[130]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444454FFFFFFFF"
)
port map (
I0 => \m_payload_i[130]_i_3_n_0\,
I1 => \m_payload_i[130]_i_4_n_0\,
I2 => wrap_buffer_available_reg,
I3 => use_wrap_buffer,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\,
I5 => mr_rvalid,
O => E(0)
);
\m_payload_i[130]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_rready,
I1 => \^m_axi_rdata_i_reg[127]\,
O => \m_payload_i[130]_i_3_n_0\
);
\m_payload_i[130]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0100FFFF"
)
port map (
I0 => \^current_word_1_reg[3]\(1),
I1 => \^current_word_1_reg[3]\(2),
I2 => \^current_word_1_reg[3]\(0),
I3 => \m_payload_i[130]_i_6_n_0\,
I4 => rd_cmd_modified,
I5 => \^q\(12),
O => \m_payload_i[130]_i_4_n_0\
);
\m_payload_i[130]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001555155555555"
)
port map (
I0 => rd_cmd_complete_wrap,
I1 => \pre_next_word_1_reg[3]_0\(3),
I2 => \^q\(12),
I3 => first_word,
I4 => \^q\(9),
I5 => rd_cmd_mask(3),
O => \m_payload_i[130]_i_6_n_0\
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002AAA2AAA80008"
)
port map (
I0 => rd_cmd_mask(0),
I1 => \pre_next_word_1_reg[3]_0\(0),
I2 => \^q\(12),
I3 => first_word,
I4 => rd_cmd_next_word(0),
I5 => cmd_step(0),
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => rd_cmd_mask(1),
I1 => cmd_step(1),
I2 => rd_cmd_next_word(1),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \pre_next_word_1_reg[3]_0\(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => cmd_step(0),
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(0),
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => rd_cmd_mask(2),
I1 => cmd_step(2),
I2 => \^q\(8),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \pre_next_word_1_reg[3]_0\(2),
I5 => \pre_next_word_1[3]_i_4_n_0\,
O => D(2)
);
\pre_next_word_1[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A880022A"
)
port map (
I0 => rd_cmd_mask(3),
I1 => \pre_next_word_1_reg[2]\,
I2 => \pre_next_word_1[3]_i_4_n_0\,
I3 => cmd_step(2),
I4 => \pre_next_word_1_reg[3]\,
O => D(3)
);
\pre_next_word_1[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEFEEEA888A8880"
)
port map (
I0 => cmd_step(1),
I1 => rd_cmd_next_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => \pre_next_word_1[3]_i_4_n_0\
);
\s_axi_rdata[31]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => \^q\(10),
I1 => first_word,
I2 => \^q\(12),
I3 => \current_word_1_reg[3]_1\(2),
I4 => rd_cmd_offset(2),
O => \s_axi_rdata[31]_0\
);
\s_axi_rdata[31]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => \^q\(11),
I1 => first_word,
I2 => \^q\(12),
I3 => \current_word_1_reg[3]_1\(3),
I4 => rd_cmd_offset(3),
O => \s_axi_rdata[31]\
);
s_axi_rlast_INST_0_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(12),
I1 => first_word,
O => s_axi_rlast_INST_0_i_10_n_0
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47B847B8FFFF"
)
port map (
I0 => \current_word_1_reg[3]_1\(0),
I1 => s_axi_rlast_INST_0_i_10_n_0,
I2 => rd_cmd_first_word(0),
I3 => cmd_last_word(0),
I4 => \current_word_1_reg[2]\,
I5 => cmd_last_word(2),
O => \^first_word_reg_0\
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47B847B8FFFF"
)
port map (
I0 => \current_word_1_reg[3]_1\(1),
I1 => s_axi_rlast_INST_0_i_10_n_0,
I2 => rd_cmd_first_word(1),
I3 => cmd_last_word(1),
I4 => \current_word_1_reg[3]_0\,
I5 => cmd_last_word(3),
O => \^first_word_reg\
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^m_axi_rdata_i_reg[127]\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
O => s_axi_rvalid
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B000"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
I2 => m_axi_arready,
I3 => s_axi_aresetn,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
rd_cmd_valid : out STD_LOGIC;
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
first_word_reg : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\s_axi_rdata[31]_0\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
mr_rvalid : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[3]_0\ : in STD_LOGIC;
\current_word_1_reg[2]\ : in STD_LOGIC;
\current_word_1_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_packed_wrap_i1_carry_n_1 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_2 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_3 : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_1 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_2 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_3 : STD_LOGIC;
signal NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_sub_sized_wrap0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
\M_AXI_RDATA_I_reg[127]\ => rd_cmd_valid,
\M_AXI_RDATA_I_reg[127]_0\(0) => \M_AXI_RDATA_I_reg[127]\(0),
Q(12 downto 0) => Q(12 downto 0),
SR(0) => SR(0),
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_RTL_LENGTH.length_counter_q_reg[7]\,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ => \USE_RTL_LENGTH.length_counter_q_reg[7]_0\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[2]\ => \current_word_1_reg[2]\,
\current_word_1_reg[3]\(3 downto 0) => \current_word_1_reg[3]\(3 downto 0),
\current_word_1_reg[3]_0\ => \current_word_1_reg[3]_0\,
\current_word_1_reg[3]_1\(3 downto 0) => \current_word_1_reg[3]_1\(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => first_word_reg,
first_word_reg_0 => first_word_reg_0,
\in\(32 downto 0) => \in\(32 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[2]\ => \pre_next_word_1_reg[2]\,
\pre_next_word_1_reg[3]\ => \pre_next_word_1_reg[3]\,
\pre_next_word_1_reg[3]_0\(3 downto 0) => \pre_next_word_1_reg[3]_0\(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
\s_axi_rdata[31]_0\ => \s_axi_rdata[31]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => s_ready_i_reg,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg
);
cmd_packed_wrap_i1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
CO(2) => cmd_packed_wrap_i1_carry_n_1,
CO(1) => cmd_packed_wrap_i1_carry_n_2,
CO(0) => cmd_packed_wrap_i1_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => \m_payload_i_reg[50]\(3 downto 0),
O(3 downto 0) => NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => SR(0)
);
sub_sized_wrap0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => sub_sized_wrap0_carry_n_1,
CO(1) => sub_sized_wrap0_carry_n_2,
CO(0) => sub_sized_wrap0_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1 downto 0) => DI(1 downto 0),
O(3 downto 0) => NLW_sub_sized_wrap0_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
\s_axi_rdata[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 130 downto 0 );
\s_axi_rdata[1]\ : out STD_LOGIC;
\s_axi_rdata[2]\ : out STD_LOGIC;
\s_axi_rdata[3]\ : out STD_LOGIC;
\s_axi_rdata[4]\ : out STD_LOGIC;
\s_axi_rdata[5]\ : out STD_LOGIC;
\s_axi_rdata[6]\ : out STD_LOGIC;
\s_axi_rdata[7]\ : out STD_LOGIC;
\s_axi_rdata[8]\ : out STD_LOGIC;
\s_axi_rdata[9]\ : out STD_LOGIC;
\s_axi_rdata[10]\ : out STD_LOGIC;
\s_axi_rdata[11]\ : out STD_LOGIC;
\s_axi_rdata[12]\ : out STD_LOGIC;
\s_axi_rdata[13]\ : out STD_LOGIC;
\s_axi_rdata[14]\ : out STD_LOGIC;
\s_axi_rdata[15]\ : out STD_LOGIC;
\s_axi_rdata[16]\ : out STD_LOGIC;
\s_axi_rdata[17]\ : out STD_LOGIC;
\s_axi_rdata[18]\ : out STD_LOGIC;
\s_axi_rdata[19]\ : out STD_LOGIC;
\s_axi_rdata[20]\ : out STD_LOGIC;
\s_axi_rdata[21]\ : out STD_LOGIC;
\s_axi_rdata[22]\ : out STD_LOGIC;
\s_axi_rdata[23]\ : out STD_LOGIC;
\s_axi_rdata[24]\ : out STD_LOGIC;
\s_axi_rdata[25]\ : out STD_LOGIC;
\s_axi_rdata[26]\ : out STD_LOGIC;
\s_axi_rdata[27]\ : out STD_LOGIC;
\s_axi_rdata[28]\ : out STD_LOGIC;
\s_axi_rdata[29]\ : out STD_LOGIC;
\s_axi_rdata[30]\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rvalid : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(130 downto 0) => Q(130 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\s_axi_rdata[0]\ => \s_axi_rdata[0]\,
\s_axi_rdata[10]\ => \s_axi_rdata[10]\,
\s_axi_rdata[11]\ => \s_axi_rdata[11]\,
\s_axi_rdata[12]\ => \s_axi_rdata[12]\,
\s_axi_rdata[13]\ => \s_axi_rdata[13]\,
\s_axi_rdata[14]\ => \s_axi_rdata[14]\,
\s_axi_rdata[15]\ => \s_axi_rdata[15]\,
\s_axi_rdata[16]\ => \s_axi_rdata[16]\,
\s_axi_rdata[17]\ => \s_axi_rdata[17]\,
\s_axi_rdata[18]\ => \s_axi_rdata[18]\,
\s_axi_rdata[19]\ => \s_axi_rdata[19]\,
\s_axi_rdata[1]\ => \s_axi_rdata[1]\,
\s_axi_rdata[20]\ => \s_axi_rdata[20]\,
\s_axi_rdata[21]\ => \s_axi_rdata[21]\,
\s_axi_rdata[22]\ => \s_axi_rdata[22]\,
\s_axi_rdata[23]\ => \s_axi_rdata[23]\,
\s_axi_rdata[24]\ => \s_axi_rdata[24]\,
\s_axi_rdata[25]\ => \s_axi_rdata[25]\,
\s_axi_rdata[26]\ => \s_axi_rdata[26]\,
\s_axi_rdata[27]\ => \s_axi_rdata[27]\,
\s_axi_rdata[28]\ => \s_axi_rdata[28]\,
\s_axi_rdata[29]\ => \s_axi_rdata[29]\,
\s_axi_rdata[2]\ => \s_axi_rdata[2]\,
\s_axi_rdata[30]\ => \s_axi_rdata[30]\,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
\s_axi_rdata[3]\ => \s_axi_rdata[3]\,
\s_axi_rdata[4]\ => \s_axi_rdata[4]\,
\s_axi_rdata[5]\ => \s_axi_rdata[5]\,
\s_axi_rdata[6]\ => \s_axi_rdata[6]\,
\s_axi_rdata[7]\ => \s_axi_rdata[7]\,
\s_axi_rdata[8]\ => \s_axi_rdata[8]\,
\s_axi_rdata[9]\ => \s_axi_rdata[9]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
\aresetn_d_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
begin
ar_pipe: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice
port map (
CO(0) => CO(0),
D(60 downto 0) => D(60 downto 0),
DI(1 downto 0) => DI(1 downto 0),
Q(43 downto 0) => Q(43 downto 0),
S(3 downto 0) => S(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0),
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]\,
cmd_push_block_reg => cmd_push_block_reg,
\in\(32 downto 0) => \in\(32 downto 0),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\m_payload_i_reg[50]_0\(0) => \m_payload_i_reg[50]\(0),
\out\ => \out\,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => s_ready_i_reg,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rready : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 43 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rready : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_arvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \^m_axi_rlast\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_19\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_20\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_21\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_22\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_23\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_24\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_25\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_26\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_27\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_28\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_29\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_30\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_33\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_4\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_5\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_modified_i : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal cmd_packed_wrap_i1 : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 26 downto 17 );
signal p_7_in : STD_LOGIC;
signal pre_next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_valid : STD_LOGIC;
signal si_register_slice_inst_n_0 : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_100 : STD_LOGIC;
signal si_register_slice_inst_n_101 : STD_LOGIC;
signal si_register_slice_inst_n_102 : STD_LOGIC;
signal si_register_slice_inst_n_103 : STD_LOGIC;
signal si_register_slice_inst_n_3 : STD_LOGIC;
signal si_register_slice_inst_n_4 : STD_LOGIC;
signal si_register_slice_inst_n_5 : STD_LOGIC;
signal si_register_slice_inst_n_6 : STD_LOGIC;
signal si_register_slice_inst_n_73 : STD_LOGIC;
signal si_register_slice_inst_n_74 : STD_LOGIC;
signal si_register_slice_inst_n_75 : STD_LOGIC;
signal si_register_slice_inst_n_76 : STD_LOGIC;
signal si_register_slice_inst_n_77 : STD_LOGIC;
signal si_register_slice_inst_n_78 : STD_LOGIC;
signal si_register_slice_inst_n_79 : STD_LOGIC;
signal si_register_slice_inst_n_90 : STD_LOGIC;
signal si_register_slice_inst_n_91 : STD_LOGIC;
signal si_register_slice_inst_n_92 : STD_LOGIC;
signal si_register_slice_inst_n_93 : STD_LOGIC;
signal si_register_slice_inst_n_98 : STD_LOGIC;
signal si_register_slice_inst_n_99 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal sub_sized_wrap0 : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \USE_READ.read_addr_inst_n_5\,
Q(130) => \^m_axi_rlast\,
Q(129 downto 128) => mr_rresp(1 downto 0),
Q(127) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(126) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(125) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(124) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(123) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(122) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(121) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(120) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(119) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(118) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(117) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(116) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(115) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(114) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(113) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(112) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(111) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(110) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(109) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(108) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(107) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(106) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(105) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(104) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(103) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(102) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(101) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(100) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(99) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(98) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(97) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(96) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(95) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(94) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(93) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(92) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(91) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(90) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(89) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(88) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(87) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(86) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(85) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(84) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(83) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(82) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(81) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(80) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(79) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(78) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(77) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(76) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(75) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(74) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(73) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(72) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(71) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(70) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(69) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(68) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(67) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(66) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(65) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
Q(64) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_READ.read_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_READ.read_addr_inst_n_29\,
\aresetn_d_reg[0]\ => si_register_slice_inst_n_0,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\s_axi_rdata[0]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
\s_axi_rdata[10]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143\,
\s_axi_rdata[11]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144\,
\s_axi_rdata[12]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145\,
\s_axi_rdata[13]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146\,
\s_axi_rdata[14]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147\,
\s_axi_rdata[15]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148\,
\s_axi_rdata[16]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149\,
\s_axi_rdata[17]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150\,
\s_axi_rdata[18]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151\,
\s_axi_rdata[19]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152\,
\s_axi_rdata[1]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134\,
\s_axi_rdata[20]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153\,
\s_axi_rdata[21]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154\,
\s_axi_rdata[22]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155\,
\s_axi_rdata[23]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156\,
\s_axi_rdata[24]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157\,
\s_axi_rdata[25]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158\,
\s_axi_rdata[26]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159\,
\s_axi_rdata[27]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160\,
\s_axi_rdata[28]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161\,
\s_axi_rdata[29]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162\,
\s_axi_rdata[2]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135\,
\s_axi_rdata[30]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163\,
\s_axi_rdata[31]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164\,
\s_axi_rdata[3]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136\,
\s_axi_rdata[4]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137\,
\s_axi_rdata[5]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138\,
\s_axi_rdata[6]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139\,
\s_axi_rdata[7]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140\,
\s_axi_rdata[8]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141\,
\s_axi_rdata[9]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(3 downto 0) => pre_next_word(3 downto 0),
E(0) => p_7_in,
\M_AXI_RDATA_I_reg[0]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
Q(130) => \^m_axi_rlast\,
Q(129 downto 128) => mr_rresp(1 downto 0),
Q(127) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(126) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(125) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(124) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(123) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(122) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(121) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(120) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(119) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(118) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(117) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(116) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(115) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(114) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(113) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(112) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(111) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(110) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(109) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(108) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(107) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(106) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(105) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(104) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(103) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(102) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(101) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(100) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(99) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(98) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(97) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(96) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(95) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(94) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(93) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(92) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(91) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(90) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(89) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(88) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(87) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(86) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(85) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(84) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(83) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(82) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(81) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(80) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(79) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(78) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(77) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(76) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(75) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(74) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(73) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(72) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(71) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(70) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(69) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(68) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(67) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(66) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(65) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
Q(64) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(3 downto 0) => next_word(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_READ.read_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_READ.read_addr_inst_n_29\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12) => rd_cmd_fix,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(11 downto 10) => rd_cmd_first_word(3 downto 2),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(9 downto 8) => rd_cmd_next_word(3 downto 2),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7) => \USE_READ.read_addr_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6) => \USE_READ.read_addr_inst_n_20\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5) => \USE_READ.read_addr_inst_n_21\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4) => \USE_READ.read_addr_inst_n_22\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3) => \USE_READ.read_addr_inst_n_23\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2) => \USE_READ.read_addr_inst_n_24\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(1) => \USE_READ.read_addr_inst_n_25\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0) => \USE_READ.read_addr_inst_n_26\,
\USE_RTL_ADDR.addr_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\,
\current_word_1_reg[0]_0\ => \USE_READ.read_addr_inst_n_28\,
\current_word_1_reg[1]_0\ => \USE_READ.read_addr_inst_n_27\,
\current_word_1_reg[3]_0\(3 downto 0) => pre_next_word_1(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\,
first_word_reg_1(3 downto 0) => current_word_1(3 downto 0),
first_word_reg_2 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\,
\m_payload_i_reg[0]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
\m_payload_i_reg[10]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143\,
\m_payload_i_reg[11]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144\,
\m_payload_i_reg[12]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145\,
\m_payload_i_reg[130]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\,
\m_payload_i_reg[13]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146\,
\m_payload_i_reg[14]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147\,
\m_payload_i_reg[15]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148\,
\m_payload_i_reg[16]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149\,
\m_payload_i_reg[17]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150\,
\m_payload_i_reg[18]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151\,
\m_payload_i_reg[19]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152\,
\m_payload_i_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134\,
\m_payload_i_reg[20]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153\,
\m_payload_i_reg[21]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154\,
\m_payload_i_reg[22]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155\,
\m_payload_i_reg[23]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156\,
\m_payload_i_reg[24]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157\,
\m_payload_i_reg[25]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158\,
\m_payload_i_reg[26]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159\,
\m_payload_i_reg[27]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160\,
\m_payload_i_reg[28]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161\,
\m_payload_i_reg[29]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162\,
\m_payload_i_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135\,
\m_payload_i_reg[30]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163\,
\m_payload_i_reg[31]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164\,
\m_payload_i_reg[3]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136\,
\m_payload_i_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137\,
\m_payload_i_reg[5]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138\,
\m_payload_i_reg[6]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139\,
\m_payload_i_reg[7]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140\,
\m_payload_i_reg[8]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141\,
\m_payload_i_reg[9]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142\,
m_valid_i_reg => \USE_READ.read_addr_inst_n_3\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[3]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\,
\pre_next_word_1_reg[3]_1\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_4\,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12\
);
\USE_READ.read_addr_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
CO(0) => sub_sized_wrap0,
D(3 downto 0) => pre_next_word(3 downto 0),
DI(1) => si_register_slice_inst_n_98,
DI(0) => si_register_slice_inst_n_99,
E(0) => \USE_READ.read_addr_inst_n_5\,
\M_AXI_RDATA_I_reg[127]\(0) => p_7_in,
Q(12) => rd_cmd_fix,
Q(11 downto 10) => rd_cmd_first_word(3 downto 2),
Q(9 downto 8) => rd_cmd_next_word(3 downto 2),
Q(7) => \USE_READ.read_addr_inst_n_19\,
Q(6) => \USE_READ.read_addr_inst_n_20\,
Q(5) => \USE_READ.read_addr_inst_n_21\,
Q(4) => \USE_READ.read_addr_inst_n_22\,
Q(3) => \USE_READ.read_addr_inst_n_23\,
Q(2) => \USE_READ.read_addr_inst_n_24\,
Q(1) => \USE_READ.read_addr_inst_n_25\,
Q(0) => \USE_READ.read_addr_inst_n_26\,
S(3) => si_register_slice_inst_n_100,
S(2) => si_register_slice_inst_n_101,
S(1) => si_register_slice_inst_n_102,
S(0) => si_register_slice_inst_n_103,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => cmd_packed_wrap_i1,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_READ.read_addr_inst_n_3\,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ => \USE_READ.read_addr_inst_n_4\,
\current_word_1_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\,
\current_word_1_reg[3]\(3 downto 0) => next_word(3 downto 0),
\current_word_1_reg[3]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\,
\current_word_1_reg[3]_1\(3 downto 0) => current_word_1(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => \USE_READ.read_addr_inst_n_27\,
first_word_reg_0 => \USE_READ.read_addr_inst_n_28\,
\in\(32) => cmd_fix_i,
\in\(31) => cmd_modified_i,
\in\(30) => cmd_complete_wrap_i,
\in\(29) => cmd_packed_wrap_i,
\in\(28 downto 25) => cmd_first_word_i(3 downto 0),
\in\(24 downto 15) => p_1_out(26 downto 17),
\in\(14) => si_register_slice_inst_n_73,
\in\(13) => si_register_slice_inst_n_74,
\in\(12) => si_register_slice_inst_n_75,
\in\(11) => si_register_slice_inst_n_76,
\in\(10) => si_register_slice_inst_n_77,
\in\(9) => si_register_slice_inst_n_78,
\in\(8) => si_register_slice_inst_n_79,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[50]\(3) => si_register_slice_inst_n_3,
\m_payload_i_reg[50]\(2) => si_register_slice_inst_n_4,
\m_payload_i_reg[50]\(1) => si_register_slice_inst_n_5,
\m_payload_i_reg[50]\(0) => si_register_slice_inst_n_6,
\m_payload_i_reg[51]\(3) => si_register_slice_inst_n_90,
\m_payload_i_reg[51]\(2) => si_register_slice_inst_n_91,
\m_payload_i_reg[51]\(1) => si_register_slice_inst_n_92,
\m_payload_i_reg[51]\(0) => si_register_slice_inst_n_93,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11\,
\pre_next_word_1_reg[3]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\,
\pre_next_word_1_reg[3]_0\(3 downto 0) => pre_next_word_1(3 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \USE_READ.read_addr_inst_n_29\,
\s_axi_rdata[31]_0\ => \USE_READ.read_addr_inst_n_30\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => \USE_READ.read_addr_inst_n_33\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\
);
si_register_slice_inst: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
CO(0) => sub_sized_wrap0,
D(60 downto 0) => D(60 downto 0),
DI(1) => si_register_slice_inst_n_98,
DI(0) => si_register_slice_inst_n_99,
Q(43 downto 0) => Q(43 downto 0),
S(3) => si_register_slice_inst_n_100,
S(2) => si_register_slice_inst_n_101,
S(1) => si_register_slice_inst_n_102,
S(0) => si_register_slice_inst_n_103,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3) => si_register_slice_inst_n_3,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2) => si_register_slice_inst_n_4,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1) => si_register_slice_inst_n_5,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => si_register_slice_inst_n_6,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3) => si_register_slice_inst_n_90,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2) => si_register_slice_inst_n_91,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1) => si_register_slice_inst_n_92,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0) => si_register_slice_inst_n_93,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_0,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_33\,
\in\(32) => cmd_fix_i,
\in\(31) => cmd_modified_i,
\in\(30) => cmd_complete_wrap_i,
\in\(29) => cmd_packed_wrap_i,
\in\(28 downto 25) => cmd_first_word_i(3 downto 0),
\in\(24 downto 15) => p_1_out(26 downto 17),
\in\(14) => si_register_slice_inst_n_73,
\in\(13) => si_register_slice_inst_n_74,
\in\(12) => si_register_slice_inst_n_75,
\in\(11) => si_register_slice_inst_n_76,
\in\(10) => si_register_slice_inst_n_77,
\in\(9) => si_register_slice_inst_n_78,
\in\(8) => si_register_slice_inst_n_79,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\m_payload_i_reg[50]\(0) => cmd_packed_wrap_i1,
\out\ => \out\,
s_axi_aresetn => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => si_register_slice_inst_n_1,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "artix7";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 4;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 128;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_1_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
begin
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_wdata(127) <= \<const0>\;
m_axi_wdata(126) <= \<const0>\;
m_axi_wdata(125) <= \<const0>\;
m_axi_wdata(124) <= \<const0>\;
m_axi_wdata(123) <= \<const0>\;
m_axi_wdata(122) <= \<const0>\;
m_axi_wdata(121) <= \<const0>\;
m_axi_wdata(120) <= \<const0>\;
m_axi_wdata(119) <= \<const0>\;
m_axi_wdata(118) <= \<const0>\;
m_axi_wdata(117) <= \<const0>\;
m_axi_wdata(116) <= \<const0>\;
m_axi_wdata(115) <= \<const0>\;
m_axi_wdata(114) <= \<const0>\;
m_axi_wdata(113) <= \<const0>\;
m_axi_wdata(112) <= \<const0>\;
m_axi_wdata(111) <= \<const0>\;
m_axi_wdata(110) <= \<const0>\;
m_axi_wdata(109) <= \<const0>\;
m_axi_wdata(108) <= \<const0>\;
m_axi_wdata(107) <= \<const0>\;
m_axi_wdata(106) <= \<const0>\;
m_axi_wdata(105) <= \<const0>\;
m_axi_wdata(104) <= \<const0>\;
m_axi_wdata(103) <= \<const0>\;
m_axi_wdata(102) <= \<const0>\;
m_axi_wdata(101) <= \<const0>\;
m_axi_wdata(100) <= \<const0>\;
m_axi_wdata(99) <= \<const0>\;
m_axi_wdata(98) <= \<const0>\;
m_axi_wdata(97) <= \<const0>\;
m_axi_wdata(96) <= \<const0>\;
m_axi_wdata(95) <= \<const0>\;
m_axi_wdata(94) <= \<const0>\;
m_axi_wdata(93) <= \<const0>\;
m_axi_wdata(92) <= \<const0>\;
m_axi_wdata(91) <= \<const0>\;
m_axi_wdata(90) <= \<const0>\;
m_axi_wdata(89) <= \<const0>\;
m_axi_wdata(88) <= \<const0>\;
m_axi_wdata(87) <= \<const0>\;
m_axi_wdata(86) <= \<const0>\;
m_axi_wdata(85) <= \<const0>\;
m_axi_wdata(84) <= \<const0>\;
m_axi_wdata(83) <= \<const0>\;
m_axi_wdata(82) <= \<const0>\;
m_axi_wdata(81) <= \<const0>\;
m_axi_wdata(80) <= \<const0>\;
m_axi_wdata(79) <= \<const0>\;
m_axi_wdata(78) <= \<const0>\;
m_axi_wdata(77) <= \<const0>\;
m_axi_wdata(76) <= \<const0>\;
m_axi_wdata(75) <= \<const0>\;
m_axi_wdata(74) <= \<const0>\;
m_axi_wdata(73) <= \<const0>\;
m_axi_wdata(72) <= \<const0>\;
m_axi_wdata(71) <= \<const0>\;
m_axi_wdata(70) <= \<const0>\;
m_axi_wdata(69) <= \<const0>\;
m_axi_wdata(68) <= \<const0>\;
m_axi_wdata(67) <= \<const0>\;
m_axi_wdata(66) <= \<const0>\;
m_axi_wdata(65) <= \<const0>\;
m_axi_wdata(64) <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(15) <= \<const0>\;
m_axi_wstrb(14) <= \<const0>\;
m_axi_wstrb(13) <= \<const0>\;
m_axi_wstrb(12) <= \<const0>\;
m_axi_wstrb(11) <= \<const0>\;
m_axi_wstrb(10) <= \<const0>\;
m_axi_wstrb(9) <= \<const0>\;
m_axi_wstrb(8) <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_wready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_arregion(3 downto 0),
D(56 downto 53) => s_axi_arqos(3 downto 0),
D(52) => s_axi_arlock(0),
D(51 downto 44) => s_axi_arlen(7 downto 0),
D(43 downto 40) => s_axi_arcache(3 downto 0),
D(39 downto 38) => s_axi_arburst(1 downto 0),
D(37 downto 35) => s_axi_arsize(2 downto 0),
D(34 downto 32) => s_axi_arprot(2 downto 0),
D(31 downto 0) => s_axi_araddr(31 downto 0),
Q(43 downto 40) => m_axi_arregion(3 downto 0),
Q(39 downto 36) => m_axi_arqos(3 downto 0),
Q(35) => m_axi_arlock(0),
Q(34 downto 31) => m_axi_arcache(3 downto 0),
Q(30 downto 28) => m_axi_arprot(2 downto 0),
Q(27 downto 0) => m_axi_araddr(31 downto 4),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_1 : entity is "system_auto_us_1,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_1 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_1;
architecture STRUCTURE of system_auto_us_1 is
signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 4;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 128;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_bvalid => '0',
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(127 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(15 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(15 downto 0),
m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"01",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '1',
s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid => '0'
);
end STRUCTURE;
|
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"BOT*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ", "ASL A ", "ORA*# ",
"BOT*$nnnnn ", "ORA $nnnn ", "ASL $nnnn ", "ASO*$nnnn ",
"BPL rel ", "ORA ($nn),Y ", "HLT* ", "ASO*($nn),Y ",
"BOT*$nn,X ", "ORA $nn,X ", "ASL $nn,X ", "ASO*$nn,X ",
"CLC ", "ORA $nnnn,Y ", "NOP* ", "ASO*$nnnn,Y ",
"BOT*$nnnn,X ", "ORA $nnnn,X ", "ASL $nnnn,X ", "ASO*$nnnn,X ",
"JSR $nnnn ", "AND ($nn,X) ", "HLT* ", "RLA*($nn,X) ",
"BIT $nn ", "AND $nn ", "ROL $nn ", "RLA*$nn ",
"PLP ", "AND # ", "ROL A ", "AND*# ",
"BIT $nnnn ", "AND $nnnn ", "ROL $nnnn ", "RLA*$nnnn ",
"BMI rel ", "AND ($nn),Y ", "HLT* ", "RLA*($nn),Y ",
"BIT*$nn,X ", "AND $nn,X ", "ROL $nn,X ", "RLA*$nn,X ",
"SEC ", "AND $nnnn,Y ", "NOP* ", "RLA*$nnnn,Y ",
"BIT*$nnnn,X ", "AND $nnnn,X ", "ROL $nnnn,X ", "RLA*$nnnn,X ",
"RTI ", "EOR ($nn,X) ", "HLT* ", "LSE*($nn,X) ",
"RDM* ", "EOR $nn ", "LSR $nn ", "LSE*$nn ",
"PHA ", "EOR # ", "LSR A ", "EOR*# ",
"JMP $nnnn ", "EOR $nnnn ", "LSR $nnnn ", "LSE*$nnnn ",
"BVC rel ", "EOR ($nn),Y ", "HLT* ", "LSE*($nn),Y ",
"RDM* ", "EOR $nn,X ", "LSR $nn,X ", "LSE*$nn,X ",
"CLI ", "EOR $nnnn,Y ", "NOP* ", "LSE*$nnnn,Y ",
"JMP*$nnnn ", "EOR $nnnn,X ", "LSR $nnnn,X ", "LSE*$nnnn,X ",
"RTS ", "ADC ($nn,X) ", "HLT* ", "RRA*($nn,X) ",
"RDM* ", "ADC $nn ", "ROR $nn ", "RRA*$nn ",
"PLA ", "ADC # ", "ROR A ", "ADC*# ",
"JMP ($nnnn) ", "ADC $nnnn ", "ROR $nnnn ", "RRA*$nnnn ",
"BVS rel ", "ADC ($nn),Y ", "HLT* ", "RRA*($nn),Y ",
"RDM* ", "ADC $nn,X ", "ROR $nn,X ", "RRA*$nn,X ",
"SEI ", "ADC $nnnn,Y ", "NOP* ", "RRA*$nnnn,Y ",
"JMP*($nnnn,X)", "ADC $nnnn,X ", "ROR $nnnn,X ", "RRA*$nnnn,X ",
"SKB* ", "STA ($nn,X) ", "SKB* ", "AXS*($nn,X) ",
"STY $nn ", "STA $nn ", "STX $nn ", "AXS*$nn ",
"DEY ", "SKB* ", "TXA ", "???* ",
"STY $nnnn ", "STA $nnnn ", "STX $nnnn ", "AXS*$nnnn ",
"BCC ", "STA ($nn),Y ", "HLT* ", "AXS*($nn),Y ",
"STY $nn,X ", "STA $nn,X ", "STX $nn,Y ", "AXS*$nn,Y ",
"TYA ", "STA $nnnn,Y ", "TXS ", "AXS*$nnnn,Y ",
"STY*$nnnn,X ", "STA $nnnn,X ", "STX*$nnnn,Y ", "AXS*$nnnn,Y ",
"LDY # ", "LDA ($nn,X) ", "LDX # ", "LAX*($nn,X) ",
"LDY $nn ", "LDA $nn ", "LDX $nn ", "LAX*$nn ",
"TAY ", "LDA # ", "TAX ", "LAX*# ",
"LDY $nnnn ", "LDA $nnnn ", "LDX $nnnn ", "LAX*$nnnn ",
"BCS ", "LDA ($nn),Y ", "HLT* ", "LAX*($nn),Y ",
"LDY $nn,X ", "LDA $nn,X ", "LDX $nn,Y ", "LAX*$nn,Y ",
"CLV ", "LDA $nnnn,Y ", "TSX ", "LAX*$nnnn,Y ",
"LDY $nnnn,X ", "LDA $nnnn,X ", "LDX $nnnn,Y ", "LAX*$nnnn,Y ",
"CPY # ", "CMP ($nn,X) ", "SKB* ", "DCM*($nn,X) ",
"CPY $nn ", "CMP $nn ", "DEC $nn ", "DCM*$nn ",
"INY ", "CMP # ", "DEX ", "SAX*# (used!)",
"CPY $nnnn ", "CMP $nnnn ", "DEC $nnnn ", "DCM*$nnnn ",
"BNE ", "CMP ($nn),Y ", "HLT* ", "DCM*($nn),Y ",
"RDM* ", "CMP $nn,X ", "DEC $nn,X ", "DCM*$nn,X ",
"CLD ", "CMP $nnnn,Y ", "NOP* ", "DCM*$nnnn,Y ",
"RDM*$nnnn,X ", "CMP $nnnn,X ", "DEC $nnnn,X ", "DCM*$nnnn,X ",
"CPX # ", "SBC ($nn,X) ", "SKB* ", "INS*($nn,X) ",
"CPX $nn ", "SBC $nn ", "INC $nn ", "INS*$nn ",
"INX ", "SBC # ", "NOP ", "SBC*# ",
"CPX $nnnn ", "SBC $nnnn ", "INC $nnnn ", "INS*$nnnn ",
"BEQ ", "SBC ($nn),Y ", "HLT* ", "INS*($nn),Y ",
"RDM* ", "SBC $nn,X ", "INC $nn,X ", "INS*$nn,X ",
"SED ", "SBC $nnnn,Y ", "NOP* ", "INS*$nnnn,Y ",
"RDM*$nnnn,X ", "SBC $nnnn,X ", "INC $nnnn,X ", "INS*$nnnn,X " );
end;
|
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"BOT*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ", "ASL A ", "ORA*# ",
"BOT*$nnnnn ", "ORA $nnnn ", "ASL $nnnn ", "ASO*$nnnn ",
"BPL rel ", "ORA ($nn),Y ", "HLT* ", "ASO*($nn),Y ",
"BOT*$nn,X ", "ORA $nn,X ", "ASL $nn,X ", "ASO*$nn,X ",
"CLC ", "ORA $nnnn,Y ", "NOP* ", "ASO*$nnnn,Y ",
"BOT*$nnnn,X ", "ORA $nnnn,X ", "ASL $nnnn,X ", "ASO*$nnnn,X ",
"JSR $nnnn ", "AND ($nn,X) ", "HLT* ", "RLA*($nn,X) ",
"BIT $nn ", "AND $nn ", "ROL $nn ", "RLA*$nn ",
"PLP ", "AND # ", "ROL A ", "AND*# ",
"BIT $nnnn ", "AND $nnnn ", "ROL $nnnn ", "RLA*$nnnn ",
"BMI rel ", "AND ($nn),Y ", "HLT* ", "RLA*($nn),Y ",
"BIT*$nn,X ", "AND $nn,X ", "ROL $nn,X ", "RLA*$nn,X ",
"SEC ", "AND $nnnn,Y ", "NOP* ", "RLA*$nnnn,Y ",
"BIT*$nnnn,X ", "AND $nnnn,X ", "ROL $nnnn,X ", "RLA*$nnnn,X ",
"RTI ", "EOR ($nn,X) ", "HLT* ", "LSE*($nn,X) ",
"RDM* ", "EOR $nn ", "LSR $nn ", "LSE*$nn ",
"PHA ", "EOR # ", "LSR A ", "EOR*# ",
"JMP $nnnn ", "EOR $nnnn ", "LSR $nnnn ", "LSE*$nnnn ",
"BVC rel ", "EOR ($nn),Y ", "HLT* ", "LSE*($nn),Y ",
"RDM* ", "EOR $nn,X ", "LSR $nn,X ", "LSE*$nn,X ",
"CLI ", "EOR $nnnn,Y ", "NOP* ", "LSE*$nnnn,Y ",
"JMP*$nnnn ", "EOR $nnnn,X ", "LSR $nnnn,X ", "LSE*$nnnn,X ",
"RTS ", "ADC ($nn,X) ", "HLT* ", "RRA*($nn,X) ",
"RDM* ", "ADC $nn ", "ROR $nn ", "RRA*$nn ",
"PLA ", "ADC # ", "ROR A ", "ADC*# ",
"JMP ($nnnn) ", "ADC $nnnn ", "ROR $nnnn ", "RRA*$nnnn ",
"BVS rel ", "ADC ($nn),Y ", "HLT* ", "RRA*($nn),Y ",
"RDM* ", "ADC $nn,X ", "ROR $nn,X ", "RRA*$nn,X ",
"SEI ", "ADC $nnnn,Y ", "NOP* ", "RRA*$nnnn,Y ",
"JMP*($nnnn,X)", "ADC $nnnn,X ", "ROR $nnnn,X ", "RRA*$nnnn,X ",
"SKB* ", "STA ($nn,X) ", "SKB* ", "AXS*($nn,X) ",
"STY $nn ", "STA $nn ", "STX $nn ", "AXS*$nn ",
"DEY ", "SKB* ", "TXA ", "???* ",
"STY $nnnn ", "STA $nnnn ", "STX $nnnn ", "AXS*$nnnn ",
"BCC ", "STA ($nn),Y ", "HLT* ", "AXS*($nn),Y ",
"STY $nn,X ", "STA $nn,X ", "STX $nn,Y ", "AXS*$nn,Y ",
"TYA ", "STA $nnnn,Y ", "TXS ", "AXS*$nnnn,Y ",
"STY*$nnnn,X ", "STA $nnnn,X ", "STX*$nnnn,Y ", "AXS*$nnnn,Y ",
"LDY # ", "LDA ($nn,X) ", "LDX # ", "LAX*($nn,X) ",
"LDY $nn ", "LDA $nn ", "LDX $nn ", "LAX*$nn ",
"TAY ", "LDA # ", "TAX ", "LAX*# ",
"LDY $nnnn ", "LDA $nnnn ", "LDX $nnnn ", "LAX*$nnnn ",
"BCS ", "LDA ($nn),Y ", "HLT* ", "LAX*($nn),Y ",
"LDY $nn,X ", "LDA $nn,X ", "LDX $nn,Y ", "LAX*$nn,Y ",
"CLV ", "LDA $nnnn,Y ", "TSX ", "LAX*$nnnn,Y ",
"LDY $nnnn,X ", "LDA $nnnn,X ", "LDX $nnnn,Y ", "LAX*$nnnn,Y ",
"CPY # ", "CMP ($nn,X) ", "SKB* ", "DCM*($nn,X) ",
"CPY $nn ", "CMP $nn ", "DEC $nn ", "DCM*$nn ",
"INY ", "CMP # ", "DEX ", "SAX*# (used!)",
"CPY $nnnn ", "CMP $nnnn ", "DEC $nnnn ", "DCM*$nnnn ",
"BNE ", "CMP ($nn),Y ", "HLT* ", "DCM*($nn),Y ",
"RDM* ", "CMP $nn,X ", "DEC $nn,X ", "DCM*$nn,X ",
"CLD ", "CMP $nnnn,Y ", "NOP* ", "DCM*$nnnn,Y ",
"RDM*$nnnn,X ", "CMP $nnnn,X ", "DEC $nnnn,X ", "DCM*$nnnn,X ",
"CPX # ", "SBC ($nn,X) ", "SKB* ", "INS*($nn,X) ",
"CPX $nn ", "SBC $nn ", "INC $nn ", "INS*$nn ",
"INX ", "SBC # ", "NOP ", "SBC*# ",
"CPX $nnnn ", "SBC $nnnn ", "INC $nnnn ", "INS*$nnnn ",
"BEQ ", "SBC ($nn),Y ", "HLT* ", "INS*($nn),Y ",
"RDM* ", "SBC $nn,X ", "INC $nn,X ", "INS*$nn,X ",
"SED ", "SBC $nnnn,Y ", "NOP* ", "INS*$nnnn,Y ",
"RDM*$nnnn,X ", "SBC $nnnn,X ", "INC $nnnn,X ", "INS*$nnnn,X " );
end;
|
-------------------------------------------------------------------------------
-- $Id: wrpfifo_top.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--wrpfifo_top.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_top.vhd
--
-- Description: This file is the top level vhdl design for the Write Packet
-- FIFO module.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
-- wrpfifo_top.vhd
-- |
-- |---> ipif_control_wr.vhd
-- |
-- |---> wrpfifo_dp_cntl.vhd
-- | |
-- | |-- pf_counter_top.vhd
-- | | |
-- | | |-- pf_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |
-- | |-- pf_occ_counter_top.vhd
-- | | |
-- | | |-- pf_occ_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |-- pf_adder.vhd
-- | | |
-- | | |-- pf_adder_bit.vhd
-- | |
-- | |
-- | |-- pf_dly1_mux.vhd
-- |
-- |---> pf_dpram.vhd
-- |
-- |
-- |
-- |
-- |---> srl16_fifo.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET March 23,2001 -- V0.00a
--
-- DET Apr-24-01
-- - Change the dual port configuration name to wdport_512x32
-- from dport_512x32.
--
-- DET May-04-01
-- - Hardcoded the MIR_ENABLE and Block_ID constant values
-- to simplify the point design compilation into the IPIF.
-- Commented out the rpfifo_lib declarations.
--
-- DET MAY-24-01
-- - v0.00B Incorporated the V0.00c dual port controller module
--
-- DET June-25-01
-- - Changed the Dual Port core to 3.2 Version and added
-- the ENB nto the core to disable the read port when the
-- FIFO is Empty. This is an attempt to eliminate read
-- warnings during MTI simulation as well as undefined
-- outputs
-- - Changed to V1.00b of the IPIF write Control module.
-- - Changed to the V1.00d version of the DP control module.
-- - Added input Generics for MIR enable and Block ID
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
-- - Added additional parameters (generics)
--
-- DET Oct. 02, 2001 (part of v1.02a version)
-- - added the optimization changes
--
--
-- DET Oct. 8, 2001 (part of v1.02a version)
-- - Changes the C_VIRTEX_II input generic to C_FAMILY of type string
-- - Changed the DP core component and instance to new parameterized
-- version (pf_dpram_select.vhd)
--
-- DET Oct. 13, 2001 (part of v1.02a version)
-- - Added the SRL FIFO option
--
--
-- DET Oct 31, 2001
-- - Changed the input generic C_FAMILY of type string back to the
-- C_VIRTEX_II of type boolean. Changed caused by lack of string
-- support in the XST synthesis tool.
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_dpram_select;
Use opb_v20_v1_10_d.srl16_fifo;
Use opb_v20_v1_10_d.ipif_control_wr;
Use opb_v20_v1_10_d.wrpfifo_dp_cntl;
-------------------------------------------------------------------------------
entity wrpfifo_top is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for enable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_FIFO_DEPTH_LOG2X : Integer range 2 to 14 := 9;
-- The number of needed address bits for the
-- required FIFO depth (= log2(fifo_depth)
-- 9 = 512 wds deep, 8 = 256 wds deep, etc.
C_FIFO_WIDTH : Integer range 1 to 128 := 32;
-- Width of FIFO data in bits
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/omission of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true;
-- Enable for Vacancy calc feature
C_SUPPORT_BURST : Boolean := true;
-- Enable for IPIF Bus burst support
C_IPIF_DBUS_WIDTH : Integer range 8 to 128 := 32;
-- Width of the IPIF data bus in bits
C_VIRTEX_II : boolean := true
-- Selection of target FPGA technology
);
port(
-- Inputs From the IPIF Bus
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the IP
IP2WFIFO_RdReq : In std_logic;
IP2WFIFO_RdMark : In std_logic;
IP2WFIFO_RdRestore : In std_logic;
IP2WFIFO_RdRelease : In std_logic;
-- Outputs to the IP
WFIFO2IP_Data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
WFIFO2IP_RdAck : Out std_logic;
WFIFO2IP_AlmostEmpty : Out std_logic;
WFIFO2IP_Empty : Out std_logic;
WFIFO2IP_Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Outputs to the IPIF DMA/SG function
WFIFO2DMA_AlmostFull : Out std_logic;
WFIFO2DMA_Full : Out std_logic;
WFIFO2DMA_Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end wrpfifo_top ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_top is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
----------------------------------------------------------------------------
-- IMPORTANT!!!!!!!!!!!!!!!!!!!
-- Set MODULE Versioning Information Here!!!
--
-- The following three constants indicate the versioning read via the MIR
----------------------------------------------------------------------------
constant VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning the WrPFIFO design
-- (0 = engineering release,
-- 1 = major release 1, etc.)
constant VERSION_MINOR : integer range 0 to 99:= 1;
-- Minor Version of the WrPFIFO design
constant VERSION_REV : integer range 0 to 25:= 1;
-- Revision letter of the WrPFIFO design
-- (0 = a, 1 = b, 2 = c, etc)
----------------------------------------------------------------------------
-- Set IPIF Block Protocol Type Here!!!!
--
-- IPIF block protocol Type (Read Packet FIFO = 2, Write PFIFO = 3)
----------------------------------------------------------------------------
Constant PFIFO_INTFC_TYPE : integer range 0 to 31 := 3;
----------------------------------------------------------------------------
-- General Use Constants
----------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
-- Dual Port interconnect
signal sig_mem_wrreq: std_logic;
signal sig_mem_wr_enable: std_logic;
signal sig_mem_wr_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
signal sig_mem_wr_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
Signal sig_fifo_wrack: std_logic;
Signal sig_fifo_rdack: std_logic;
signal sig_fifo_full: std_logic;
signal sig_fifo_empty: std_logic;
signal sig_fifo_almost_full: std_logic;
signal sig_fifo_almost_empty: std_logic;
signal sig_fifo_occupancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
signal sig_fifo_vacancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_burst_wr_xfer: std_logic;
Signal sig_fifo_logic_reset: std_logic;
signal sig_fifo_deadlock : std_logic;
Signal sig_mem_rdreq : std_logic;
signal sig_mem_rd_enable : std_logic;
-------------------------------------------------------------------------------
------------------------------- start processes -------------------------------
begin
-- connect I/O signals to internals
WFIFO2IP_RdAck <= sig_fifo_rdack;
WFIFO2IP_Empty <= sig_fifo_empty;
WFIFO2IP_AlmostEmpty <= sig_fifo_almost_empty;
WFIFO2IP_Occupancy <= sig_fifo_occupancy;
WFIFO2DMA_AlmostFull <= sig_fifo_almost_full;
WFIFO2DMA_Full <= sig_fifo_full ;
WFIFO2DMA_Vacancy <= sig_fifo_vacancy;
-- Some Dual Port signal assignments (vhdl wrapper)
--sig_mem_wr_enable <= not(sig_fifo_full);
sig_mem_rdreq <= IP2WFIFO_RdReq;
WFIFO2IP_Data <= sig_mem_rd_data;
I_IPIF_INTERFACE_BLOCK : entity opb_v20_v1_10_d.ipif_control_wr
Generic map (
C_MIR_ENABLE => C_MIR_ENABLE ,
C_BLOCK_ID => C_BLOCK_ID ,
C_INTFC_TYPE => PFIFO_INTFC_TYPE,
C_VERSION_MAJOR => VERSION_MAJOR,
C_VERSION_MINOR => VERSION_MINOR,
C_VERSION_REV => VERSION_REV,
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_SUPPORT_BURST => C_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => C_IPIF_DBUS_WIDTH
)
port map (
-- Inputs From the IPIF Bus
Bus_rst => Bus_rst ,
Bus_clk => Bus_clk ,
Bus_RdReq => Bus_RdReq ,
Bus_WrReq => Bus_WrReq ,
Bus2FIFO_RdCE1 => Bus2FIFO_RdCE1,
Bus2FIFO_RdCE2 => Bus2FIFO_RdCE2,
Bus2FIFO_RdCE3 => Bus2FIFO_RdCE3,
Bus2FIFO_WrCE1 => Bus2FIFO_WrCE1,
Bus2FIFO_WrCE2 => Bus2FIFO_WrCE2,
Bus2FIFO_WrCE3 => Bus2FIFO_WrCE3,
Bus_DBus => Bus_DBus ,
-- Inputs from the FIFO Interface Logic
Fifo_WrAck => sig_fifo_wrack,
Vacancy => sig_fifo_vacancy,
AlmostFull => sig_fifo_almost_full,
Full => sig_fifo_full,
Deadlock => sig_fifo_deadlock,
-- Outputs to the FIFO
Fifo_wr_data => sig_mem_wr_data,
Fifo_Reset => sig_fifo_logic_reset,
Fifo_WrReq => sig_mem_wrreq,
Fifo_burst_wr_xfer => sig_burst_wr_xfer,
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock => FIFO2IRPT_DeadLock ,
FIFO2Bus_DBus => FIFO2Bus_DBus ,
FIFO2Bus_WrAck => FIFO2Bus_WrAck ,
FIFO2Bus_RdAck => FIFO2Bus_RdAck ,
FIFO2Bus_Error => FIFO2Bus_Error ,
FIFO2Bus_Retry => FIFO2Bus_Retry ,
FIFO2Bus_ToutSup => FIFO2Bus_ToutSup
);
USE_BLOCK_RAM : if (C_FIFO_DEPTH_LOG2X > 4 or
C_INCLUDE_PACKET_MODE = true) generate
begin
-- Connect the Dual Port Address Controller the VHDL wrapper
I_DP_CONTROLLER: entity opb_v20_v1_10_d.wrpfifo_dp_cntl
Generic map (
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_PACKET_MODE => C_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map(
-- Inputs
Bus_rst => sig_fifo_logic_reset,
Bus_clk => Bus_clk,
Rdreq => sig_mem_rdreq,
Wrreq => sig_mem_wrreq,
Burst_wr_xfer => sig_burst_wr_xfer,
Mark => IP2WFIFO_RdMark,
Restore => IP2WFIFO_RdRestore,
Release => IP2WFIFO_RdRelease,
-- Outputs
WrAck => sig_fifo_wrack,
RdAck => sig_fifo_rdack,
Full => sig_fifo_full,
Empty => sig_fifo_empty,
Almost_Full => sig_fifo_almost_full,
Almost_Empty => sig_fifo_almost_empty,
DeadLock => sig_fifo_deadlock,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy,
DP_core_wren => sig_mem_wr_enable,
Wr_Addr => sig_mem_wr_addr,
DP_core_rden => sig_mem_rd_enable,
Rd_Addr => sig_mem_rd_addr
);
-- Dual Port Core connection
I_DP_CORE : entity opb_v20_v1_10_d.pf_dpram_select
generic map(
C_DP_DATA_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_VIRTEX_II => C_VIRTEX_II
)
port map(
-- Write Port signals
Wr_rst => sig_fifo_logic_reset,
Wr_Clk => Bus_Clk,
Wr_Enable => sig_mem_wr_enable,
Wr_Req => sig_mem_wrreq,
Wr_Address => sig_mem_wr_addr,
Wr_Data => sig_mem_wr_data,
-- Read Port Signals
Rd_rst => sig_fifo_logic_reset,
Rd_Clk => Bus_Clk,
Rd_Enable => sig_mem_rd_enable,
Rd_Address => sig_mem_rd_addr,
Rd_Data => sig_mem_rd_data
);
end generate USE_BLOCK_RAM;
USE_SRL_CORE : if (C_FIFO_DEPTH_LOG2X <= 4 and
C_INCLUDE_PACKET_MODE = False) generate
begin
sig_fifo_deadlock <= '0';
sig_fifo_rdack <= sig_mem_rdreq and not(sig_fifo_empty);
sig_fifo_wrack <= sig_mem_wrreq and not(sig_fifo_full);
I_SRL_MEM : entity opb_v20_v1_10_d.srl16_fifo
generic map (
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_FIFO_DEPTH_LOG2X => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map (
Bus_clk => Bus_Clk,
Bus_rst => sig_fifo_logic_reset,
Wr_Req => sig_mem_wrreq,
Wr_Data => sig_mem_wr_data,
Rd_Req => sig_mem_rdreq,
Rd_Data => sig_mem_rd_data,
Full => sig_fifo_full,
Almostfull => sig_fifo_almost_full,
Empty => sig_fifo_empty,
Almostempty => sig_fifo_almost_empty,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy
);
end generate USE_SRL_CORE;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: wrpfifo_top.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--wrpfifo_top.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_top.vhd
--
-- Description: This file is the top level vhdl design for the Write Packet
-- FIFO module.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
-- wrpfifo_top.vhd
-- |
-- |---> ipif_control_wr.vhd
-- |
-- |---> wrpfifo_dp_cntl.vhd
-- | |
-- | |-- pf_counter_top.vhd
-- | | |
-- | | |-- pf_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |
-- | |-- pf_occ_counter_top.vhd
-- | | |
-- | | |-- pf_occ_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |-- pf_adder.vhd
-- | | |
-- | | |-- pf_adder_bit.vhd
-- | |
-- | |
-- | |-- pf_dly1_mux.vhd
-- |
-- |---> pf_dpram.vhd
-- |
-- |
-- |
-- |
-- |---> srl16_fifo.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET March 23,2001 -- V0.00a
--
-- DET Apr-24-01
-- - Change the dual port configuration name to wdport_512x32
-- from dport_512x32.
--
-- DET May-04-01
-- - Hardcoded the MIR_ENABLE and Block_ID constant values
-- to simplify the point design compilation into the IPIF.
-- Commented out the rpfifo_lib declarations.
--
-- DET MAY-24-01
-- - v0.00B Incorporated the V0.00c dual port controller module
--
-- DET June-25-01
-- - Changed the Dual Port core to 3.2 Version and added
-- the ENB nto the core to disable the read port when the
-- FIFO is Empty. This is an attempt to eliminate read
-- warnings during MTI simulation as well as undefined
-- outputs
-- - Changed to V1.00b of the IPIF write Control module.
-- - Changed to the V1.00d version of the DP control module.
-- - Added input Generics for MIR enable and Block ID
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
-- - Added additional parameters (generics)
--
-- DET Oct. 02, 2001 (part of v1.02a version)
-- - added the optimization changes
--
--
-- DET Oct. 8, 2001 (part of v1.02a version)
-- - Changes the C_VIRTEX_II input generic to C_FAMILY of type string
-- - Changed the DP core component and instance to new parameterized
-- version (pf_dpram_select.vhd)
--
-- DET Oct. 13, 2001 (part of v1.02a version)
-- - Added the SRL FIFO option
--
--
-- DET Oct 31, 2001
-- - Changed the input generic C_FAMILY of type string back to the
-- C_VIRTEX_II of type boolean. Changed caused by lack of string
-- support in the XST synthesis tool.
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_dpram_select;
Use opb_v20_v1_10_d.srl16_fifo;
Use opb_v20_v1_10_d.ipif_control_wr;
Use opb_v20_v1_10_d.wrpfifo_dp_cntl;
-------------------------------------------------------------------------------
entity wrpfifo_top is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for enable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_FIFO_DEPTH_LOG2X : Integer range 2 to 14 := 9;
-- The number of needed address bits for the
-- required FIFO depth (= log2(fifo_depth)
-- 9 = 512 wds deep, 8 = 256 wds deep, etc.
C_FIFO_WIDTH : Integer range 1 to 128 := 32;
-- Width of FIFO data in bits
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/omission of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true;
-- Enable for Vacancy calc feature
C_SUPPORT_BURST : Boolean := true;
-- Enable for IPIF Bus burst support
C_IPIF_DBUS_WIDTH : Integer range 8 to 128 := 32;
-- Width of the IPIF data bus in bits
C_VIRTEX_II : boolean := true
-- Selection of target FPGA technology
);
port(
-- Inputs From the IPIF Bus
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the IP
IP2WFIFO_RdReq : In std_logic;
IP2WFIFO_RdMark : In std_logic;
IP2WFIFO_RdRestore : In std_logic;
IP2WFIFO_RdRelease : In std_logic;
-- Outputs to the IP
WFIFO2IP_Data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
WFIFO2IP_RdAck : Out std_logic;
WFIFO2IP_AlmostEmpty : Out std_logic;
WFIFO2IP_Empty : Out std_logic;
WFIFO2IP_Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Outputs to the IPIF DMA/SG function
WFIFO2DMA_AlmostFull : Out std_logic;
WFIFO2DMA_Full : Out std_logic;
WFIFO2DMA_Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end wrpfifo_top ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_top is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
----------------------------------------------------------------------------
-- IMPORTANT!!!!!!!!!!!!!!!!!!!
-- Set MODULE Versioning Information Here!!!
--
-- The following three constants indicate the versioning read via the MIR
----------------------------------------------------------------------------
constant VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning the WrPFIFO design
-- (0 = engineering release,
-- 1 = major release 1, etc.)
constant VERSION_MINOR : integer range 0 to 99:= 1;
-- Minor Version of the WrPFIFO design
constant VERSION_REV : integer range 0 to 25:= 1;
-- Revision letter of the WrPFIFO design
-- (0 = a, 1 = b, 2 = c, etc)
----------------------------------------------------------------------------
-- Set IPIF Block Protocol Type Here!!!!
--
-- IPIF block protocol Type (Read Packet FIFO = 2, Write PFIFO = 3)
----------------------------------------------------------------------------
Constant PFIFO_INTFC_TYPE : integer range 0 to 31 := 3;
----------------------------------------------------------------------------
-- General Use Constants
----------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
-- Dual Port interconnect
signal sig_mem_wrreq: std_logic;
signal sig_mem_wr_enable: std_logic;
signal sig_mem_wr_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
signal sig_mem_wr_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_addr: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
Signal sig_fifo_wrack: std_logic;
Signal sig_fifo_rdack: std_logic;
signal sig_fifo_full: std_logic;
signal sig_fifo_empty: std_logic;
signal sig_fifo_almost_full: std_logic;
signal sig_fifo_almost_empty: std_logic;
signal sig_fifo_occupancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
signal sig_fifo_vacancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_burst_wr_xfer: std_logic;
Signal sig_fifo_logic_reset: std_logic;
signal sig_fifo_deadlock : std_logic;
Signal sig_mem_rdreq : std_logic;
signal sig_mem_rd_enable : std_logic;
-------------------------------------------------------------------------------
------------------------------- start processes -------------------------------
begin
-- connect I/O signals to internals
WFIFO2IP_RdAck <= sig_fifo_rdack;
WFIFO2IP_Empty <= sig_fifo_empty;
WFIFO2IP_AlmostEmpty <= sig_fifo_almost_empty;
WFIFO2IP_Occupancy <= sig_fifo_occupancy;
WFIFO2DMA_AlmostFull <= sig_fifo_almost_full;
WFIFO2DMA_Full <= sig_fifo_full ;
WFIFO2DMA_Vacancy <= sig_fifo_vacancy;
-- Some Dual Port signal assignments (vhdl wrapper)
--sig_mem_wr_enable <= not(sig_fifo_full);
sig_mem_rdreq <= IP2WFIFO_RdReq;
WFIFO2IP_Data <= sig_mem_rd_data;
I_IPIF_INTERFACE_BLOCK : entity opb_v20_v1_10_d.ipif_control_wr
Generic map (
C_MIR_ENABLE => C_MIR_ENABLE ,
C_BLOCK_ID => C_BLOCK_ID ,
C_INTFC_TYPE => PFIFO_INTFC_TYPE,
C_VERSION_MAJOR => VERSION_MAJOR,
C_VERSION_MINOR => VERSION_MINOR,
C_VERSION_REV => VERSION_REV,
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_SUPPORT_BURST => C_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => C_IPIF_DBUS_WIDTH
)
port map (
-- Inputs From the IPIF Bus
Bus_rst => Bus_rst ,
Bus_clk => Bus_clk ,
Bus_RdReq => Bus_RdReq ,
Bus_WrReq => Bus_WrReq ,
Bus2FIFO_RdCE1 => Bus2FIFO_RdCE1,
Bus2FIFO_RdCE2 => Bus2FIFO_RdCE2,
Bus2FIFO_RdCE3 => Bus2FIFO_RdCE3,
Bus2FIFO_WrCE1 => Bus2FIFO_WrCE1,
Bus2FIFO_WrCE2 => Bus2FIFO_WrCE2,
Bus2FIFO_WrCE3 => Bus2FIFO_WrCE3,
Bus_DBus => Bus_DBus ,
-- Inputs from the FIFO Interface Logic
Fifo_WrAck => sig_fifo_wrack,
Vacancy => sig_fifo_vacancy,
AlmostFull => sig_fifo_almost_full,
Full => sig_fifo_full,
Deadlock => sig_fifo_deadlock,
-- Outputs to the FIFO
Fifo_wr_data => sig_mem_wr_data,
Fifo_Reset => sig_fifo_logic_reset,
Fifo_WrReq => sig_mem_wrreq,
Fifo_burst_wr_xfer => sig_burst_wr_xfer,
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock => FIFO2IRPT_DeadLock ,
FIFO2Bus_DBus => FIFO2Bus_DBus ,
FIFO2Bus_WrAck => FIFO2Bus_WrAck ,
FIFO2Bus_RdAck => FIFO2Bus_RdAck ,
FIFO2Bus_Error => FIFO2Bus_Error ,
FIFO2Bus_Retry => FIFO2Bus_Retry ,
FIFO2Bus_ToutSup => FIFO2Bus_ToutSup
);
USE_BLOCK_RAM : if (C_FIFO_DEPTH_LOG2X > 4 or
C_INCLUDE_PACKET_MODE = true) generate
begin
-- Connect the Dual Port Address Controller the VHDL wrapper
I_DP_CONTROLLER: entity opb_v20_v1_10_d.wrpfifo_dp_cntl
Generic map (
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_PACKET_MODE => C_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map(
-- Inputs
Bus_rst => sig_fifo_logic_reset,
Bus_clk => Bus_clk,
Rdreq => sig_mem_rdreq,
Wrreq => sig_mem_wrreq,
Burst_wr_xfer => sig_burst_wr_xfer,
Mark => IP2WFIFO_RdMark,
Restore => IP2WFIFO_RdRestore,
Release => IP2WFIFO_RdRelease,
-- Outputs
WrAck => sig_fifo_wrack,
RdAck => sig_fifo_rdack,
Full => sig_fifo_full,
Empty => sig_fifo_empty,
Almost_Full => sig_fifo_almost_full,
Almost_Empty => sig_fifo_almost_empty,
DeadLock => sig_fifo_deadlock,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy,
DP_core_wren => sig_mem_wr_enable,
Wr_Addr => sig_mem_wr_addr,
DP_core_rden => sig_mem_rd_enable,
Rd_Addr => sig_mem_rd_addr
);
-- Dual Port Core connection
I_DP_CORE : entity opb_v20_v1_10_d.pf_dpram_select
generic map(
C_DP_DATA_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_VIRTEX_II => C_VIRTEX_II
)
port map(
-- Write Port signals
Wr_rst => sig_fifo_logic_reset,
Wr_Clk => Bus_Clk,
Wr_Enable => sig_mem_wr_enable,
Wr_Req => sig_mem_wrreq,
Wr_Address => sig_mem_wr_addr,
Wr_Data => sig_mem_wr_data,
-- Read Port Signals
Rd_rst => sig_fifo_logic_reset,
Rd_Clk => Bus_Clk,
Rd_Enable => sig_mem_rd_enable,
Rd_Address => sig_mem_rd_addr,
Rd_Data => sig_mem_rd_data
);
end generate USE_BLOCK_RAM;
USE_SRL_CORE : if (C_FIFO_DEPTH_LOG2X <= 4 and
C_INCLUDE_PACKET_MODE = False) generate
begin
sig_fifo_deadlock <= '0';
sig_fifo_rdack <= sig_mem_rdreq and not(sig_fifo_empty);
sig_fifo_wrack <= sig_mem_wrreq and not(sig_fifo_full);
I_SRL_MEM : entity opb_v20_v1_10_d.srl16_fifo
generic map (
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_FIFO_DEPTH_LOG2X => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map (
Bus_clk => Bus_Clk,
Bus_rst => sig_fifo_logic_reset,
Wr_Req => sig_mem_wrreq,
Wr_Data => sig_mem_wr_data,
Rd_Req => sig_mem_rdreq,
Rd_Data => sig_mem_rd_data,
Full => sig_fifo_full,
Almostfull => sig_fifo_almost_full,
Empty => sig_fifo_empty,
Almostempty => sig_fifo_almost_empty,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy
);
end generate USE_SRL_CORE;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end AveragingFilter_process;
architecture rtl of AveragingFilter_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : unsigned(12 downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
sum := unsigned('0' & '0' & '0' & '0' & '0' & p22) + unsigned('0' & '0' & '0' & '0' & '0' & p21) + unsigned('0' & '0' & '0' & '0' & '0' & p20)
+ unsigned('0' & '0' & '0' & '0' & '0' & p12) + unsigned('0' & '0' & '0' & '0' & '0' & p11) + unsigned('0' & '0' & '0' & '0' & '0' & p10)
+ unsigned('0' & '0' & '0' & '0' & '0' & p02) + unsigned('0' & '0' & '0' & '0' & '0' & p01) + unsigned('0' & '0' & '0' & '0' & '0' & p00);
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
if (unsigned(sum) >= to_unsigned(2048,13)) then
value_data <= (others => '1');
value_dv <= '1';
else
value_data <= std_logic_vector(shift_right(sum,3))(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1816.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01816ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of bit;
END c07s01b00x00p08n01i01816ent;
ARCHITECTURE c07s01b00x00p08n01i01816arch OF c07s01b00x00p08n01i01816ent IS
signal s_int : small_int := 0;
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= s_bus'right(small_int);
wait;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01816 - Type names are not permitted as primaries in an attribute argument."
severity ERROR;
END PROCESS TESTING;
END c07s01b00x00p08n01i01816arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1816.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01816ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of bit;
END c07s01b00x00p08n01i01816ent;
ARCHITECTURE c07s01b00x00p08n01i01816arch OF c07s01b00x00p08n01i01816ent IS
signal s_int : small_int := 0;
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= s_bus'right(small_int);
wait;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01816 - Type names are not permitted as primaries in an attribute argument."
severity ERROR;
END PROCESS TESTING;
END c07s01b00x00p08n01i01816arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1816.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01816ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of bit;
END c07s01b00x00p08n01i01816ent;
ARCHITECTURE c07s01b00x00p08n01i01816arch OF c07s01b00x00p08n01i01816ent IS
signal s_int : small_int := 0;
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= s_bus'right(small_int);
wait;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01816 - Type names are not permitted as primaries in an attribute argument."
severity ERROR;
END PROCESS TESTING;
END c07s01b00x00p08n01i01816arch;
|
----------------------------------------------------------------------------------
-- Company: digilent.com
-- Engineer: Robert Bocos
--
-- Create Date: 2021
-- Design Name:
-- Module Name: ConfigClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: 2021.1
-- Description:
--
-- Dependencies: PkgZmodDigitizer.vhd, TWI_Ctl.vhd, ResetBridge.vhd, SyncAsync.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------
--
-- This module configures the CDCE6214-Q1 clock generator over I2C.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.PkgTWI_Utils.ALL;
use work.PkgZmodDigitizer.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ConfigClockGen is
Generic(
-- Clock Generator I2C shortened config for simulation
kCDCE_SimulationConfig : boolean := false;
-- Clock Generator I2C shortened configuration number of commands to send over I2C for simulation (zero based)
kCDCE_SimulationCmdTotal : integer range 0 to kCDCE_RegNrZeroBased := kCDCE_RegNrZeroBased;
-- Clock Generator I2C 8 bit config address (0xCE(Fall-Back Mode), 0xD0(Default Mode), 0xD2)
kCDCEI2C_Addr : std_logic_vector(7 downto 0) := x"CE";
-- Clock Generator input reference clock selection parameter ('0' selects SECREF(XTAL) and '1' selects PRIREF(FPGA))
kRefSel : std_logic := '0';
-- Clock Generator EEPROM Page selection parameter ('0' selects Page 0 and '1' selects Page 1)
kHwSwCtrlSel : std_logic := '1';
-- Parameter identifying the CDCE output frequency with SECREF(XTAL) as reference frequency:
-- 0 -> 122.88MHz
-- 1 -> 50MHz
-- 2 -> 80MHz
-- 3 -> 100MHz
-- 4 -> 110MHz
-- 5 -> 120MHz
-- 6 -> 125MHz
kFreqSel : integer range 0 to CDCE_I2C_Cmds'length := 0
);
Port (
-- 100MHZ clock input.
RefClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in RefClk domain).
arRst : in std_logic;
-- Clock Generator configuration done succesful signal
rInitConfigDoneClockGen : out std_logic;
-- Clock Generator PLL lock signal sent via the GPIO1 or GPIO4 port
aCG_PLL_Lock : in std_logic;
-- Clock Generator PLL lock signal sent via the GPIO1 or GPIO4 port and synchronized in the RefClk domain
rPLL_LockClockGen : out std_logic;
-- rConfigADCEnable is used to hold the ConfigADC module in reset until the Clock Generator is configured and locked
rConfigADCEnable : out std_logic;
-- Clock Generator reference selection signal ('0' selects SECREF(XTAL) and '1' selects PRIREF(FPGA))
aREFSEL : out std_logic;
-- Clock Generator EEPROM Page selection signal
aHW_SW_CTRL : out std_logic;
-- Clock Generator power down signal, passthrough output
rPDNout_n : out std_logic;
----------------------------------------------------------------------------------
-- IIC bus signals
----------------------------------------------------------------------------------
s_scl_i : in std_logic; -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o : out std_logic; -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t : out std_logic; -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i : in std_logic; -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o : out std_logic; -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t : out std_logic -- IIC Serial Data Output Enable to 3-state buffer (required)
);
end ConfigClockGen;
architecture Behavioral of ConfigClockGen is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of s_scl_i: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO of s_scl_o: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO of s_scl_t: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_T";
ATTRIBUTE X_INTERFACE_INFO of s_sda_i: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO of s_sda_o: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO of s_sda_t: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_T";
signal rRst : std_logic;
signal rI2C_ErrorType : error_type;
signal rCmdCnt : unsigned(6 downto 0) := (others => '0');
signal rIncCmdCnt, rConfigDone, rReadBackDone : std_logic := '0';
signal rRstCmdCnt : std_logic := '0';
signal rPLL_LockClockGen_Loc : std_logic := '0';
signal rConfigADCEnable_Loc : std_logic := '0';
signal rReadBackErr : std_logic := '0';
constant kCmdTotal : integer range 0 to ((CDCE_I2C_Cmds(kFreqSel)'length)-1) := ((CDCE_I2C_Cmds(kFreqSel)'length)-1);
constant kReadBackInt : integer range 0 to ((CDCE_I2C_Cmds(kFreqSel)'length)-1) := 83;
signal rState : FsmStatesI2C_t := stIdle;
signal rNState : FsmStatesI2C_t;
signal rI2C_DataIn, rI2C_DataOut, rI2C_Address : std_logic_vector(7 downto 0);
signal rI2C_Stb, rI2C_Done, rI2C_Error, rI2C_Msg, rI2C_Stp : std_logic;
signal aREFSEL_TriStateCtl : std_logic;
signal aHW_SW_CTRL_TriStateCtl : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of rCmdCnt, rIncCmdCnt, rConfigDone, rReadBackDone, rConfigADCEnable_Loc, rRstCmdCnt, rReadBackErr, rState, rNState, rI2C_DataIn, rI2C_DataOut, rI2C_Address, rI2C_Stb, rI2C_Stp, rI2C_Done, rI2C_Error, rI2C_Msg : signal is "TRUE";
begin
OBUFT_REFSEL_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => aREFSEL, -- Buffer output (connect directly to top-level port)
I => kRefSel, -- Buffer input
T => aREFSEL_TriStateCtl -- 3-state enable input
);
OBUFT_HWSWCTRL_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => aHW_SW_CTRL, -- Buffer output (connect directly to top-level port)
I => kHwSwCtrlSel, -- Buffer input
T => aHW_SW_CTRL_TriStateCtl -- 3-state enable input
);
-- Instantiate the I2C Master Transmitter
TWI_Inst: entity work.TWI_Ctl
Generic Map(
CLOCKFREQ => 100
)
Port Map(
MSG_I => rI2C_Msg,
STB_I => rI2C_Stb,
STP_I => rI2C_Stp,
A_I => rI2C_Address,
D_I => rI2C_DataIn,
D_O => rI2C_DataOut,
DONE_O => rI2C_Done,
ERR_O => rI2C_Error,
ERRTYPE_O => rI2C_ErrorType,
CLK => RefClk,
SRST => rRst,
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
s_scl_i => s_scl_i,
s_scl_o => s_scl_o,
s_scl_t => s_scl_t,
s_sda_i => s_sda_i,
s_sda_o => s_sda_o,
s_sda_t => s_sda_t
);
TWI_Ctl_Reset_Synchro: entity work.ResetBridge
Generic map(
kPolarity => '1')
Port map(
aRst => arRst,
OutClk => RefClk,
aoRst => rRst);
Synchro_CDCE_PLL: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => arRst,
aIn => aCG_PLL_Lock,
OutClk => RefClk,
oOut => rPLL_LockClockGen_Loc);
rPLL_LockClockGen <= rPLL_LockClockGen_Loc;
rConfigADCEnable <= rConfigADCEnable_Loc;
--Configuration of the ADC over SPI should be done after rConfigADCEnable is asserted which only happens after the CDCE clock generator is configured
--and the PLL inside the CDCE is locked, otherwise the ADC should be reset and reconfigured
ConfigADC_Enable: process (RefClk, arRst, rConfigDone, rReadBackDone, rPLL_LockClockGen_Loc)
begin
if (arRst = '1') then
rConfigADCEnable_Loc <= '0';
elsif (rising_edge(RefClk)) then
if (rPLL_LockClockGen_Loc = '1' and rConfigDone = '1' and kCDCE_SimulationConfig = true) then
rConfigADCEnable_Loc <= '1';
elsif (rPLL_LockClockGen_Loc = '1' and rConfigDone = '1' and rReadBackDone = '1') then
rConfigADCEnable_Loc <= '1';
else
rConfigADCEnable_Loc <= '0';
end if;
end if;
end process ConfigADC_Enable;
--Registered Clock Generator configuration done succesfully signal output
ConfigClockGenDone: process (RefClk, arRst, rConfigDone, rReadBackDone)
begin
if (arRst = '1') then
rInitConfigDoneClockGen <= '0';
elsif (rising_edge(RefClk)) then
if (rConfigDone = '1' and kCDCE_SimulationConfig = true) then
rInitConfigDoneClockGen <= '1';
elsif (rConfigDone = '1' and rReadBackDone = '1') then
rInitConfigDoneClockGen <= '1';
else
rInitConfigDoneClockGen <= '0';
end if;
end if;
end process ConfigClockGenDone;
-- ROM/RAM sync output
RegisteredOutput: process (RefClk, arRst)
begin
if (arRst = '1') then
rI2C_DataIn <= (others => '0');
rConfigDone <= '0';
rRstCmdCnt <= '0';
rReadBackErr <= '0';
rReadBackDone <= '0';
rPDNout_n <= '0';
elsif Rising_Edge(RefClk) then
if(rState = stRegAddress_H) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(31 downto 24);--Register Address High
rRstCmdCnt <= '1';
elsif (rState = stRegAddress_L) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(23 downto 16);--Register Address Low
rRstCmdCnt <= '1';
elsif (rState = stRegData_H) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(15 downto 8);--Register Data High
rRstCmdCnt <= '1';
elsif (rState = stRegData_L) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(to_integer(rCmdCnt))(7 downto 0);--Register Data Low
rRstCmdCnt <= '1';
elsif (rState = StCheckCmdCnt) then
rRstCmdCnt <= '1';
if (kCDCE_SimulationConfig = true) then
if (rCmdCnt = kCDCE_SimulationCmdTotal) then
rConfigDone <= '1';
rRstCmdCnt <= '0';
end if;
elsif (rCmdCnt = kCmdTotal) then
rConfigDone <= '1';
rRstCmdCnt <= '0';
else
rRstCmdCnt <= '1';
rConfigDone <= '0';
end if;
elsif (rState = stIdle) then
rReadBackErr <= '0';
rRstCmdCnt <= '0';
rPDNout_n <= '1';
elsif (rState = stReadBackAddress_H) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(31 downto 24);--Register Address High
elsif (rState = stReadBackAddress_L) then
rI2C_DataIn <= CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(23 downto 16);--Register Address Low
elsif (rState = stReadBackData_H) then
if (rI2C_Done = '1' and rI2C_Error = '0') then
if CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(15 downto 8) /= (rI2C_DataOut and CDCE_I2C_Masks(kReadBackInt)(15 downto 8)) then
rReadBackErr <= '1';
end if;
end if;
elsif (rState = stReadBackData_L) then
if (rI2C_Done = '1' and rI2C_Error = '0') then
if CDCE_I2C_Cmds(kFreqSel)(kReadBackInt)(7 downto 0) /= (rI2C_DataOut and CDCE_I2C_Masks(kReadBackInt)(7 downto 0)) then
rReadBackErr <= '1';
end if;
end if;
elsif (rState = stCheckReadBackError) then
if (rReadBackErr = '1') then
rConfigDone <= '0';
rReadBackDone <= '0';
else
rReadBackDone <= '1';
end if;
end if;
end if;
end process RegisteredOutput;
-- Counter used to track the number of successfully sent commands.
ProcCmdCounter: process (RefClk, arRst)
begin
if (arRst = '1') then
rCmdCnt <= (others => '0');
elsif (rising_edge(RefClk)) then
if (rRstCmdCnt = '0') then
rCmdCnt <= (others => '0');
elsif (rIncCmdCnt = '1') then
rCmdCnt <= rCmdCnt + 1;
end if;
end if;
end process;
-- State machine synchronous process.
ProcSyncFsm: process (RefClk, arRst)
begin
if (arRst = '1') then
rState <= stIdle;
elsif (rising_edge(RefClk)) then
rState <= rNState;
end if;
end process;
--MOORE State-Machine - Outputs based on state only
rI2C_Stb <= '1' when (rState = stRegAddress_H or rState = stRegAddress_L or rState = stRegData_H or rState = stRegData_L) else
'1' when (rState = stReadBackAddress_H or rState = stReadBackAddress_L or rState = stReadBackData_H or rState = stReadBackData_L) else
'0';
rI2C_Msg <= '1' when (rState = stRegAddress_H or rState = stReadBackAddress_H) else
'1' when (rState = stReadBackData_H) else
'0';
rI2C_Stp <= '1' when (rState = stRegAddress_H or rState = stReadBackAddress_H) else
'0';
rI2C_Address <= (kCDCEI2C_Addr(7 downto 1) & '1') when (rState = stReadBackData_H or rState = stReadBackData_L) else kCDCEI2C_Addr;
--MEALY State-Machine
rIncCmdCnt <= '1' when (rState = stCheckConfigDone and rConfigDone = '0') else
'0';
aREFSEL_TriStateCtl <= '1' when (kCDCEI2C_Addr = x"CE") else '0';
aHW_SW_CTRL_TriStateCtl <= '1' when (kCDCEI2C_Addr = x"CE") else '0';
NextStateDecode: process (rState, rI2C_Done, rI2C_Error, rConfigDone, rReadBackDone, rReadBackErr)
begin
--declare default state for next_state to avoid latches
rNState <= rState;
case (rState) is
when stIdle =>
if (rConfigDone = '0') then
rNState <= stRegAddress_H;
elsif (kCDCE_SimulationConfig = false) then
if (rReadBackDone = '0') then
rNState <= stReadBackAddress_H;
end if;
end if;
when stRegAddress_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stRegAddress_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stRegAddress_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stRegData_H;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stRegData_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stRegData_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stRegData_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stCheckCmdCnt;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stCheckCmdCnt =>
rNState <= stCheckConfigDone;
when stCheckConfigDone =>
if (rConfigDone = '1') then
rNState <= stIdle;
else
rNState <= stRegAddress_H;
end if;
when stReadBackAddress_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stReadBackAddress_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stReadBackAddress_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stReadBackData_H;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stReadBackData_H =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stReadBackData_L;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stReadBackData_L =>
if (rI2C_Done = '1' and rI2C_Error = '0') then
rNState <= stCheckReadBackError;
elsif (rI2C_Error = '1') then
rNState <= stIdle;
end if;
when stCheckReadBackError =>
if (rReadBackErr = '1') then
rNState <= stIdle;
else
rNState <= stCheckReadBackDone;
end if;
when stCheckReadBackDone =>
if (rReadBackDone = '1') then
rNState <= stIdle;
else
rNState <= stReadBackAddress_H;
end if;
when others =>
rNState <= stIdle;
end case;
end process NextStateDecode;
end Behavioral; |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
data_out : out std_logic_vector(23 downto 0) -- data_out.wire
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNJGR7GQ2L is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJGR7GQ2L;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_cast_GN6OMCQQS7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN6OMCQQS7;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
direction : in std_logic := 'X'; -- wire
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
r : out std_logic_vector(WIDTH-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic (
family : string := "Stratix";
direction : string := "AddAdd";
data3b_const : string := "00000000";
data2b_const : string := "00000000";
representation : string := "SIGNED";
dataWidth : integer := 8;
data4b_const : string := "00000000";
number_multipliers : integer := 2;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 0;
data1b_const : string := "00000000";
use_b_consts : natural := 0
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(17 downto 0); -- wire
user_aclr : in std_logic := 'X'; -- wire
ena : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiply_add_GNKLXFKAO3;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_constant_GNPXZ5JSVR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPXZ5JSVR;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_cast_GN7IAAYCSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7IAAYCSZ;
signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr
signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena
signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr
signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena
signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b
signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion2:input
signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b]
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input]
signal constant5_output_wire : std_logic_vector(3 downto 0); -- Constant5:output -> Barrel_Shifter:distance
signal bus_conversion5_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion5:output -> Multiply_Add:data1a
signal bus_conversion4_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion4:output -> Multiply_Add:data2a
signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data3a
signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a
signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> data_out_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Multiply_Add:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Multiply_Add:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion2 : component alt_dspbuilder_cast_GNJGR7GQ2L
generic map (
round => 0,
saturate => 0
)
port map (
input => barrel_shifter_r_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GN6OMCQQS7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map (
DISTANCE_WIDTH => 4,
NDIRECTION => 1,
SIGNED => 0,
use_dedicated_circuitry => "false",
PIPELINE => 0,
WIDTH => 18
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => multiply_add_result_wire, -- a.wire
r => barrel_shifter_r_wire, -- r.wire
distance => constant5_output_wire, -- distance.wire
ena => barrel_shifterenavcc_output_wire, -- ena.wire
user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire
);
barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => barrel_shifteruser_aclrgnd_output_wire -- output.wire
);
barrel_shifterenavcc : component alt_dspbuilder_vcc_GN
port map (
output => barrel_shifterenavcc_output_wire -- output.wire
);
multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3
generic map (
family => "Cyclone V",
direction => "AddAdd",
data3b_const => "00011110",
data2b_const => "10010110",
representation => "UNSIGNED",
dataWidth => 8,
data4b_const => "01001100",
number_multipliers => 3,
pipeline_register => "NoRegister",
use_dedicated_circuitry => 1,
data1b_const => "01001100",
use_b_consts => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data1a => bus_conversion5_output_wire, -- data1a.wire
data2a => bus_conversion4_output_wire, -- data2a.wire
data3a => bus_conversion3_output_wire, -- data3a.wire
result => multiply_add_result_wire, -- result.wire
user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiply_addenavcc_output_wire -- ena.wire
);
multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiply_adduser_aclrgnd_output_wire -- output.wire
);
multiply_addenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiply_addenavcc_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation1_output_wire, -- input.wire
output => data_out -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNPXZ5JSVR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "1000",
width => 4
)
port map (
output => constant5_output_wire -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_concatenation_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GN7IAAYCSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module
|
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
data_out : out std_logic_vector(23 downto 0) -- data_out.wire
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNJGR7GQ2L is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJGR7GQ2L;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_cast_GN6OMCQQS7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN6OMCQQS7;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
direction : in std_logic := 'X'; -- wire
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
r : out std_logic_vector(WIDTH-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic (
family : string := "Stratix";
direction : string := "AddAdd";
data3b_const : string := "00000000";
data2b_const : string := "00000000";
representation : string := "SIGNED";
dataWidth : integer := 8;
data4b_const : string := "00000000";
number_multipliers : integer := 2;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 0;
data1b_const : string := "00000000";
use_b_consts : natural := 0
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(17 downto 0); -- wire
user_aclr : in std_logic := 'X'; -- wire
ena : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiply_add_GNKLXFKAO3;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_constant_GNPXZ5JSVR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPXZ5JSVR;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_cast_GN7IAAYCSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7IAAYCSZ;
signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr
signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena
signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr
signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena
signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b
signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion2:input
signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b]
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input]
signal constant5_output_wire : std_logic_vector(3 downto 0); -- Constant5:output -> Barrel_Shifter:distance
signal bus_conversion5_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion5:output -> Multiply_Add:data1a
signal bus_conversion4_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion4:output -> Multiply_Add:data2a
signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data3a
signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a
signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> data_out_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Multiply_Add:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Multiply_Add:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion2 : component alt_dspbuilder_cast_GNJGR7GQ2L
generic map (
round => 0,
saturate => 0
)
port map (
input => barrel_shifter_r_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GN6OMCQQS7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map (
DISTANCE_WIDTH => 4,
NDIRECTION => 1,
SIGNED => 0,
use_dedicated_circuitry => "false",
PIPELINE => 0,
WIDTH => 18
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => multiply_add_result_wire, -- a.wire
r => barrel_shifter_r_wire, -- r.wire
distance => constant5_output_wire, -- distance.wire
ena => barrel_shifterenavcc_output_wire, -- ena.wire
user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire
);
barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => barrel_shifteruser_aclrgnd_output_wire -- output.wire
);
barrel_shifterenavcc : component alt_dspbuilder_vcc_GN
port map (
output => barrel_shifterenavcc_output_wire -- output.wire
);
multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3
generic map (
family => "Cyclone V",
direction => "AddAdd",
data3b_const => "00011110",
data2b_const => "10010110",
representation => "UNSIGNED",
dataWidth => 8,
data4b_const => "01001100",
number_multipliers => 3,
pipeline_register => "NoRegister",
use_dedicated_circuitry => 1,
data1b_const => "01001100",
use_b_consts => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data1a => bus_conversion5_output_wire, -- data1a.wire
data2a => bus_conversion4_output_wire, -- data2a.wire
data3a => bus_conversion3_output_wire, -- data3a.wire
result => multiply_add_result_wire, -- result.wire
user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiply_addenavcc_output_wire -- ena.wire
);
multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiply_adduser_aclrgnd_output_wire -- output.wire
);
multiply_addenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiply_addenavcc_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation1_output_wire, -- input.wire
output => data_out -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNPXZ5JSVR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "1000",
width => 4
)
port map (
output => constant5_output_wire -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_concatenation_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GN7IAAYCSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module
|
-------------------------------------------------------------------------------
-- correct_one_bit_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit_64.vhd
--
-- Description: Identifies single bit to correct in 64-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit_64 is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 7));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 7);
DCorr : out std_logic);
end entity Correct_One_Bit_64;
architecture IMP of Correct_One_Bit_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 7)) return natural is
begin -- function find_one
for I in 0 to 7 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 6);
signal lut_corr_val : std_logic_vector(0 to 6);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 7);
lut_corr_val <= Correct_Value(1 to 7);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 6);
lut_corr_val <= Correct_Value(0 to 6);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY b14BCD IS
PORT ( in_bin: IN STD_LOGIC_VECTOR(13 downto 0);
out_migl: OUT STD_LOGIC_VECTOR (3 downto 0);
out_cent: OUT STD_LOGIC_VECTOR (3 downto 0);
out_dec : OUT STD_LOGIC_VECTOR (3 downto 0);
out_unit: OUT STD_LOGIC_VECTOR (3 downto 0));
END b14BCD;
ARCHITECTURE behavior OF b14BCD IS
SIGNAL in_int, migl, cent, dec, unit: integer;
BEGIN
in_int<=TO_INTEGER(UNSIGNED(in_bin));
migl<=in_int/1000;
out_migl<=STD_LOGIC_VECTOR(TO_UNSIGNED((migl), 4));
cent<=(in_int-migl*1000)/100;
out_cent<=STD_LOGIC_VECTOR(TO_UNSIGNED((cent), 4));
dec<=(in_int-migl*1000-cent*100)/10;
out_dec<=STD_LOGIC_VECTOR(TO_UNSIGNED((dec), 4));
unit<=(in_int-migl*1000-cent*100-dec*10);
out_unit<=STD_LOGIC_VECTOR(TO_UNSIGNED((unit), 4));
END behavior; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2408.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02408ent IS
END c07s03b02x00p08n05i02408ent;
ARCHITECTURE c07s03b02x00p08n05i02408arch OF c07s03b02x00p08n05i02408ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
BEGIN
BYTEV1 := BYTE'( others => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '1' );
BYTEV2 := BYTE'( others => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '0' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '1' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '0' ) )
report "***PASSED TEST: c07s03b02x00p08n05i02408"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '1' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '0' ) )
report "***FAILED TEST: c07s03b02x00p08n05i02408 - Others should work well by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02408arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2408.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02408ent IS
END c07s03b02x00p08n05i02408ent;
ARCHITECTURE c07s03b02x00p08n05i02408arch OF c07s03b02x00p08n05i02408ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
BEGIN
BYTEV1 := BYTE'( others => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '1' );
BYTEV2 := BYTE'( others => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '0' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '1' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '0' ) )
report "***PASSED TEST: c07s03b02x00p08n05i02408"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '1' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '0' ) )
report "***FAILED TEST: c07s03b02x00p08n05i02408 - Others should work well by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02408arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2408.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02408ent IS
END c07s03b02x00p08n05i02408ent;
ARCHITECTURE c07s03b02x00p08n05i02408arch OF c07s03b02x00p08n05i02408ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV1 : BYTE;
variable BYTEV2 : BYTE;
BEGIN
BYTEV1 := BYTE'( others => '1' );
assert( BYTEV1( 0 ) = '1' );
assert( BYTEV1( 1 ) = '1' );
assert( BYTEV1( 2 ) = '1' );
assert( BYTEV1( 3 ) = '1' );
assert( BYTEV1( 4 ) = '1' );
assert( BYTEV1( 5 ) = '1' );
assert( BYTEV1( 6 ) = '1' );
assert( BYTEV1( 7 ) = '1' );
BYTEV2 := BYTE'( others => '0' );
assert( BYTEV2( 0 ) = '0' );
assert( BYTEV2( 1 ) = '0' );
assert( BYTEV2( 2 ) = '0' );
assert( BYTEV2( 3 ) = '0' );
assert( BYTEV2( 4 ) = '0' );
assert( BYTEV2( 5 ) = '0' );
assert( BYTEV2( 6 ) = '0' );
assert( BYTEV2( 7 ) = '0' );
wait for 5 ns;
assert NOT( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '1' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '0' ) )
report "***PASSED TEST: c07s03b02x00p08n05i02408"
severity NOTE;
assert ( ( BYTEV1( 0 ) = '1' ) and
( BYTEV1( 1 ) = '1' ) and
( BYTEV1( 2 ) = '1' ) and
( BYTEV1( 3 ) = '1' ) and
( BYTEV1( 4 ) = '1' ) and
( BYTEV1( 5 ) = '1' ) and
( BYTEV1( 6 ) = '1' ) and
( BYTEV1( 7 ) = '1' ) and
( BYTEV2( 0 ) = '0' ) and
( BYTEV2( 1 ) = '0' ) and
( BYTEV2( 2 ) = '0' ) and
( BYTEV2( 3 ) = '0' ) and
( BYTEV2( 4 ) = '0' ) and
( BYTEV2( 5 ) = '0' ) and
( BYTEV2( 6 ) = '0' ) and
( BYTEV2( 7 ) = '0' ) )
report "***FAILED TEST: c07s03b02x00p08n05i02408 - Others should work well by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02408arch;
|
-- Testbench for the Polyphase_SSB module
--
-- Original authors Diego Riste and Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity PolyphaseSSB_tb is
end;
architecture bench of PolyphaseSSB_tb is
signal clk, clk_oserdes: std_logic := '0';
signal reset: std_logic := '0';
constant CLK_PERIOD : time := 4ns;
constant CLK_OSERDES_PERIOD : time := 2ns;
constant IN_DATA_WIDTH : natural := 14;
constant OUT_DATA_WIDTH : natural := 14;
constant OUT_DATA_SCALE : integer := 2**(OUT_DATA_WIDTH-1)-1;
signal wfm_in_re : std_logic_vector(4*IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal wfm_in_im : std_logic_vector(4*IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal phinc : std_logic_vector(23 downto 0) := (others => '0');
signal phoff : std_logic_vector(23 downto 0) := (others => '0');
signal wfm_out_re : std_logic_vector(4*OUT_DATA_WIDTH-1 downto 0);
signal wfm_out_im : std_logic_vector(4*OUT_DATA_WIDTH-1 downto 0);
signal wfm_out_vld : std_logic := '0';
signal wfm_oserdes_re, wfm_oserdes_im : std_logic_vector(OUT_DATA_WIDTH-1 downto 0);
--define different stages for testbench, corresponding to different SSB parameters
type TESTBENCH_STATE_t is (RESETTING, BASEBAND_RAMP_RE, BASEBAND_PH_SHIFT, SSB_ON, SSB_PH_SHIFT, MAX_RANGE, DONE);
signal testbench_state : TESTBENCH_STATE_t;
signal stop_the_clocks : boolean := false;
signal checking_finished : boolean := false;
begin
uut: entity work.PolyphaseSSB
generic map (
IN_DATA_WIDTH => IN_DATA_WIDTH,
OUT_DATA_WIDTH => OUT_DATA_WIDTH
)
port map (
clk => clk,
rst => reset,
phase_increment => phinc,
phase_offset => phoff,
waveform_in_re => wfm_in_re,
waveform_in_im => wfm_in_im,
waveform_out_re => wfm_out_re,
waveform_out_im => wfm_out_im,
out_vld => wfm_out_vld
);
oserdes_re: entity work.FakeOSERDES
generic map (
SAMPLE_WIDTH => OUT_DATA_WIDTH,
CLK_PERIOD => CLK_OSERDES_PERIOD
)
port map (
clk_in => clk_oserdes,
reset => reset,
data_in => wfm_out_re,
data_out => wfm_oserdes_re
);
oserdes_im: entity work.FakeOSERDES
generic map (
SAMPLE_WIDTH => OUT_DATA_WIDTH,
CLK_PERIOD => CLK_OSERDES_PERIOD
)
port map (
clk_in => clk_oserdes,
reset => reset,
data_in => wfm_out_im,
data_out => wfm_oserdes_im
);
clk <= not clk after CLK_PERIOD/2 when not stop_the_clocks;
clk_oserdes <= not clk_oserdes after CLK_OSERDES_PERIOD/2 when not stop_the_clocks;
stimulus: process
constant MAX_INPUT : std_logic_vector(4*IN_DATA_WIDTH-1 downto 0) :=
std_logic_vector(to_signed(2**(IN_DATA_WIDTH-1)-1, IN_DATA_WIDTH))
& std_logic_vector(to_signed(2**(IN_DATA_WIDTH-1)-1, IN_DATA_WIDTH))
& std_logic_vector(to_signed(2**(IN_DATA_WIDTH-1)-1, IN_DATA_WIDTH))
& std_logic_vector(to_signed(2**(IN_DATA_WIDTH-1)-1, IN_DATA_WIDTH));
begin
--Resetting
testbench_state <= RESETTING;
reset <= '1';
wait for 100ns;
reset <= '0';
wait for 20ns;
wait until rising_edge(clk);
--clk in baseband ramp on real axis
testbench_state <= BASEBAND_RAMP_RE;
for i in -2048 to 2047 loop
--ramp from min to max
wfm_in_re <= std_logic_vector(to_signed(4*i+3, IN_DATA_WIDTH))
& std_logic_vector(to_signed(4*i+2, IN_DATA_WIDTH))
& std_logic_vector(to_signed(4*i+1, IN_DATA_WIDTH))
& std_logic_vector(to_signed(4*i, IN_DATA_WIDTH));
wait until rising_edge(clk);
end loop ;
testbench_state <= BASEBAND_PH_SHIFT;
--set I quadrature to max
wfm_in_re <= MAX_INPUT;
--shift phase by pi/2 (2^22, 1/4 circle)
phoff <= std_logic_vector(to_unsigned(2**22, 24));
wait for 1 us;
testbench_state <= SSB_ON;
phoff <= (others => '0');
--turn on SSB mod., (2^24, 1/100 clk)
phinc <= std_logic_vector(to_unsigned((2**24)/64, 24));
wait for 10 us;
testbench_state <= SSB_PH_SHIFT;
--shift phase by pi/2
phoff <= std_logic_vector(to_unsigned(2**22, 24));
wait for 10 us;
testbench_state <= MAX_RANGE;
--set I and Q quadratures to max
wfm_in_re <= MAX_INPUT;
wfm_in_im <= MAX_INPUT;
wait for 10 us;
testbench_state <= DONE;
wait for 100ns;
assert checking_finished report "Checking process failed to finish!";
stop_the_clocks <= true;
wait;
end process;
check : process
variable ind : integer := 0;
variable wfm_check_re : signed(OUT_DATA_WIDTH-1 downto 0);
variable wfm_check_im : signed(OUT_DATA_WIDTH-1 downto 0);
variable slice_re : signed(OUT_DATA_WIDTH-1 downto 0);
variable slice_im : signed(OUT_DATA_WIDTH-1 downto 0);
begin
--sync. with wfm_out_xx
wait until testbench_state = BASEBAND_RAMP_RE;
wait until rising_edge(clk) and wfm_out_re /= std_logic_vector(to_signed(0, wfm_out_re'length));
for ct in -2048 to 2047 loop
--ramp amplitude
for ct2 in 0 to 3 loop
wfm_check_re := to_signed(2**(OUT_DATA_WIDTH-IN_DATA_WIDTH)*(4*ct + ct2), OUT_DATA_WIDTH);
--Arbitrarly allow difference of 2 due to fixed point errors
slice_re := signed(wfm_out_re((ct2+1)*OUT_DATA_WIDTH-1 downto ct2*OUT_DATA_WIDTH));
slice_im := signed(wfm_out_im((ct2+1)*OUT_DATA_WIDTH-1 downto ct2*OUT_DATA_WIDTH));
assert abs(wfm_check_re - slice_re) <= 2 report "real output wrong in BASEBAND_RAMP_RE! expected " & integer'image(to_integer(wfm_check_re)) & " but got " & integer'image(to_integer(slice_re)) ;
assert abs(slice_im) <= 2 report "imag output wrong in BASEBAND_RAMP_RE! expected " & integer'image(to_integer(wfm_check_im)) & " but got " & integer'image(to_integer(slice_im)) ;
end loop;
wait until rising_edge(clk);
end loop ;
report "Finished checking BASEBAND_RAMP_RE";
wait until rising_edge(clk) and testbench_state = BASEBAND_PH_SHIFT;
--wait until DDS is valid (4 cycles) and multiplier pipeline delay (4 cycles)
--already well into delay from above
for ct in 0 to 3 loop
wait until rising_edge(clk);
end loop;
--shift phase by pi/2
wfm_check_im := to_signed(OUT_DATA_SCALE, OUT_DATA_WIDTH);
wfm_check_re := (others => '0');
assert abs(wfm_check_re - signed(wfm_oserdes_re)) <= 2 report "real output wrong in BASEBAND_PH_SHIFT!";
assert abs(wfm_check_im - signed(wfm_oserdes_im)) <= 2 report "imag output wrong in BASEBAND_PH_SHIFT!";
report "Finished checking BASEBAND_PH_SHIFT";
wait until rising_edge(clk) and testbench_state = SSB_ON;
--wait until DDS is valid (4 cycles) and multiplier pipeline delay (4 cycles)
for ct in 0 to 8 loop
wait until rising_edge(clk);
end loop ;
ind := 3;
while testbench_state /= SSB_PH_SHIFT loop
for ct2 in 0 to 3 loop
ind := ind+1;
wfm_check_re := to_signed(integer(cos(2.0*MATH_PI*0.25*(1.0/64)*real(ind))*real(OUT_DATA_SCALE)), OUT_DATA_WIDTH);
wfm_check_im := to_signed(integer(sin(2.0*MATH_PI*0.25*(1.0/64)*real(ind))*real(OUT_DATA_SCALE)), OUT_DATA_WIDTH);
--Arbitrarly allow differences of 4 due to fixed point errors
slice_re := signed(wfm_out_re((ct2+1)*OUT_DATA_WIDTH-1 downto ct2*OUT_DATA_WIDTH));
slice_im := signed(wfm_out_im((ct2+1)*OUT_DATA_WIDTH-1 downto ct2*OUT_DATA_WIDTH));
assert abs(wfm_check_re - slice_re) <= 4 report "real output wrong in SSB_ON! expected " & integer'image(to_integer(wfm_check_re)) & " but got " & integer'image(to_integer(slice_re)) ;
assert abs(wfm_check_im - slice_im) <= 4 report "imag output wrong in SSB_ON! expected " & integer'image(to_integer(wfm_check_im)) & " but got " & integer'image(to_integer(slice_im)) ;
end loop;
wait until rising_edge(clk);
end loop;
report "Finished checking SSB_ON";
--wait until DDS is valid (4 cycles) and multiplier pipeline delay (4 cycles)
for ct in 0 to 8 loop
wait until rising_edge(clk);
ind := ind + 4;
end loop;
while testbench_state /= MAX_RANGE loop
for ct2 in 0 to 3 loop
ind := ind+1;
--cos(2pi * freq * time); freq and time are in timestep units; freq is 1/4 because of 4 wide samples
wfm_check_re := to_signed(integer(cos(2.0*MATH_PI*0.25*(1.0/64)*real(ind) + MATH_PI/2.0)*real(OUT_DATA_SCALE)), OUT_DATA_WIDTH);
wfm_check_im := to_signed(integer(sin(2.0*MATH_PI*0.25*(1.0/64)*real(ind) + MATH_PI/2.0)*real(OUT_DATA_SCALE)), OUT_DATA_WIDTH);
--Arbitrarly allow difference of 4 due to fixed point errors
slice_re := signed(wfm_out_re((ct2+1)*OUT_DATA_WIDTH-1 downto ct2*OUT_DATA_WIDTH));
slice_im := signed(wfm_out_im((ct2+1)*OUT_DATA_WIDTH-1 downto ct2*OUT_DATA_WIDTH));
assert abs(wfm_check_re - slice_re) <= 4 report "real output wrong in SSB_PH_SHIFT! expected " & integer'image(to_integer(wfm_check_re)) & " but got " & integer'image(to_integer(slice_re)) ;
assert abs(wfm_check_im - slice_im) <= 4 report "imag output wrong in SSB_PH_SHIFT! expected " & integer'image(to_integer(wfm_check_im)) & " but got " & integer'image(to_integer(slice_im)) ;
end loop;
wait until rising_edge(clk);
end loop;
report "Finished checking SSB_PH_SHIFT";
checking_finished <= true;
wait;
end process ;
end;
|
--
-- Parameterisable N to M mux.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use IEEE.numeric_std.all;
entity ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : in STD_LOGIC; --signal to all components to go into their init state
Start : In Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Done : Out Std_logic;
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end ParamExp;
architecture RTL of ParamExp is
type MEM is array (0 to 7) of sfixed(BIT_TOP downto BIT_BOTTOM);
signal ISPOSITIVE : STD_LOGIC := '0';
signal ISGREATERTHANONE : STD_LOGIC := '0';
signal X_integer : sfixed(BIT_TOP downto 0);
signal X_fraction : sfixed(0 downto BIT_BOTTOM);
signal Output_int : sfixed(BIT_TOP downto BIT_BOTTOM);
signal Done_int : Std_logic;
signal output_fraction : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_fraction_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal current_term : sfixed(BIT_TOP downto BIT_BOTTOM);
signal current_term_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal COUNT_FRACTION : unsigned(3 downto 0);
signal COUNT_FRACTION_next : unsigned(3 downto 0);
signal DONEFRACTION : STD_LOGIC := '0';
signal DONEFRACTION_next : STD_LOGIC := '0';
signal output_integer : sfixed(BIT_TOP downto BIT_BOTTOM);
signal output_integer_next : sfixed(BIT_TOP downto BIT_BOTTOM);
signal COUNT_INTEGER : unsigned(BIT_TOP+1 downto 0);
signal COUNT_INTEGER_next : unsigned(BIT_TOP+1 downto 0);
signal DONEINTEGER : STD_LOGIC := '0';
signal DONEINTEGER_next : STD_LOGIC := '0';
signal E : sfixed(BIT_TOP downto BIT_BOTTOM) := to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM);
signal EInv : sfixed(BIT_TOP downto BIT_BOTTOM) := resize(reciprocal(to_sfixed(2.71828182845904523536028747135266249775724709369995,BIT_TOP,BIT_BOTTOM)),BIT_TOP,BIT_BOTTOM);
signal EMul : sfixed(BIT_TOP downto BIT_BOTTOM);
signal n1: sfixed (BIT_TOP downto 0);
signal n2: sfixed (n1'high + 1 downto n1'low);
signal n3: ufixed (BIT_TOP + 1 downto 0);
begin
splitUpXProcess: process(X,X_integer,ispositive,E,EInv)
begin
X_integer <= resize(abs(X) - 0.5,BIT_TOP,0);
X_fraction <= resize(abs(X) - X_integer,0,BIT_BOTTOM);
if To_slv ( resize ( X ,BIT_TOP,BIT_BOTTOM))(BIT_TOP-BIT_BOTTOM) = '0' then
ISPOSITIVE <= '1';
else
ISPOSITIVE <= '0';
end if;
if (ISPOSITIVE = '1') then
EMul <= E;
else
EMul <= EInv;
end if;
end process splitUpXProcess;
fractionCombProcess: process(COUNT_FRACTION,Start,output_fraction,current_term,X_fraction,ISPOSITIVE,current_term_next,init_model)
variable MEM8Xsfixed : MEM := (to_sfixed (1,BIT_TOP, BIT_BOTTOM),to_sfixed (0.5,BIT_TOP, BIT_BOTTOM),to_sfixed (0.33333333,BIT_TOP, BIT_BOTTOM),to_sfixed (0.25,BIT_TOP, BIT_BOTTOM),
to_sfixed (0.2,BIT_TOP, BIT_BOTTOM),to_sfixed (0.16666666667,BIT_TOP, BIT_BOTTOM),to_sfixed (0.142857142857,BIT_TOP, BIT_BOTTOM),to_sfixed (0.125,BIT_TOP, BIT_BOTTOM));
begin
output_fraction_next <= output_fraction;
COUNT_FRACTION_next <= COUNT_FRACTION;
current_term_next <= current_term;
DONEFRACTION_next <= '0';
current_term_next <= resize(MEM8Xsfixed(to_integer(unsigned(COUNT_FRACTION(2 downto 0)))) *
resize(X_fraction * current_term,BIT_TOP, BIT_BOTTOM),BIT_TOP, BIT_BOTTOM);
if init_model = '1' then
DONEFRACTION_next <= '1';
COUNT_FRACTION_next <= "1001";
output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if Start = '1' then
DONEFRACTION_next <= '0';
COUNT_FRACTION_next <= "0000";
output_fraction_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
current_term_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
elsif COUNT_FRACTION = "1001" then
DONEFRACTION_next <= '1';
current_term_next <= current_term;
else
DONEFRACTION_next <= '0';
if (ISPOSITIVE = '1') then
output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM);
else
if (COUNT_FRACTION(0) = '0') then
output_fraction_next <= resize(output_fraction - current_term_next,BIT_TOP, BIT_BOTTOM);
else
output_fraction_next <= resize(output_fraction + current_term_next,BIT_TOP, BIT_BOTTOM);
end if;
end if;
COUNT_FRACTION_next <= COUNT_FRACTION + 1;
end if;
end if;
end process fractionCombProcess;
fractionSynProcess: process(clk)
variable Sel : integer;
begin
if clk'event and clk = '1' then
output_fraction <= output_fraction_next;
COUNT_FRACTION <= COUNT_FRACTION_next;
current_term <= current_term_next;
DONEFRACTION <= DONEFRACTION_next;
--report "The value of output_fraction = " & real'image(to_real(output_fraction)) & " and current_term " &
-- real'image(to_real(current_term));
end if;
end process fractionSynProcess;
integerCombProcess: process(COUNT_INTEGER,output_integer,x_integer,Start,EMul,init_model)
begin
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= COUNT_INTEGER;
output_integer_next <= output_integer;
if init_model = '1' then
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= to_unsigned(0,COUNT_INTEGER_next'length);
output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if Start = '1' then
DONEINTEGER_next <= '0';
COUNT_INTEGER_next <= unsigned(ufixed(abs(X_integer)));
output_integer_next <= to_sfixed (1,BIT_TOP, BIT_BOTTOM);
else
if COUNT_INTEGER = 0 then
DONEINTEGER_next <= '1';
COUNT_INTEGER_next <= COUNT_INTEGER;
output_integer_next <= output_integer;
else
DONEINTEGER_next <= '0';
output_integer_next <= resize(output_integer * EMul,BIT_TOP,BIT_BOTTOM);
COUNT_INTEGER_next <= COUNT_INTEGER - 1;
end if;
end if;
end if;
end process integerCombProcess;
integerSynProcess: process(clk,x_integer,count_integer,output_integer)
begin
COUNT_INTEGER <= COUNT_INTEGER;
output_integer <= output_integer;
if clk = '1' and clk'event then
COUNT_INTEGER <= COUNT_INTEGER_next;
output_integer <= output_integer_next;
DONEINTEGER <= DONEINTEGER_next;
end if;
end process integerSynProcess;
outputCombProcess: process(output_fraction,output_integer,DONEINTEGER,DONEFRACTION)
begin
Output_int <= resize(output_fraction * output_integer,BIT_TOP, BIT_BOTTOM);
if DONEFRACTION = '1' and DONEINTEGER = '1' then
Done_int <= '1';
else
Done_int <= '0';
end if;
end process outputCombProcess;
Done <= Done_int;
Output <= Output_int;
--process (DONEFRACTION)
--begin
-- if (DONEFRACTION'event or DONEINTEGER'event) and DONEFRACTION = '1' and DONEINTEGER = '1' then
-- report "The value of X_integer = " & real'image(to_real(X_integer)) & " and X_fraction " & real'image(to_real(X_fraction));
-- report "The value of exp( " & real'image(to_real(X)) & " ) = " &
-- real'image(to_real(output_integer)) & " * " & real'image(to_real(output_fraction));
-- end if;
--end process;
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2956.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02956ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
--- Failure_here
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end;
END c02s02b00x00p02n01i02956ent;
ARCHITECTURE c02s02b00x00p02n01i02956arch OF c02s02b00x00p02n01i02956ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02956 - Missing keyword begin."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02956arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2956.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02956ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
--- Failure_here
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end;
END c02s02b00x00p02n01i02956ent;
ARCHITECTURE c02s02b00x00p02n01i02956arch OF c02s02b00x00p02n01i02956ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02956 - Missing keyword begin."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02956arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2956.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02956ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
--- Failure_here
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end;
END c02s02b00x00p02n01i02956ent;
ARCHITECTURE c02s02b00x00p02n01i02956arch OF c02s02b00x00p02n01i02956ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02956 - Missing keyword begin."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02956arch;
|
library ieee;
use ieee.float_pkg.all;
entity tb_test is
generic (
runner_cfg : string := "h");
end tb_test;
architecture tb of tb_test is
begin
test_runner : process
-- Makes the implicit "=" directly visible.
alias fp32 is float32;
begin
assert not (zerofp = neg_zerofp) severity failure;
wait;
end process test_runner;
test_runner2 : process
-- Only the user-defined "=" is visible.
begin
assert zerofp = neg_zerofp severity failure;
wait;
end process test_runner2;
end;
|
library ieee;
use ieee.float_pkg.all;
entity tb_test is
generic (
runner_cfg : string := "h");
end tb_test;
architecture tb of tb_test is
begin
test_runner : process
-- Makes the implicit "=" directly visible.
alias fp32 is float32;
begin
assert not (zerofp = neg_zerofp) severity failure;
wait;
end process test_runner;
test_runner2 : process
-- Only the user-defined "=" is visible.
begin
assert zerofp = neg_zerofp severity failure;
wait;
end process test_runner2;
end;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus is
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
-- NEED RESULT: ARCH00011: Unassociated scalar generics with globally static subtype take on default expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00011
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00011)
-- ENT00011_Test_Bench(ARCH00011_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00011 of GENERIC_STANDARD_TYPES is
begin
L1 :
block
generic (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
test_report ( "ARCH00011" ,
"Unassociated scalar generics with globally static subtype" &
" take on default expression" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00011 ;
--
entity ENT00011_Test_Bench is
end ENT00011_Test_Bench ;
--
architecture ARCH00011_Test_Bench of ENT00011_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00011 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00011_Test_Bench ;
|
package pack1 is
type t is (foo, bar, baz);
alias a is t;
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
package pack2 is
constant k : t := foo; -- OK
procedure test1;
end package;
package body pack2 is
function height (height : integer) return integer is
begin
return height * 2;
end function;
procedure test1 is
begin
assert height ( height => 1 ) = 2; -- OK
end procedure;
end package body;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE05";
when 16#00069# => romdata <= X"8410A25F";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"05248820";
when 16#00077# => romdata <= X"8410A3CD";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE05";
when 16#00069# => romdata <= X"8410A25F";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"05248820";
when 16#00077# => romdata <= X"8410A3CD";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000080";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
type chars is (A, B, C);
type char_counts is array (chars) of integer;
type two_d is array (1 to 3, 4 to 6) of integer;
type ab_chars is array (chars range A to B) of integer;
end package;
architecture a of e is
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
signal c : char_counts;
signal t : two_d;
signal u : ten_ints := ( 1 | 2 | 3 => 4, others => 2);
signal v : ten_ints := ( 1 ! 2 ! 3 => 4, others => 2);
begin
process is
begin
x(0) <= 1;
y(2) <= n(2);
y(3)(5) <= n(2)(1);
x(1 to 3) <= z(1 to 3);
a := (x'range => 5);
a := (x'reverse_range => 3);
end process;
end architecture;
|
package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
type chars is (A, B, C);
type char_counts is array (chars) of integer;
type two_d is array (1 to 3, 4 to 6) of integer;
type ab_chars is array (chars range A to B) of integer;
end package;
architecture a of e is
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
signal c : char_counts;
signal t : two_d;
signal u : ten_ints := ( 1 | 2 | 3 => 4, others => 2);
signal v : ten_ints := ( 1 ! 2 ! 3 => 4, others => 2);
begin
process is
begin
x(0) <= 1;
y(2) <= n(2);
y(3)(5) <= n(2)(1);
x(1 to 3) <= z(1 to 3);
a := (x'range => 5);
a := (x'reverse_range => 3);
end process;
end architecture;
|
package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
type chars is (A, B, C);
type char_counts is array (chars) of integer;
type two_d is array (1 to 3, 4 to 6) of integer;
type ab_chars is array (chars range A to B) of integer;
end package;
architecture a of e is
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
signal c : char_counts;
signal t : two_d;
signal u : ten_ints := ( 1 | 2 | 3 => 4, others => 2);
signal v : ten_ints := ( 1 ! 2 ! 3 => 4, others => 2);
begin
process is
begin
x(0) <= 1;
y(2) <= n(2);
y(3)(5) <= n(2)(1);
x(1 to 3) <= z(1 to 3);
a := (x'range => 5);
a := (x'reverse_range => 3);
end process;
end architecture;
|
package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
type chars is (A, B, C);
type char_counts is array (chars) of integer;
type two_d is array (1 to 3, 4 to 6) of integer;
type ab_chars is array (chars range A to B) of integer;
end package;
architecture a of e is
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
signal c : char_counts;
signal t : two_d;
signal u : ten_ints := ( 1 | 2 | 3 => 4, others => 2);
signal v : ten_ints := ( 1 ! 2 ! 3 => 4, others => 2);
begin
process is
begin
x(0) <= 1;
y(2) <= n(2);
y(3)(5) <= n(2)(1);
x(1 to 3) <= z(1 to 3);
a := (x'range => 5);
a := (x'reverse_range => 3);
end process;
end architecture;
|
-- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming strb is left high between accesses)
-- set port low bits to input
-- set RmW, strb to 1, 0 (10 = command "read low-nibble")
-- read the value of b3..b0
-- set strb 1 (11 = command "read high-nibble)
-- read the value of b7..b4 in the low bits of the data you read.
-- for multi-byte reads, repeat last four steps
-- Note: always read the low nibble first, because the high nibble is latched at the same time
-- make sure you wait at least three cycles between writes and reads:
-- OUT <port>, <regA>
-- ORI <regA>, 0x10 // take the opportunity to set up next out value
-- NOP
-- IN <regB>, <port> // read the low nibble
-- OUT <port>, <regA> // set up hi nibble read
-- ANDI <regB>, 0x0F // extract low nibble
-- ANDI <regA>, 0xEF // take the opportunity to set up next out value
-- IN <regC>, <port> // read the high nibble
-- ANDI <regC>, 0x0F
-- SWAP
-- OR <RegC>, <RegB> // build the byte
-- <store it>
-- <check for more data available, then loop>
-- this code should be able to input about one byte/microsecond with 16MHz processor.
-- to write this peripheral:
-- (assuming strb is left high between accesses)
-- set RnW to 0 (strb no change, so no write yet; output buffers now disabled)
-- set port low bits to output
-- write the lo-nibble value, with b5, b4 = 00
-- write the hi-nibble value, with b5, b4 = 01
-- for multi-byte writes, repeat last two steps
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity arduinointerface is
port (
-- arduino pins
data: inout Std_Logic_Vector (3 downto 0);
strb: in Std_Logic;
RnW: in Std_Logic;
clk: in Std_Logic;
rst: in Std_Logic;
-- io pins
rd, wr: out Std_Logic := '0';
q: out Std_Logic_Vector (7 downto 0);
i: in Std_Logic_Vector (7 downto 0)
);
end arduinointerface;
architecture behavioural of arduinointerface is
signal RnWin : Std_Logic_Vector (2 downto 0); -- metastability chain -> shifting down (low bit is "last" value)
signal strbin : Std_Logic_Vector (2 downto 0); -- metastability chain -> shifting down (low bit is "last" value)
signal dout : Std_Logic_Vector (3 downto 0); -- latch for high nibble when low nibble is read
begin
process (clk, strb, RnW, rst)
begin
if rst = '1' then
wr <= '0';
rd <= '0';
RnWin <= (others => '0');
strbin <= (others => '0');
q <= (others => '0');
dout <= (others => '0');
elsif rising_edge(clk) then
-- strobes output for use by peripheral, indicating a read or write has taken place.
wr <= (strbin(1) and not strbin(0)) and not RnWin(1); -- positive-going write pulse edge generated when second nibble written
rd <= (strbin(1) and not strbin(0)) and RnWin(1); -- poistive-going read pulse generated when host requests second nibble
-- shift the metastability chains down
RnWin <= RnW & RnWin (RnWin'length-1 downto 1);
strbin <= strb & strbin (strbin'length-1 downto 1);
-- deal with strobe events
if strbin(1) /= strbin(0) then -- we have a strobe event
if RnWin(1) = '0' then -- we are being written
if strbin(1) = '1' then -- latch the high nibble
q(7 downto 4) <= data;
else -- latch the low nibble
q(3 downto 0) <= data;
end if;
else
if strbin(1) = '0' then -- we're reading the low nibble, so...
dout <= i(7 downto 4); -- ... latch the high nibble at the same time
end if;
end if;
end if;
end if;
end process;
tristate : process (RnWin(1), strbin(1), data) -- Behavioral representation of tri-states.
begin -- pattern from http://www.altera.co.uk/support/examples/vhdl/v_bidir.html
if RnWin(1) = '1' then -- we are being read
if strbin(1) = '0' then -- read the low nibble
data <= i(3 downto 0);
else -- read the high nibble
data <= dout;
end if;
else -- we are being written
data <= "ZZZZ";
end if;
end process;
end behavioural; |
package pkg1 is
generic (type t; c : t);
generic map (t => natural, c => 5);
function f return t;
end pkg1;
package body pkg1 is
function f return t is
begin
return c;
end f;
end pkg1;
entity tb is
end tb;
architecture behav of tb is
begin
assert work.pkg1.f = 5;
end behav;
|
package pkg1 is
generic (type t; c : t);
generic map (t => natural, c => 5);
function f return t;
end pkg1;
package body pkg1 is
function f return t is
begin
return c;
end f;
end pkg1;
entity tb is
end tb;
architecture behav of tb is
begin
assert work.pkg1.f = 5;
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
G8f1gqSMQCnQAMasovp609G+Xtml3VQEkPOLMPqVhr1MIayxmJvmZ4o3wKbACMMSFBE4+TcLKolU
Lw320DyaNQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Ug2hg9EpJHXCwIW/al+lR0FQjskKd87pvEXs/ZrL+skznkgUSgLQmC7SJ1oq3QiIqqkep7bUmCVy
we8veKFtu8UfykilTmrnjhTRdAyMYPoc3U6Xbx5Lq7rKnI/dAU/tITqfnX/1RQy97jQ/SOLgi6Dx
Yo7ZJsrm1WJdM+ksPHo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WHtDk6ccWwa0v84+eT11XdXj5G/EYMvPkJ4c5ahUoFGrSqd4gCHCAiolaFpA/e9DhneCRB1la9T/
pcL5IfFfIGM3uNKFFSit1QvzldlM9fpLEMG1OdKNnCRVWp69DgncRuK0JLBlQrlzmwFPjSPfCkyT
SEkKYrcZY2nTdIQ5SLbgqmjNzBcF93ZKwLjze8ccIl9IKNsMpuM1vjvfRM1mgbHdq3Ml+paIzHV0
xzVAzQV7PIanAnzCPVohQpY7U6lCMXZhdciaVjLnPU5sGZdsbkX6VOlL2+/1RPeyueXcWdtS++rj
2qxFe0Bc7E82KYYoGLqRi7Kb8S75TETIsjFkDw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hN3ysJNjoyNBp70dJlaVUOhqqcr2mzYQ/HE9e1MilSDPcz/jN0bqHs9I5KLnIRDQVc/IjMTf1Hvs
CXBTyaSSTFYhpbstaj7kuVfj+BSQj315KjRV1WRKrqyjaqC3oomV+UaFLj2hd/eYIDHnlBcZI0Xf
jKHWzWg0zMrOnchT9Co=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UsVeqgYjuMLz0rai2LA/hZgwQYWVqJGgjFEXQzv9Y+00hP0ur0N5wKZ9COZQf5vaZTwTyOuPtLrX
SZ1NivgvLjstd7l/BODfmRL2canlzh9O8ND44uYj8try0D9PZpZwdkT2+zPnuHOxwOFn6VpPXRDB
8FQLsnOO9RcGzwbgafC0XYO0L5v9yMpxHheu0CqhuQIESPCXp9hByn29OUbPWz+JzoxZM9/hX70F
Rt4HIj6Pw8i0zqLHF3yApqbjUxE3z9pw9XF12lIjbLj5J13qY7Nvp8M071o7YEVT56vnb1d2sbU4
7FN2+vPsLWjaWsmIWAB5eBk4jEavWlXcqmKlbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10688)
`protect data_block
HHsQld+/7Dz+EiOmk7gLHdNnjCBw31fY64ZvJOKWIqDx/80No14YTTrE1li9v7pnl+KQvGfUcjW2
KQ3j8+Z+QrBfcojaRRbqgsCEN3VXRR8tvvJg3gcd4+Y2du3PNsza9nEQm5fgWLCRAPrEQtqCAfaf
1RcYBqDQ4CVO87+eW/usEHoDNO35oggBpqLI8bAWJHDvhbRedL2vHU7SFbYM7TLBwgo7oxWIX0Pw
wpE/ONYAPpOEAiSlWIfWQLpzZcEEESBsuJNhcl5suVc5wloVCby/5SKhpwpeJOHFCWoKuHhz5dwC
Vqk3GomybRHbEMPIpg9px+tMBZSIFHTq0nmcsUOJbjE0MUh1xpQfWq6UbIvdtz3SUzWz39h4gmP+
zdCGa+3TmEI1GILj9hgg2eDoRuVcg9ZnMvKkf4UU8Vwu9s3hSxdTbt0AbKo0tCsVSUDRAkOkSGZP
Otgd9r9Q2foNREaPP528cIf6ZTPBiqjZ9NsgoFY4bqcBRYACy7YPzQiIniRKFa+mGsU4oWzbmbZ2
WFhIhRE6ugan4H1fxkfxLoSYLzTx/az2dPiI1hfRt1OdDuPDdisrSt0kPcvTQwZWLcchem2WcDTy
G1qrLH7Z3hx5I5UJ1bTgb2NWq8c807i9U3t6vawpfKHA45/WXrxJkuK4Bse7GGYJKiOgin4O1nlr
Grjw6zqc65NzRwwKG4C6DYtBYVg5muz6wmTqTSrOT5OQFX+I3ozS/jUNfhgd1zbF/ojhvdgr2k98
OhMngpmBlOvXPU/CWBqR4MEeMzUd+GsXhqV7W5kdEruzBx7x6nFj0I8optuwkG/HdW+Au6trrqm0
TZljCLVx9FCtbMVnfkVTN2nBr+d1GaZnLeXCb55HvgYJxlqsbcG399YHChCBKBny0KPB6uikWVl6
4f+r+6H+MBkywYQ6/tFr1dPPBW6bOAnXeA6W8xYv+VCVdE5y6rlGkBVoXaZnqxzrNRi0IVb5QoE8
gYygUxtz4QTVM40Is6HUF5lR2o/rcDgQZrmfNHu51W28mbOkob6ehToUPcDhhUsdgCmJt6C9oqC/
2XkfBG931GBN13y+k8P1XEgnczCqOftH/JFfdqqA4h6Ysc1dk4FtRXe+jHmYdKQ5nmTcVL5GqLQo
2AkYkLh/RXXGKiyRgOVX4JLM/J7mbWQsK/SwzzBdPF8jLrOZMHA7fF3J6OsjhxMSmAwvg5BjS1Kr
yw1mfi/ooPuf9FFmxjOoiubyr2JTdIJOcCzSpmpZg/RxmaIyRfdWv2DZvPfxjrkuc/1JO/QAjfzo
qnyb4Dk8tIpik+BXtjejsYh2xm+f2BK9O0V7ta031oDhhcdcSI/8CxF8qY5Wub9Vg4hJyUZp/xS8
+ORO1s63FdHiWGNBI1vJzn2uDXY4EKTvJfZk69nh3AgIk2n95FSP+0O3oFnQTGWNGzGRbAsqUF2C
mmBgF/Y+eZgjn4fwQ5+KOcyOYHiQL732ic6FSfzN/+xOBNrgPsfsuL16FOe861RgKLhKx2wl+c2t
IW0OzFWCgV6SbZorsG9A/c++IEGwK/10qU8GVKdtKoLSDNVmWLikF4OaV7B0SryF3DGRgJuDHnWH
m1RE7rvqbwRLbO6KLN+Y4cEpmuO10GP0iHRaeKK7G5p0t/gGgpahlS5PafntE6wfKyra1i32EleC
oui5JjAZ/3dLcnimzsOcPMRSBKeMOrpa8av8moMymiKoej+dsYDbnjJhrEdGYitbn20a7QW0RvC9
SDVpFC9GgOenhWqV6IxHbhMq2zJa+hj9Xa7qO25ib3MZmBDoGQVeZsHbBsvK/ByijQ9n2KxvTAsH
No39PfE3AaUrWp3PdsVWniex3CBP/aJEsZuvoIXeFnAwWkZwDhDVPxwkpl+S90DYFKY3vBpnj35U
mGXAkLV44VEejrb+biDE1g6x+o6/2eeLqwmouew4U9em7PxtMDdoljLI7LprDQ+sC24tQgFxNGeV
XE/qHr3G0ieGUkuAZvkMiy0TvE+HHedYXSJHVkJlVDNr3pUQaFk0TKiK0oBlQzd0pBZdeFr8MywW
LQQDQuv5Nzh1DHWIksd7kxCS133eBDipjVh92XKOJ1Yj/W+LcRUYdc+UHKynjhA/HV2vNY8kBCco
M5pgFvQfDd7JB1zOiwM7C2x3aG9uVg2zp1MTjPLI6myzF4d4xaAz8a+P4uONLXMVlAmQcGIswTql
V+z7CbOGcmmZmsR4EJsIes0YkOjrWA/LhOESA2WYhGKwbFUmkQVbKxIZ/qZrqR2prKaDxsJpB/Q1
KJZ+CvUaNHAu8xO+z91Ftki4V26PIfswL5BERN+e4ry1eHJzhPOfC3eC2wvK8oR1elwE7Fwi6SZk
COAR4nz0A13YPWN5YTQffnrYQ8K7qkjSAtBB0Qo9Ob9lp8GjfH8ytzegEbfFCBFJT/y+wbBQeKcb
/1qQd90Rfr7MuFzjkY2K8+HAHIKcuScMask2qu4HybSYKyDePNXq3As0oJsuMeDlxJ9+YrqeRzgR
angHRgBFfH1ZqIW2sRCMQ+flUQwdw9e098Nv9ZYm9uYsTVP221YzNnbOP8lNWPAqFzJRgYiC4pvy
S+AMqD1GdELfeN47XNZKN35ndSDY+09TUx0Oeup0Fk687Z5NhaP1zXfTSpwwyIvJth/eVSx80UFw
kOSHuOCdYxF2HX7KCqWx994AgZowW8pv0Xh03fyXSlY0lFY9lAVh+amnI+CHbcb8zm4EQS3HrHMy
eo8HWSsiemYl1zp6KTaLa2XeJuA8JcJs2A7Qh5eqRkPXT7fIOQTzGFd/k8sE8d2gNdEIK1iY5TCz
Bqg6mJIAnwYNXx59zrG5G1cjnHWFMgRpfB9beck8WrwNqZBLFLeIiDgw31/E2btD1KiMmTJNUUeT
xzlCM3vcF7NTJMt5SaadnBnN5TBoQj2xT15Ki7Ymv5LDVR52AnjPL05CWfg5oIYLPWKyLD+Vl7Gd
YnBOJvOeGdyb2ih6GZXCCbQ9wxVm/Hh5m9jQHqf0/5WX5ry1UdVsdXchvIyYxAjrCiLMI6X1nEOu
3ikYftBeavMC8+eQS44Qlab1OHnUJhVPJtWnekoguEU9eAW+ufNp2OP1Nd8ruS4lgP82MVIcSwdx
LP+Df2ue4ZPNIzbrjAaAusH6lfqVCGOmTz7Po8HVkVL7Ga+pDjoc3M6iQR1Scg0z0E5Hqh9r7oJ2
UOhwaOmFir/2icNfukLXM8EAkIuDg6BWUMzMDIdIZ+f58XMXLSPPl7q4ao9kHa1U7+3rZW4q+E+Y
ws8LOLOqRwiNiH3ySWZcmYaI6zf83bZzceWXSs5CvbCELMc0k3y2eHewGEmvnT2LETxAudBfGK0w
JZN0JKDP4TvyZChWQ19QDTtClEBui9XGzOD59E2LzrbCBc9Aa+pqHOPkaZnSdeXBpNiplW2P7bJh
eSKXh/jziCq5zpnmeZzj5jjA4YOJ5eMgg879NJV6NEsncTIP7dOI66TwQz3Cjgz4U7WVrRBbM24B
vcPNCUmNDtt2hcvOisb3nc80duTpF+oImp6zv4wOHBO0lnzMUd2kDXPG6k97U6hhFUULH8E9udKm
ZOg7zSEP+xCrHOKuNTGk1v1AkWOwWrR+HgZwEmJITNjWEf+UdGJe0Buk3PfOpkQK2KySUXgZSXzy
HWsdgtgd3KL0TqYiVNQN1iHd9qz/0dRQuCafEv4WCYjsGGMj49x43AZo2xXkb9cD7qb9skTpImfd
vijnHdQv91OeCf5eLsTrgYDXXSJCNezjj7Z0OZPoaQ6bXjXZUOGvTabvjtIOtAgN3MpKk5Xd7/Is
eIscc5WQGucIB1Q2BFAUCluSn9gUEoF4n1hoHi6wp2OnRj7clMngp+DCx73Zqw2p6PvB3WHnaeXm
83zjmC2FDFgnGKq9UWLzl0G1Q/UnvKo8R0kOnWGmatITK2scMuqJDdaTrOesL15lRz20yJiBadjp
glS6sd6FDhz9d9UBmc4Pv5XqJRjGh9Mtpie4NIqP6d1mOuJTlinbrwO9yXAYEXM8hxfaRvrfTlb/
3ljiUYy89RK215fu2cx/GshPKeWcC7eTwI4H2PpZOeoDo3X0fVvPfluN1lUUuDDPUG7YBPxKZtyz
L+JCTeuPQs8J0GcCBGYcL0wDBAiMR3Nzg3jBw0rcjgX0ryOEhjfPaOEYEYXcjbKJ/2kinfKVL8CO
cdLaMEH36jZr99T4Ar0ClQtsb+vn6SEKzMqYk7g/GFU6EFkZdyz3vV71R3o8QXSjXBHz0+8sxA6h
wVDgGdSAyFKv8nIB9Qm7fXH03pCasLPmVFI2+4hLMDWIfjRVWLNv8Su5U0LOPHC644os3xx+PkB+
U7ofxyw1tI2pTNDNBthYN94jG0eanF9Dtxa6mQ4oR3gHrvv5cUKxXiX/Ch/PbZIqeiWMtFQyjDC4
OtmvJA0fP03MztghfxIadCj/PCCu1G+82ZR7CWggOUtnvvpjylnz3n1R2c2dbfeg06pjbzNDOHAD
/iuoYb9BC6S88/bg1g6rPGKpsou8OJXFSG27W7c9HnXSqQmoEmIkg/jnkpy3GuygoYGquk/2kgn2
3n1dgnbVvRVtTjyETGX0iGczsgf1gRvWRWH2V/3lsjL3com2CPAv9e9g5AIvGQg5/CIgu1z1IuF4
yS/Zjlczyll4r7aCMnSpH1I55ihjR+GC4ucsjY8eWnNDOsKl0UrlH+jJGzdXwWe81nLI4jnJKMhg
dCwjKoj1THQbYcopJ+RmCiRkME0kkNRUv2ukTupaseZGuVutuhaU8ZfN4eCHRmKcAuvkcwbJFPeQ
fgguHzqOkXRT6XgZxULbJHWQf3axMRFidtT60vzLHsZNaN92Da8rKY/QuYyLWqucFWfhvnG9md5V
ohtp3z8phCpctlL4rHLaFJDq40uIXNPenMRTc7Vt8fs3nBZeM9wasSJRVEpl37repcohGFkhRNeh
GjHSyPcRw7xlWjdaNBsXWvqyZjaC6qKyuNr0vk+LAKTFvw0QH72oQoPzU7v9TA8ORp8OLMLbUGan
84kUQGvkIoUDNi/FYyaS8lb3vLM/V+wAnsz7oTlplNPS756CrllM9C3lOl97OLgYTuyQntDv7dzD
CGC2t8cbinUzbvJVH4vD5mJRz/NUTBAROloZx75citPsagIRItOPbTvAlMVxEeIUOmvFA5/drE/E
vxXqnCEka5CWUKb9h9SGCGvAmw3+VIWxWPTpNWJfgwek9LcamkDu2ggs6W98nbwGFWliv7ouI1D0
YSF5r7/PHvN3Tg+n3ogB/FWMfA3mvngHfZSbl68JffQconu/FllpZ2TDP4TpmiIjBZ7T3BZPK/uK
y3qi8vQFUqZp8sAXdJI+aTUIJVsTIhaA0HrX+aV7wnyyFpqm321j/chz4ZJmcDip984JrazzDqaS
uGcJBwO6FVzcWmPeKyJngUEw/h5yxhYxc3f/rqggA8fdtBm5zbDgODxDbdGXBs7PKCeHexxKAD42
LSSIMyAaF3x2oQ85yuhRaNkhCdh4juBvbc0XwMxn30xonLnyya84Q8iQOLcLy6t9bs7fJiktVt5Z
Tdj30otHoALZY6giZEdZRX9t5lKjZrKI5aq4z5F7+42L7afbaCAeTei6a1zRjkAslI/TkVh4zsAh
9yxj2Pffw2PhwSq+TV7KEBwa9Oc9xJi/kTKzx1avHwMgPS1DTYqZkpYwecb1okUbEggYvMYfQEe9
FlwytVY9KatFYiaRSB5XjwY9FpueU+ooQFY7cPg2qDc0nYLDsgjnaIzysuYDL585OJLboQ3/KpGQ
hNpZ7SbPmnKrZyZG8L01K46/W1XmbDOj5jBqbhMAnn/o8lE0xlkNd0qJ5NuH0UQOKQnkMiWdslkT
0giPAPhfB4lU5OqXy+3taRmiv//4iCHD7faJQ7/cda2rTLuhsIAQ0rRmBzTrKat6mh8d95jDLm0E
4I93ewdCNryCNQD4n4vmUhLcoZfiUJJe/iSfuLi19bcseWILvYiKOR2/xsP+3FoSZNpxY0R+zuEV
SCUSjB2ECT1+oOZm2qtlJB5dk/kBxveu1ZkynQnjfJdX/7WUfzZNRPifcUuyST2XB2cERLO0HXZ7
Go00HdYx4uhs8cgzJMxQxedMN/lXOEwgWle8daVh4Go7W0QfhmSuqKTEHwtJc3qqkHgYMcJr3DjL
eEWKN6BRCJ4zI3m7gT7FFqxkR8kOXnVPmwcdt7ZR541FQAw7a4z5Vatd5MHQcZo1T/xrYh6Jx0IN
vvQzgo14jdajuuPvvm3bWwAi0/xZ+USx+56AQWwlbLwpEqB078bm2zxl1hpEhOkloaQI71Il74Nz
a4GUAF70h70pS+ncf5zbbSvwaS5Xl+reIVx5lDuBtTwXvZOgg86mOmYdeupIuzDz+w28V8WenOk5
eiUtEAd+FgP/RL5qzNSgD2GmFm3tJEb+pFdt3Zq+eCz8u6+Z82Ke2t7lKVfNbjCIRFXu2D09v35A
Swhc8qzq/m6c1TMoUlzGjr3Tnkd5uy6v5aPmXryAqR7ZC4UeT81r7/4TWzs06Q0Yx0jLowT3MzdH
3ZXLKyjJ7A33MW5niLN38EvJBUIObmlnl5f/Awpox5Q1h+j55hxrJHYVaXsjMmhyHeuPasCBm1pV
PFMtK0yCtiPOpt8VJNapPwoonrxiVU76RmgGBPguok0ty521tmizYDpePdBX53lteoqJLLvVrMcK
KxSgsvkiUEqneAUkuwQxglTAAoUT6PpJ/XEybBF4Vqq4KyVjnzTufwIfG2e+8f/fAzg+ix5bJCtv
lgYdly10w1VpMGuQOxGBHZ7ArwJIjig4w4Ne1A/shsKShXD1tLHEXqk0aA3BEWYnicFswUI34os1
H+pcFk+2IUja6etA51BgJe4OS35zWAuAQ1mXTq70WI38ZCoEaB74UhcLuWCN1omLrEQ+KKK6FQbf
TdsxkxrJFkWdosE7TXFzbq0v+pNjVDZ0orL3F25yJZqKxZhxl4gOevy7HdJaPWWSWNyZmaitybEr
nDIpOk9axeQAo1e6/py3gG1pyAEroFks1gzh/BEzkIGjY5JdIdZfT2bkQY9cW0CKcbgis/0yYXg9
w/sAykvQrWSOihxeBkcPI3cfStuilJwuXh1OJegSH9Kz4owt0xikAU2YWjPoyXaHVB8guzAUueet
h8qfOOLo9kMzlD0IfAHhxCNdx5Cz/3CII9SFfUitRYG35lHjHa0vPwU2LQIXhOkhgxAmRL+v7M9E
RwbPUH3G4o2AIO6Z1UGcAModkNT+nwkjQdoo5hDKMJ40+bgev0nbIShWpygcNKRxv1RwCxCwuFJd
J+WL+GYepcyazEObMSDjZDW5YlvA6snzeuNugX90mc6T6LrpJuoDQD8CLW68zQQHfxJ3q6PbfIBd
dfmgBjWoeGcBudkmBNiJc8GBz07zsnnSxnsRptzvUWcVsVGP+r4ztrSS88/jihRLMd4w0XhILyWx
noj50BgGfeqEU+smkEEotXypMT63Qzra61LRuxPn/TCYpW213ulwDuDq2cxdjZxFaqI+6BJBrcV+
Ov3xekwinpgHPxDkWdTP8vn0NVhDUjn/0dZSzbXaA3vtNAB93OP2RdLOZKcxJ2RghGWI8uC6t7i/
0hu8DXAvuaI5UEwfDOcaEbrnmAKakC689EJftOk06d3CuT5ktLiN1GL2lfOLfnpN8aW2zbJ7EZnf
RXyviVtqeE906KBJKLXcS5wbMzhMBFh5+dXH8uw2L92fO0EU2uETpVH9hVKcqw2Me3phPOfF520o
Cy335DklPeqQCTskxdsnI6LT8TDpdO94KTivj8l9Nad2jsXlvlEc2deWQYYp/4OLAuFYq7uvB4PM
HjadFs09qoPJu+/sxvrudAoDabChblb+XL2llJY4nadZpwfCMqns3OEARaSwBsLCMYXxmJHjhTYC
S8m0+vYDSe8T76teQsc7OO61HI4bckpz5Eystv5h/mz0PgSEIR8wbqX/dfZ5NWG7Q6+sHssb82hl
t0UG6dFrwnu3CVzIJgeE2qKjSj1h4useak1sR1DsfiYemC6XesXvnR90Q3SzwxHvbwm/SqiGp5M+
8+5dLQbZhkeZufU8Z58EbGRJ8x0iJCGvHmv0srLa1L0rnXmol7idvs+k9SroK5pJ3GsIgZdTEacv
pqqhD4gjZns2Zrv0bKnpmQg8EIyur6Gc4eINkC8GGvdpwKYmym1v+P9dPAQwW5Gq7L483aEJ8HEG
FCXe0yAHoSTOQWznLazhqsOjAtodxnquxUekNFaguOLXEwJMelShtQRzcXOUPgAqx2D1of9daS/F
mbPQrqE516iMbyqv2pSgfiyFB8a+4RiU8aRZR5qR7rwkpAjXoeGx+CgXV8FjDGm91ofJL49yC8nr
NNiuQ/zf5ueWp87J4tHjvhQexGpBdr8NcAD79kFswWmfrpnL6uNpE71zXyHr7XHoQ/FLiqgDcixo
kuoP+LN+T8Ljh7Qist8+e9KFx0NJsoKLBMMF7zuuEVtd4KylD/ZxKk48kTUKioLPAM4ZaFvx6jfn
NKmpa3kuQCWurVa5N/X2TFQGOkvuB9cLKnWKTyIT6fmfgwBYCPDaBVkavmL0jl//tNn0vPc06d5q
N9Hd3nTPVX6++RqBn71skXzTNRm5+qYsGD97yU2rFl2n8NQXY5pUFOvv1oW3mQdzFfgybRL0CwQm
CPA50NoYXEnUWyOQkkpkMg2U9TyS9G+FH2XnH9Os+eZJcpVm7QFgeRyNFmYUP7G7jrMFmhbLlm/M
8gmC0yffvsfraxYjrcxFmn8mP3fnQPkQMPcEs+yuPiKq8UjEZD5qaIkjgbT8ytDryz33qY/JPC4Z
VRMTyGPt0drMu+3eKjdiILe0hIv6BpfOp6fCjpDKhDGzhipPSC76R6h/RFRfaUZKl0VwmTGLzfyy
6VpRKQoUqmFBHALJk1BnLSfmNXC/7ERjU1DMUpRDTUUHfAgHpZt7MhQscA4mSkMecSuOhkDx85hi
wABQreKszs41eGS2Ew/vTaExdx3DEsWSVQAwaraildDpMtalkD1vkb+qU46BHYlobN87dLVaFd+v
SaYDJxZbcSyRIP12Yj6t3ZewxIYIt15QDq2XsmKlnz4q2N0bvjAs/RSXmUzZqdZ/pGD3TzvEYoa2
/NDpoFSwnhDoWFeyPqOpcoWjiLcHBwsEy+UClZZrbDJiw6StvwJPhShiD2dLG1pt7Z6UmV8Cfms2
AgY1bWG2hAyagYIN1eqwcspiqQMMP5rWG7ytC/5FsWtokjJ434hNvwYf/m3h13eBxTrQbqm91keu
TiKnE4RK/EpbFycuUiG+2qXLAVPY6OdS/ov1X82YkDe79h3JHK3Z2oXRQyAnrLyZHx6lXDc4C7+u
UzqZPZf4dypc/P9PbJEhF55CewglWQUFVel6ZheeWKm4oNGRLfXBDX2XXKE8Ldy575Mu9nNSZRUw
/qjCHdPaihG/yUGwlB2Qz2tcI6nfsVIZAHTl+8cpo7r2Q5jOoAHcHqqDoilhhT01/BvL7q53vxin
tuFlWkqqs9xuyqGpRlyRKnBF6240el1l5Odgw9tIAQCiMGc7TSsVbOU4lQZ6nd+49OoV3feopIhq
i36XivIeU+BbMu2elLYnO4HPf+mxbDVuv06GoKuARByy3jZOaBeyLSy+Oyum3PrKPUbh2v0GT68F
LU8FFcRuJ7v4jFbfPc0PYEvL6TbVYFj55v0ytT0Ix4OKZfRfwnNcjqJvklQYeG89ZQPXCnhhit4E
lbnpMwg42M8zMNRvXOt6f+e5VkeHMSKpMyYSmhn3hbuzRfR40xpQ8WH3zHbpxV6mr2BRT7wdZCmX
vg7FrACRksoYyBLvPm98L2wSZX9ViuTH8Qq+IyHwhACUTV7YoBDTUjEn4xCHhCxc9oTOFfC5GtLO
R258pqElU8irbs2Uz5yD71F8TeHl9d53aWCRBpGnqgDXeBzb1gGtdm+YSNUL2UwEGqXGc8feYUM/
O6pJmEw7BTatiNscDRK4D3LSIXW4Nt4uPb+Q8rpuxkE2yId+xXyl6hJ07z6gZB18Iq19NzeFxelE
BjXZVfSvXM37fReR2VYFzOxxAL0HGJ1ANRblqUZ4sH/iWISimXc3wDttMw3PCLg/Ub3NRsVBrT2A
VLL3oShJirCLYvfD5COg1C3hYXmyclC41KWIkr3SRRv/W5J08yA4ozI8PWFu8821ur8mljyyRmrI
/AWXGDI2CnW4s+p9qFSqgKAziHf/v7d+EQMQKqIMVpIV/5JmnOOjqm5V80asUepNOO6z+FWOhmKn
H+X5cO2JkazfT7aHMdSu14RMZxk9+B2UPz7k3UmtNeRZY6trDh67o0xSHEXxQ1kyXzS/CYNWljHc
tHoJb16rwZBIN2zsPQYDju8a3tmA9BmNigKg0JIhtUi9XbieMKmOV9S/476dZx7FvqcVSbes0wMI
apd7JErGefoS6JPiBemIX/DtR7Wq0XfaLxXKrK2Ssk0JGIzaUxeIGk2KJsMIDVslzcK1l9jrsXrX
7+EGlW/9K5xWqLWWOwo9Dl3XqSN2+W8UfAKrdsbE47iHqKdfPwXfbQgoyEfjn0YLwRbk/EOF/wys
nQ6o1BwuLDXOHpmELONs+KQl2J/wcuMMeSLUBI5z5WP6vXNpwUPvzt6o5Cq0qlzfd5696DXCxxTz
w8ATZLfWcl36JgoEINTGQYd8qbIW3LKZ7Q33YFCVQw4hGq+lqmUzwnwYQJzChd3pA6ANde31I9zx
Rrxil/DKEqEqkS2uuZMpLWu5cIUyOH2jvNGSObN+iK4ywjscZmY4KP8NSNQ6hNPDJ4qtY9ETWNsv
jA75dunBGl7p0jlGI03xyxP2Ldj7NbevgZ3OUmaZ2Lm54uP3LBpsUXv929XzLz0yRwdZed1TW4CN
2V/WzNjyq3Cw4P27RnGskUlrpIZqDiow3oYhTMIXcG81hnF2sxDFNS0+vk+UUYjYb3uAFINR39X3
TGDf8N0qBSgi3qNWIW4BesQbjcP+Xyv6KbuINFEvFgicshW1WBXxSl7q5zm98ZKnPOntZjnG0Jhg
8WE11GQ2+ASDS3HO1vbsHEJVkn4blANVmOlltZNoVwdCgS41xG/unhP4uiRVRC2m1vjyB6zFS8Ad
J+ek0AYfgbyqnhJI6I112VbQzjG+Qj32+ykpF6hIkV6xZs/xgoRzhxB3KHn7f+MUVE7+/VFmx45z
p1L67GAGmWASJY+qTvILhI0GLqmac02hI75WR9vbq1OguYqC39OiNTHfiTJPodXWgPJTzKHnGepv
stwzEb5YKI4uCLL8e2niu+qE01DAAYh0EDDQG9R4V03MvRu0N2L/bY9TCeBor0W4phwuAOZQTNeJ
kPFtJmjCc4eCeBsH2RsA6xM3m91Isx7DsG7L0mscBfMM3Kxw2I75o0gBNrwo87A9jNacbUPcU55q
wg2aQqPDgp4gBhgxnr5FHYETFlH/Un30k1f1vYyXjTXJZVDH65L2R3gapNn2Ca35uGWMYpj3hQb6
uHJ3ffkWjf6Y7MkWMQTEGyDZrvApuUwJMN+5fu1TN7hkEHWyFzdQTlMB2IvhKlWhoE2IzQydzTu/
+veiqHWZjnr8hPgS/Y7G6iHrvpMN4W48R4Ytr9NkJdGDym2OwdTWVDJ+Ss7Oq7qcLKRvsJSx7s2Q
kFM/P3TUnQTwToj6KDxl3iXnmcV3EOEyY06X3a0y8rYpKxh2VShcD3jSpEhF2hLcU4wbzruwaKjm
st+Te3dYaFRFaVdxqVyeMbD2AM9vMySy68+av5m5VtvFg2NkIAYzIKK3W2cu3910Plj7GeeL/GjW
Tn/J7+XOxHpK8ocrjsrWi//JDc0J0mWPPYQ88KWdAy+zSeJrwMRPYp0k6+rMIrz+ZTavA46fX9ir
L5uFv3gSYe3/8pTDgwqrrQNvn0HvK3BJ5B1/kLATnM9l1jsDlRYiCOr/F90Y+GfDN+nmsIqBZ1s6
xrOa3PkqEqPVwMHyWy5BUWvOtmxs7MFvKnAIrTDGId4BxKalgZAtNrTnyYrKLYMgnt1hULbkyutE
sriaMjYxUuToduWTle6aAVM4qXDgED7yJLz2Ia3sgaFt/XNBg3rmS+mBSalB/ABjnXQemUkizrac
AqgNz7UGPAzurOqnK1Wk8N3fA+1Hrr7/R3ImKKVhS+yX9xMJ3tBRe2mRz6EFRmopyAijExjXJGCa
+TaYlqMtmP3DiZvaLJRPLS4dyxomOV6OmFyNIya4RRozE6QuY/jsHLDu2DXbLIvSMoCtMpGcYYYH
46vp01XxdL2S4wrw6zVy8oVL0fNGeakDZLqxmMu921Y5DPw6S+O8Nmnn+OUiYi3F4yK6/8zu+ymB
2ayZUUAxYpdCkNeQ3qVauAITCaWI5rLzvLUIlkwqTwttpBXkZkK66Eo6aSCb+P79TvburZjpf4qL
Li6FkE8xmi0fJH4bBkl5mClNJ4rCmDrPdpjqYTHKdidpm10uTWX9z6Mw1hOcpl0i81E4tbbkbtsp
SuNDf03hJUYUoUir/iLFrYwSuLHSVGyABKD9lbliTK/mfbQJIzBw/HkMg3LakEfR7i4OYn1/6XiQ
Qpx5MUR6HwShZFhTBsjIod6ICEzJ0cufm9azvZ5MdUcLu9g2pkhQqr8T7XIfjmznXbwrCXIXSJL0
0QRRin8RfMgymnyp6DbkbuNCHlh8RU+IqfgCO+v9hH8YNxc6H90I71BtD3MjVruaG4+nzTD/hdsC
kmadIjnD8yFljLWzHLw2g54JQA1eax/w+cOxz20yLvvQ0af2G5yZ0Kwb4mIJsWkQTKoBVobdP2H3
2/F2zXLsgzTql6IRq87YfgKcwgqrYmjVE8gWfoyBFikLJ26wD0F9xG4gRx5zxAZuI4yhbv8relVX
hn2D1ld5eNEv3jJjeaUcLlbpSTvL9xizAtIz23TT1EB9i/tjcuIXA6CErkopzS9dl2Udxnsa3ilK
rFqv7oFFca3zIZmVjuS+3x3bhFp34nLcKOdQf0iT1ZJ171ITpWduSoIOmMthCKfurw2ccNRfRfWt
U4Ae7f/VfhBNx+/Nnw7dgQQGK2Jb4i71uuAFSWiklh0ulmzhb8KRrZFYBaIg1/kTuDrrgAJm0PKV
CNPFLO6KbW3ZOO9XEvIkrCsRlSU06xtTYEWrKJbhGKOiq3HxASLTH0Tu45MFCEGjRs1tBVLRq9Po
AmbhOSWsI6SPiFoCd0e1h4WbchZ0cuA8OhJRvQ/1zGd7/VEAG/yeK6yQrCR+VjdkSTPb5vTG39yl
SUEKUSY1yvC5tKoiZIcUJGCH221B7/SPlcyXtUeJjoZ6/l39Oc4xoBTxhW3K57rVuqGYRWfMHugN
IyWdKqiXtqQufQGmZTSyBaV/xzNp81fDA0loOrXbDI1+prBh++A+3WwI8dlDeaQpAxQas1g0YPZt
PuLxStvD8gebyEoNYjugE14bV1ePW1QoNZJFJp1gxu8BXVZIUHUob6iwN0FcUAw7E3cxuoSDvP9P
V5uB9wX0qHQGGymnWo3O6M4Xv4qiayzxO47piQAd2F2gxz355gUzIx0rll6qX5Anz3MIv5cujHPt
guPeJOTijlRfjurUklv3oC0vK1N/WRXHX9aOjDUHepfbclW35k93fcTTqvbfgdh7mGvTlz3q7M7q
BlFSTNcnr8O/YrwWNkYeIoO/eJoVvXza+Cm8zxGbDUOjSTJC8NqpJqUh9saKEv1xWX5q0craSzBu
Vw7pzqqLDzCOVh5P2iXvHkD9pzQr2uOZ836wM2S028rD9A2Fgb0Bc6lXpHk9eVBUr5Y8rRk+Wil2
BFEtipon0BBf3R34nLWEngnD7xeR4U6HtJZL/zf9C8hfkROlsRrxLcKfe0byKO/MP28d3+jjyfOw
q//2DRpgxeJUFDoJGmA0tcwzUuPJO50ooTOvkhAXf+LK6KHKtsgJ2W8nEJ+J4r386AA23lsyVSYk
flKLJ8qhQx6T0mr09KTDbVAAP2bc9Nim2CN0Xg/5Gki459r63EGfFS7pdpKR8ewGjPVwAZEHvr/P
g9y6PwdhJyHAPY7IeFbxMoQeAaOjGRjtEQ9Ro9tfO7tAjfrzmSwFO395j72lnU4yii4vUAU3sTmL
KQuE5uLzStluKJZOsWy8sib4f1GDY1r8RhQVRZSuRZITwf5KGeYXsCoAF1DggrkvUDsOAmacjgP0
WsNj08QoZTAy67YBJoZH7B5wEtxwjweI+NAtJv8UPxfZjI/2dEX2CwFBjlvXMFBFbk+fy2dtGSzt
cygR9Ou2G6PM2sKsYGbOcz/pZgdlh9KGmchRBVA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
G8f1gqSMQCnQAMasovp609G+Xtml3VQEkPOLMPqVhr1MIayxmJvmZ4o3wKbACMMSFBE4+TcLKolU
Lw320DyaNQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Ug2hg9EpJHXCwIW/al+lR0FQjskKd87pvEXs/ZrL+skznkgUSgLQmC7SJ1oq3QiIqqkep7bUmCVy
we8veKFtu8UfykilTmrnjhTRdAyMYPoc3U6Xbx5Lq7rKnI/dAU/tITqfnX/1RQy97jQ/SOLgi6Dx
Yo7ZJsrm1WJdM+ksPHo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WHtDk6ccWwa0v84+eT11XdXj5G/EYMvPkJ4c5ahUoFGrSqd4gCHCAiolaFpA/e9DhneCRB1la9T/
pcL5IfFfIGM3uNKFFSit1QvzldlM9fpLEMG1OdKNnCRVWp69DgncRuK0JLBlQrlzmwFPjSPfCkyT
SEkKYrcZY2nTdIQ5SLbgqmjNzBcF93ZKwLjze8ccIl9IKNsMpuM1vjvfRM1mgbHdq3Ml+paIzHV0
xzVAzQV7PIanAnzCPVohQpY7U6lCMXZhdciaVjLnPU5sGZdsbkX6VOlL2+/1RPeyueXcWdtS++rj
2qxFe0Bc7E82KYYoGLqRi7Kb8S75TETIsjFkDw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hN3ysJNjoyNBp70dJlaVUOhqqcr2mzYQ/HE9e1MilSDPcz/jN0bqHs9I5KLnIRDQVc/IjMTf1Hvs
CXBTyaSSTFYhpbstaj7kuVfj+BSQj315KjRV1WRKrqyjaqC3oomV+UaFLj2hd/eYIDHnlBcZI0Xf
jKHWzWg0zMrOnchT9Co=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UsVeqgYjuMLz0rai2LA/hZgwQYWVqJGgjFEXQzv9Y+00hP0ur0N5wKZ9COZQf5vaZTwTyOuPtLrX
SZ1NivgvLjstd7l/BODfmRL2canlzh9O8ND44uYj8try0D9PZpZwdkT2+zPnuHOxwOFn6VpPXRDB
8FQLsnOO9RcGzwbgafC0XYO0L5v9yMpxHheu0CqhuQIESPCXp9hByn29OUbPWz+JzoxZM9/hX70F
Rt4HIj6Pw8i0zqLHF3yApqbjUxE3z9pw9XF12lIjbLj5J13qY7Nvp8M071o7YEVT56vnb1d2sbU4
7FN2+vPsLWjaWsmIWAB5eBk4jEavWlXcqmKlbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10688)
`protect data_block
HHsQld+/7Dz+EiOmk7gLHdNnjCBw31fY64ZvJOKWIqDx/80No14YTTrE1li9v7pnl+KQvGfUcjW2
KQ3j8+Z+QrBfcojaRRbqgsCEN3VXRR8tvvJg3gcd4+Y2du3PNsza9nEQm5fgWLCRAPrEQtqCAfaf
1RcYBqDQ4CVO87+eW/usEHoDNO35oggBpqLI8bAWJHDvhbRedL2vHU7SFbYM7TLBwgo7oxWIX0Pw
wpE/ONYAPpOEAiSlWIfWQLpzZcEEESBsuJNhcl5suVc5wloVCby/5SKhpwpeJOHFCWoKuHhz5dwC
Vqk3GomybRHbEMPIpg9px+tMBZSIFHTq0nmcsUOJbjE0MUh1xpQfWq6UbIvdtz3SUzWz39h4gmP+
zdCGa+3TmEI1GILj9hgg2eDoRuVcg9ZnMvKkf4UU8Vwu9s3hSxdTbt0AbKo0tCsVSUDRAkOkSGZP
Otgd9r9Q2foNREaPP528cIf6ZTPBiqjZ9NsgoFY4bqcBRYACy7YPzQiIniRKFa+mGsU4oWzbmbZ2
WFhIhRE6ugan4H1fxkfxLoSYLzTx/az2dPiI1hfRt1OdDuPDdisrSt0kPcvTQwZWLcchem2WcDTy
G1qrLH7Z3hx5I5UJ1bTgb2NWq8c807i9U3t6vawpfKHA45/WXrxJkuK4Bse7GGYJKiOgin4O1nlr
Grjw6zqc65NzRwwKG4C6DYtBYVg5muz6wmTqTSrOT5OQFX+I3ozS/jUNfhgd1zbF/ojhvdgr2k98
OhMngpmBlOvXPU/CWBqR4MEeMzUd+GsXhqV7W5kdEruzBx7x6nFj0I8optuwkG/HdW+Au6trrqm0
TZljCLVx9FCtbMVnfkVTN2nBr+d1GaZnLeXCb55HvgYJxlqsbcG399YHChCBKBny0KPB6uikWVl6
4f+r+6H+MBkywYQ6/tFr1dPPBW6bOAnXeA6W8xYv+VCVdE5y6rlGkBVoXaZnqxzrNRi0IVb5QoE8
gYygUxtz4QTVM40Is6HUF5lR2o/rcDgQZrmfNHu51W28mbOkob6ehToUPcDhhUsdgCmJt6C9oqC/
2XkfBG931GBN13y+k8P1XEgnczCqOftH/JFfdqqA4h6Ysc1dk4FtRXe+jHmYdKQ5nmTcVL5GqLQo
2AkYkLh/RXXGKiyRgOVX4JLM/J7mbWQsK/SwzzBdPF8jLrOZMHA7fF3J6OsjhxMSmAwvg5BjS1Kr
yw1mfi/ooPuf9FFmxjOoiubyr2JTdIJOcCzSpmpZg/RxmaIyRfdWv2DZvPfxjrkuc/1JO/QAjfzo
qnyb4Dk8tIpik+BXtjejsYh2xm+f2BK9O0V7ta031oDhhcdcSI/8CxF8qY5Wub9Vg4hJyUZp/xS8
+ORO1s63FdHiWGNBI1vJzn2uDXY4EKTvJfZk69nh3AgIk2n95FSP+0O3oFnQTGWNGzGRbAsqUF2C
mmBgF/Y+eZgjn4fwQ5+KOcyOYHiQL732ic6FSfzN/+xOBNrgPsfsuL16FOe861RgKLhKx2wl+c2t
IW0OzFWCgV6SbZorsG9A/c++IEGwK/10qU8GVKdtKoLSDNVmWLikF4OaV7B0SryF3DGRgJuDHnWH
m1RE7rvqbwRLbO6KLN+Y4cEpmuO10GP0iHRaeKK7G5p0t/gGgpahlS5PafntE6wfKyra1i32EleC
oui5JjAZ/3dLcnimzsOcPMRSBKeMOrpa8av8moMymiKoej+dsYDbnjJhrEdGYitbn20a7QW0RvC9
SDVpFC9GgOenhWqV6IxHbhMq2zJa+hj9Xa7qO25ib3MZmBDoGQVeZsHbBsvK/ByijQ9n2KxvTAsH
No39PfE3AaUrWp3PdsVWniex3CBP/aJEsZuvoIXeFnAwWkZwDhDVPxwkpl+S90DYFKY3vBpnj35U
mGXAkLV44VEejrb+biDE1g6x+o6/2eeLqwmouew4U9em7PxtMDdoljLI7LprDQ+sC24tQgFxNGeV
XE/qHr3G0ieGUkuAZvkMiy0TvE+HHedYXSJHVkJlVDNr3pUQaFk0TKiK0oBlQzd0pBZdeFr8MywW
LQQDQuv5Nzh1DHWIksd7kxCS133eBDipjVh92XKOJ1Yj/W+LcRUYdc+UHKynjhA/HV2vNY8kBCco
M5pgFvQfDd7JB1zOiwM7C2x3aG9uVg2zp1MTjPLI6myzF4d4xaAz8a+P4uONLXMVlAmQcGIswTql
V+z7CbOGcmmZmsR4EJsIes0YkOjrWA/LhOESA2WYhGKwbFUmkQVbKxIZ/qZrqR2prKaDxsJpB/Q1
KJZ+CvUaNHAu8xO+z91Ftki4V26PIfswL5BERN+e4ry1eHJzhPOfC3eC2wvK8oR1elwE7Fwi6SZk
COAR4nz0A13YPWN5YTQffnrYQ8K7qkjSAtBB0Qo9Ob9lp8GjfH8ytzegEbfFCBFJT/y+wbBQeKcb
/1qQd90Rfr7MuFzjkY2K8+HAHIKcuScMask2qu4HybSYKyDePNXq3As0oJsuMeDlxJ9+YrqeRzgR
angHRgBFfH1ZqIW2sRCMQ+flUQwdw9e098Nv9ZYm9uYsTVP221YzNnbOP8lNWPAqFzJRgYiC4pvy
S+AMqD1GdELfeN47XNZKN35ndSDY+09TUx0Oeup0Fk687Z5NhaP1zXfTSpwwyIvJth/eVSx80UFw
kOSHuOCdYxF2HX7KCqWx994AgZowW8pv0Xh03fyXSlY0lFY9lAVh+amnI+CHbcb8zm4EQS3HrHMy
eo8HWSsiemYl1zp6KTaLa2XeJuA8JcJs2A7Qh5eqRkPXT7fIOQTzGFd/k8sE8d2gNdEIK1iY5TCz
Bqg6mJIAnwYNXx59zrG5G1cjnHWFMgRpfB9beck8WrwNqZBLFLeIiDgw31/E2btD1KiMmTJNUUeT
xzlCM3vcF7NTJMt5SaadnBnN5TBoQj2xT15Ki7Ymv5LDVR52AnjPL05CWfg5oIYLPWKyLD+Vl7Gd
YnBOJvOeGdyb2ih6GZXCCbQ9wxVm/Hh5m9jQHqf0/5WX5ry1UdVsdXchvIyYxAjrCiLMI6X1nEOu
3ikYftBeavMC8+eQS44Qlab1OHnUJhVPJtWnekoguEU9eAW+ufNp2OP1Nd8ruS4lgP82MVIcSwdx
LP+Df2ue4ZPNIzbrjAaAusH6lfqVCGOmTz7Po8HVkVL7Ga+pDjoc3M6iQR1Scg0z0E5Hqh9r7oJ2
UOhwaOmFir/2icNfukLXM8EAkIuDg6BWUMzMDIdIZ+f58XMXLSPPl7q4ao9kHa1U7+3rZW4q+E+Y
ws8LOLOqRwiNiH3ySWZcmYaI6zf83bZzceWXSs5CvbCELMc0k3y2eHewGEmvnT2LETxAudBfGK0w
JZN0JKDP4TvyZChWQ19QDTtClEBui9XGzOD59E2LzrbCBc9Aa+pqHOPkaZnSdeXBpNiplW2P7bJh
eSKXh/jziCq5zpnmeZzj5jjA4YOJ5eMgg879NJV6NEsncTIP7dOI66TwQz3Cjgz4U7WVrRBbM24B
vcPNCUmNDtt2hcvOisb3nc80duTpF+oImp6zv4wOHBO0lnzMUd2kDXPG6k97U6hhFUULH8E9udKm
ZOg7zSEP+xCrHOKuNTGk1v1AkWOwWrR+HgZwEmJITNjWEf+UdGJe0Buk3PfOpkQK2KySUXgZSXzy
HWsdgtgd3KL0TqYiVNQN1iHd9qz/0dRQuCafEv4WCYjsGGMj49x43AZo2xXkb9cD7qb9skTpImfd
vijnHdQv91OeCf5eLsTrgYDXXSJCNezjj7Z0OZPoaQ6bXjXZUOGvTabvjtIOtAgN3MpKk5Xd7/Is
eIscc5WQGucIB1Q2BFAUCluSn9gUEoF4n1hoHi6wp2OnRj7clMngp+DCx73Zqw2p6PvB3WHnaeXm
83zjmC2FDFgnGKq9UWLzl0G1Q/UnvKo8R0kOnWGmatITK2scMuqJDdaTrOesL15lRz20yJiBadjp
glS6sd6FDhz9d9UBmc4Pv5XqJRjGh9Mtpie4NIqP6d1mOuJTlinbrwO9yXAYEXM8hxfaRvrfTlb/
3ljiUYy89RK215fu2cx/GshPKeWcC7eTwI4H2PpZOeoDo3X0fVvPfluN1lUUuDDPUG7YBPxKZtyz
L+JCTeuPQs8J0GcCBGYcL0wDBAiMR3Nzg3jBw0rcjgX0ryOEhjfPaOEYEYXcjbKJ/2kinfKVL8CO
cdLaMEH36jZr99T4Ar0ClQtsb+vn6SEKzMqYk7g/GFU6EFkZdyz3vV71R3o8QXSjXBHz0+8sxA6h
wVDgGdSAyFKv8nIB9Qm7fXH03pCasLPmVFI2+4hLMDWIfjRVWLNv8Su5U0LOPHC644os3xx+PkB+
U7ofxyw1tI2pTNDNBthYN94jG0eanF9Dtxa6mQ4oR3gHrvv5cUKxXiX/Ch/PbZIqeiWMtFQyjDC4
OtmvJA0fP03MztghfxIadCj/PCCu1G+82ZR7CWggOUtnvvpjylnz3n1R2c2dbfeg06pjbzNDOHAD
/iuoYb9BC6S88/bg1g6rPGKpsou8OJXFSG27W7c9HnXSqQmoEmIkg/jnkpy3GuygoYGquk/2kgn2
3n1dgnbVvRVtTjyETGX0iGczsgf1gRvWRWH2V/3lsjL3com2CPAv9e9g5AIvGQg5/CIgu1z1IuF4
yS/Zjlczyll4r7aCMnSpH1I55ihjR+GC4ucsjY8eWnNDOsKl0UrlH+jJGzdXwWe81nLI4jnJKMhg
dCwjKoj1THQbYcopJ+RmCiRkME0kkNRUv2ukTupaseZGuVutuhaU8ZfN4eCHRmKcAuvkcwbJFPeQ
fgguHzqOkXRT6XgZxULbJHWQf3axMRFidtT60vzLHsZNaN92Da8rKY/QuYyLWqucFWfhvnG9md5V
ohtp3z8phCpctlL4rHLaFJDq40uIXNPenMRTc7Vt8fs3nBZeM9wasSJRVEpl37repcohGFkhRNeh
GjHSyPcRw7xlWjdaNBsXWvqyZjaC6qKyuNr0vk+LAKTFvw0QH72oQoPzU7v9TA8ORp8OLMLbUGan
84kUQGvkIoUDNi/FYyaS8lb3vLM/V+wAnsz7oTlplNPS756CrllM9C3lOl97OLgYTuyQntDv7dzD
CGC2t8cbinUzbvJVH4vD5mJRz/NUTBAROloZx75citPsagIRItOPbTvAlMVxEeIUOmvFA5/drE/E
vxXqnCEka5CWUKb9h9SGCGvAmw3+VIWxWPTpNWJfgwek9LcamkDu2ggs6W98nbwGFWliv7ouI1D0
YSF5r7/PHvN3Tg+n3ogB/FWMfA3mvngHfZSbl68JffQconu/FllpZ2TDP4TpmiIjBZ7T3BZPK/uK
y3qi8vQFUqZp8sAXdJI+aTUIJVsTIhaA0HrX+aV7wnyyFpqm321j/chz4ZJmcDip984JrazzDqaS
uGcJBwO6FVzcWmPeKyJngUEw/h5yxhYxc3f/rqggA8fdtBm5zbDgODxDbdGXBs7PKCeHexxKAD42
LSSIMyAaF3x2oQ85yuhRaNkhCdh4juBvbc0XwMxn30xonLnyya84Q8iQOLcLy6t9bs7fJiktVt5Z
Tdj30otHoALZY6giZEdZRX9t5lKjZrKI5aq4z5F7+42L7afbaCAeTei6a1zRjkAslI/TkVh4zsAh
9yxj2Pffw2PhwSq+TV7KEBwa9Oc9xJi/kTKzx1avHwMgPS1DTYqZkpYwecb1okUbEggYvMYfQEe9
FlwytVY9KatFYiaRSB5XjwY9FpueU+ooQFY7cPg2qDc0nYLDsgjnaIzysuYDL585OJLboQ3/KpGQ
hNpZ7SbPmnKrZyZG8L01K46/W1XmbDOj5jBqbhMAnn/o8lE0xlkNd0qJ5NuH0UQOKQnkMiWdslkT
0giPAPhfB4lU5OqXy+3taRmiv//4iCHD7faJQ7/cda2rTLuhsIAQ0rRmBzTrKat6mh8d95jDLm0E
4I93ewdCNryCNQD4n4vmUhLcoZfiUJJe/iSfuLi19bcseWILvYiKOR2/xsP+3FoSZNpxY0R+zuEV
SCUSjB2ECT1+oOZm2qtlJB5dk/kBxveu1ZkynQnjfJdX/7WUfzZNRPifcUuyST2XB2cERLO0HXZ7
Go00HdYx4uhs8cgzJMxQxedMN/lXOEwgWle8daVh4Go7W0QfhmSuqKTEHwtJc3qqkHgYMcJr3DjL
eEWKN6BRCJ4zI3m7gT7FFqxkR8kOXnVPmwcdt7ZR541FQAw7a4z5Vatd5MHQcZo1T/xrYh6Jx0IN
vvQzgo14jdajuuPvvm3bWwAi0/xZ+USx+56AQWwlbLwpEqB078bm2zxl1hpEhOkloaQI71Il74Nz
a4GUAF70h70pS+ncf5zbbSvwaS5Xl+reIVx5lDuBtTwXvZOgg86mOmYdeupIuzDz+w28V8WenOk5
eiUtEAd+FgP/RL5qzNSgD2GmFm3tJEb+pFdt3Zq+eCz8u6+Z82Ke2t7lKVfNbjCIRFXu2D09v35A
Swhc8qzq/m6c1TMoUlzGjr3Tnkd5uy6v5aPmXryAqR7ZC4UeT81r7/4TWzs06Q0Yx0jLowT3MzdH
3ZXLKyjJ7A33MW5niLN38EvJBUIObmlnl5f/Awpox5Q1h+j55hxrJHYVaXsjMmhyHeuPasCBm1pV
PFMtK0yCtiPOpt8VJNapPwoonrxiVU76RmgGBPguok0ty521tmizYDpePdBX53lteoqJLLvVrMcK
KxSgsvkiUEqneAUkuwQxglTAAoUT6PpJ/XEybBF4Vqq4KyVjnzTufwIfG2e+8f/fAzg+ix5bJCtv
lgYdly10w1VpMGuQOxGBHZ7ArwJIjig4w4Ne1A/shsKShXD1tLHEXqk0aA3BEWYnicFswUI34os1
H+pcFk+2IUja6etA51BgJe4OS35zWAuAQ1mXTq70WI38ZCoEaB74UhcLuWCN1omLrEQ+KKK6FQbf
TdsxkxrJFkWdosE7TXFzbq0v+pNjVDZ0orL3F25yJZqKxZhxl4gOevy7HdJaPWWSWNyZmaitybEr
nDIpOk9axeQAo1e6/py3gG1pyAEroFks1gzh/BEzkIGjY5JdIdZfT2bkQY9cW0CKcbgis/0yYXg9
w/sAykvQrWSOihxeBkcPI3cfStuilJwuXh1OJegSH9Kz4owt0xikAU2YWjPoyXaHVB8guzAUueet
h8qfOOLo9kMzlD0IfAHhxCNdx5Cz/3CII9SFfUitRYG35lHjHa0vPwU2LQIXhOkhgxAmRL+v7M9E
RwbPUH3G4o2AIO6Z1UGcAModkNT+nwkjQdoo5hDKMJ40+bgev0nbIShWpygcNKRxv1RwCxCwuFJd
J+WL+GYepcyazEObMSDjZDW5YlvA6snzeuNugX90mc6T6LrpJuoDQD8CLW68zQQHfxJ3q6PbfIBd
dfmgBjWoeGcBudkmBNiJc8GBz07zsnnSxnsRptzvUWcVsVGP+r4ztrSS88/jihRLMd4w0XhILyWx
noj50BgGfeqEU+smkEEotXypMT63Qzra61LRuxPn/TCYpW213ulwDuDq2cxdjZxFaqI+6BJBrcV+
Ov3xekwinpgHPxDkWdTP8vn0NVhDUjn/0dZSzbXaA3vtNAB93OP2RdLOZKcxJ2RghGWI8uC6t7i/
0hu8DXAvuaI5UEwfDOcaEbrnmAKakC689EJftOk06d3CuT5ktLiN1GL2lfOLfnpN8aW2zbJ7EZnf
RXyviVtqeE906KBJKLXcS5wbMzhMBFh5+dXH8uw2L92fO0EU2uETpVH9hVKcqw2Me3phPOfF520o
Cy335DklPeqQCTskxdsnI6LT8TDpdO94KTivj8l9Nad2jsXlvlEc2deWQYYp/4OLAuFYq7uvB4PM
HjadFs09qoPJu+/sxvrudAoDabChblb+XL2llJY4nadZpwfCMqns3OEARaSwBsLCMYXxmJHjhTYC
S8m0+vYDSe8T76teQsc7OO61HI4bckpz5Eystv5h/mz0PgSEIR8wbqX/dfZ5NWG7Q6+sHssb82hl
t0UG6dFrwnu3CVzIJgeE2qKjSj1h4useak1sR1DsfiYemC6XesXvnR90Q3SzwxHvbwm/SqiGp5M+
8+5dLQbZhkeZufU8Z58EbGRJ8x0iJCGvHmv0srLa1L0rnXmol7idvs+k9SroK5pJ3GsIgZdTEacv
pqqhD4gjZns2Zrv0bKnpmQg8EIyur6Gc4eINkC8GGvdpwKYmym1v+P9dPAQwW5Gq7L483aEJ8HEG
FCXe0yAHoSTOQWznLazhqsOjAtodxnquxUekNFaguOLXEwJMelShtQRzcXOUPgAqx2D1of9daS/F
mbPQrqE516iMbyqv2pSgfiyFB8a+4RiU8aRZR5qR7rwkpAjXoeGx+CgXV8FjDGm91ofJL49yC8nr
NNiuQ/zf5ueWp87J4tHjvhQexGpBdr8NcAD79kFswWmfrpnL6uNpE71zXyHr7XHoQ/FLiqgDcixo
kuoP+LN+T8Ljh7Qist8+e9KFx0NJsoKLBMMF7zuuEVtd4KylD/ZxKk48kTUKioLPAM4ZaFvx6jfn
NKmpa3kuQCWurVa5N/X2TFQGOkvuB9cLKnWKTyIT6fmfgwBYCPDaBVkavmL0jl//tNn0vPc06d5q
N9Hd3nTPVX6++RqBn71skXzTNRm5+qYsGD97yU2rFl2n8NQXY5pUFOvv1oW3mQdzFfgybRL0CwQm
CPA50NoYXEnUWyOQkkpkMg2U9TyS9G+FH2XnH9Os+eZJcpVm7QFgeRyNFmYUP7G7jrMFmhbLlm/M
8gmC0yffvsfraxYjrcxFmn8mP3fnQPkQMPcEs+yuPiKq8UjEZD5qaIkjgbT8ytDryz33qY/JPC4Z
VRMTyGPt0drMu+3eKjdiILe0hIv6BpfOp6fCjpDKhDGzhipPSC76R6h/RFRfaUZKl0VwmTGLzfyy
6VpRKQoUqmFBHALJk1BnLSfmNXC/7ERjU1DMUpRDTUUHfAgHpZt7MhQscA4mSkMecSuOhkDx85hi
wABQreKszs41eGS2Ew/vTaExdx3DEsWSVQAwaraildDpMtalkD1vkb+qU46BHYlobN87dLVaFd+v
SaYDJxZbcSyRIP12Yj6t3ZewxIYIt15QDq2XsmKlnz4q2N0bvjAs/RSXmUzZqdZ/pGD3TzvEYoa2
/NDpoFSwnhDoWFeyPqOpcoWjiLcHBwsEy+UClZZrbDJiw6StvwJPhShiD2dLG1pt7Z6UmV8Cfms2
AgY1bWG2hAyagYIN1eqwcspiqQMMP5rWG7ytC/5FsWtokjJ434hNvwYf/m3h13eBxTrQbqm91keu
TiKnE4RK/EpbFycuUiG+2qXLAVPY6OdS/ov1X82YkDe79h3JHK3Z2oXRQyAnrLyZHx6lXDc4C7+u
UzqZPZf4dypc/P9PbJEhF55CewglWQUFVel6ZheeWKm4oNGRLfXBDX2XXKE8Ldy575Mu9nNSZRUw
/qjCHdPaihG/yUGwlB2Qz2tcI6nfsVIZAHTl+8cpo7r2Q5jOoAHcHqqDoilhhT01/BvL7q53vxin
tuFlWkqqs9xuyqGpRlyRKnBF6240el1l5Odgw9tIAQCiMGc7TSsVbOU4lQZ6nd+49OoV3feopIhq
i36XivIeU+BbMu2elLYnO4HPf+mxbDVuv06GoKuARByy3jZOaBeyLSy+Oyum3PrKPUbh2v0GT68F
LU8FFcRuJ7v4jFbfPc0PYEvL6TbVYFj55v0ytT0Ix4OKZfRfwnNcjqJvklQYeG89ZQPXCnhhit4E
lbnpMwg42M8zMNRvXOt6f+e5VkeHMSKpMyYSmhn3hbuzRfR40xpQ8WH3zHbpxV6mr2BRT7wdZCmX
vg7FrACRksoYyBLvPm98L2wSZX9ViuTH8Qq+IyHwhACUTV7YoBDTUjEn4xCHhCxc9oTOFfC5GtLO
R258pqElU8irbs2Uz5yD71F8TeHl9d53aWCRBpGnqgDXeBzb1gGtdm+YSNUL2UwEGqXGc8feYUM/
O6pJmEw7BTatiNscDRK4D3LSIXW4Nt4uPb+Q8rpuxkE2yId+xXyl6hJ07z6gZB18Iq19NzeFxelE
BjXZVfSvXM37fReR2VYFzOxxAL0HGJ1ANRblqUZ4sH/iWISimXc3wDttMw3PCLg/Ub3NRsVBrT2A
VLL3oShJirCLYvfD5COg1C3hYXmyclC41KWIkr3SRRv/W5J08yA4ozI8PWFu8821ur8mljyyRmrI
/AWXGDI2CnW4s+p9qFSqgKAziHf/v7d+EQMQKqIMVpIV/5JmnOOjqm5V80asUepNOO6z+FWOhmKn
H+X5cO2JkazfT7aHMdSu14RMZxk9+B2UPz7k3UmtNeRZY6trDh67o0xSHEXxQ1kyXzS/CYNWljHc
tHoJb16rwZBIN2zsPQYDju8a3tmA9BmNigKg0JIhtUi9XbieMKmOV9S/476dZx7FvqcVSbes0wMI
apd7JErGefoS6JPiBemIX/DtR7Wq0XfaLxXKrK2Ssk0JGIzaUxeIGk2KJsMIDVslzcK1l9jrsXrX
7+EGlW/9K5xWqLWWOwo9Dl3XqSN2+W8UfAKrdsbE47iHqKdfPwXfbQgoyEfjn0YLwRbk/EOF/wys
nQ6o1BwuLDXOHpmELONs+KQl2J/wcuMMeSLUBI5z5WP6vXNpwUPvzt6o5Cq0qlzfd5696DXCxxTz
w8ATZLfWcl36JgoEINTGQYd8qbIW3LKZ7Q33YFCVQw4hGq+lqmUzwnwYQJzChd3pA6ANde31I9zx
Rrxil/DKEqEqkS2uuZMpLWu5cIUyOH2jvNGSObN+iK4ywjscZmY4KP8NSNQ6hNPDJ4qtY9ETWNsv
jA75dunBGl7p0jlGI03xyxP2Ldj7NbevgZ3OUmaZ2Lm54uP3LBpsUXv929XzLz0yRwdZed1TW4CN
2V/WzNjyq3Cw4P27RnGskUlrpIZqDiow3oYhTMIXcG81hnF2sxDFNS0+vk+UUYjYb3uAFINR39X3
TGDf8N0qBSgi3qNWIW4BesQbjcP+Xyv6KbuINFEvFgicshW1WBXxSl7q5zm98ZKnPOntZjnG0Jhg
8WE11GQ2+ASDS3HO1vbsHEJVkn4blANVmOlltZNoVwdCgS41xG/unhP4uiRVRC2m1vjyB6zFS8Ad
J+ek0AYfgbyqnhJI6I112VbQzjG+Qj32+ykpF6hIkV6xZs/xgoRzhxB3KHn7f+MUVE7+/VFmx45z
p1L67GAGmWASJY+qTvILhI0GLqmac02hI75WR9vbq1OguYqC39OiNTHfiTJPodXWgPJTzKHnGepv
stwzEb5YKI4uCLL8e2niu+qE01DAAYh0EDDQG9R4V03MvRu0N2L/bY9TCeBor0W4phwuAOZQTNeJ
kPFtJmjCc4eCeBsH2RsA6xM3m91Isx7DsG7L0mscBfMM3Kxw2I75o0gBNrwo87A9jNacbUPcU55q
wg2aQqPDgp4gBhgxnr5FHYETFlH/Un30k1f1vYyXjTXJZVDH65L2R3gapNn2Ca35uGWMYpj3hQb6
uHJ3ffkWjf6Y7MkWMQTEGyDZrvApuUwJMN+5fu1TN7hkEHWyFzdQTlMB2IvhKlWhoE2IzQydzTu/
+veiqHWZjnr8hPgS/Y7G6iHrvpMN4W48R4Ytr9NkJdGDym2OwdTWVDJ+Ss7Oq7qcLKRvsJSx7s2Q
kFM/P3TUnQTwToj6KDxl3iXnmcV3EOEyY06X3a0y8rYpKxh2VShcD3jSpEhF2hLcU4wbzruwaKjm
st+Te3dYaFRFaVdxqVyeMbD2AM9vMySy68+av5m5VtvFg2NkIAYzIKK3W2cu3910Plj7GeeL/GjW
Tn/J7+XOxHpK8ocrjsrWi//JDc0J0mWPPYQ88KWdAy+zSeJrwMRPYp0k6+rMIrz+ZTavA46fX9ir
L5uFv3gSYe3/8pTDgwqrrQNvn0HvK3BJ5B1/kLATnM9l1jsDlRYiCOr/F90Y+GfDN+nmsIqBZ1s6
xrOa3PkqEqPVwMHyWy5BUWvOtmxs7MFvKnAIrTDGId4BxKalgZAtNrTnyYrKLYMgnt1hULbkyutE
sriaMjYxUuToduWTle6aAVM4qXDgED7yJLz2Ia3sgaFt/XNBg3rmS+mBSalB/ABjnXQemUkizrac
AqgNz7UGPAzurOqnK1Wk8N3fA+1Hrr7/R3ImKKVhS+yX9xMJ3tBRe2mRz6EFRmopyAijExjXJGCa
+TaYlqMtmP3DiZvaLJRPLS4dyxomOV6OmFyNIya4RRozE6QuY/jsHLDu2DXbLIvSMoCtMpGcYYYH
46vp01XxdL2S4wrw6zVy8oVL0fNGeakDZLqxmMu921Y5DPw6S+O8Nmnn+OUiYi3F4yK6/8zu+ymB
2ayZUUAxYpdCkNeQ3qVauAITCaWI5rLzvLUIlkwqTwttpBXkZkK66Eo6aSCb+P79TvburZjpf4qL
Li6FkE8xmi0fJH4bBkl5mClNJ4rCmDrPdpjqYTHKdidpm10uTWX9z6Mw1hOcpl0i81E4tbbkbtsp
SuNDf03hJUYUoUir/iLFrYwSuLHSVGyABKD9lbliTK/mfbQJIzBw/HkMg3LakEfR7i4OYn1/6XiQ
Qpx5MUR6HwShZFhTBsjIod6ICEzJ0cufm9azvZ5MdUcLu9g2pkhQqr8T7XIfjmznXbwrCXIXSJL0
0QRRin8RfMgymnyp6DbkbuNCHlh8RU+IqfgCO+v9hH8YNxc6H90I71BtD3MjVruaG4+nzTD/hdsC
kmadIjnD8yFljLWzHLw2g54JQA1eax/w+cOxz20yLvvQ0af2G5yZ0Kwb4mIJsWkQTKoBVobdP2H3
2/F2zXLsgzTql6IRq87YfgKcwgqrYmjVE8gWfoyBFikLJ26wD0F9xG4gRx5zxAZuI4yhbv8relVX
hn2D1ld5eNEv3jJjeaUcLlbpSTvL9xizAtIz23TT1EB9i/tjcuIXA6CErkopzS9dl2Udxnsa3ilK
rFqv7oFFca3zIZmVjuS+3x3bhFp34nLcKOdQf0iT1ZJ171ITpWduSoIOmMthCKfurw2ccNRfRfWt
U4Ae7f/VfhBNx+/Nnw7dgQQGK2Jb4i71uuAFSWiklh0ulmzhb8KRrZFYBaIg1/kTuDrrgAJm0PKV
CNPFLO6KbW3ZOO9XEvIkrCsRlSU06xtTYEWrKJbhGKOiq3HxASLTH0Tu45MFCEGjRs1tBVLRq9Po
AmbhOSWsI6SPiFoCd0e1h4WbchZ0cuA8OhJRvQ/1zGd7/VEAG/yeK6yQrCR+VjdkSTPb5vTG39yl
SUEKUSY1yvC5tKoiZIcUJGCH221B7/SPlcyXtUeJjoZ6/l39Oc4xoBTxhW3K57rVuqGYRWfMHugN
IyWdKqiXtqQufQGmZTSyBaV/xzNp81fDA0loOrXbDI1+prBh++A+3WwI8dlDeaQpAxQas1g0YPZt
PuLxStvD8gebyEoNYjugE14bV1ePW1QoNZJFJp1gxu8BXVZIUHUob6iwN0FcUAw7E3cxuoSDvP9P
V5uB9wX0qHQGGymnWo3O6M4Xv4qiayzxO47piQAd2F2gxz355gUzIx0rll6qX5Anz3MIv5cujHPt
guPeJOTijlRfjurUklv3oC0vK1N/WRXHX9aOjDUHepfbclW35k93fcTTqvbfgdh7mGvTlz3q7M7q
BlFSTNcnr8O/YrwWNkYeIoO/eJoVvXza+Cm8zxGbDUOjSTJC8NqpJqUh9saKEv1xWX5q0craSzBu
Vw7pzqqLDzCOVh5P2iXvHkD9pzQr2uOZ836wM2S028rD9A2Fgb0Bc6lXpHk9eVBUr5Y8rRk+Wil2
BFEtipon0BBf3R34nLWEngnD7xeR4U6HtJZL/zf9C8hfkROlsRrxLcKfe0byKO/MP28d3+jjyfOw
q//2DRpgxeJUFDoJGmA0tcwzUuPJO50ooTOvkhAXf+LK6KHKtsgJ2W8nEJ+J4r386AA23lsyVSYk
flKLJ8qhQx6T0mr09KTDbVAAP2bc9Nim2CN0Xg/5Gki459r63EGfFS7pdpKR8ewGjPVwAZEHvr/P
g9y6PwdhJyHAPY7IeFbxMoQeAaOjGRjtEQ9Ro9tfO7tAjfrzmSwFO395j72lnU4yii4vUAU3sTmL
KQuE5uLzStluKJZOsWy8sib4f1GDY1r8RhQVRZSuRZITwf5KGeYXsCoAF1DggrkvUDsOAmacjgP0
WsNj08QoZTAy67YBJoZH7B5wEtxwjweI+NAtJv8UPxfZjI/2dEX2CwFBjlvXMFBFbk+fy2dtGSzt
cygR9Ou2G6PM2sKsYGbOcz/pZgdlh9KGmchRBVA=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
G8f1gqSMQCnQAMasovp609G+Xtml3VQEkPOLMPqVhr1MIayxmJvmZ4o3wKbACMMSFBE4+TcLKolU
Lw320DyaNQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Ug2hg9EpJHXCwIW/al+lR0FQjskKd87pvEXs/ZrL+skznkgUSgLQmC7SJ1oq3QiIqqkep7bUmCVy
we8veKFtu8UfykilTmrnjhTRdAyMYPoc3U6Xbx5Lq7rKnI/dAU/tITqfnX/1RQy97jQ/SOLgi6Dx
Yo7ZJsrm1WJdM+ksPHo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WHtDk6ccWwa0v84+eT11XdXj5G/EYMvPkJ4c5ahUoFGrSqd4gCHCAiolaFpA/e9DhneCRB1la9T/
pcL5IfFfIGM3uNKFFSit1QvzldlM9fpLEMG1OdKNnCRVWp69DgncRuK0JLBlQrlzmwFPjSPfCkyT
SEkKYrcZY2nTdIQ5SLbgqmjNzBcF93ZKwLjze8ccIl9IKNsMpuM1vjvfRM1mgbHdq3Ml+paIzHV0
xzVAzQV7PIanAnzCPVohQpY7U6lCMXZhdciaVjLnPU5sGZdsbkX6VOlL2+/1RPeyueXcWdtS++rj
2qxFe0Bc7E82KYYoGLqRi7Kb8S75TETIsjFkDw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hN3ysJNjoyNBp70dJlaVUOhqqcr2mzYQ/HE9e1MilSDPcz/jN0bqHs9I5KLnIRDQVc/IjMTf1Hvs
CXBTyaSSTFYhpbstaj7kuVfj+BSQj315KjRV1WRKrqyjaqC3oomV+UaFLj2hd/eYIDHnlBcZI0Xf
jKHWzWg0zMrOnchT9Co=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UsVeqgYjuMLz0rai2LA/hZgwQYWVqJGgjFEXQzv9Y+00hP0ur0N5wKZ9COZQf5vaZTwTyOuPtLrX
SZ1NivgvLjstd7l/BODfmRL2canlzh9O8ND44uYj8try0D9PZpZwdkT2+zPnuHOxwOFn6VpPXRDB
8FQLsnOO9RcGzwbgafC0XYO0L5v9yMpxHheu0CqhuQIESPCXp9hByn29OUbPWz+JzoxZM9/hX70F
Rt4HIj6Pw8i0zqLHF3yApqbjUxE3z9pw9XF12lIjbLj5J13qY7Nvp8M071o7YEVT56vnb1d2sbU4
7FN2+vPsLWjaWsmIWAB5eBk4jEavWlXcqmKlbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10688)
`protect data_block
HHsQld+/7Dz+EiOmk7gLHdNnjCBw31fY64ZvJOKWIqDx/80No14YTTrE1li9v7pnl+KQvGfUcjW2
KQ3j8+Z+QrBfcojaRRbqgsCEN3VXRR8tvvJg3gcd4+Y2du3PNsza9nEQm5fgWLCRAPrEQtqCAfaf
1RcYBqDQ4CVO87+eW/usEHoDNO35oggBpqLI8bAWJHDvhbRedL2vHU7SFbYM7TLBwgo7oxWIX0Pw
wpE/ONYAPpOEAiSlWIfWQLpzZcEEESBsuJNhcl5suVc5wloVCby/5SKhpwpeJOHFCWoKuHhz5dwC
Vqk3GomybRHbEMPIpg9px+tMBZSIFHTq0nmcsUOJbjE0MUh1xpQfWq6UbIvdtz3SUzWz39h4gmP+
zdCGa+3TmEI1GILj9hgg2eDoRuVcg9ZnMvKkf4UU8Vwu9s3hSxdTbt0AbKo0tCsVSUDRAkOkSGZP
Otgd9r9Q2foNREaPP528cIf6ZTPBiqjZ9NsgoFY4bqcBRYACy7YPzQiIniRKFa+mGsU4oWzbmbZ2
WFhIhRE6ugan4H1fxkfxLoSYLzTx/az2dPiI1hfRt1OdDuPDdisrSt0kPcvTQwZWLcchem2WcDTy
G1qrLH7Z3hx5I5UJ1bTgb2NWq8c807i9U3t6vawpfKHA45/WXrxJkuK4Bse7GGYJKiOgin4O1nlr
Grjw6zqc65NzRwwKG4C6DYtBYVg5muz6wmTqTSrOT5OQFX+I3ozS/jUNfhgd1zbF/ojhvdgr2k98
OhMngpmBlOvXPU/CWBqR4MEeMzUd+GsXhqV7W5kdEruzBx7x6nFj0I8optuwkG/HdW+Au6trrqm0
TZljCLVx9FCtbMVnfkVTN2nBr+d1GaZnLeXCb55HvgYJxlqsbcG399YHChCBKBny0KPB6uikWVl6
4f+r+6H+MBkywYQ6/tFr1dPPBW6bOAnXeA6W8xYv+VCVdE5y6rlGkBVoXaZnqxzrNRi0IVb5QoE8
gYygUxtz4QTVM40Is6HUF5lR2o/rcDgQZrmfNHu51W28mbOkob6ehToUPcDhhUsdgCmJt6C9oqC/
2XkfBG931GBN13y+k8P1XEgnczCqOftH/JFfdqqA4h6Ysc1dk4FtRXe+jHmYdKQ5nmTcVL5GqLQo
2AkYkLh/RXXGKiyRgOVX4JLM/J7mbWQsK/SwzzBdPF8jLrOZMHA7fF3J6OsjhxMSmAwvg5BjS1Kr
yw1mfi/ooPuf9FFmxjOoiubyr2JTdIJOcCzSpmpZg/RxmaIyRfdWv2DZvPfxjrkuc/1JO/QAjfzo
qnyb4Dk8tIpik+BXtjejsYh2xm+f2BK9O0V7ta031oDhhcdcSI/8CxF8qY5Wub9Vg4hJyUZp/xS8
+ORO1s63FdHiWGNBI1vJzn2uDXY4EKTvJfZk69nh3AgIk2n95FSP+0O3oFnQTGWNGzGRbAsqUF2C
mmBgF/Y+eZgjn4fwQ5+KOcyOYHiQL732ic6FSfzN/+xOBNrgPsfsuL16FOe861RgKLhKx2wl+c2t
IW0OzFWCgV6SbZorsG9A/c++IEGwK/10qU8GVKdtKoLSDNVmWLikF4OaV7B0SryF3DGRgJuDHnWH
m1RE7rvqbwRLbO6KLN+Y4cEpmuO10GP0iHRaeKK7G5p0t/gGgpahlS5PafntE6wfKyra1i32EleC
oui5JjAZ/3dLcnimzsOcPMRSBKeMOrpa8av8moMymiKoej+dsYDbnjJhrEdGYitbn20a7QW0RvC9
SDVpFC9GgOenhWqV6IxHbhMq2zJa+hj9Xa7qO25ib3MZmBDoGQVeZsHbBsvK/ByijQ9n2KxvTAsH
No39PfE3AaUrWp3PdsVWniex3CBP/aJEsZuvoIXeFnAwWkZwDhDVPxwkpl+S90DYFKY3vBpnj35U
mGXAkLV44VEejrb+biDE1g6x+o6/2eeLqwmouew4U9em7PxtMDdoljLI7LprDQ+sC24tQgFxNGeV
XE/qHr3G0ieGUkuAZvkMiy0TvE+HHedYXSJHVkJlVDNr3pUQaFk0TKiK0oBlQzd0pBZdeFr8MywW
LQQDQuv5Nzh1DHWIksd7kxCS133eBDipjVh92XKOJ1Yj/W+LcRUYdc+UHKynjhA/HV2vNY8kBCco
M5pgFvQfDd7JB1zOiwM7C2x3aG9uVg2zp1MTjPLI6myzF4d4xaAz8a+P4uONLXMVlAmQcGIswTql
V+z7CbOGcmmZmsR4EJsIes0YkOjrWA/LhOESA2WYhGKwbFUmkQVbKxIZ/qZrqR2prKaDxsJpB/Q1
KJZ+CvUaNHAu8xO+z91Ftki4V26PIfswL5BERN+e4ry1eHJzhPOfC3eC2wvK8oR1elwE7Fwi6SZk
COAR4nz0A13YPWN5YTQffnrYQ8K7qkjSAtBB0Qo9Ob9lp8GjfH8ytzegEbfFCBFJT/y+wbBQeKcb
/1qQd90Rfr7MuFzjkY2K8+HAHIKcuScMask2qu4HybSYKyDePNXq3As0oJsuMeDlxJ9+YrqeRzgR
angHRgBFfH1ZqIW2sRCMQ+flUQwdw9e098Nv9ZYm9uYsTVP221YzNnbOP8lNWPAqFzJRgYiC4pvy
S+AMqD1GdELfeN47XNZKN35ndSDY+09TUx0Oeup0Fk687Z5NhaP1zXfTSpwwyIvJth/eVSx80UFw
kOSHuOCdYxF2HX7KCqWx994AgZowW8pv0Xh03fyXSlY0lFY9lAVh+amnI+CHbcb8zm4EQS3HrHMy
eo8HWSsiemYl1zp6KTaLa2XeJuA8JcJs2A7Qh5eqRkPXT7fIOQTzGFd/k8sE8d2gNdEIK1iY5TCz
Bqg6mJIAnwYNXx59zrG5G1cjnHWFMgRpfB9beck8WrwNqZBLFLeIiDgw31/E2btD1KiMmTJNUUeT
xzlCM3vcF7NTJMt5SaadnBnN5TBoQj2xT15Ki7Ymv5LDVR52AnjPL05CWfg5oIYLPWKyLD+Vl7Gd
YnBOJvOeGdyb2ih6GZXCCbQ9wxVm/Hh5m9jQHqf0/5WX5ry1UdVsdXchvIyYxAjrCiLMI6X1nEOu
3ikYftBeavMC8+eQS44Qlab1OHnUJhVPJtWnekoguEU9eAW+ufNp2OP1Nd8ruS4lgP82MVIcSwdx
LP+Df2ue4ZPNIzbrjAaAusH6lfqVCGOmTz7Po8HVkVL7Ga+pDjoc3M6iQR1Scg0z0E5Hqh9r7oJ2
UOhwaOmFir/2icNfukLXM8EAkIuDg6BWUMzMDIdIZ+f58XMXLSPPl7q4ao9kHa1U7+3rZW4q+E+Y
ws8LOLOqRwiNiH3ySWZcmYaI6zf83bZzceWXSs5CvbCELMc0k3y2eHewGEmvnT2LETxAudBfGK0w
JZN0JKDP4TvyZChWQ19QDTtClEBui9XGzOD59E2LzrbCBc9Aa+pqHOPkaZnSdeXBpNiplW2P7bJh
eSKXh/jziCq5zpnmeZzj5jjA4YOJ5eMgg879NJV6NEsncTIP7dOI66TwQz3Cjgz4U7WVrRBbM24B
vcPNCUmNDtt2hcvOisb3nc80duTpF+oImp6zv4wOHBO0lnzMUd2kDXPG6k97U6hhFUULH8E9udKm
ZOg7zSEP+xCrHOKuNTGk1v1AkWOwWrR+HgZwEmJITNjWEf+UdGJe0Buk3PfOpkQK2KySUXgZSXzy
HWsdgtgd3KL0TqYiVNQN1iHd9qz/0dRQuCafEv4WCYjsGGMj49x43AZo2xXkb9cD7qb9skTpImfd
vijnHdQv91OeCf5eLsTrgYDXXSJCNezjj7Z0OZPoaQ6bXjXZUOGvTabvjtIOtAgN3MpKk5Xd7/Is
eIscc5WQGucIB1Q2BFAUCluSn9gUEoF4n1hoHi6wp2OnRj7clMngp+DCx73Zqw2p6PvB3WHnaeXm
83zjmC2FDFgnGKq9UWLzl0G1Q/UnvKo8R0kOnWGmatITK2scMuqJDdaTrOesL15lRz20yJiBadjp
glS6sd6FDhz9d9UBmc4Pv5XqJRjGh9Mtpie4NIqP6d1mOuJTlinbrwO9yXAYEXM8hxfaRvrfTlb/
3ljiUYy89RK215fu2cx/GshPKeWcC7eTwI4H2PpZOeoDo3X0fVvPfluN1lUUuDDPUG7YBPxKZtyz
L+JCTeuPQs8J0GcCBGYcL0wDBAiMR3Nzg3jBw0rcjgX0ryOEhjfPaOEYEYXcjbKJ/2kinfKVL8CO
cdLaMEH36jZr99T4Ar0ClQtsb+vn6SEKzMqYk7g/GFU6EFkZdyz3vV71R3o8QXSjXBHz0+8sxA6h
wVDgGdSAyFKv8nIB9Qm7fXH03pCasLPmVFI2+4hLMDWIfjRVWLNv8Su5U0LOPHC644os3xx+PkB+
U7ofxyw1tI2pTNDNBthYN94jG0eanF9Dtxa6mQ4oR3gHrvv5cUKxXiX/Ch/PbZIqeiWMtFQyjDC4
OtmvJA0fP03MztghfxIadCj/PCCu1G+82ZR7CWggOUtnvvpjylnz3n1R2c2dbfeg06pjbzNDOHAD
/iuoYb9BC6S88/bg1g6rPGKpsou8OJXFSG27W7c9HnXSqQmoEmIkg/jnkpy3GuygoYGquk/2kgn2
3n1dgnbVvRVtTjyETGX0iGczsgf1gRvWRWH2V/3lsjL3com2CPAv9e9g5AIvGQg5/CIgu1z1IuF4
yS/Zjlczyll4r7aCMnSpH1I55ihjR+GC4ucsjY8eWnNDOsKl0UrlH+jJGzdXwWe81nLI4jnJKMhg
dCwjKoj1THQbYcopJ+RmCiRkME0kkNRUv2ukTupaseZGuVutuhaU8ZfN4eCHRmKcAuvkcwbJFPeQ
fgguHzqOkXRT6XgZxULbJHWQf3axMRFidtT60vzLHsZNaN92Da8rKY/QuYyLWqucFWfhvnG9md5V
ohtp3z8phCpctlL4rHLaFJDq40uIXNPenMRTc7Vt8fs3nBZeM9wasSJRVEpl37repcohGFkhRNeh
GjHSyPcRw7xlWjdaNBsXWvqyZjaC6qKyuNr0vk+LAKTFvw0QH72oQoPzU7v9TA8ORp8OLMLbUGan
84kUQGvkIoUDNi/FYyaS8lb3vLM/V+wAnsz7oTlplNPS756CrllM9C3lOl97OLgYTuyQntDv7dzD
CGC2t8cbinUzbvJVH4vD5mJRz/NUTBAROloZx75citPsagIRItOPbTvAlMVxEeIUOmvFA5/drE/E
vxXqnCEka5CWUKb9h9SGCGvAmw3+VIWxWPTpNWJfgwek9LcamkDu2ggs6W98nbwGFWliv7ouI1D0
YSF5r7/PHvN3Tg+n3ogB/FWMfA3mvngHfZSbl68JffQconu/FllpZ2TDP4TpmiIjBZ7T3BZPK/uK
y3qi8vQFUqZp8sAXdJI+aTUIJVsTIhaA0HrX+aV7wnyyFpqm321j/chz4ZJmcDip984JrazzDqaS
uGcJBwO6FVzcWmPeKyJngUEw/h5yxhYxc3f/rqggA8fdtBm5zbDgODxDbdGXBs7PKCeHexxKAD42
LSSIMyAaF3x2oQ85yuhRaNkhCdh4juBvbc0XwMxn30xonLnyya84Q8iQOLcLy6t9bs7fJiktVt5Z
Tdj30otHoALZY6giZEdZRX9t5lKjZrKI5aq4z5F7+42L7afbaCAeTei6a1zRjkAslI/TkVh4zsAh
9yxj2Pffw2PhwSq+TV7KEBwa9Oc9xJi/kTKzx1avHwMgPS1DTYqZkpYwecb1okUbEggYvMYfQEe9
FlwytVY9KatFYiaRSB5XjwY9FpueU+ooQFY7cPg2qDc0nYLDsgjnaIzysuYDL585OJLboQ3/KpGQ
hNpZ7SbPmnKrZyZG8L01K46/W1XmbDOj5jBqbhMAnn/o8lE0xlkNd0qJ5NuH0UQOKQnkMiWdslkT
0giPAPhfB4lU5OqXy+3taRmiv//4iCHD7faJQ7/cda2rTLuhsIAQ0rRmBzTrKat6mh8d95jDLm0E
4I93ewdCNryCNQD4n4vmUhLcoZfiUJJe/iSfuLi19bcseWILvYiKOR2/xsP+3FoSZNpxY0R+zuEV
SCUSjB2ECT1+oOZm2qtlJB5dk/kBxveu1ZkynQnjfJdX/7WUfzZNRPifcUuyST2XB2cERLO0HXZ7
Go00HdYx4uhs8cgzJMxQxedMN/lXOEwgWle8daVh4Go7W0QfhmSuqKTEHwtJc3qqkHgYMcJr3DjL
eEWKN6BRCJ4zI3m7gT7FFqxkR8kOXnVPmwcdt7ZR541FQAw7a4z5Vatd5MHQcZo1T/xrYh6Jx0IN
vvQzgo14jdajuuPvvm3bWwAi0/xZ+USx+56AQWwlbLwpEqB078bm2zxl1hpEhOkloaQI71Il74Nz
a4GUAF70h70pS+ncf5zbbSvwaS5Xl+reIVx5lDuBtTwXvZOgg86mOmYdeupIuzDz+w28V8WenOk5
eiUtEAd+FgP/RL5qzNSgD2GmFm3tJEb+pFdt3Zq+eCz8u6+Z82Ke2t7lKVfNbjCIRFXu2D09v35A
Swhc8qzq/m6c1TMoUlzGjr3Tnkd5uy6v5aPmXryAqR7ZC4UeT81r7/4TWzs06Q0Yx0jLowT3MzdH
3ZXLKyjJ7A33MW5niLN38EvJBUIObmlnl5f/Awpox5Q1h+j55hxrJHYVaXsjMmhyHeuPasCBm1pV
PFMtK0yCtiPOpt8VJNapPwoonrxiVU76RmgGBPguok0ty521tmizYDpePdBX53lteoqJLLvVrMcK
KxSgsvkiUEqneAUkuwQxglTAAoUT6PpJ/XEybBF4Vqq4KyVjnzTufwIfG2e+8f/fAzg+ix5bJCtv
lgYdly10w1VpMGuQOxGBHZ7ArwJIjig4w4Ne1A/shsKShXD1tLHEXqk0aA3BEWYnicFswUI34os1
H+pcFk+2IUja6etA51BgJe4OS35zWAuAQ1mXTq70WI38ZCoEaB74UhcLuWCN1omLrEQ+KKK6FQbf
TdsxkxrJFkWdosE7TXFzbq0v+pNjVDZ0orL3F25yJZqKxZhxl4gOevy7HdJaPWWSWNyZmaitybEr
nDIpOk9axeQAo1e6/py3gG1pyAEroFks1gzh/BEzkIGjY5JdIdZfT2bkQY9cW0CKcbgis/0yYXg9
w/sAykvQrWSOihxeBkcPI3cfStuilJwuXh1OJegSH9Kz4owt0xikAU2YWjPoyXaHVB8guzAUueet
h8qfOOLo9kMzlD0IfAHhxCNdx5Cz/3CII9SFfUitRYG35lHjHa0vPwU2LQIXhOkhgxAmRL+v7M9E
RwbPUH3G4o2AIO6Z1UGcAModkNT+nwkjQdoo5hDKMJ40+bgev0nbIShWpygcNKRxv1RwCxCwuFJd
J+WL+GYepcyazEObMSDjZDW5YlvA6snzeuNugX90mc6T6LrpJuoDQD8CLW68zQQHfxJ3q6PbfIBd
dfmgBjWoeGcBudkmBNiJc8GBz07zsnnSxnsRptzvUWcVsVGP+r4ztrSS88/jihRLMd4w0XhILyWx
noj50BgGfeqEU+smkEEotXypMT63Qzra61LRuxPn/TCYpW213ulwDuDq2cxdjZxFaqI+6BJBrcV+
Ov3xekwinpgHPxDkWdTP8vn0NVhDUjn/0dZSzbXaA3vtNAB93OP2RdLOZKcxJ2RghGWI8uC6t7i/
0hu8DXAvuaI5UEwfDOcaEbrnmAKakC689EJftOk06d3CuT5ktLiN1GL2lfOLfnpN8aW2zbJ7EZnf
RXyviVtqeE906KBJKLXcS5wbMzhMBFh5+dXH8uw2L92fO0EU2uETpVH9hVKcqw2Me3phPOfF520o
Cy335DklPeqQCTskxdsnI6LT8TDpdO94KTivj8l9Nad2jsXlvlEc2deWQYYp/4OLAuFYq7uvB4PM
HjadFs09qoPJu+/sxvrudAoDabChblb+XL2llJY4nadZpwfCMqns3OEARaSwBsLCMYXxmJHjhTYC
S8m0+vYDSe8T76teQsc7OO61HI4bckpz5Eystv5h/mz0PgSEIR8wbqX/dfZ5NWG7Q6+sHssb82hl
t0UG6dFrwnu3CVzIJgeE2qKjSj1h4useak1sR1DsfiYemC6XesXvnR90Q3SzwxHvbwm/SqiGp5M+
8+5dLQbZhkeZufU8Z58EbGRJ8x0iJCGvHmv0srLa1L0rnXmol7idvs+k9SroK5pJ3GsIgZdTEacv
pqqhD4gjZns2Zrv0bKnpmQg8EIyur6Gc4eINkC8GGvdpwKYmym1v+P9dPAQwW5Gq7L483aEJ8HEG
FCXe0yAHoSTOQWznLazhqsOjAtodxnquxUekNFaguOLXEwJMelShtQRzcXOUPgAqx2D1of9daS/F
mbPQrqE516iMbyqv2pSgfiyFB8a+4RiU8aRZR5qR7rwkpAjXoeGx+CgXV8FjDGm91ofJL49yC8nr
NNiuQ/zf5ueWp87J4tHjvhQexGpBdr8NcAD79kFswWmfrpnL6uNpE71zXyHr7XHoQ/FLiqgDcixo
kuoP+LN+T8Ljh7Qist8+e9KFx0NJsoKLBMMF7zuuEVtd4KylD/ZxKk48kTUKioLPAM4ZaFvx6jfn
NKmpa3kuQCWurVa5N/X2TFQGOkvuB9cLKnWKTyIT6fmfgwBYCPDaBVkavmL0jl//tNn0vPc06d5q
N9Hd3nTPVX6++RqBn71skXzTNRm5+qYsGD97yU2rFl2n8NQXY5pUFOvv1oW3mQdzFfgybRL0CwQm
CPA50NoYXEnUWyOQkkpkMg2U9TyS9G+FH2XnH9Os+eZJcpVm7QFgeRyNFmYUP7G7jrMFmhbLlm/M
8gmC0yffvsfraxYjrcxFmn8mP3fnQPkQMPcEs+yuPiKq8UjEZD5qaIkjgbT8ytDryz33qY/JPC4Z
VRMTyGPt0drMu+3eKjdiILe0hIv6BpfOp6fCjpDKhDGzhipPSC76R6h/RFRfaUZKl0VwmTGLzfyy
6VpRKQoUqmFBHALJk1BnLSfmNXC/7ERjU1DMUpRDTUUHfAgHpZt7MhQscA4mSkMecSuOhkDx85hi
wABQreKszs41eGS2Ew/vTaExdx3DEsWSVQAwaraildDpMtalkD1vkb+qU46BHYlobN87dLVaFd+v
SaYDJxZbcSyRIP12Yj6t3ZewxIYIt15QDq2XsmKlnz4q2N0bvjAs/RSXmUzZqdZ/pGD3TzvEYoa2
/NDpoFSwnhDoWFeyPqOpcoWjiLcHBwsEy+UClZZrbDJiw6StvwJPhShiD2dLG1pt7Z6UmV8Cfms2
AgY1bWG2hAyagYIN1eqwcspiqQMMP5rWG7ytC/5FsWtokjJ434hNvwYf/m3h13eBxTrQbqm91keu
TiKnE4RK/EpbFycuUiG+2qXLAVPY6OdS/ov1X82YkDe79h3JHK3Z2oXRQyAnrLyZHx6lXDc4C7+u
UzqZPZf4dypc/P9PbJEhF55CewglWQUFVel6ZheeWKm4oNGRLfXBDX2XXKE8Ldy575Mu9nNSZRUw
/qjCHdPaihG/yUGwlB2Qz2tcI6nfsVIZAHTl+8cpo7r2Q5jOoAHcHqqDoilhhT01/BvL7q53vxin
tuFlWkqqs9xuyqGpRlyRKnBF6240el1l5Odgw9tIAQCiMGc7TSsVbOU4lQZ6nd+49OoV3feopIhq
i36XivIeU+BbMu2elLYnO4HPf+mxbDVuv06GoKuARByy3jZOaBeyLSy+Oyum3PrKPUbh2v0GT68F
LU8FFcRuJ7v4jFbfPc0PYEvL6TbVYFj55v0ytT0Ix4OKZfRfwnNcjqJvklQYeG89ZQPXCnhhit4E
lbnpMwg42M8zMNRvXOt6f+e5VkeHMSKpMyYSmhn3hbuzRfR40xpQ8WH3zHbpxV6mr2BRT7wdZCmX
vg7FrACRksoYyBLvPm98L2wSZX9ViuTH8Qq+IyHwhACUTV7YoBDTUjEn4xCHhCxc9oTOFfC5GtLO
R258pqElU8irbs2Uz5yD71F8TeHl9d53aWCRBpGnqgDXeBzb1gGtdm+YSNUL2UwEGqXGc8feYUM/
O6pJmEw7BTatiNscDRK4D3LSIXW4Nt4uPb+Q8rpuxkE2yId+xXyl6hJ07z6gZB18Iq19NzeFxelE
BjXZVfSvXM37fReR2VYFzOxxAL0HGJ1ANRblqUZ4sH/iWISimXc3wDttMw3PCLg/Ub3NRsVBrT2A
VLL3oShJirCLYvfD5COg1C3hYXmyclC41KWIkr3SRRv/W5J08yA4ozI8PWFu8821ur8mljyyRmrI
/AWXGDI2CnW4s+p9qFSqgKAziHf/v7d+EQMQKqIMVpIV/5JmnOOjqm5V80asUepNOO6z+FWOhmKn
H+X5cO2JkazfT7aHMdSu14RMZxk9+B2UPz7k3UmtNeRZY6trDh67o0xSHEXxQ1kyXzS/CYNWljHc
tHoJb16rwZBIN2zsPQYDju8a3tmA9BmNigKg0JIhtUi9XbieMKmOV9S/476dZx7FvqcVSbes0wMI
apd7JErGefoS6JPiBemIX/DtR7Wq0XfaLxXKrK2Ssk0JGIzaUxeIGk2KJsMIDVslzcK1l9jrsXrX
7+EGlW/9K5xWqLWWOwo9Dl3XqSN2+W8UfAKrdsbE47iHqKdfPwXfbQgoyEfjn0YLwRbk/EOF/wys
nQ6o1BwuLDXOHpmELONs+KQl2J/wcuMMeSLUBI5z5WP6vXNpwUPvzt6o5Cq0qlzfd5696DXCxxTz
w8ATZLfWcl36JgoEINTGQYd8qbIW3LKZ7Q33YFCVQw4hGq+lqmUzwnwYQJzChd3pA6ANde31I9zx
Rrxil/DKEqEqkS2uuZMpLWu5cIUyOH2jvNGSObN+iK4ywjscZmY4KP8NSNQ6hNPDJ4qtY9ETWNsv
jA75dunBGl7p0jlGI03xyxP2Ldj7NbevgZ3OUmaZ2Lm54uP3LBpsUXv929XzLz0yRwdZed1TW4CN
2V/WzNjyq3Cw4P27RnGskUlrpIZqDiow3oYhTMIXcG81hnF2sxDFNS0+vk+UUYjYb3uAFINR39X3
TGDf8N0qBSgi3qNWIW4BesQbjcP+Xyv6KbuINFEvFgicshW1WBXxSl7q5zm98ZKnPOntZjnG0Jhg
8WE11GQ2+ASDS3HO1vbsHEJVkn4blANVmOlltZNoVwdCgS41xG/unhP4uiRVRC2m1vjyB6zFS8Ad
J+ek0AYfgbyqnhJI6I112VbQzjG+Qj32+ykpF6hIkV6xZs/xgoRzhxB3KHn7f+MUVE7+/VFmx45z
p1L67GAGmWASJY+qTvILhI0GLqmac02hI75WR9vbq1OguYqC39OiNTHfiTJPodXWgPJTzKHnGepv
stwzEb5YKI4uCLL8e2niu+qE01DAAYh0EDDQG9R4V03MvRu0N2L/bY9TCeBor0W4phwuAOZQTNeJ
kPFtJmjCc4eCeBsH2RsA6xM3m91Isx7DsG7L0mscBfMM3Kxw2I75o0gBNrwo87A9jNacbUPcU55q
wg2aQqPDgp4gBhgxnr5FHYETFlH/Un30k1f1vYyXjTXJZVDH65L2R3gapNn2Ca35uGWMYpj3hQb6
uHJ3ffkWjf6Y7MkWMQTEGyDZrvApuUwJMN+5fu1TN7hkEHWyFzdQTlMB2IvhKlWhoE2IzQydzTu/
+veiqHWZjnr8hPgS/Y7G6iHrvpMN4W48R4Ytr9NkJdGDym2OwdTWVDJ+Ss7Oq7qcLKRvsJSx7s2Q
kFM/P3TUnQTwToj6KDxl3iXnmcV3EOEyY06X3a0y8rYpKxh2VShcD3jSpEhF2hLcU4wbzruwaKjm
st+Te3dYaFRFaVdxqVyeMbD2AM9vMySy68+av5m5VtvFg2NkIAYzIKK3W2cu3910Plj7GeeL/GjW
Tn/J7+XOxHpK8ocrjsrWi//JDc0J0mWPPYQ88KWdAy+zSeJrwMRPYp0k6+rMIrz+ZTavA46fX9ir
L5uFv3gSYe3/8pTDgwqrrQNvn0HvK3BJ5B1/kLATnM9l1jsDlRYiCOr/F90Y+GfDN+nmsIqBZ1s6
xrOa3PkqEqPVwMHyWy5BUWvOtmxs7MFvKnAIrTDGId4BxKalgZAtNrTnyYrKLYMgnt1hULbkyutE
sriaMjYxUuToduWTle6aAVM4qXDgED7yJLz2Ia3sgaFt/XNBg3rmS+mBSalB/ABjnXQemUkizrac
AqgNz7UGPAzurOqnK1Wk8N3fA+1Hrr7/R3ImKKVhS+yX9xMJ3tBRe2mRz6EFRmopyAijExjXJGCa
+TaYlqMtmP3DiZvaLJRPLS4dyxomOV6OmFyNIya4RRozE6QuY/jsHLDu2DXbLIvSMoCtMpGcYYYH
46vp01XxdL2S4wrw6zVy8oVL0fNGeakDZLqxmMu921Y5DPw6S+O8Nmnn+OUiYi3F4yK6/8zu+ymB
2ayZUUAxYpdCkNeQ3qVauAITCaWI5rLzvLUIlkwqTwttpBXkZkK66Eo6aSCb+P79TvburZjpf4qL
Li6FkE8xmi0fJH4bBkl5mClNJ4rCmDrPdpjqYTHKdidpm10uTWX9z6Mw1hOcpl0i81E4tbbkbtsp
SuNDf03hJUYUoUir/iLFrYwSuLHSVGyABKD9lbliTK/mfbQJIzBw/HkMg3LakEfR7i4OYn1/6XiQ
Qpx5MUR6HwShZFhTBsjIod6ICEzJ0cufm9azvZ5MdUcLu9g2pkhQqr8T7XIfjmznXbwrCXIXSJL0
0QRRin8RfMgymnyp6DbkbuNCHlh8RU+IqfgCO+v9hH8YNxc6H90I71BtD3MjVruaG4+nzTD/hdsC
kmadIjnD8yFljLWzHLw2g54JQA1eax/w+cOxz20yLvvQ0af2G5yZ0Kwb4mIJsWkQTKoBVobdP2H3
2/F2zXLsgzTql6IRq87YfgKcwgqrYmjVE8gWfoyBFikLJ26wD0F9xG4gRx5zxAZuI4yhbv8relVX
hn2D1ld5eNEv3jJjeaUcLlbpSTvL9xizAtIz23TT1EB9i/tjcuIXA6CErkopzS9dl2Udxnsa3ilK
rFqv7oFFca3zIZmVjuS+3x3bhFp34nLcKOdQf0iT1ZJ171ITpWduSoIOmMthCKfurw2ccNRfRfWt
U4Ae7f/VfhBNx+/Nnw7dgQQGK2Jb4i71uuAFSWiklh0ulmzhb8KRrZFYBaIg1/kTuDrrgAJm0PKV
CNPFLO6KbW3ZOO9XEvIkrCsRlSU06xtTYEWrKJbhGKOiq3HxASLTH0Tu45MFCEGjRs1tBVLRq9Po
AmbhOSWsI6SPiFoCd0e1h4WbchZ0cuA8OhJRvQ/1zGd7/VEAG/yeK6yQrCR+VjdkSTPb5vTG39yl
SUEKUSY1yvC5tKoiZIcUJGCH221B7/SPlcyXtUeJjoZ6/l39Oc4xoBTxhW3K57rVuqGYRWfMHugN
IyWdKqiXtqQufQGmZTSyBaV/xzNp81fDA0loOrXbDI1+prBh++A+3WwI8dlDeaQpAxQas1g0YPZt
PuLxStvD8gebyEoNYjugE14bV1ePW1QoNZJFJp1gxu8BXVZIUHUob6iwN0FcUAw7E3cxuoSDvP9P
V5uB9wX0qHQGGymnWo3O6M4Xv4qiayzxO47piQAd2F2gxz355gUzIx0rll6qX5Anz3MIv5cujHPt
guPeJOTijlRfjurUklv3oC0vK1N/WRXHX9aOjDUHepfbclW35k93fcTTqvbfgdh7mGvTlz3q7M7q
BlFSTNcnr8O/YrwWNkYeIoO/eJoVvXza+Cm8zxGbDUOjSTJC8NqpJqUh9saKEv1xWX5q0craSzBu
Vw7pzqqLDzCOVh5P2iXvHkD9pzQr2uOZ836wM2S028rD9A2Fgb0Bc6lXpHk9eVBUr5Y8rRk+Wil2
BFEtipon0BBf3R34nLWEngnD7xeR4U6HtJZL/zf9C8hfkROlsRrxLcKfe0byKO/MP28d3+jjyfOw
q//2DRpgxeJUFDoJGmA0tcwzUuPJO50ooTOvkhAXf+LK6KHKtsgJ2W8nEJ+J4r386AA23lsyVSYk
flKLJ8qhQx6T0mr09KTDbVAAP2bc9Nim2CN0Xg/5Gki459r63EGfFS7pdpKR8ewGjPVwAZEHvr/P
g9y6PwdhJyHAPY7IeFbxMoQeAaOjGRjtEQ9Ro9tfO7tAjfrzmSwFO395j72lnU4yii4vUAU3sTmL
KQuE5uLzStluKJZOsWy8sib4f1GDY1r8RhQVRZSuRZITwf5KGeYXsCoAF1DggrkvUDsOAmacjgP0
WsNj08QoZTAy67YBJoZH7B5wEtxwjweI+NAtJv8UPxfZjI/2dEX2CwFBjlvXMFBFbk+fy2dtGSzt
cygR9Ou2G6PM2sKsYGbOcz/pZgdlh9KGmchRBVA=
`protect end_protected
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_04 is
end entity fg_a_04;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_04 is
signal clk, reset, d, q, q_n : std_ulogic;
begin
-- code from book
ff1 : process (reset, clk) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff1;
q_n <= not q;
-- end code from book
stimulus : process is
begin
reset <= '0'; clk <= '0'; d <= '1'; wait for 10 ns;
reset <= '1', '0' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
clk <= '1', '0' after 20 ns;
d <= '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_04 is
end entity fg_a_04;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_04 is
signal clk, reset, d, q, q_n : std_ulogic;
begin
-- code from book
ff1 : process (reset, clk) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff1;
q_n <= not q;
-- end code from book
stimulus : process is
begin
reset <= '0'; clk <= '0'; d <= '1'; wait for 10 ns;
reset <= '1', '0' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
clk <= '1', '0' after 20 ns;
d <= '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_04 is
end entity fg_a_04;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_04 is
signal clk, reset, d, q, q_n : std_ulogic;
begin
-- code from book
ff1 : process (reset, clk) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff1;
q_n <= not q;
-- end code from book
stimulus : process is
begin
reset <= '0'; clk <= '0'; d <= '1'; wait for 10 ns;
reset <= '1', '0' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
clk <= '1', '0' after 20 ns;
d <= '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: background_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY background_tb IS
END ENTITY;
ARCHITECTURE background_tb_ARCH OF background_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
background_synth_inst:ENTITY work.background_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Author: Stefan Lohse
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package utilities_pkg is
type t_frequency is range 0 to natural'high units
Hz; -- primary unit
kHz = 1000 Hz; -- secondary unit
MHz = 1000 kHz; -- secondary unit
GHz = 1000 MHz; -- secondary unit
end units;
function to_period(b: t_frequency) return time;
function log2_ceil(a : integer) return natural;
function isSimulation return boolean;
-- ite = if-then-else
function ite( cond: boolean; A: integer; B : integer) return integer;
constant SIMULATION : boolean; -- deferred constant declaration
end package;
package body utilities_pkg is
function to_period(b: t_frequency) return time is
constant result : real := 1.0/real(t_frequency'pos(B));
begin
return result * 1 sec;
end function;
function log2_ceil(a : integer) return natural is
variable pow2 : natural; -- equivalent zu := natural'left
begin
if a = 0 then
return 1;
end if;
for i in 0 to 31 loop
pow2 := 2**i;
if pow2 > a then
return i;
end if;
end loop;
end function;
function isSimulation return boolean is
begin
return is_x('X');
end function;
constant SIMULATION : boolean := isSimulation;
function ite( cond: boolean; A: integer; B : integer) return integer is
begin
if cond then
return A;
else
return B;
end if;
end function;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use work.utilities_pkg.all;
package uart_pkg is
type t_baudrate is range 0 to natural'high units -- oder (natural'low to natural'high) oder (1 to 1000000)
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
end units;
function to_period(b: t_baudrate) return time;
function timing_to_cycles(period: time; frequency: t_frequency) return integer;
function ite( cond: boolean; A: t_baudrate; B : t_baudrate) return t_baudrate;
end package;
package body uart_pkg is
function to_period(b: t_baudrate) return time is
constant result : real := 1.0/real(t_baudrate'pos(B));
begin
return result * 1 sec;
end function;
function timing_to_cycles(period: time; frequency: t_frequency) return integer is
variable res_real : real;
begin
res_real := real(time'pos(period)) / 1.0E12;
res_real := real(t_frequency'pos(frequency)) * res_real;
return integer(ceil(res_real));
end function;
function ite( cond: boolean; A: t_baudrate; B : t_baudrate) return t_baudrate is
begin
if cond then
return A;
else
return B;
end if;
end function;
end package body;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.uart_pkg.ALL;
use work.utilities_pkg.all;
entity uart is
generic (
uart_oversampling : positive := 16;
num_of_databits : positive := 8
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
valid : out STD_LOGIC;
error : out STD_LOGIC;
data : out STD_LOGIC_VECTOR(num_of_databits-1 downto 0);
uart_strobe : in STD_LOGIC
);
end entity;
architecture rtl of uart is
signal shift_reg : std_logic_vector(num_of_databits-1 downto 0);
signal shift_en : std_logic;
signal cntbit_value : unsigned(log2ceil(num_of_databits) downto 0);
signal cntbit_en : std_logic;
signal cntbit_rst : std_logic;
signal cntsamp_value : unsigned(log2ceil(num_of_databits) downto 0);
signal cntsamp_en : std_logic;
signal cntsamp_rst : std_logic;
type t_state is (s_idle, s_startbit, s_receive, s_stopbit, s_error);
signal current_state : t_state := s_idle;
signal next_state : t_state;
begin
shift: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
shift_reg <= (others => '0');
elsif shift_en = '1' then
shift_reg <= rx & shift_reg(shift_reg'right downto 1);
end if;
end if;
end process;
data <= shift_reg;
cntbit: process(clk)
begin
if rising_edge(clk) then
if cntbit_rst = '1' then
cntbit_value <= (others => '0');
elsif cntbit_en = '1' then
cntbit_value <= cntbit_value + 1;
end if;
end if;
end process;
cntsamp: process(clk)
begin
if rising_edge(clk) then
if cntsamp_rst = '1' then
cntsamp_value <= (others => '0');
elsif cntsamp_en = '1' then
cntsamp_value <= cntsamp_value + 1;
end if;
end if;
end process;
-- FSM
fsmreg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
current_state <= s_idle;
else
current_state <= next_state;
end if;
end if;
end process;
fsmcomb: process(current_state, uart_strobe, rx, cntbit_value, cntsamp_value)
begin
-- default values;
next_state <= current_state;
valid <= '0';
error <= '0';
cntbit_en <= '0';
cntbit_rst <= '0';
cntsamp_en <= '0';
cntsamp_rst <= '0';
case current_state is
when s_idle =>
cntsamp_rst <= '1';
cntbit_rst <= '1';
if rx = '0' then
next_state <= s_startbit;
end if;
when s_startbit =>
cntsamp_en <= uart_strobe;
if cntsamp_value = (uart_oversampling/2)-1 then
cntsamp_rst <= '1';
next_state <= s_receive;
end if;
when s_receive =>
cntsamp_en <= uart_strobe;
if cntsamp_value = uart_oversampling-1 then
cntsamp_rst <= '1';
cntbit_en <= '1';
shift_en <= '1';
end if;
if cntbit_value = num_of_databits then
cntsamp_rst <= '1';
next_state <= s_stopbit;
end if;
when s_stopbit =>
cntsamp_en <= uart_strobe;
valid <= '1';
if (cntsamp_value = 15) and rx = '1' then
next_state <= s_idle;
elsif (cntsamp_value = 15) and rx = '0' then
next_state <= s_error;
end if;
when s_error =>
error <= '1';
end case;
end process;
end architecture;
|
component add
port (
clk : in std_logic;
in : in std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0)
);
end component add;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_motor_puerta IS
END tb_motor_puerta;
ARCHITECTURE behavior OF tb_motor_puerta IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT motor_puerta
PORT(
CLK : IN std_logic;
RST : IN std_logic;
nivel : IN std_logic;
celula : IN std_logic;
accionar_puerta : IN std_logic;
actuador_puerta : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal nivel : std_logic := '0';
signal celula : std_logic := '0';
signal accionar_puerta : std_logic := '0';
--Outputs
signal actuador_puerta : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: motor_puerta PORT MAP (
CLK => CLK,
RST => RST,
nivel => nivel,
celula => celula,
accionar_puerta => accionar_puerta,
actuador_puerta => actuador_puerta
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '0';
celula <= '0';
WAIT FOR 3 ns;
accionar_puerta <= '0';
WAIT FOR 20 ns;
celula <= '0';
WAIT FOR 5 ns;
accionar_puerta <= '1';
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 5 ns;
RST <= '0';
WAIT FOR 5 ns;
celula <= '1';
WAIT FOR 5 ns;
accionar_puerta <= '1';
WAIT FOR 20 ns;
celula <= '1';
WAIT FOR 5 ns;
accionar_puerta <= '0';
WAIT FOR 10 ns;
nivel <= '1';
WAIT FOR 10 ns;
celula <= '0';
WAIT FOR 5 ns;
accionar_puerta <= '0';
WAIT FOR 5 ns;
nivel <= '0';
WAIT FOR 15 ns;
ASSERT false
REPORT "Simulacion finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP TX
-- doesnt handle segmentation
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - fixed up setting of tx_result control defaults
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added handling of broadcast address
-- Revision 0.05 - Fix cks calc when add of high bits causes another ovf
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_TX is
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4_TX;
architecture Behavioral of IPv4_TX is
type tx_state_type is (
IDLE,
WAIT_MAC, -- waiting for response from ARP for mac lookup
WAIT_CHN, -- waiting for tx access to MAC channel
SEND_ETH_HDR, -- sending the ethernet header
SEND_IP_HDR, -- sending the IP header
SEND_USER_DATA -- sending the users data
);
type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- Configuration
constant IP_TTL : std_logic_vector (7 downto 0) := x"80";
-- TX state variables
signal tx_state : tx_state_type;
signal tx_count : unsigned (11 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal tx_mac : std_logic_vector (47 downto 0);
signal tx_mac_chn_reqd : std_logic;
signal tx_hdr_cks : std_logic_vector (23 downto 0);
signal mac_lookup_req : std_logic;
signal crc_state : crc_state_type;
signal arp_req_ip_reg : std_logic_vector (31 downto 0);
signal mac_data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_mac_value : std_logic_vector (47 downto 0);
signal set_tx_mac : std_logic;
signal tx_count_val : unsigned (11 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_chn_reqd : set_clr_type;
signal set_mac_lku_req : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
function inv_if_one(s1 : std_logic_vector; en : std_logic) return std_logic_vector is
--this function inverts all the bits of a vector if
--'en' is '1'.
variable Z : std_logic_vector(s1'high downto s1'low);
begin
for i in (s1'low) to s1'high loop
Z(i) := en xor s1(i);
end loop;
return Z;
end inv_if_one; -- end function
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
ip_tx_start, ip_tx, our_ip_address, our_mac_address, arp_req_rslt, --clk,
mac_tx_granted, mac_data_out_ready,
-- state variables
tx_state, tx_count, tx_result_reg, tx_mac, tx_mac_chn_reqd,
mac_lookup_req, tx_hdr_cks, arp_req_ip_reg, mac_data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_mac_value, set_tx_mac, tx_count_mode,
tx_data, set_last, set_chn_reqd, set_mac_lku_req, total_length,
tx_data_valid, tx_count_val
)
begin
-- set output followers
ip_tx_result <= tx_result_reg;
mac_tx_req <= tx_mac_chn_reqd;
arp_req_req.lookup_req <= mac_lookup_req;
arp_req_req.ip <= arp_req_ip_reg;
-- set initial values for combinatorial outputs
mac_data_out_first <= '0';
case tx_state is
when SEND_ETH_HDR | SEND_IP_HDR =>
mac_data_out <= tx_data;
tx_data_valid <= mac_data_out_ready; -- generated internally
mac_data_out_last <= set_last;
when SEND_USER_DATA =>
mac_data_out <= ip_tx.data.data_out;
tx_data_valid <= ip_tx.data.data_out_valid;
mac_data_out_last <= ip_tx.data.data_out_last;
when others =>
mac_data_out <= (others => '0');
tx_data_valid <= '0'; -- not transmitting during this phase
mac_data_out_last <= '0';
end case;
mac_data_out_valid <= tx_data_valid and mac_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_tx_mac <= '0';
set_chn_reqd <= HOLD;
set_mac_lku_req <= HOLD;
next_tx_result <= IPTX_RESULT_NONE;
set_tx_result <= '0';
tx_count_val <= (others => '0');
tx_mac_value <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(ip_tx.hdr.data_length) + 20); -- total length = user data length + header length (bytes)
-- TX FSM
case tx_state is
when IDLE =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
set_chn_reqd <= CLR;
if ip_tx_start = '1' then
-- check header count for error if too high
if unsigned(ip_tx.hdr.data_length) > 8980 then
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
else
next_tx_result <= IPTX_RESULT_SENDING;
set_tx_result <= '1';
-- TODO - check if we already have the mac addr for this ip, if so, bypass the WAIT_MAC state
if ip_tx.hdr.dst_ip_addr = IP_BC_ADDR then
-- for IP broadcast, dont need to look up the MAC addr
tx_mac_value <= MAC_BC_ADDR;
set_tx_mac <= '1';
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
else
-- need to req the mac address for this ip
set_mac_lku_req <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
end if;
end if;
else
set_mac_lku_req <= CLR;
end if;
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer
-- if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
tx_mac_value <= arp_req_rslt.mac;
set_tx_mac <= '1';
set_chn_reqd <= SET;
-- check for optimise when already have the channel
-- if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
-- else
-- next_tx_state <= WAIT_CHN;
-- set_tx_state <= '1';
-- end if;
-- elsif arp_req_rslt.got_err = '1' then
-- set_mac_lku_req <= CLR;
-- next_tx_result <= IPTX_RESULT_ERR;
-- set_tx_result <= '1';
-- next_tx_state <= IDLE;
-- set_tx_state <= '1';
-- end if;
when WAIT_CHN =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
end if;
-- probably should handle a timeout here
when SEND_ETH_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"00d" then
tx_count_mode <= RST;
next_tx_state <= SEND_IP_HDR;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" =>
mac_data_out_first <= mac_data_out_ready;
tx_data <= tx_mac (47 downto 40); -- trg = mac from ARP lookup
when x"001" => tx_data <= tx_mac (39 downto 32);
when x"002" => tx_data <= tx_mac (31 downto 24);
when x"003" => tx_data <= tx_mac (23 downto 16);
when x"004" => tx_data <= tx_mac (15 downto 8);
when x"005" => tx_data <= tx_mac (7 downto 0);
when x"006" => tx_data <= our_mac_address (47 downto 40); -- src = our mac
when x"007" => tx_data <= our_mac_address (39 downto 32);
when x"008" => tx_data <= our_mac_address (31 downto 24);
when x"009" => tx_data <= our_mac_address (23 downto 16);
when x"00a" => tx_data <= our_mac_address (15 downto 8);
when x"00b" => tx_data <= our_mac_address (7 downto 0);
when x"00c" => tx_data <= x"08"; -- pkt type = 0800 : IP
when x"00d" => tx_data <= x"00";
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_IP_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"013" then
tx_count_val <= x"001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" => tx_data <= x"45"; -- v4, 5 words in hdr
when x"001" => tx_data <= x"00"; -- service type
when x"002" => tx_data <= total_length (15 downto 8); -- total length
when x"003" => tx_data <= total_length (7 downto 0);
when x"004" => tx_data <= x"00"; -- identification
when x"005" => tx_data <= x"00";
when x"006" => tx_data <= x"00"; -- flags and fragment offset
when x"007" => tx_data <= x"00";
when x"008" => tx_data <= IP_TTL; -- TTL
when x"009" => tx_data <= ip_tx.hdr.protocol; -- protocol
when x"00a" => tx_data <= tx_hdr_cks (15 downto 8); -- HDR checksum
when x"00b" => tx_data <= tx_hdr_cks (7 downto 0); -- HDR checksum
when x"00c" => tx_data <= our_ip_address (31 downto 24); -- src ip
when x"00d" => tx_data <= our_ip_address (23 downto 16);
when x"00e" => tx_data <= our_ip_address (15 downto 8);
when x"00f" => tx_data <= our_ip_address (7 downto 0);
when x"010" => tx_data <= ip_tx.hdr.dst_ip_addr (31 downto 24); -- dst ip
when x"011" => tx_data <= ip_tx.hdr.dst_ip_addr (23 downto 16);
when x"012" => tx_data <= ip_tx.hdr.dst_ip_addr (15 downto 8);
when x"013" => tx_data <= ip_tx.hdr.dst_ip_addr (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_USER_DATA =>
ip_tx_data_out_ready <= mac_data_out_ready;-- and mac_data_out_ready_reg; -- in this state, we are always ready to accept user data for tx
if mac_data_out_ready = '1' then
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_SENT;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
if ip_tx.data.data_out_last = '0' then
next_tx_result <= IPTX_RESULT_ERR;
end if;
elsif ip_tx.data.data_out_last = '1' then
-- TX terminated due to receiving last indication from upstream - end with error
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= ip_tx.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk)--, reset, mac_data_out_ready_reg)
begin
-- if rising_edge(clk) then
-- mac_data_out_ready_reg <= mac_data_out_ready;
-- else
-- mac_data_out_ready_reg <= mac_data_out_ready_reg;
-- end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= x"000";
tx_result_reg <= IPTX_RESULT_NONE;
tx_mac <= (others => '0');
tx_mac_chn_reqd <= '0';
mac_lookup_req <= '0';
else
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- control arp lookup request
case set_mac_lku_req is
when SET =>
arp_req_ip_reg <= ip_tx.hdr.dst_ip_addr;
mac_lookup_req <= '1';
when CLR =>
mac_lookup_req <= '0';
arp_req_ip_reg <= arp_req_ip_reg;
when HOLD =>
mac_lookup_req <= mac_lookup_req;
arp_req_ip_reg <= arp_req_ip_reg;
end case;
-- save MAC
if set_tx_mac = '1' then
tx_mac <= tx_mac_value;
else
tx_mac <= tx_mac;
end if;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Process to calculate CRC in parallel with pkt out processing
-- this process must yield a valid CRC before it is required to be used in the hdr
-----------------------------------------------------------------------------
crc : process (clk)--, reset)
begin
if rising_edge(clk) then
case crc_state is
when IDLE =>
if ip_tx_start = '1' then
tx_hdr_cks <= x"004500"; -- vers & hdr len & service
crc_state <= TOT_LEN;
end if;
when TOT_LEN =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(total_length));
crc_state <= ID;
when ID =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= FLAGS;
when FLAGS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= TTL;
when TTL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(IP_TTL & ip_tx.hdr.protocol));
crc_state <= CKS;
when CKS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= SAH;
when SAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(31 downto 16)));
crc_state <= SAL;
when SAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(15 downto 0)));
crc_state <= DAH;
when DAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
crc_state <= DAL;
when DAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
crc_state <= ADDOVF;
when ADDOVF =>
tx_hdr_cks <= std_logic_vector ((unsigned(tx_hdr_cks) and x"00ffff")+ unsigned(tx_hdr_cks(23 downto 16)));
crc_state <= FINAL;
when FINAL =>
tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
crc_state <= WAIT_END;
when WAIT_END =>
tx_hdr_cks <= tx_hdr_cks;
if ip_tx_start = '0' then
crc_state <= IDLE;
else
crc_state <= WAIT_END;
end if;
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 02:43:18 04/10/2009
-- Design Name:
-- Module Name: Comp_FullAdder - Behavioral
-- Project Name: Full Adder
-- Target Devices:
-- Tool versions:
-- Description: A standard full adder
--
-- Dependencies: Gate_And.vhd, Gate_Or.vhd, Gate_Xor.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_FullAdder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end Comp_FullAdder;
architecture Behavioral of Comp_FullAdder is
component Gate_And is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
component Gate_Or is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
component Gate_Xor is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal S0 : STD_LOGIC;
signal S1 : STD_LOGIC;
signal S2 : STD_LOGIC;
begin
G1: Gate_Xor port map (A, B, S0);
G2: Gate_Xor port map (S0, Cin, S);
G3: Gate_And port map (Cin, S0, S1);
G4: Gate_And port map (A, B, S2);
G5: Gate_Or port map (S1, S2, Cout);
end Behavioral;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3, a 32-bit processor
--
--Module Title: ConditionBlock
--Module Description:
-- This module handles the condition flags and sending them to the IF stage.
-- It holds the pin, equal, greater than, less than, and carry/overflow flags. It also
-- holds a constant '1' and constant '0' flag. The output is normally the '0' flag,
-- which tells the IF stage to not branch. If a branch instruction is to be executed,
-- the relevant flag is placed on the output. The '1' flag is used for jump
-- instructions, which tells the IF stage to branch.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ConditionBlock is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
flags : in STD_LOGIC_VECTOR(4 downto 0);
cond_out : out STD_LOGIC);
end ConditionBlock;
architecture Behavioral of ConditionBlock is
--//Components\\--
--A generic rising-edge-triggered register
component GenReg is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
--//Signals\\--
--Carries the output of the flags register
signal flags_reg_out : STD_LOGIC_VECTOR(3 downto 0);
--\\Signals//--
begin
--All this process does is take the select bits and, according
--to them, outputs a different flag to be sent to the IF stage
main: process (sel, flags_reg_out, flags(4)) is
begin
case (sel) is
when b"001" =>
cond_out <= flags_reg_out(0);
when b"010" =>
cond_out <= flags_reg_out(1);
when b"011" =>
cond_out <= flags_reg_out(2);
when b"100" =>
cond_out <= flags_reg_out(3);
when b"101" =>
cond_out <= flags(4);
when b"110" => --The two constant flags down here have to do
cond_out <= '1'; --with either a jump, in which case the '1' is placed
when others => --on the output. If just regular instructions are being
cond_out <= '0'; --performed, the '0' is placed on the output, which tells the
end case; --IF stage not to branch
end process;
--Register that holds the flags. Except for the pin flag, which doesn't need to be delayed
--by a cycle like the other flags since it comes from MEMIO, which is a cycle ahead.
--The reason the flags need to be delayed a cycle is that the branch instruction is coming
--directly after the condition being tested.
flags_reg: GenReg generic map (size => 4)
port map (clock => clock,
enable => '1',
reset => reset,
data => flags(3 downto 0),
output => flags_reg_out);
end Behavioral;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.constants.all;
entity function_5 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_5 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(63 downto 0);
variable rTemp2 : SIGNED(31 downto 0);
variable rTemp3 : SIGNED(31 downto 0);
begin
rTemp1 := (signed(INPUT_1 srl 2) * x"1E000000") --* signed(INPUT_2));
OUTPUT_1 <= std_logic_vector((rTemp1(32+(FIXED-1) downto FIXED)) sll 8); --x1*y1
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
-- Automatically generated: write_netlist -wraprm_lec -vhdl -module slowadt7410-wrapreconfmodule-lec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SlowADT7410 is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
I2C_ReceiveSend_n_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_StartProcess_o : out std_logic;
I2C_Busy_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_Data_o : out std_logic_vector(7 downto 0);
I2C_Data_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
WaitCounterPresetH_i : in std_logic_vector(15 downto 0);
WaitCounterPresetL_i : in std_logic_vector(15 downto 0)
);
attribute intersynth_port : string;
attribute intersynth_conntype : string;
attribute intersynth_param : string;
attribute intersynth_port of Reset_n_i : signal is "Reset_n_i";
attribute intersynth_port of Clk_i : signal is "Clk_i";
attribute intersynth_port of Enable_i : signal is "ReconfModuleIn_s";
attribute intersynth_conntype of Enable_i : signal is "Bit";
attribute intersynth_port of CpuIntr_o : signal is "ReconfModuleIRQs_s";
attribute intersynth_conntype of CpuIntr_o : signal is "Bit";
attribute intersynth_port of I2C_ReceiveSend_n_o : signal is "I2C_ReceiveSend_n";
attribute intersynth_conntype of I2C_ReceiveSend_n_o : signal is "Bit";
attribute intersynth_port of I2C_ReadCount_o : signal is "I2C_ReadCount";
attribute intersynth_conntype of I2C_ReadCount_o : signal is "Byte";
attribute intersynth_port of I2C_StartProcess_o : signal is "I2C_StartProcess";
attribute intersynth_conntype of I2C_StartProcess_o : signal is "Bit";
attribute intersynth_port of I2C_Busy_i : signal is "I2C_Busy";
attribute intersynth_conntype of I2C_Busy_i : signal is "Bit";
attribute intersynth_port of I2C_FIFOReadNext_o : signal is "I2C_FIFOReadNext";
attribute intersynth_conntype of I2C_FIFOReadNext_o : signal is "Bit";
attribute intersynth_port of I2C_FIFOWrite_o : signal is "I2C_FIFOWrite";
attribute intersynth_conntype of I2C_FIFOWrite_o : signal is "Bit";
attribute intersynth_port of I2C_Data_o : signal is "I2C_DataIn";
attribute intersynth_conntype of I2C_Data_o : signal is "Byte";
attribute intersynth_port of I2C_Data_i : signal is "I2C_DataOut";
attribute intersynth_conntype of I2C_Data_i : signal is "Byte";
attribute intersynth_port of I2C_Error_i : signal is "I2C_Error";
attribute intersynth_conntype of I2C_Error_i : signal is "Bit";
attribute intersynth_param of PeriodCounterPresetH_i : signal is "PeriodCounterPresetH_i";
attribute intersynth_conntype of PeriodCounterPresetH_i : signal is "Word";
attribute intersynth_param of PeriodCounterPresetL_i : signal is "PeriodCounterPresetL_i";
attribute intersynth_conntype of PeriodCounterPresetL_i : signal is "Word";
attribute intersynth_param of SensorValue_o : signal is "SensorValue_o";
attribute intersynth_conntype of SensorValue_o : signal is "Word";
attribute intersynth_param of Threshold_i : signal is "Threshold_i";
attribute intersynth_conntype of Threshold_i : signal is "Word";
attribute intersynth_param of WaitCounterPresetH_i : signal is "WaitCounterPresetH_i";
attribute intersynth_conntype of WaitCounterPresetH_i : signal is "Word";
attribute intersynth_param of WaitCounterPresetL_i : signal is "WaitCounterPresetL_i";
attribute intersynth_conntype of WaitCounterPresetL_i : signal is "Word";
end SlowADT7410;
architecture WrapReconfModule of SlowADT7410 is
component MyReconfigLogic
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end component;
signal ReconfModuleIn_s : std_logic_vector(7 downto 0);
signal ReconfModuleIRQs_s : std_logic_vector(4 downto 0);
signal I2C_ReadCount_s : std_logic_vector(3 downto 0);
signal AdcDoConvert_s : std_logic;
signal CfgIntfDOut_s : std_logic_vector(15 downto 0);
signal I2C_Divider800_s : std_logic_vector(15 downto 0);
signal I2C_ErrAckParam_s : std_logic;
signal I2C_F100_400_n_s : std_logic;
signal Outputs_s : std_logic_vector(7 downto 0);
signal ParamIntfDOut_s : std_logic_vector(15 downto 0);
signal ReconfModuleOut_s : std_logic_vector(7 downto 0);
signal SPI_CPHA_s : std_logic;
signal SPI_CPOL_s : std_logic;
signal SPI_DataIn_s : std_logic_vector(7 downto 0);
signal SPI_LSBFE_s : std_logic;
signal SPI_ReadNext_s : std_logic;
signal SPI_SPPR_SPR_s : std_logic_vector(7 downto 0);
signal SPI_Write_s : std_logic;
begin
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o,
I2C_ReadCount_o => I2C_ReadCount_s,
I2C_StartProcess_o => I2C_StartProcess_o,
I2C_Busy_i => I2C_Busy_i,
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o,
I2C_FIFOWrite_o => I2C_FIFOWrite_o,
I2C_DataIn_o => I2C_Data_o,
I2C_DataOut_i => I2C_Data_i,
I2C_Error_i => I2C_Error_i,
AdcConvComplete_i => '0',
AdcDoConvert_o => AdcDoConvert_s,
AdcValue_i => "0000000000",
CfgIntfDOut_o => CfgIntfDOut_s,
I2C_Divider800_o => I2C_Divider800_s,
I2C_ErrAckParam_o => I2C_ErrAckParam_s,
I2C_Errors_i => "00000000",
I2C_F100_400_n_o => I2C_F100_400_n_s,
I2C_FIFOEmpty_i => '0',
I2C_FIFOFull_i => '0',
Inputs_i => "00000000",
Outputs_o => Outputs_s,
ParamIntfDOut_o => ParamIntfDOut_s,
PerAddr_i => "00000000000000",
PerDIn_i => "0000000000000000",
PerEn_i => '0',
PerWr_i => "00",
ReconfModuleOut_o => ReconfModuleOut_s,
SPI_CPHA_o => SPI_CPHA_s,
SPI_CPOL_o => SPI_CPOL_s,
SPI_DataIn_o => SPI_DataIn_s,
SPI_DataOut_i => "00000000",
SPI_FIFOEmpty_i => '0',
SPI_FIFOFull_i => '0',
SPI_LSBFE_o => SPI_LSBFE_s,
SPI_ReadNext_o => SPI_ReadNext_s,
SPI_SPPR_SPR_o => SPI_SPPR_SPR_s,
SPI_Transmission_i => '0',
SPI_Write_o => SPI_Write_s
);
CpuIntr_o <= ReconfModuleIRQs_s(0);
I2C_ReadCount_o <= "0000" & I2C_ReadCount_s;
ReconfModuleIn_s <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & Enable_i;
end WrapReconfModule;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity sipisoAluControl is
port (
clk : in std_logic;
rst : in std_logic;
strobeA : in std_logic;
strobeB: in std_logic;
shiftA : out std_logic;
loadB : out std_logic;
loadC : out std_logic;
shiftC : out std_logic;
startC: out std_logic
);
end sipisoAluControl;
-- EA <= oBuffer(0);
-- LDB <= oBuffer(1);
-- LDC <= oBuffer(2);
-- SHIFTC <= oBuffer(3);
architecture FSM_OPC of sipisoAluControl is
type TYPE_STATE is (S0, AF0, AF1, AF2, AF3, WB, BS, BF, WA, AS0, AS1, AS2, AS3, C0, C1, C2, C3);
signal CURRENT_STATE: TYPE_STATE := S0;
signal NEXT_STATE: TYPE_STATE := S0;
signal intO: std_logic_vector(4 downto 0) := "00000";
begin
P_OPC : process(clk, rst)
begin
if rst='1' then
CURRENT_STATE <= S0;
elsif (clk ='1' and clk'EVENT) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process P_OPC;
P_NEXT_STATE : process(CURRENT_STATE, strobeA, strobeB)
begin
-- NEXT_STATE <= CURRENT_STATE; --redundant
case CURRENT_STATE is
when S0 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BF;
else
NEXT_STATE <= S0;
end if;
when AF0 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
else
NEXT_STATE <= AF1;
end if;
when AF1 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
else
NEXT_STATE <= AF2;
end if;
when AF2 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
else
NEXT_STATE <= AF3;
end if;
when AF3 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BS;
else
NEXT_STATE <= WB;
end if;
when WB =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BS;
else
NEXT_STATE <= WB;
end if;
when BS =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AS0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BS;
else
NEXT_STATE <= C0;
end if;
when BF =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AS0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BF;
else
NEXT_STATE <= WA;
end if;
when WA =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AS0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BF;
else
NEXT_STATE <= WA;
end if;
when AS0 =>
if strobeA = '0' and strobeB = '1' then
NEXT_STATE <= AS0;
else
NEXT_STATE <= AS1;
end if;
when AS1 =>
if strobeA = '0' and strobeB = '1' then
NEXT_STATE <= AS0;
else
NEXT_STATE <= AS2;
end if;
when AS2 =>
if strobeA = '0' and strobeB = '1' then
NEXT_STATE <= AS0;
else
NEXT_STATE <= AS3;
end if;
when AS3 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AS0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BS;
else
NEXT_STATE <= C0;
end if;
when C0 => NEXT_STATE <= C1;
when C1 => NEXT_STATE <= C2;
when C2 => NEXT_STATE <= C3;
when C3 =>
if strobeA = '1' and strobeB = '0' then
NEXT_STATE <= AF0;
elsif strobeA = '0' and strobeB = '1' then
NEXT_STATE <= BF;
else
NEXT_STATE <= S0;
end if;
end case;
end process P_NEXT_STATE;
P_OUTPUTS: process(CURRENT_STATE)
begin
--O <= '0';
case CURRENT_STATE is
when S0 | WA | WB | AF3 | AS3 => intO <= "00000";
when BF | BS => intO <= "00010";
when AF0 | AF1 | AF2 | AS0 | AS1 | AS2 => intO <= "00001";
when C0 => intO <= "10100";
when C1 | C2 | C3 => intO <= "01000";
end case;
end process P_OUTPUTS;
shiftA <= intO(0);
loadB <= intO(1);
loadC <= intO(2);
shiftC <= intO(3);
startC <= intO(4);
end FSM_OPC;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:prog_rom:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_prog_rom_0_0 IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END RAT_prog_rom_0_0;
ARCHITECTURE RAT_prog_rom_0_0_arch OF RAT_prog_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT prog_rom IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END COMPONENT prog_rom;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "prog_rom,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_prog_rom_0_0_arch : ARCHITECTURE IS "RAT_prog_rom_0_0,prog_rom,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "RAT_prog_rom_0_0,prog_rom,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=prog_rom,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : prog_rom
PORT MAP (
ADDRESS => ADDRESS,
INSTRUCTION => INSTRUCTION,
CLK => CLK
);
END RAT_prog_rom_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:prog_rom:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_prog_rom_0_0 IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END RAT_prog_rom_0_0;
ARCHITECTURE RAT_prog_rom_0_0_arch OF RAT_prog_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT prog_rom IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END COMPONENT prog_rom;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "prog_rom,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_prog_rom_0_0_arch : ARCHITECTURE IS "RAT_prog_rom_0_0,prog_rom,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "RAT_prog_rom_0_0,prog_rom,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=prog_rom,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : prog_rom
PORT MAP (
ADDRESS => ADDRESS,
INSTRUCTION => INSTRUCTION,
CLK => CLK
);
END RAT_prog_rom_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3091.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p02n01i03091ent IS
END c05s01b00x00p02n01i03091ent;
ARCHITECTURE c05s01b00x00p02n01i03091arch OF c05s01b00x00p02n01i03091ent IS
type a is range 1 to 10;
attribute left : integer;
attribute left of : type is 5; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p02n01i03091 - Missing entity specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p02n01i03091arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3091.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p02n01i03091ent IS
END c05s01b00x00p02n01i03091ent;
ARCHITECTURE c05s01b00x00p02n01i03091arch OF c05s01b00x00p02n01i03091ent IS
type a is range 1 to 10;
attribute left : integer;
attribute left of : type is 5; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p02n01i03091 - Missing entity specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p02n01i03091arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3091.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p02n01i03091ent IS
END c05s01b00x00p02n01i03091ent;
ARCHITECTURE c05s01b00x00p02n01i03091arch OF c05s01b00x00p02n01i03091ent IS
type a is range 1 to 10;
attribute left : integer;
attribute left of : type is 5; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p02n01i03091 - Missing entity specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p02n01i03091arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY base_zynq_design_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_xlconcat_0_0;
ARCHITECTURE base_zynq_design_xlconcat_0_0_arch OF base_zynq_design_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT xlconcat;
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 1,
NUM_PORTS => 1
)
PORT MAP (
In0 => In0,
In1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END base_zynq_design_xlconcat_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc315.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00315ent IS
END c03s02b00x00p03n02i00315ent;
ARCHITECTURE c03s02b00x00p03n02i00315arch OF c03s02b00x00p03n02i00315ent IS
type FT is file of integer;
type a12 is array (1 to 10) of FT; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00315 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00315arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc315.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00315ent IS
END c03s02b00x00p03n02i00315ent;
ARCHITECTURE c03s02b00x00p03n02i00315arch OF c03s02b00x00p03n02i00315ent IS
type FT is file of integer;
type a12 is array (1 to 10) of FT; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00315 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00315arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc315.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00315ent IS
END c03s02b00x00p03n02i00315ent;
ARCHITECTURE c03s02b00x00p03n02i00315arch OF c03s02b00x00p03n02i00315ent IS
type FT is file of integer;
type a12 is array (1 to 10) of FT; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00315 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00315arch;
|
-- VHDL de um mapeador de caracteres
library ieee;
use ieee.std_logic_1164.all;
entity mapeador_caractere is
port(
caractere: in std_logic_vector(6 downto 0);
posicao_memoria: out std_logic_vector(6 downto 0)
);
end mapeador_caractere;
architecture estrutural of mapeador_caractere is
begin
process (caractere)
begin
case caractere is
when "0110111" =>
posicao_memoria <= "0001011";
when "0111000" =>
posicao_memoria <= "0001111";
when "0111001" =>
posicao_memoria <= "0010011";
when "0110100" =>
posicao_memoria <= "0100011";
when "0110101" =>
posicao_memoria <= "0100111";
when "0110110" =>
posicao_memoria <= "0101011";
when "0110001" =>
posicao_memoria <= "0111011";
when "0110010" =>
posicao_memoria <= "0111111";
when "0110011" =>
posicao_memoria <= "1000011";
when others =>
null;
end case;
end process;
end estrutural;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_c_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_c_e-e.vhd,v 1.1 2004/04/06 10:50:38 wig Exp $
-- $Date: 2004/04/06 10:50:38 $
-- $Log: inst_c_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:38 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_c_e
--
entity inst_c_e is
-- Generics:
-- No Generated Generics for Entity inst_c_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_c_e
end inst_c_e;
--
-- End of Generated Entity inst_c_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity issue96 is
end entity;
architecture foo of issue96 is
function "&" (l: string; r: natural) return string is
begin
report "called the user function";
assert r <= 255
report "&, natural " & natural'IMAGE(r) &
" argument out of character range"
severity ERROR;
return l & character'VAL(r);
end function;
constant a: string := "abcd";
constant b: string := "efgh";
begin
assert FALSE
report "concatenated string is " & a & -- Line 18
character'VAL(16#42#) & b &
" " & a & 16#42# & b
severity NOTE;
end architecture;
|
entity tb_uassoc01 is
end tb_uassoc01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_uassoc01 is
signal i1 : std_logic_vector(3 downto 0);
signal i2 : std_logic_vector(7 downto 0);
signal o : std_logic_vector(3 downto 0);
begin
dut: entity work.uassoc01
port map (i1, i2, o);
process
begin
i1 <= "1100";
i2 <= b"1010_1010";
wait for 1 ns;
assert o = "0110" severity failure;
wait;
end process;
end behav;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_COMMSMATRIX is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_ENVMFABREMAPBASE: in vl_logic_vector(19 downto 0);
COM_PROTREGIONSIZE: in vl_logic_vector(4 downto 0);
COM_PROTREGIONBASE: in vl_logic_vector(31 downto 0);
COM_MASTERENABLE: in vl_logic_vector(2 downto 0);
COM_CLEARSTATUS : in vl_logic_vector(4 downto 0);
COM_WEIGHTEDMODE: in vl_logic;
COM_ERRORSTATUS : out vl_logic_vector(4 downto 0);
COM_ERRORINTERRUPT: out vl_logic;
M3_HADDRI : in vl_logic_vector(31 downto 0);
M3_HTRANSI1 : in vl_logic;
M3_HSIZEI : in vl_logic_vector(2 downto 0);
M3_HADDRD : in vl_logic_vector(31 downto 0);
M3_HTRANSD1 : in vl_logic;
M3_HWRITED : in vl_logic;
M3_HSIZED : in vl_logic_vector(2 downto 0);
M3_HWDATAD : in vl_logic_vector(31 downto 0);
M3_HRDATAI : out vl_logic_vector(31 downto 0);
M3_HREADYI : out vl_logic;
M3_HRESPI : out vl_logic;
M3_HRDATAD : out vl_logic_vector(31 downto 0);
M3_HREADYD : out vl_logic;
M3_HRESPD : out vl_logic;
M3_HADDRS : in vl_logic_vector(31 downto 0);
M3_HTRANSS1 : in vl_logic;
M3_HWRITES : in vl_logic;
M3_HSIZES : in vl_logic_vector(2 downto 0);
M3_HWDATAS : in vl_logic_vector(31 downto 0);
M3_HMASTLOCKS : in vl_logic;
M3_HRDATAS : out vl_logic_vector(31 downto 0);
M3_HREADYS : out vl_logic;
M3_HRESPS : out vl_logic;
DS_FM_HADDR : in vl_logic_vector(31 downto 0);
DS_FM_HMASTLOCK : in vl_logic;
DS_FM_HSIZE : in vl_logic_vector(2 downto 0);
DS_FM_HTRANS1 : in vl_logic;
DS_FM_HWRITE : in vl_logic;
DS_FM_HWDATA : in vl_logic_vector(31 downto 0);
DS_FM_HRDATA : out vl_logic_vector(31 downto 0);
DS_FM_HREADY : out vl_logic;
DS_FM_HRESP : out vl_logic;
MAC_HWRITE : in vl_logic;
MAC_HADDR : in vl_logic_vector(31 downto 0);
MAC_HTRANS1 : in vl_logic;
MAC_HSIZE : in vl_logic_vector(2 downto 0);
MAC_HWDATA : in vl_logic_vector(31 downto 0);
MAC_HRDATA : out vl_logic_vector(31 downto 0);
MAC_HREADY : out vl_logic;
MAC_HRESP : out vl_logic;
PDMA_HADDR : in vl_logic_vector(31 downto 0);
PDMA_HSIZE : in vl_logic_vector(2 downto 0);
PDMA_HTRANS1 : in vl_logic;
PDMA_HWDATA : in vl_logic_vector(31 downto 0);
PDMA_HWRITE : in vl_logic;
PDMA_HRDATA : out vl_logic_vector(31 downto 0);
PDMA_HREADY : out vl_logic;
PDMA_HRESP : out vl_logic;
ESRAM0_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM0_HREADYOUT: in vl_logic;
ESRAM0_HRESP : in vl_logic;
ESRAM0_HADDR : out vl_logic_vector(31 downto 0);
ESRAM0_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM0_HTRANS1 : out vl_logic;
ESRAM0_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM0_HWRITE : out vl_logic;
ESRAM0_HSEL : out vl_logic;
ESRAM0_HREADY : out vl_logic;
ESRAM1_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM1_HREADYOUT: in vl_logic;
ESRAM1_HRESP : in vl_logic;
ESRAM1_HADDR : out vl_logic_vector(31 downto 0);
ESRAM1_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM1_HTRANS1 : out vl_logic;
ESRAM1_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM1_HWRITE : out vl_logic;
ESRAM1_HSEL : out vl_logic;
ESRAM1_HREADY : out vl_logic;
ENVM_HRDATA : in vl_logic_vector(31 downto 0);
ENVM_HREADYOUT : in vl_logic;
ENVM_HRESP : in vl_logic;
ENVM_HADDR : out vl_logic_vector(31 downto 0);
ENVM_HSIZE : out vl_logic_vector(2 downto 0);
ENVM_HTRANS1 : out vl_logic;
ENVM_HWDATA : out vl_logic_vector(31 downto 0);
ENVM_HWRITE : out vl_logic;
ENVM_HSEL : out vl_logic;
ENVM_HREADY : out vl_logic;
EM_HRDATA : in vl_logic_vector(31 downto 0);
EM_HREADYOUT : in vl_logic;
EM_HRESP : in vl_logic;
EM_HADDR : out vl_logic_vector(31 downto 0);
EM_HSIZE : out vl_logic_vector(2 downto 0);
EM_HTRANS1 : out vl_logic;
EM_HWDATA : out vl_logic_vector(31 downto 0);
EM_HWRITE : out vl_logic;
EM_HSEL : out vl_logic;
EM_HREADY : out vl_logic;
ACE_HRDATA : in vl_logic_vector(31 downto 0);
ACE_HREADYOUT : in vl_logic;
ACE_HRESP : in vl_logic;
ACE_HADDR : out vl_logic_vector(31 downto 0);
ACE_HSIZE : out vl_logic_vector(2 downto 0);
ACE_HTRANS1 : out vl_logic;
ACE_HREADY : out vl_logic;
ACE_HWDATA : out vl_logic_vector(31 downto 0);
ACE_HWRITE : out vl_logic;
ACE_HSEL : out vl_logic;
DS_HM_HRDATA : in vl_logic_vector(31 downto 0);
DS_HM_HREADYOUT : in vl_logic;
DS_HM_HRESP : in vl_logic;
DS_HM_HADDR : out vl_logic_vector(31 downto 0);
DS_HM_HSIZE : out vl_logic_vector(2 downto 0);
DS_HM_HTRANS1 : out vl_logic;
DS_HM_HSEL : out vl_logic;
DS_HM_HWRITE : out vl_logic;
DS_HM_HWDATA : out vl_logic_vector(31 downto 0);
DS_HM_HREADY : out vl_logic;
DS_HM_HMASTLOCK : out vl_logic;
PER0_HRDATA : in vl_logic_vector(31 downto 0);
PER0_HREADYOUT : in vl_logic;
PER0_HRESP : in vl_logic;
PER0_HADDR : out vl_logic_vector(31 downto 0);
PER0_HSIZE : out vl_logic_vector(2 downto 0);
PER0_HTRANS1 : out vl_logic;
PER0_HREADY : out vl_logic;
PER0_HWDATA : out vl_logic_vector(31 downto 0);
PER0_HWRITE : out vl_logic;
PER0_HSEL : out vl_logic;
PER1_HRDATA : in vl_logic_vector(31 downto 0);
PER1_HREADYOUT : in vl_logic;
PER1_HRESP : in vl_logic;
PER1_HADDR : out vl_logic_vector(31 downto 0);
PER1_HSIZE : out vl_logic_vector(2 downto 0);
PER1_HTRANS1 : out vl_logic;
PER1_HREADY : out vl_logic;
PER1_HWDATA : out vl_logic_vector(31 downto 0);
PER1_HWRITE : out vl_logic;
PER1_HSEL : out vl_logic
);
end F2DSS_COMMSMATRIX;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_COMMSMATRIX is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_ENVMFABREMAPBASE: in vl_logic_vector(19 downto 0);
COM_PROTREGIONSIZE: in vl_logic_vector(4 downto 0);
COM_PROTREGIONBASE: in vl_logic_vector(31 downto 0);
COM_MASTERENABLE: in vl_logic_vector(2 downto 0);
COM_CLEARSTATUS : in vl_logic_vector(4 downto 0);
COM_WEIGHTEDMODE: in vl_logic;
COM_ERRORSTATUS : out vl_logic_vector(4 downto 0);
COM_ERRORINTERRUPT: out vl_logic;
M3_HADDRI : in vl_logic_vector(31 downto 0);
M3_HTRANSI1 : in vl_logic;
M3_HSIZEI : in vl_logic_vector(2 downto 0);
M3_HADDRD : in vl_logic_vector(31 downto 0);
M3_HTRANSD1 : in vl_logic;
M3_HWRITED : in vl_logic;
M3_HSIZED : in vl_logic_vector(2 downto 0);
M3_HWDATAD : in vl_logic_vector(31 downto 0);
M3_HRDATAI : out vl_logic_vector(31 downto 0);
M3_HREADYI : out vl_logic;
M3_HRESPI : out vl_logic;
M3_HRDATAD : out vl_logic_vector(31 downto 0);
M3_HREADYD : out vl_logic;
M3_HRESPD : out vl_logic;
M3_HADDRS : in vl_logic_vector(31 downto 0);
M3_HTRANSS1 : in vl_logic;
M3_HWRITES : in vl_logic;
M3_HSIZES : in vl_logic_vector(2 downto 0);
M3_HWDATAS : in vl_logic_vector(31 downto 0);
M3_HMASTLOCKS : in vl_logic;
M3_HRDATAS : out vl_logic_vector(31 downto 0);
M3_HREADYS : out vl_logic;
M3_HRESPS : out vl_logic;
DS_FM_HADDR : in vl_logic_vector(31 downto 0);
DS_FM_HMASTLOCK : in vl_logic;
DS_FM_HSIZE : in vl_logic_vector(2 downto 0);
DS_FM_HTRANS1 : in vl_logic;
DS_FM_HWRITE : in vl_logic;
DS_FM_HWDATA : in vl_logic_vector(31 downto 0);
DS_FM_HRDATA : out vl_logic_vector(31 downto 0);
DS_FM_HREADY : out vl_logic;
DS_FM_HRESP : out vl_logic;
MAC_HWRITE : in vl_logic;
MAC_HADDR : in vl_logic_vector(31 downto 0);
MAC_HTRANS1 : in vl_logic;
MAC_HSIZE : in vl_logic_vector(2 downto 0);
MAC_HWDATA : in vl_logic_vector(31 downto 0);
MAC_HRDATA : out vl_logic_vector(31 downto 0);
MAC_HREADY : out vl_logic;
MAC_HRESP : out vl_logic;
PDMA_HADDR : in vl_logic_vector(31 downto 0);
PDMA_HSIZE : in vl_logic_vector(2 downto 0);
PDMA_HTRANS1 : in vl_logic;
PDMA_HWDATA : in vl_logic_vector(31 downto 0);
PDMA_HWRITE : in vl_logic;
PDMA_HRDATA : out vl_logic_vector(31 downto 0);
PDMA_HREADY : out vl_logic;
PDMA_HRESP : out vl_logic;
ESRAM0_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM0_HREADYOUT: in vl_logic;
ESRAM0_HRESP : in vl_logic;
ESRAM0_HADDR : out vl_logic_vector(31 downto 0);
ESRAM0_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM0_HTRANS1 : out vl_logic;
ESRAM0_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM0_HWRITE : out vl_logic;
ESRAM0_HSEL : out vl_logic;
ESRAM0_HREADY : out vl_logic;
ESRAM1_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM1_HREADYOUT: in vl_logic;
ESRAM1_HRESP : in vl_logic;
ESRAM1_HADDR : out vl_logic_vector(31 downto 0);
ESRAM1_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM1_HTRANS1 : out vl_logic;
ESRAM1_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM1_HWRITE : out vl_logic;
ESRAM1_HSEL : out vl_logic;
ESRAM1_HREADY : out vl_logic;
ENVM_HRDATA : in vl_logic_vector(31 downto 0);
ENVM_HREADYOUT : in vl_logic;
ENVM_HRESP : in vl_logic;
ENVM_HADDR : out vl_logic_vector(31 downto 0);
ENVM_HSIZE : out vl_logic_vector(2 downto 0);
ENVM_HTRANS1 : out vl_logic;
ENVM_HWDATA : out vl_logic_vector(31 downto 0);
ENVM_HWRITE : out vl_logic;
ENVM_HSEL : out vl_logic;
ENVM_HREADY : out vl_logic;
EM_HRDATA : in vl_logic_vector(31 downto 0);
EM_HREADYOUT : in vl_logic;
EM_HRESP : in vl_logic;
EM_HADDR : out vl_logic_vector(31 downto 0);
EM_HSIZE : out vl_logic_vector(2 downto 0);
EM_HTRANS1 : out vl_logic;
EM_HWDATA : out vl_logic_vector(31 downto 0);
EM_HWRITE : out vl_logic;
EM_HSEL : out vl_logic;
EM_HREADY : out vl_logic;
ACE_HRDATA : in vl_logic_vector(31 downto 0);
ACE_HREADYOUT : in vl_logic;
ACE_HRESP : in vl_logic;
ACE_HADDR : out vl_logic_vector(31 downto 0);
ACE_HSIZE : out vl_logic_vector(2 downto 0);
ACE_HTRANS1 : out vl_logic;
ACE_HREADY : out vl_logic;
ACE_HWDATA : out vl_logic_vector(31 downto 0);
ACE_HWRITE : out vl_logic;
ACE_HSEL : out vl_logic;
DS_HM_HRDATA : in vl_logic_vector(31 downto 0);
DS_HM_HREADYOUT : in vl_logic;
DS_HM_HRESP : in vl_logic;
DS_HM_HADDR : out vl_logic_vector(31 downto 0);
DS_HM_HSIZE : out vl_logic_vector(2 downto 0);
DS_HM_HTRANS1 : out vl_logic;
DS_HM_HSEL : out vl_logic;
DS_HM_HWRITE : out vl_logic;
DS_HM_HWDATA : out vl_logic_vector(31 downto 0);
DS_HM_HREADY : out vl_logic;
DS_HM_HMASTLOCK : out vl_logic;
PER0_HRDATA : in vl_logic_vector(31 downto 0);
PER0_HREADYOUT : in vl_logic;
PER0_HRESP : in vl_logic;
PER0_HADDR : out vl_logic_vector(31 downto 0);
PER0_HSIZE : out vl_logic_vector(2 downto 0);
PER0_HTRANS1 : out vl_logic;
PER0_HREADY : out vl_logic;
PER0_HWDATA : out vl_logic_vector(31 downto 0);
PER0_HWRITE : out vl_logic;
PER0_HSEL : out vl_logic;
PER1_HRDATA : in vl_logic_vector(31 downto 0);
PER1_HREADYOUT : in vl_logic;
PER1_HRESP : in vl_logic;
PER1_HADDR : out vl_logic_vector(31 downto 0);
PER1_HSIZE : out vl_logic_vector(2 downto 0);
PER1_HTRANS1 : out vl_logic;
PER1_HREADY : out vl_logic;
PER1_HWDATA : out vl_logic_vector(31 downto 0);
PER1_HWRITE : out vl_logic;
PER1_HSEL : out vl_logic
);
end F2DSS_COMMSMATRIX;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_COMMSMATRIX is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_ENVMFABREMAPBASE: in vl_logic_vector(19 downto 0);
COM_PROTREGIONSIZE: in vl_logic_vector(4 downto 0);
COM_PROTREGIONBASE: in vl_logic_vector(31 downto 0);
COM_MASTERENABLE: in vl_logic_vector(2 downto 0);
COM_CLEARSTATUS : in vl_logic_vector(4 downto 0);
COM_WEIGHTEDMODE: in vl_logic;
COM_ERRORSTATUS : out vl_logic_vector(4 downto 0);
COM_ERRORINTERRUPT: out vl_logic;
M3_HADDRI : in vl_logic_vector(31 downto 0);
M3_HTRANSI1 : in vl_logic;
M3_HSIZEI : in vl_logic_vector(2 downto 0);
M3_HADDRD : in vl_logic_vector(31 downto 0);
M3_HTRANSD1 : in vl_logic;
M3_HWRITED : in vl_logic;
M3_HSIZED : in vl_logic_vector(2 downto 0);
M3_HWDATAD : in vl_logic_vector(31 downto 0);
M3_HRDATAI : out vl_logic_vector(31 downto 0);
M3_HREADYI : out vl_logic;
M3_HRESPI : out vl_logic;
M3_HRDATAD : out vl_logic_vector(31 downto 0);
M3_HREADYD : out vl_logic;
M3_HRESPD : out vl_logic;
M3_HADDRS : in vl_logic_vector(31 downto 0);
M3_HTRANSS1 : in vl_logic;
M3_HWRITES : in vl_logic;
M3_HSIZES : in vl_logic_vector(2 downto 0);
M3_HWDATAS : in vl_logic_vector(31 downto 0);
M3_HMASTLOCKS : in vl_logic;
M3_HRDATAS : out vl_logic_vector(31 downto 0);
M3_HREADYS : out vl_logic;
M3_HRESPS : out vl_logic;
DS_FM_HADDR : in vl_logic_vector(31 downto 0);
DS_FM_HMASTLOCK : in vl_logic;
DS_FM_HSIZE : in vl_logic_vector(2 downto 0);
DS_FM_HTRANS1 : in vl_logic;
DS_FM_HWRITE : in vl_logic;
DS_FM_HWDATA : in vl_logic_vector(31 downto 0);
DS_FM_HRDATA : out vl_logic_vector(31 downto 0);
DS_FM_HREADY : out vl_logic;
DS_FM_HRESP : out vl_logic;
MAC_HWRITE : in vl_logic;
MAC_HADDR : in vl_logic_vector(31 downto 0);
MAC_HTRANS1 : in vl_logic;
MAC_HSIZE : in vl_logic_vector(2 downto 0);
MAC_HWDATA : in vl_logic_vector(31 downto 0);
MAC_HRDATA : out vl_logic_vector(31 downto 0);
MAC_HREADY : out vl_logic;
MAC_HRESP : out vl_logic;
PDMA_HADDR : in vl_logic_vector(31 downto 0);
PDMA_HSIZE : in vl_logic_vector(2 downto 0);
PDMA_HTRANS1 : in vl_logic;
PDMA_HWDATA : in vl_logic_vector(31 downto 0);
PDMA_HWRITE : in vl_logic;
PDMA_HRDATA : out vl_logic_vector(31 downto 0);
PDMA_HREADY : out vl_logic;
PDMA_HRESP : out vl_logic;
ESRAM0_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM0_HREADYOUT: in vl_logic;
ESRAM0_HRESP : in vl_logic;
ESRAM0_HADDR : out vl_logic_vector(31 downto 0);
ESRAM0_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM0_HTRANS1 : out vl_logic;
ESRAM0_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM0_HWRITE : out vl_logic;
ESRAM0_HSEL : out vl_logic;
ESRAM0_HREADY : out vl_logic;
ESRAM1_HRDATA : in vl_logic_vector(31 downto 0);
ESRAM1_HREADYOUT: in vl_logic;
ESRAM1_HRESP : in vl_logic;
ESRAM1_HADDR : out vl_logic_vector(31 downto 0);
ESRAM1_HSIZE : out vl_logic_vector(2 downto 0);
ESRAM1_HTRANS1 : out vl_logic;
ESRAM1_HWDATA : out vl_logic_vector(31 downto 0);
ESRAM1_HWRITE : out vl_logic;
ESRAM1_HSEL : out vl_logic;
ESRAM1_HREADY : out vl_logic;
ENVM_HRDATA : in vl_logic_vector(31 downto 0);
ENVM_HREADYOUT : in vl_logic;
ENVM_HRESP : in vl_logic;
ENVM_HADDR : out vl_logic_vector(31 downto 0);
ENVM_HSIZE : out vl_logic_vector(2 downto 0);
ENVM_HTRANS1 : out vl_logic;
ENVM_HWDATA : out vl_logic_vector(31 downto 0);
ENVM_HWRITE : out vl_logic;
ENVM_HSEL : out vl_logic;
ENVM_HREADY : out vl_logic;
EM_HRDATA : in vl_logic_vector(31 downto 0);
EM_HREADYOUT : in vl_logic;
EM_HRESP : in vl_logic;
EM_HADDR : out vl_logic_vector(31 downto 0);
EM_HSIZE : out vl_logic_vector(2 downto 0);
EM_HTRANS1 : out vl_logic;
EM_HWDATA : out vl_logic_vector(31 downto 0);
EM_HWRITE : out vl_logic;
EM_HSEL : out vl_logic;
EM_HREADY : out vl_logic;
ACE_HRDATA : in vl_logic_vector(31 downto 0);
ACE_HREADYOUT : in vl_logic;
ACE_HRESP : in vl_logic;
ACE_HADDR : out vl_logic_vector(31 downto 0);
ACE_HSIZE : out vl_logic_vector(2 downto 0);
ACE_HTRANS1 : out vl_logic;
ACE_HREADY : out vl_logic;
ACE_HWDATA : out vl_logic_vector(31 downto 0);
ACE_HWRITE : out vl_logic;
ACE_HSEL : out vl_logic;
DS_HM_HRDATA : in vl_logic_vector(31 downto 0);
DS_HM_HREADYOUT : in vl_logic;
DS_HM_HRESP : in vl_logic;
DS_HM_HADDR : out vl_logic_vector(31 downto 0);
DS_HM_HSIZE : out vl_logic_vector(2 downto 0);
DS_HM_HTRANS1 : out vl_logic;
DS_HM_HSEL : out vl_logic;
DS_HM_HWRITE : out vl_logic;
DS_HM_HWDATA : out vl_logic_vector(31 downto 0);
DS_HM_HREADY : out vl_logic;
DS_HM_HMASTLOCK : out vl_logic;
PER0_HRDATA : in vl_logic_vector(31 downto 0);
PER0_HREADYOUT : in vl_logic;
PER0_HRESP : in vl_logic;
PER0_HADDR : out vl_logic_vector(31 downto 0);
PER0_HSIZE : out vl_logic_vector(2 downto 0);
PER0_HTRANS1 : out vl_logic;
PER0_HREADY : out vl_logic;
PER0_HWDATA : out vl_logic_vector(31 downto 0);
PER0_HWRITE : out vl_logic;
PER0_HSEL : out vl_logic;
PER1_HRDATA : in vl_logic_vector(31 downto 0);
PER1_HREADYOUT : in vl_logic;
PER1_HRESP : in vl_logic;
PER1_HADDR : out vl_logic_vector(31 downto 0);
PER1_HSIZE : out vl_logic_vector(2 downto 0);
PER1_HTRANS1 : out vl_logic;
PER1_HREADY : out vl_logic;
PER1_HWDATA : out vl_logic_vector(31 downto 0);
PER1_HWRITE : out vl_logic;
PER1_HSEL : out vl_logic
);
end F2DSS_COMMSMATRIX;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umc_components
-- File: umc_components.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC 0.18 component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umc_components is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
-- single-port memory
component SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
end;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- WB SLAVE SINGLE REGISTER TESTBENCH (wb_slave_single_reg_tb.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wb_slave_single_reg_comp.all;
-------------------------------------------------------------------------------
ENTITY wb_slave_single_reg_tb is
-------------------------------------------------------------------------------
begin
end wb_slave_single_reg_tb;
-------------------------------------------------------------------------------
ARCHITECTURE simulation of wb_slave_single_reg_tb is
-------------------------------------------------------------------------------
-- constants
constant CLK_PERIOD : time := 10 ns;
-- signals
signal clk : std_logic;
signal rst : std_logic;
signal uut_in : wb_slave_in_type;
signal uut_out : wb_slave_out_type;
begin
-------------------------------------------------
STIMULI_PROC :
-------------------------------------------------
process begin
-- hold reset for 100 ns and 10 clock cycles
rst <= '1';
uut_in.dat_i <= (others => '0');
uut_in.adr_i <= (others => '0');
uut_in.stb_i <= '0';
uut_in.we_i <= '0';
wait for 100 ns;
rst <= '0';
wait for CLK_PERIOD*10;
-- single write
assert false report "Perform single write" severity note;
uut_in.dat_i <= x"FFFFFFFF";
uut_in.adr_i <= std_logic_vector(to_unsigned(15,32));
uut_in.stb_i <= '1';
uut_in.we_i <= '1';
wait for CLK_PERIOD;
if (uut_out.ack_o = '0') then wait until uut_out.ack_o = '1'; end if;
uut_in.stb_i <= '0';
wait for CLK_PERIOD;
-- single write (wrong address)
assert false report "Perform single write with wrong address" severity note;
uut_in.dat_i <= x"00000000";
uut_in.adr_i <= std_logic_vector(to_unsigned(10,32));
uut_in.stb_i <= '1';
uut_in.we_i <= '1';
wait for CLK_PERIOD;
if (uut_out.ack_o = '0') then wait until uut_out.ack_o = '1'; end if;
uut_in.stb_i <= '0';
wait for CLK_PERIOD;
-- single read
assert false report "Perform single read" severity note;
uut_in.adr_i <= std_logic_vector(to_unsigned(15,32));
uut_in.stb_i <= '1';
uut_in.we_i <= '0';
wait for CLK_PERIOD;
if (uut_out.ack_o = '0') then wait until uut_out.ack_o = '1'; end if;
uut_in.stb_i <= '0';
wait for CLK_PERIOD;
wait; -- forever
end process STIMULI_PROC;
-------------------------------------------------
-- UUT instantiation
-------------------------------------------------
UUT : entity work.wb_slave_single_reg
generic map (
register_address => to_unsigned(15,32)
)
port map (
clk_i => clk,
rst_i => rst,
wb_in => uut_in,
wb_out=> uut_out
);
-------------------------------------------------
CLK_GENERATOR :
-------------------------------------------------
process begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLK_GENERATOR;
end simulation;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.