content stringlengths 1 1.04M ⌀ |
|---|
--******************************************************************************--
-- Author: Weihao Ming --
-- Date: 2014-01-13 --
-- Module: EE3A1 RISC Microprocessor --
-- Description: Re-order buffer. Placing before instruction decoder --
-- and automatic re-order ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
library ieee;
use ieee.std_logic_1164.all;
entity FA10_tb is
end FA10_tb;
architecture tb of FA10_tb is
component FA10
port(
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0);
Sout : out std_logic_vector(9 downto 0);
Cout : out st... |
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty.... |
--
-- Grab bag of miscellaneous VHDL-2008 syntax
--
entity vhdl2008 is
end entity;
package genpack is
generic ( x : integer := 5; y : boolean ); -- OK
generic map ( x => 5, y => false ); -- OK
constant c : bit_vector(1 to x) := (1 to x => '1');
end package;
package genpack2 is
generic ( x :... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_extract_header - Behavioral
--
-- Description: Extract the TCP header fields
--
------------------------------------------------------------------------------------
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:26:49 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBCU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versi... |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eithe... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:15 09/10/2016
-- Design Name:
-- Module Name: C:/Users/Yoshio/git/ecorun/ecorun_fi_hardware/fi_timer/FiTimer/TestStepper.vhd
-- Project Name: FiTimer
-- Target Device:
-- Tool ve... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:49:32 06/15/2015
-- Design Name:
-- Module Name: Stepper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_975;
architecture augh of cmp_975 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_975;
architecture augh of cmp_975 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VE... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VE... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VE... |
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port
(i_foo : in std_logic;
o_foo : out std_logic;
clock : in std_logic);
end entity issue;
architecture beh of issue is
begin
process (clock)
variable v_foo : std_logic := i_foo;
begin
-- works without the if... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BiStableLatch is port(
Q : out std_logic;
nQ : out std_logic
);
end BiStableLatch;
architecture structual of BiStableLatch is
component NOT1 is port(
a: in std_logic;
z: out std_logic);
end component;
component REP is port(
a: in std_logic;
z: out... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity frame_buffer is
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA ... |
-- DATASHEET: https://drive.google.com/open?id=0BxW0H68Pf2sKWXYxVkhYYUw2dVE
--timer mode reset is needed before timer starts.
-- clock : input
-- reset : input
-- data_in[]: input params [5], input address_base [22]
-- params : input [3]
-- read_params : input
-- write_params : input
-- reconfig : input
-- reset_timer ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end entity priority_enc... |
-- 1 bit synchronizer based of n flip-flops for clock-domain crossings.
-- drive constant `data_in` to use as a reset synchronizer
--
-- Original author: Colm Ryan
--
-- Copyright (c) 2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
generic (
RESET_VALUE : std_... |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- this block decode the Non-Return-to-Zero Inverted encoded data on USB bus.
ENTITY NRZIdecode is
port(clk, rst, data0: IN STD_LOGIC; -- data0 = data+, data1 = data-, clk goes to normal clock
enable: IN STD_LOGIC; -- when this line is high (for a clock cycle), the dec... |
entity func_test3 is
generic (NBITS: natural := 6);
end entity;
architecture fum of func_test3 is
type remains is (r0, r1, r2, r3, r4); -- remainder values
function mod5 (dividend: bit_vector) return boolean is
type remain_array is array (NBITS downto 0) of remains;
type branch is array (r... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
--========================================================================
-- mytypes.vhd :: Nova global type definitions
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
package my_types... |
-- NEED RESULT: ARCH00094.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094.P2: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094.P3: Multi transport transactions occurred on signal asg with s... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_impl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_impl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_impl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_impl... |
-- $Id: sys_conf_ba3_msim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Defini... |
-------------------------------------------------------------------------------
--
-- $Id$
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Oct 18 11:23:39 2017
-- Host : vldmr-PC running 64-bit Service ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:58 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity snum04 is
port (ok : out boolean);
end snum04;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum04 is
-- add uns nat
constant a1 : unsigned (7 downto 0) := x"1d";
constant b1 : unsigned (3 downto 0) := x"5";
constant r1 : unsigned (11 downto 0) := a1 * b... |
entity sub is
generic ( W : natural );
port ( o : out bit_vector(1 to 2);
p : in bit_vector(1 to W) );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity directmap3 is
end entity;
architecture test... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.fLink_definitions.ALL;
entity loopbackDevice_v1_0_S00_AXI is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyon... |
-------------------------------------------------------------------------------
--
-- $Id$
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity complemento4 is
Port ( entrada : in STD_LOGIC_VECTOR (3 downto 0) := "0000";
sel : in STD_LOGIC := '1';
saida : out STD_LOGIC_VECTOR (3 downto 0)
);
end complemento4;
architecture Behavioral of complemento4 is
signal aux : STD_LOGIC_VECT... |
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
---------------------------------------------------------------------------
-- edge-detector.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- ... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
end entity FIFO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
------------------------------------
-- 32 BIT CARRY LOOK AHEAD ADDER --
-- PORT MAPPING --
-- A : 32 bit input value --
-- B : 32 bit input value --
-- CIN : 1 bit input carry --
------------------------------------
-- C : 32 bit output value A+B --
-- COUT : 1 bit output c... |
-------------------------------------------------------------------------------
--! @file onewire_control.vhd
--! @author Johannes Walter <johannes@greenshire.io>
--! @copyright LGPL v2.1
--! @brief Control all 1-wire interfaces.
------------------------------------------------------------------------------... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:04 2017
-- Host : EffulgentTome running 64-bit maj... |
-- Fichier : clk_exemple.vhdl
-- created by Yann Guidon / ygdes.com
-- jeu. avril 15 15:28:24 CEST 2010
-- jeu. avril 15 21:05:36 CEST 2010
-- clk_exemple.vhdl : just an example for the use of the synchronised clock generator
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute i... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : std_logic;
I_DATA : std_logic_vector(31 downto 0);
I_RD_EN : std_logi... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY instruction_memory_tb IS
END instruction_memory_tb;
ARCHITECTURE behavior OF instruction_memory_tb IS
constant PROGRAM_FILENAME : string := "F:\Projects\MyStuff\TIS100\Assembler\multiply.prg";
-- Component Declaration for the Unit Under Test (UUT)
CO... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <n3vu0r@qu1x.org>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 Novem... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.08.2013 13:49:00
-- Design Name:
-- Module Name: main_sim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of FIFO is
function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
function func1 return integer is
begin
end function func1;
-- Violations follow
function func1 return integer;
function func1 return integer;
pure function ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietar... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietar... |
----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.package1.ALL;
entity top1 is
port(
clk : in std_logic;
rst : in std_logic;
en ... |
-- Package for helping to implement midi synthesis on an FPGA
-- Midi enumerates musical notes. This package contains functions to help
-- implementation of this on an FPGA.
--
-- To generate notes, we will generate sine waves. this will be implemented
-- using lookup tables which store sin(x).
--
-- the following char... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_136 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_136;
architecture augh of cmp_136 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_136 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_136;
architecture augh of cmp_136 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
------------------ Dataflow_HA ------------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder_dataflow --
entity half_adder_dataflow is
port (a, b : in std_logic;
sum, carry : out std_logic
);
end half_adder_dataflow;
... |
------------------ Dataflow_HA ------------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder_dataflow --
entity half_adder_dataflow is
port (a, b : in std_logic;
sum, carry : out std_logic
);
end half_adder_dataflow;
... |
library verilog;
use verilog.vl_types.all;
entity altera_reset_controller is
generic(
NUM_RESET_INPUTS: integer := 6;
USE_RESET_REQUEST_IN0: integer := 0;
USE_RESET_REQUEST_IN1: integer := 0;
USE_RESET_REQUEST_IN2: integer := 0;
USE_RESET_REQUEST_IN3: integer := 0;
US... |
library verilog;
use verilog.vl_types.all;
entity altera_reset_controller is
generic(
NUM_RESET_INPUTS: integer := 6;
USE_RESET_REQUEST_IN0: integer := 0;
USE_RESET_REQUEST_IN1: integer := 0;
USE_RESET_REQUEST_IN2: integer := 0;
USE_RESET_REQUEST_IN3: integer := 0;
US... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../rtl/dummy_ctrl_regs.vhd
-- Author : auto-gene... |
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