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-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
library ieee;
use ieee.std_logic_1164.all;
entity tb_output01 is
end tb_output01;
architecture behav of tb_output01 is
signal i : std_logic;
signal o : std_logic_vector (1 downto 0);
begin
inst: entity work.output01
port map (i => i, o => o);
process
begin
i <= '0';
wait for 1 ns;
assert o ... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:25:38 11/17/2013
-- Design Name:
-- Module Name: My_4x1Mux_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- Wraps ComBlock 5402 server into something more AXI compatible
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com5402pkg.all; -- defines global types, number of TCP streams, etc
use work.com5402_wrapper_pkg.all;
entity com5402_wrapper is
generic (
SIMULATION : std_logic := '0';
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
----------------------------... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity LFSR15 is
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(14 downto 0)
);
end LFSR15;
architecture RTL of LFSR15 is
signal FEEDBACK : std_logic;
signal SR : std_logic_vector(14 downto 0);
begin
RAN... |
-- Copyright (c) 2017-2019 Tampere University of Technology.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without res... |
-- Copyright (c) 2017-2019 Tampere University of Technology.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without res... |
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. ... |
-- Copyright (c) 2009 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_bit.all;
use work.all;
use work.YaGraphConPackage.all;
entity YaGraphCon is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural
);
port(
-- ... |
-- NEED RESULT: ARCH00397.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00397.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00397: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH0039... |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_propos... |
package pkg_c is
type byte_vector_access_t is access string;
type extbuf_access_t is access string(1 to integer'high);
impure function
get_addr(
id : integer
) return extbuf_access_t;
attribute foreign of get_addr : function is "VHPIDIRECT get_addr";
impure function
get_baddr(
id : integer
... |
-- lcdctrl.vhd : High-level LCD controller with BUSY
-- Copyright (C) 2011/2012 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
--
-- LICENSE TERMS
--
-- Redistribution and use in source and binary forms, with or without... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gr is
port(clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(15 downto 0);
... |
-------------------------------------------------------------------------------
-- Title : Memory that is simulated with predefined values
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Si... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2; -- This comment is okay
end process;
-- Violations below
process
begin
sig1 <= sig2 and
-- Some comment
sig3 or -- This comment is okay
-- other comment
sig4;
end process;
end architecture RTL;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Rea... |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Rea... |
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use work.UtilityPkg.all;
entity GtpS6 is
generic (
-- Reference clock selection --
-- 000: CLK00/CLK01 selected
-- 001: GCLK00/GCLK01 selected
-- 010: PLLCLK00/PLLCLK01 selected... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major releas... |
-- LEON4 Statistics Module
constant CFG_STAT_ENABLE : integer := CONFIG_STAT_ENABLE;
constant CFG_STAT_CNT : integer := CONFIG_STAT_CNT;
constant CFG_STAT_NMAX : integer := CONFIG_STAT_NMAX;
|
-------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package TIA_NTSCLookups is
constant sync_level: unsigned(7 downto 0) := X"05";--was 05 is 0
constant blank_level: unsigned(7 downto 0) := X"5a";--was 5a is 41
type lum_lut_type is array (0 to 7) of unsigned(7 downto 0);
constant lum_lut... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_880;
architecture augh of cmp_880 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_880;
architecture augh of cmp_880 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- ... |
------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:32 2017
-- Host : DarkCube running 64-bit major releas... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 11:21:36 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.tube_comp_pack.all;
entity CoProSPI is
port (
-- Host
h_clk : in std_logic;
h_cs_b : in std_logic;
h_rdnw : in std_logic;
h_addr : in ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
target :=
expr1 when condition1 else
expr2 when condition2 else
...
exprN when conditionN;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY SimpleUnit_b IS
PORT(a : IN STD_LOGIC;
b : OUT STD_LOGIC
);
END SimpleUnit_b;
ARCHITECTURE rtl OF SimpleUnit_b IS
BEGIN
b <= a;
END ARCHITECTURE rtl; |
package p is
type UNSIGNED is array (NATURAL range <>) of bit;
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
end package;
package body p is
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
package encoder_module_pkg is
type encoder_type is record
a : std_logic;
b : std_logic;
end record encoder_type;
component encoder_module
generic (
BASE_ADDRESS : integ... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
package encoder_module_pkg is
type encoder_type is record
a : std_logic;
b : std_logic;
end record encoder_type;
component encoder_module
generic (
BASE_ADDRESS : integ... |
architecture RTL of FIFO is begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
signal a : std_logic;
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is -- Comment
signal a : std_logic;
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is... |
library ieee;
use ieee.std_logic_1164.all;
use work.decode_pkg.all;
use work.common.all;
use work.encode_pkg.all;
entity decoder_tb is
end entity decoder_tb;
architecture testbench of decoder_tb is
-- inputs
signal insn : word;
-- outputs
signal decoded : decoded_t;
procedure verify_r_type (i... |
library ieee;
use ieee.std_logic_1164.all;
use work.decode_pkg.all;
use work.common.all;
use work.encode_pkg.all;
entity decoder_tb is
end entity decoder_tb;
architecture testbench of decoder_tb is
-- inputs
signal insn : word;
-- outputs
signal decoded : decoded_t;
procedure verify_r_type (i... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_cell IS
GENERIC(width : positive);
PORT(
SEL, WE : IN std_logic;
D_IN : IN std_logic_vector(width-1 DOWNTO 0);
D_OUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END sram_cell;
ARCHITECTURE primitive OF sram_cell IS
SIGNAL B : std_logic... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_cell IS
GENERIC(width : positive);
PORT(
SEL, WE : IN std_logic;
D_IN : IN std_logic_vector(width-1 DOWNTO 0);
D_OUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END sram_cell;
ARCHITECTURE primitive OF sram_cell IS
SIGNAL B : std_logic... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_cell IS
GENERIC(width : positive);
PORT(
SEL, WE : IN std_logic;
D_IN : IN std_logic_vector(width-1 DOWNTO 0);
D_OUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END sram_cell;
ARCHITECTURE primitive OF sram_cell IS
SIGNAL B : std_logic... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- rgb_in.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
entity rgb_in is
port (
VGA_CLK : ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VolCtrl is
generic(INTBIT_WIDTH : positive; -- := 24;
FRACBIT_WIDTH : positive --:= 8
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VolCtrl is
generic(INTBIT_WIDTH : positive; -- := 24;
FRACBIT_WIDTH : positive --:= 8
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VolCtrl is
generic(INTBIT_WIDTH : positive; -- := 24;
FRACBIT_WIDTH : positive --:= 8
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed... |
library verilog;
use verilog.vl_types.all;
entity regfile is
generic(
text_start : integer := 4194304
);
port(
rn_data : out vl_logic_vector(31 downto 0);
rm_data : out vl_logic_vector(31 downto 0);
rs_data : out vl_logic_vector(31 downto... |
library verilog;
use verilog.vl_types.all;
entity regfile is
generic(
text_start : integer := 4194304
);
port(
rn_data : out vl_logic_vector(31 downto 0);
rm_data : out vl_logic_vector(31 downto 0);
rs_data : out vl_logic_vector(31 downto... |
library verilog;
use verilog.vl_types.all;
entity regfile is
generic(
text_start : integer := 4194304
);
port(
rn_data : out vl_logic_vector(31 downto 0);
rm_data : out vl_logic_vector(31 downto 0);
rs_data : out vl_logic_vector(31 downto... |
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