content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity abs_1 is
port (
si : in std_logic_vector(4 downto 0);
smo : out std_logic_vector(4 downto 0);
se : in std_logic_vector (0 downto 0);
s : in std_logic_vector (0 downto 0)
);
end entity;
architecture behav of abs_1 is
signal nsi :... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-------------------------------------------------------------------------------
--
-- T48 Microcontroller Core
--
-- $Id: t48_core.vhd,v 1.12 2006-07-14 01:12:08 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistr... |
--Frequency Divider
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIV_FREQ IS
PORT( CLK_IN_1HZ :IN STD_LOGIC;
RST :IN STD_LOGIC;
CLK_OUT_05HZ:OUT STD_LOGIC);
END ENTITY DIV_FREQ;
ARCHITECTURE ART1 OF DIV_FREQ IS
BEGIN
PROCESS (CLK_IN_1HZ,... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a reset ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a reset ... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_addr_counter is
port (
clock : in std_logic;
load_value : in unsigned(25 downto 0);
do_load : in std_logic;
do_inc : in std_logic;
inc_by_4 : in std_logic;
address : out ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_addr_counter is
port (
clock : in std_logic;
load_value : in unsigned(25 downto 0);
do_load : in std_logic;
do_inc : in std_logic;
inc_by_4 : in std_logic;
address : out ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_addr_counter is
port (
clock : in std_logic;
load_value : in unsigned(25 downto 0);
do_load : in std_logic;
do_inc : in std_logic;
inc_by_4 : in std_logic;
address : out ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_517 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_517;
architecture augh of sub_517 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_517 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_517;
architecture augh of sub_517 is
signal carry_inA : std_l... |
entity sub is
port (
i : in bit_vector(0 to 7);
o : out bit_vector(0 to 7) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture te... |
entity sub is
port (
i : in bit_vector(0 to 7);
o : out bit_vector(0 to 7) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture te... |
entity sub is
port (
i : in bit_vector(0 to 7);
o : out bit_vector(0 to 7) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture te... |
entity sub is
port (
i : in bit_vector(0 to 7);
o : out bit_vector(0 to 7) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture te... |
entity sub is
port (
i : in bit_vector(0 to 7);
o : out bit_vector(0 to 7) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture te... |
library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then... |
-- Projeto gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: and3.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and3 is
port (a,b,c: in std_logic; y: out std_logic);
end and3;
architecture logica of and3 is
begin
-- C... |
library verilog;
use verilog.vl_types.all;
entity ex_stage is
port(
clk : in vl_logic;
reset : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
int_detect : in vl_logic;
fwd_data : out ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
entity mdim01 is
port (a0, a1 : std_logic_vector (3 downto 0);
o0 : out std_logic_vector (3 downto 0));
end mdim01;
architecture behav of mdim01 is
type t_matrix is array (0 to 1, 3 downto 0) of boolean;
constant mat : t_matrix :=
(0 => (3 => true, 2 => tru... |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that t... |
-------------------------------------------------------------------------------
-- Title : Vectoring-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_vectoring_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:00:23 11/19/2015
-- Design Name:
-- Module Name: ImageFilter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:37:19 2017
-- Host : vldmr-PC running 64-bit Service Pack... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may ... |
-- $Id: gsr_pulse_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: gsr_pulse - sim
-- Description: pulse GSR ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY signal_generator IS
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC; --unused
led: OUT STD_LOGIC;
clock_out : OUT STD_LOGIC);
END signal_generator;
ARCHITECTURE behavior of signal_generator IS
S... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_jed;
architecture behaviour of ex7_jed is
constant s1: std_logic_vector(3 downto 0) := "0101... |
entity array2 is
end entity;
architecture test of array2 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
begin
process is
variable a : int_array_Nx4(1 to 4);
variable b : int_array(1 to 4);
begin
a(1... |
entity array2 is
end entity;
architecture test of array2 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
begin
process is
variable a : int_array_Nx4(1 to 4);
variable b : int_array(1 to 4);
begin
a(1... |
entity array2 is
end entity;
architecture test of array2 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
begin
process is
variable a : int_array_Nx4(1 to 4);
variable b : int_array(1 to 4);
begin
a(1... |
entity array2 is
end entity;
architecture test of array2 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
begin
process is
variable a : int_array_Nx4(1 to 4);
variable b : int_array(1 to 4);
begin
a(1... |
entity array2 is
end entity;
architecture test of array2 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
begin
process is
variable a : int_array_Nx4(1 to 4);
variable b : int_array(1 to 4);
begin
a(1... |
-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Found... |
-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Found... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity ent is
end entity;
architecture a of ent is
type boolean_vec_t is array (integer range <>) of boolean;
function resolved(vec : boolean_vec_t) return boolean is
begin
return true;
end function;
subtype resolved_boolean_t is resolved boolean;
signal sig : resolved_boolean_t;
begin
main : pro... |
entity ent is
end entity;
architecture a of ent is
type boolean_vec_t is array (integer range <>) of boolean;
function resolved(vec : boolean_vec_t) return boolean is
begin
return true;
end function;
subtype resolved_boolean_t is resolved boolean;
signal sig : resolved_boolean_t;
begin
main : pro... |
entity ent is
end entity;
architecture a of ent is
type boolean_vec_t is array (integer range <>) of boolean;
function resolved(vec : boolean_vec_t) return boolean is
begin
return true;
end function;
subtype resolved_boolean_t is resolved boolean;
signal sig : resolved_boolean_t;
begin
main : pro... |
-- Altera Microperipheral Reference Design Version 0802
--**********************************************************************************************
--
-- System: A8251
-- Component: Testbench top level
--
-- File: tb_a8251_top.vhd
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera... |
-------------------------------------------------------------------------------
--! @file openfilter-rtl-ea.vhd
--
--! @brief OpenFILTER
--
--! @details This is the openFILTER used for blocking failures on the RMII lines.
--! Note: RxDv and RxDat have to be synchron to iClk
--! The following Conditi... |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_TRFC : integer := CONFIG_DDR2SP_TRFC;
constant CFG_DDR2SP_DATAWIDTH : integer := C... |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_TRFC : integer := CONFIG_DDR2SP_TRFC;
constant CFG_DDR2SP_DATAWIDTH : integer := C... |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_TRFC : integer := CONFIG_DDR2SP_TRFC;
constant CFG_DDR2SP_DATAWIDTH : integer := C... |
-- DDR controller
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
constant CFG_DDR2SP_TRFC : integer := CONFIG_DDR2SP_TRFC;
constant CFG_DDR2SP_DATAWIDTH : integer := C... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity bounds is
end entity;
architecture test of bounds is
type foo is range 1 to 5;
type my_vec1 is array (positive range <>) of integer;
type my_vec2 is array (foo range <>) of integer;
signal s : my_vec1(1 to 10);
signal n : my_vec1(1 downto 10);
subtype bool_true is boolean range true to... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RISING_EDGE_DETECTOR
-- AUTHORS: Tomáš Bannert <xbanne00@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, p... |
library verilog;
use verilog.vl_types.all;
entity microc is
port(
clk : in vl_logic;
reset : in vl_logic;
s_inc : in vl_logic;
s_inm : in vl_logic;
we3 : in vl_logic;
s_es : in vl... |
package repro3_sortnet_tb is
generic (
DATA_BITS : positive
);
subtype T_DATA is bit_vector(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
procedure dec (v : inout natural);
end repro3_sortnet_tb;
package body repro3_sortnet_tb is
procedure dec (v : inout natura... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:23 01/22/2014
-- Design Name:
-- Module Name: Multiply16Booth4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- Testebench gerado via script.
-- Data: Sáb,31/12/2011-01:19:07
-- Autor: rogerio
-- Comentario: Teste da entidade nand2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nand2_tb is
end nand2_tb;
architecture logica of nand2_tb is
-- Declaração do componente.
component nand... |
-- ************************
-- * Archivo de Registros *
-- ************************
-- Usa indexado dinámico.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity archivo_reg is
generic(
DIR_ANCHO: integer:=2; -- Número de bits para la dirección
DATOS_ANCHO: integer:=8 -- Nú... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
archit... |
-- VHDL Entity r65c02_tc.regbank_axy.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 20:45:48 27.08.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity regbank_axy is... |
--------------------------------------------------------------------------------
-- Title : Burst-capable wishbone to AXI bridge
-- Project :
-------------------------------------------------------------------------------
-- File : wb_axiburst_bridge.vhd
-- Author : Jose Lopez
-- Company : U... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:27:57
-- Nombre del módulo: clk0_25Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproxima... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:27:57
-- Nombre del módulo: clk0_25Hz - Behavioral
-- Comentarios adicionales:
-- Implementación mediante aproxima... |
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Utility functions for CRC calculation
-- Inspired by "Automatic Generation of Parallel CRC Circuits" by Michael Sprachmann
library i... |
-------------------------------------------------------------------------------
-- Title : Add Channels
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Scale Channels with an factor and add
----------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKDE2NVCC is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKDE2NVCC is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKDE2NVCC is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKDE2NVCC is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic; ... |
library ieee;
use ieee.std_logic_1164.all;
entity lfsr_tb is
end entity lfsr_tb;
architecture bhr of lfsr_tb is
component lfsr is
generic(
init : in std_logic_vector(63 downto 0) := X"0000000000000001"
);
port(
clk : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
--
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequ... |
--
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequ... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
-- NEED RESULT: ARCH00435: Bit string literals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
... |
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