content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity deslocador_bit is
port (
);
end deslocador_bit;
architecture Behavioral of deslocador_bit is
begin
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity deslocador_bit is
port (
);
end deslocador_bit;
architecture Behavioral of deslocador_bit is
begin
end Behavioral;
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of th... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Fri Sep 22 20:11:26 2017
-- Host : vldmr-PC running 64-bit Service Pack... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
---------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:11:19 04/22/2016
-- Design Name:
-- Module Name: SH_PCREG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:11:19 04/22/2016
-- Design Name:
-- Module Name: SH_PCREG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:11:19 04/22/2016
-- Design Name:
-- Module Name: SH_PCREG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity FA is
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
COUT : out std_logic;
S : out std_logic
);
end FA;
architecture fa_estr of FA is
begin
COUT <= (A and B) or (A and C) or (C and B);
S <= ((not C) and (A xor B)) or (C and (A xnor B));
end ... |
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity circuit is
--generic declarations
port (
a: in std_logic;
b: in std_logic;
c: in std_logic;
clk: in std_logic;
reg_z: out std_logic);
end entity;
------------------... |
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file ... |
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file ... |
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
-- synthesis translate_off
library std;
use std.textio.all;
--use work.file_io_pkg.all;
-- synthesis translate_on
entity proc_registers is
generic (
vector_... |
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : entity fifo_dsn.INST1(rtl);
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
);
U_INST3 : INST3
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
POR... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
--
-- This file is part of IP_register
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version ... |
-- $Id: tb_s3board_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either v... |
--------------------------------------------------------------------------------
-- Company: Dossmatik GmbH
-- Create Date: 21:08:31 05/17/2011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench
-- test for VHPI
--------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- Company: Dossmatik GmbH
-- Create Date: 21:08:31 05/17/2011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench
-- test for VHPI
--------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- Title : R4B user core
-- Design : r4b
-- Author : Bulent Selek
-- Company : Best Bilgisayar ve Elektronik Sanayi Ticaret
--
-------------------------------------------------------------------------------
--
-- File : ts7300_usercore.v... |
entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
|
entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
|
entity paren3 is
end paren3;
architecture behav of paren3
is
subtype a is integer;
constant b : real := 3.15;
begin
assert a(b) = 3;
end behav;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
END if;
END if;
-- Violations below
if a = '1' t... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
-- Behavioral
entity SUMGENERATOR is
generic(
NBIT: integer := NSUMG; --32,64
NCSB: integer := NCSUMG --8,16
);
port (
A: in std_logic_vector(NBIT-1 downto 0);
B: in std_logic_vector(NBIT-1 ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* ... |
entity e is
end entity;
architecture a of e is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
-- report "v = " & to_string(v) severity note; -- works
-- repor... |
entity e is
end entity;
architecture a of e is
begin
process
type LongInteger is range -2**47 to 2**47-1;
variable v : LongInteger;
begin
v := 12345678901;
report "v = " & LongInteger'image(v) severity note;
-- report "v = " & to_string(v) severity note; -- works
-- repor... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Mon Nov 30 13:52:22 2015
-- Host : centennial.andrew.cmu.edu running 64... |
-- NEED RESULT: ARCH00410.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00410: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00410: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00410: One i... |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_In_Deserializer.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **************************... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin end block BLOCK_LABEL;
-- Violations below
BLOCK_LABEL : block is begin end block BLOCK_LABEL;
end architecture RTL;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_8_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_8_e-... |
entity case1 is
end;
architecture behav of case1 is
begin
process
begin
for i in 1 to 10 loop
case i is
when 1 =>
report "one";
wait for 1 ns;
when 2 =>
report "two";
wait for 2 ns;
when 3 =>
report "three";
wait for 3 ns... |
entity case1 is
end;
architecture behav of case1 is
begin
process
begin
for i in 1 to 10 loop
case i is
when 1 =>
report "one";
wait for 1 ns;
when 2 =>
report "two";
wait for 2 ns;
when 3 =>
report "three";
wait for 3 ns... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_PCSOURCE is
Port ( PCdisp30 : in STD_LOGIC_VECTOR (31 downto 0);
PCSEUdisp22 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR(31 downto 0);
PCSOURCE : i... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $I... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: tetris_control.vhd
-- // Date: 12/9/2004
-- // Description: Tetris program controller
-- // Class: CSE 378
-- =============================... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architectu... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c... |
library verilog;
use verilog.vl_types.all;
entity NbitCounter_vlg_check_tst is
port(
Q : in vl_logic_vector(15 downto 0);
sampler_rx : in vl_logic
);
end NbitCounter_vlg_check_tst;
|
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