content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
--
-- Title : inv
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : inv.vhd
-- Generated : Fri ... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks13@live.com)
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Tar... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks13@live.com)
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Tar... |
--!
--! \file osif_core.vhd
--!
--! OSIF logic and interface to IPIF
--!
--! The osif_core contains processes for OS request handling. Also, it
--! instantiates the DCR slave module, which manages communication
--! between the CPU and the OSIF.
--!
--! There are two sets of registers, one for each direction (logic to ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ---------------------------... |
[styling]
attribute=attribute
block_comment=block_comment
comment=comment
comment_line_bang=comment_line_bang
identifier=identifier
keyword=keyword
number=number
operator=operator
stdfunction=stdfunction
stdoperator=stdoperator
stdpackage=stdpackage
stdtype=stdtype
string=string
stringeol=stringeol
userword=type
[keyw... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:17 10/31/2011
-- Design Name:
-- Module Name: /home/cvargasc/Documentos/Uniandes/201120/Fundamentos de Sistemas Digitales/Laboratorios/practica7/practica7/testPreEscalador.vhd
-- Pr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
--autor: igor macedo silva
--description: generic multiplexer for a generic number of inputs and generic bus size.
library ieee;
use ieee.std_logic_1164.all;
--creation of specifc package for array input
package barramento is
--constant insize: integer := 4;
--constant bussize: integer := 4;
--type int_matrix is a... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------
-- Author: Mike Field <hamster@snap.net.nz>
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity epp_interface is
port (
clk : in std_logic;
fifo_rd : out STD_LOGIC := ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gigatron_tb is
end entity;
architecture rtl of gigatron_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal reset : std_logic := '1';
signal spi_req : std_logic;
signal red : unsigned(4 downto 0);
signal grn :... |
library verilog;
use verilog.vl_types.all;
entity altfp_mult is
generic(
width_exp : integer := 8;
width_man : integer := 23;
dedicated_multiplier_circuitry: string := "AUTO";
reduced_functionality: string := "NO";
pipeline : integer := 5;
denorma... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
-- Routines to help output text at a higher level of abstraction.
package tbu_text_out_pkg is
--type integer_vector is array (natural range <>) of integer;
procedure put(text: string);
procedure put(value:... |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1 <= sig2; sig2 <= sig3; -- Comment 1
siga <= sigb; sigb <= sigc; sigc <= sigd;
end process;
end architecture RTL;
|
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:52 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- revision history:
-- 07.08.2015 Patrick Appenheimer created
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.cpu_pack.all;
entity tb_fsm is
end entity tb_fsm;
architecture behav_tb_fsm of tb_fsm is
-- -------- SIMULATION CONSTANTS -----
con... |
-------------------------------------------------------------------------------
-- Entity: gpio
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
--------------------------------------------------------... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\output_enable.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -----------------------------------------... |
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab9_new_lib;
CONFIGURATION execute_struct_config OF execute IS
FOR struct
... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:36 11/21/2013
-- Design Name:
-- Module Name: MUX_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:36 11/21/2013
-- Design Name:
-- Module Name: MUX_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Da... |
package pkg is
end pkg;
|
package pkg is
end pkg;
|
package pkg is
end pkg;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee... |
--!
--! @file: pkg_adder.vhd
--! @brief: package that holds full adder
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package pkg_adder is
component full_adde... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SubBytes_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity single_crl is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
player : in std_logic; -- '0' player 1 ;
-- '1' palyer 2
saida : out std_logic_vector(1 d... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
---- UART code taken from http://www.bealto.com/fpga-uart.html
-- -- Eric Bainville
-- -- Mar 2013
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library work;
--use work.math_real.all;
--entity basic_uart is
-- generic (
-- DIVISOR: natural := 54 -- DIVISOR = 1... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
-- $Id: fx2_2fifoctl_ic.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_ic - syn
-- Description: ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
--This is the initial implementation of a left shift function. There is also a ready function for left or right shift declared in ieee.numeric_std . But we found it out later so we kept our initial implementation.
entity left_shift_by_1 is
port( data_in: in std_logic_vecto... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_PHASE_ACCUMS is
port(
PRESETN : in vl_logic;
HCLK : in vl_logic;
DAC0_IN : in vl_logic_vector(23 downto 0);
DAC1_IN : in vl_logic_vector(23 downto 0);
DAC2_IN ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_PHASE_ACCUMS is
port(
PRESETN : in vl_logic;
HCLK : in vl_logic;
DAC0_IN : in vl_logic_vector(23 downto 0);
DAC1_IN : in vl_logic_vector(23 downto 0);
DAC2_IN ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_PHASE_ACCUMS is
port(
PRESETN : in vl_logic;
HCLK : in vl_logic;
DAC0_IN : in vl_logic_vector(23 downto 0);
DAC1_IN : in vl_logic_vector(23 downto 0);
DAC2_IN ... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: addition/subtraction entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- ... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: addition/subtraction entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- ... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: addition/subtraction entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end control;
architecture con of control is
signal count:std_logic_vector(3 downto 0):="0000";
signal w,l:bit;
begin
process(reset,rb)
begin
if re... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity simple01 is
port (a, b, c : in std_logic;
z : out std_logic);
end simple01;
architecture behav of simple01 is
begin
process(A, B, C)
variable temp : std_logic;
begin
case a is
when '1' =>
assert b = '0';
z <= '0';
when... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
------------------------------------------------------------------------------... |
--
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 08:58:01 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity regNZ is
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity biaser is
generic(
EXP_BITS: natural := 6
);
port (
operation : in std_logic; --Indicates whether to add or remove the bias
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
exp_out: out std_logic_vector(EXP_BITS - 1 downto 0)
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY fsm_challenge IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
initx, inity, loady, loadx, plot, i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: tx_Mem_Reader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--
-- Revision 1.00 - first release. 20.03.2008
--
-- ... |
-------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- o... |
-- Generic registers file.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
-- 5-port (three reads, two writes on the same clock cycle)
-- The registers file is completely s... |
-- Generic registers file.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
-- 5-port (three reads, two writes on the same clock cycle)
-- The registers file is completely s... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_... |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description:
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instanti... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
termi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_gen is
end clk_gen;
architecture behavior of clk_gen is
component filter
port( data_ext: in std_logic_vector( 7 downto 0);
clock, start, rst: in std_logic;
done: out std_logic);
end com... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mcmgmt is
port
(
mcmgmt_clk: in std_logic;
mcmgmt_rst: in std_logic;
mcmgmt_port_mem1_oe: out std_logic;
mcmgmt_port_mem1_we: out std_logic;
mcmgmt_port_mem1_en: out std_logic;
mcmgmt_port_mem... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:33:37 11/19/2014
-- Design Name:
-- Module Name: pwm_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
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