content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used ... |
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used ... |
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used ... |
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used ... |
----------------------------------------------------------------------------
---- Create Date: 14:30:08 07/28/2010 ----
---- Design Name: lfsr_pkg ----
---- Project Name: lfsr_randgen ----
---- Description: ----
---- This is the package file used ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SignalShorter_16x1 is
Port (
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC);
end SignalShorter_16x1;
architecture skeleton of SignalShorter_16x1 is
begin
process(input) is
variable verifier : STD_LOGIC;
begin
verifier := '0';... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredoutput(template2)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity os16 is
port(
clock:in std_logic;
address:in std_logic_vector(13 downto 0);
q:out std_logic_vector(7 downto 0)
);
end os16;
a... |
entity something is
end entity;
architecture arch of something is
begin
end architecture;
configuration testbench of something is
for arch
end for;
end;
entity c01s03b01x00p12n01i00863ent is
end entity;
architecture c01s03b01x00p12n01i00863arch of c01s03b01x00p12n01i00863ent is
begin
K:block
componen... |
--*****************************************************************************
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
-- Implementation of Filter H_a3(z)
-- using Complex Frequency sampling filer (FSF) as Hilbert transformer
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following co... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following co... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following co... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following co... |
------------------------------------------------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following co... |
-- median_filter.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils_v1_00_a;
use utils_v1_00_a.ctl_bypass;
---
-- Performs median filtering on RGB window bus.... |
entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),... |
entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),... |
entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),... |
entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Projeto gerado via script.
-- Data: Sex,30/12/2011-23:36:18
-- Autor: rogerio
-- Comentario: Descrição da Entidade: inversor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity inversor is
port (a: in std_logic; y: out std_logic);
end inversor;
architecture logica of inversor i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 200... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Volume_Pregain_Top_Module is
generic(
INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out sign... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Volume_Pregain_Top_Module is
generic(
INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer
);
port(
OUT_VOLCTRL_L : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out sign... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
library std;
use std.textio.all;
entity harness_logic_32 is
end entity;
architecture tb of harn... |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0'when rd_en = '1' else '1';
... |
---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--u... |
entity attr10 is
end entity;
architecture test of attr10 is
begin
process is
constant s : string := "1234";
constant n : integer := 1234;
begin
for i in 1 to 4 loop
report character'image(integer'image(n)(i));
assert integer'image(n)(i) = s(i);
end loop;... |
entity attr10 is
end entity;
architecture test of attr10 is
begin
process is
constant s : string := "1234";
constant n : integer := 1234;
begin
for i in 1 to 4 loop
report character'image(integer'image(n)(i));
assert integer'image(n)(i) = s(i);
end loop;... |
entity attr10 is
end entity;
architecture test of attr10 is
begin
process is
constant s : string := "1234";
constant n : integer := 1234;
begin
for i in 1 to 4 loop
report character'image(integer'image(n)(i));
assert integer'image(n)(i) = s(i);
end loop;... |
entity attr10 is
end entity;
architecture test of attr10 is
begin
process is
constant s : string := "1234";
constant n : integer := 1234;
begin
for i in 1 to 4 loop
report character'image(integer'image(n)(i));
assert integer'image(n)(i) = s(i);
end loop;... |
entity attr10 is
end entity;
architecture test of attr10 is
begin
process is
constant s : string := "1234";
constant n : integer := 1234;
begin
for i in 1 to 4 loop
report character'image(integer'image(n)(i));
assert integer'image(n)(i) = s(i);
end loop;... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 11:21:36 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.all;
use UNISIM.vcomponents.all;
entity eightdiv is
port(
clk : in std_logic;
clk_out : out std_logic;
clkdiv_out : out std_logic
);
end eightdiv;
architecture Behavioral of eightdiv is
constant low : std_logic := '0';
constant high : std_logic... |
-- Simple sin/cos LUT
-- Register input/output to allow usual quarter-wave symmetry
--
-- Original author Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity SinCosLUT is
generic (
PHASE_WIDTH : natural := 14;
... |
-- niosii_system_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any la... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myguarded is
Po... |
library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
port(
clk : in vl_logic;
ce : in vl_logic;
a : in vl_logic_vector(15 downto 0);
b : in vl_logic_vector(7 d... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1 <=sig2;
sig2 <= sig3;
end process;
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_clocks_stdsync_sv6 is
port(
clk : in vl_logic;
din : in vl_logic;
dout : out vl_logic;
reset_n : in vl_logic
);
end usb_system_clocks_stdsync_sv6;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: divider_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
------------------------------------------------... |
-------------------------------------------------------------------------------
--! @file nShiftRegRtl.vhd
--
--! @brief Shift register with n-bit-width
--
--! @details This shift register implementation provides a configurable width.
-------------------------------------------------------------------------------
--
--... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Pre... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
-------------------------------------------------------------------------------
--! @file axiLiteSlaveWrapper-rtl-ea.vhd
--
--! @brief AXI lite slave wrapper on avalon slave interface signals
--
--! @details AXI lite slave will convert AXI slave interface singal to Avalon
--! interface signals.
--
---------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity DataPath is
port (
clk : in std_logic;
u232c_in : out u232c_in_t;
u232c_out : in u232c_out_t;
sramLoad : out boolean := true;
sramAddr : out sram_addr := (others => '0');
... |
entity assert7 is
end entity;
architecture test of assert7 is
impure function func (x : integer) return integer is
begin
assert x > 0;
return -x;
end function;
function resolved (x : bit_vector) return bit is
begin
return '1';
end function;
subtype rbit is resolve... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_195 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_195;
architecture augh of mul_195 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_195 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_195;
architecture augh of mul_195 is
signal tmp_res : signed(... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_hot is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_hot;
architecture behaviour of s832_hot is
constant s00000: std_logic_vector(24 downto 0... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register32X32 is
Port(
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic_vector(31 downto 0);
i_rA_sel : in std_logic_vector(31 downto 0);
i_rB_sel : in std_logic_vector(31 downt... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register32X32 is
Port(
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic_vector(31 downto 0);
i_rA_sel : in std_logic_vector(31 downto 0);
i_rB_sel : in std_logic_vector(31 downt... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
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