content stringlengths 1 1.04M ⌀ |
|---|
constant SPIFSMLength : integer := 1295;
constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "0000100111000010011001000001000000000000011100000000101010100000010010100000011000011000001001000010001110010000001001100010000000000001000100000000000111000000000000000010010001100000010010000000001000000... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process... |
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process... |
architecture rtl of fifo is
begin
process begin
my_signal := '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal := '1' when input = "0000" else
m... |
-- DDR2 memory interface
-- Andrew Read, March 2016
-- This project is based on a working DDR2 interface very kindly donated by a friend
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_textio.all;
entity SDRAM_CTRL is
port (
CLK : in std_logic; -- 125MHz clock
... |
library ieee;
use ieee.std_logic_1164.all;
package memory_types is
type memory_16b is array (15 downto 0) of std_logic_vector(7 downto 0);
end package memory_types;
|
library ieee;
use ieee.std_logic_1164.all;
package memory_types is
type memory_16b is array (15 downto 0) of std_logic_vector(7 downto 0);
end package memory_types;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ac_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MI... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:52 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Core IS
PORT(
cl... |
component soc_design is
port (
clock_clk : in std_logic := 'X'; -- clk
fpga_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_design;
u0 : component soc_design
port map (
clock_clk => CONNECTED_TO_clock_clk, -- clock.clk
fpga_reset_n => CONNECTED_TO_fpga_reset_n -- fpga.res... |
----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Binary polynomial divider
-- Computes the g/h mod f IN GF(2**m)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- g_i - First input value
-... |
-------------------------------------------------------------------------------
--! @file asyncFifo-syn-a.vhd
--
--! @brief The asynchronous Fifo architecture for Altera
--
--! @details This is a dual clock fifo generated in Megawizard!
--
-------------------------------------------------------------------------------
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:33 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versi... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:33 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versi... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_bug_e
--
-- Generated
-- by: wig
-- on: Thu Oct 6 12:55:50 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
entity tb_ret03 is
end tb_ret03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ret03 is
signal d : std_logic_vector (7 downto 0);
signal r : integer;
begin
dut: entity work.ret03
port map (d, r);
process
begin
d <= x"01";
wait for 1 ns;
assert r = 0 severity failure;
... |
-- Company: ZPU4 generic memory interface CPU
-- Engineer: Øyvind Harboe
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_arith.ALL;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
entity zpu_core is
Port ( clk : in std_logic;
areset : in std_l... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.Display_Management_pkg.all;
entity OSD_border is --===========================================================================
generic(
enable_debug : boolean := true;
resolution : string := "1920x1080@60Hz"
);
... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ddrv4
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cmp01 is
port (l : std_logic_vector(3 downto 0);
r : std_logic_vector(3 downto 0);
eq : out std_logic;
ne : out std_logic;
lt : out std_logic;
le : out std_logic;
ge : out std_logic;
g... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: scrambler_all_channels - Behavioral
-- Description: A x^16+x^5+x^4+x^3+1 LFSR scxrambler for DisplayPort
--
-- Scrambler LFSR is reset when a K.28.0 passes t... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_586 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_586;
architecture augh of sub_586 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_586 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_586;
architecture augh of sub_586 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: ou... |
library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: ou... |
library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: ou... |
library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: ou... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
--
-- Title : ctrl_game_block.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:28:20 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
--
-- my_fpga_test_gates.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use work.tbmsgs.all;
entity my_fpga_test_gates is
end entity;
architecture sim of my_fpga_test_gates is
signal clk : std_logic := '0';
signal n_rst : std_logic := '0';
signal up : std_logic := '0';
signal dn : std_logic := '... |
library IEEE;
use IEEE.std_logic_1164.all;
entity compara_zero_8bits is
generic (N: integer := 10);
port (
in_0,in_1: in std_logic_vector((N - 1) downto 0);
out_0: out std_logic
);
end entity;
architecture circuito of compara_zero_8bits is
begin
compara_zero_8bits <= (
(in_0(0) xnor in_1(0)) and
(in_0(1)... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! ... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! ... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE RS232_test IS
-------------------------------------------------------------------------------
-- Procedure for sending one byte over the RS232 serial input
-------------------------------------------------------------------------------
procedure Trans... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE RS232_test IS
-------------------------------------------------------------------------------
-- Procedure for sending one byte over the RS232 serial input
-------------------------------------------------------------------------------
procedure Trans... |
-------------------------------------------------------------------------------
-- Title : Dynamic adder/subtractor
-- Project :
-------------------------------------------------------------------------------
-- File : addsub.vhd
-- Author : Aylons <concordic@aylons.com>
-- Company :
-- Created ... |
--
-- USB Full-Speed/Hi-Speed Device Controller core - ep1_loopback.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restrictio... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "2013_big_drive"
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyri... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD... |
entity subent is
port (
a : in string(1 to 2) := "AB";
b : out string(1 to 2));
end entity subent;
architecture test of subent is
begin
b(1) <= a(1);
b(2) <= a(2);
end architecture test;
entity test is
end entity test;
architecture test of test is
signal b : string(1 to 2);
begi... |
entity subent is
port (
a : in string(1 to 2) := "AB";
b : out string(1 to 2));
end entity subent;
architecture test of subent is
begin
b(1) <= a(1);
b(2) <= a(2);
end architecture test;
entity test is
end entity test;
architecture test of test is
signal b : string(1 to 2);
begi... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:56:50 2019
-- Host : varun-laptop running 64-bit Service ... |
-- NEED RESULT: ARCH00687: Allocators with dynamic composite subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity clockgen is
port (
ext_clk, async_resetb : in std_ulogic;
clk, sync_reset : out std_ulogic
);
end clockgen;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_builtin.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *****************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_vdma_afifo_builtin.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *****************... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C3 is
port (A: in std_logic;
B: in std_logic;
C: in std_logic;
F: out std_logic
);
end C3;
architecture c3_estr of C3 is
begin
F <= (B or C) and (not A);
end c3_estr; |
-- SIMON 64/128
-- feistel round function
-- Inner-round pipelining using negative-edge triggered registers
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- v_in: plaintext block
-- v_k: subkey
-- v_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cu is
-- Control unit input sizes
constant OPCODE_SIZE : integer := 6; -- OPCODE field size
constant FUNC_SIZE : integer := 11; -- FUNC field size
subtype OPCODE_TYPE is std_logic_vector(OPCODE_SIZE - 1 downto 0);
-- I-Type instructi... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
termi... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic... |
--###############################
--# Project Name : I2C slave
--# File : i2cslave.vhd
--# Project : i2c slave for FPGA
--# Engineer : Philippe THIRION
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity I2CSLAVE is
g... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 22:11:05 2017
-- Host : GILAMONSTER running 64-bit major rel... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:22:26
-- Design Name:
-- Module Name: rem_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Fri Nov 2 15:01:50 2018
-- Host : graviton running 64-bit Debian GNU/L... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity biaser_tb is
end entity;
architecture biaser_tb_arq of biaser_tb is
signal operation : std_logic := '0';
signal exp_in: std_logic_vector(2 downto 0) := (others => '0');
signal exp_out: std_logic_vector(2 downto 0) := (others => '0');
co... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-- Component Declaration
entity sbox is port (
b_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
clock, reset : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end ... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-- Component Declaration
entity sbox is port (
b_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
clock, reset : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end ... |
library IEEE, STD;
use STD.textio.all;
use WORK.std_logic_textio.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bstest_tb is
end bstest_tb;
architecture tb_arch of bstest_tb is
-- UUT component
component bstest
port (
sldsw : in std_logic_vector(3 downto 0);
button : in ... |
-- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter)
-- Copyright (C) 2014 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Ján Jusko xjusko00
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- -... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE rc5_pkg IS
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
type rc5_rom_4 is array (0 to 3) of std_logic_vector(31 downto 0);
type rc5_key_StateType is (ST_IDLE, -- In this state RC5 key expansion is ready for input
ST_KEY_I... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
set : in std_logic;
reset : in std_logic;
q : out std_logic
);
end;
architecture a of ent is
signal s : std_logic;
begin
process(clk, set, reset)
begin
if set = '1' then
... |
-- Algoritmo CORDIC
-- (Rehecho de forma iterativa)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.MATH_REAL.all;
library work;
use work.cordic_lib.all;
entity cordic is
generic (
P : natural := 16 -- Cantidad de iteraciones, determina la precisión
);
... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: rom.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is ... |
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