content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is acc... |
entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is acc... |
entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is acc... |
-- Descp: counts number of exact matches
--
-- entity name: g05_num_matches
--
-- Version 1.0
-- Author: Felix Dube; felix.dube@mail.mcgill.ca & Auguste Lalande; auguste.lalande@mail.mcgill.ca
-- Date: October 1, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_num_matches is
port (
P1, P2, P3, ... |
component ghrd_10as066n2_clk_0 is
port (
in_clk : in std_logic := 'X'; -- clk
out_clk : out std_logic -- clk
);
end component ghrd_10as066n2_clk_0;
u0 : component ghrd_10as066n2_clk_0
port map (
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
out_clk => CONNECTED_TO_out_clk -- out_clk.c... |
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity ff32_en_IR is
generic (
SIZE : integer := 32
);
PORT(
D : in std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic;
Q : out std_logic_vector(SIZE - 1... |
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity ff32_en_IR is
generic (
SIZE : integer := 32
);
PORT(
D : in std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic;
Q : out std_logic_vector(SIZE - 1... |
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any ... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "AvalonSTToI2S"
-- Project :
-------------------------------------------------------------------------------
-- File : AvalonSTToI2S_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- ... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 250MS/s core registers
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs.vhd
-- Author : auto-gener... |
--
-- FIFO
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017-2019 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
-- Description:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
use FPGALIB.Numeric.all;
use FPGALIB.Sync.all;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.zpupkg.all;
use work.zpu_config.all;
use work.wishbone_pkg.all;
package zpu_top_pkg is
component zpu_wb_bridge is
port ( -- Native ZPU interface
clk : in std_logic;
areset : in st... |
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LogicalAND_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end LogicalAND_2x16;
architecture skeleton of LogicalAND_2x16 is
begin
output <= input_A AND input_B;
end skelet... |
architecture RTL of ENTITY_NAME is
begin
process
begin
SEL_LABEL : with some expression select ?
some target <= transport some expression when some choice | some other choice | some other other choice,
some expression when some choice,
... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- The CPU, only the stateless parts
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.memory_map.all;
-- We keep keep all state (registers, memory) out of the CPU
-- This allows for testbenches that can instantiate them internally
-- and check whether everything works as expected
entity cpu ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:53 02/04/2014
-- Design Name:
-- Module Name: E:/EE4321-VHDL/Project-1/testBench.vhd
-- Project Name: Project-1
-- Target Device:
-- Tool versions:
-- Description: ... |
-- Test shared variables in -2008 with --relax=shared
entity shared4 is
end entity;
architecture test of shared4 is
shared variable x : natural;
begin
g0: for i in 1 to 10 generate
begin
p1: process is
begin
for i in 1 to 1000 loop
x := x + 1; --... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
librar... |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
librar... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:51:17 12/20/2009
-- Design Name:
-- Module Name: output_pin_cntl - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Descrip... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:51:17 12/20/2009
-- Design Name:
-- Module Name: output_pin_cntl - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Descrip... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- RGB2YUV
-- transforms RGB to YUV
-- Y = 0.299 * R + 0.587 * G + 0.114 * B
-- U = 0.492 * (B - Y) = 0.436 * B - 0.147 * R + 0.289 * G
-- V = 0.877 * (R - Y) = 0.615 * R - 0.515 * G + 0.100 * B
--
-- delay: 2 clk cycles
--
-- file: rgb2yuv.vhd
-- author: Sebastian Weiss <dl3yc@darc.de>
-- version: 0.1
lib... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 4
--This component takes 2 mantissas that were already equalized and adds them
entity expanded_mantissa_adder is
generic(
BITS : natural := 16
);
port(
man_1_in : in std_logic_vector(BITS - 1 downto 0);
man_2_in : in std_logic_vect... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
... |
-- Bridge from TCP receive and send streams to an AXI memory map
-- Also can route packets to/from CPLD interface
--
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_pkg.all;
entity TCP_AXI_DMA is
port... |
-------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lmb_bram_elaborate is
generic (
... |
architecture behav of tb is
begin
assert false report "Hello world" severity note;
end behav;
|
architecture behav of tb is
begin
assert false report "Hello world" severity note;
end behav;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleUnitReanamedPort4 IS
PORT(
b_rx_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b_rx_last : IN STD_LOGIC;
b_rx_ready : OUT STD_LOGIC;
b_rx_valid : IN STD_LOGIC;
b_tx_data : OUT STD_LOGIC_VECTOR(63 DOWN... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_with_checkers_top is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_with_checkers_top is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_with_checkers_top is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
----------------------------------... |
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
----------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity determ_adc is
generic (
N : positive := 16;
DA_RESET_DELAY: positive
);
port(
CLK1, spi_sck_i, conv_i: in std_logic;
spi_miso_o: out std_logic
);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity determ_adc is
generic (
N : positive := 16;
DA_RESET_DELAY: positive
);
port(
CLK1, spi_sck_i, conv_i: in std_logic;
spi_miso_o: out std_logic
);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity determ_adc is
generic (
N : positive := 16;
DA_RESET_DELAY: positive
);
port(
CLK1, spi_sck_i, conv_i: in std_logic;
spi_miso_o: out std_logic
);... |
---------------------------------------------------------------
-- Title : fpga_pkg_2 example for many devices
-- Project :
---------------------------------------------------------------
-- File : manny_devices.vhd
-- Author : Florian Wombacher
-- Email : Florian.Wombacher@men.de... |
--
-- Simple Dual-Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity SimpleDualPortRAM is
generic (
AWIDTH ... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:35 2019
-- Host : varun-laptop running 64-bit Service ... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:35 2019
-- Host : varun-laptop running 64-bit Service ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: pmodenc - Behavioral
-- Description: Process the quadrature signals from the rotary encode on
-- the Digilent PMODENC
--
------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- #############################################################################
-- DE0_Nano_SoC_top_level.vhd
-- ==========================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule... |
library ieee;
use ieee.std_logic_1164.all;
entity tri is
port (i, en : std_logic;
o : out std_logic);
end tri;
architecture behav of tri is
begin
o <= i when en = '1' else 'Z';
end behav;
|
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port( carry: in STD_LOGIC;
aluop : in STD_LOGIC_VECTOR (5 downto 0);
crs1 : in STD_LOGIC_VECTOR (31 downto 0);
crs2 : in STD_LOGIC_VECTOR (31 downto 0);
r : out STD_LOGIC_VECTOR... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
-- $Id: nexys3_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexy... |
library ieee;
use ieee.std_logic_1164.all;
entity SyncReg is
generic (n: integer := 4);
port
(
Din: in std_logic_vector(n-1 downto 0);
EN: in std_logic;
CLK: in std_logic;
DOut: out std_logic_vector(n-1 downto 0)
);
end SyncReg;
architecture Struct of SyncReg is
component DESync
port (
D, E, CLK :... |
entity wave4 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of wave4 is
type mem_t is array (natural range <>) of std_logic_vector(7 downto 0);
signal mem : mem_t(0 to 9);
signal dout : std_logic_vector(7 downto 0);
signal addr : natural range 0 to 7;
begin
dout <= m... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:45:34 10/22/2015
-- Design Name:
-- Module Name: register16_with_we - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_moore is
port(w3 : in std_logic_vector(28 downto 0);
-- clock
sys... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_moore is
port(w3 : in std_logic_vector(28 downto 0);
-- clock
sys... |
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