content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
a... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/29/2017 12:10:39 PM
-- Design Name:
-- Module Name: Concat - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description... |
------------------------------
entity array_slices is
--generic declarations
port (
row: in integer range 0 to 3;
column: in integer range 0 to 4;
slice1: out bit ;
slice2: out bit_vector(1 to 2) ;
slice3: out bit_vector(1 to 4) ;
slice4: out bit_vector(1 to 3) ;);
en... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psl.all;
use work.mmio_package.all;
entity mmio is
port (
i : in mmio_in;
o : out mmio_out
);
end entity mmio;
architecture logic of mmio is
signal q, r : ... |
--------------------------------------------------------------------------------
-- ion_core.vhdl -- MIPS32r2(tm) compatible CPU core
--------------------------------------------------------------------------------
-- This is the main project module. It contains the CPU plus the TCMs and caches
-- if it is configured t... |
-- megafunction wizard: %RAM initializer%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMEM_INIT
-- ============================================================
-- File Name: ram_init.vhd
-- Megafunction Name(s):
-- ALTMEM_INIT
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- megafunction wizard: %RAM initializer%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMEM_INIT
-- ============================================================
-- File Name: ram_init.vhd
-- Megafunction Name(s):
-- ALTMEM_INIT
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/15/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: Camellia top level module, for 128/192/256-bit keys
--
-- Copyright (C... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ROC_WIDTH : constant is 1;
attribute mti_svvh_generic_type of TOC_WI... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- This VHDL application uses processes to generate 3 types of digital signals (triangular, saw-tooth, and sine) with FPGA hardware.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY generador IS
PORT
(
AB : OUT STD_LOGIC; -- Señal... |
CONFIGURATION Decoder_Behavior_config OF Decoder IS
FOR Behavior
END FOR;
END Decoder_Behavior_config; |
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-----------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-----------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00564: Aliasing - composite generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity unite is
Port (
LED : out std_ulogic_vector(3 downto 0);
CLK_66MHZ : in std_ulogic;
SDA, SCL: inout std_logic;
USER_RESET : in std_logic
);
end unite;
architecture Behavioral of unite is
signal duty_cycle : unsigned(7 downto... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--Copyright (C) 2017 Siavoosh Payandeh Azad
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity RegisterFile is
generic (BitWidth: integer);
port ( clk : in std_logic;
rst: in std_logic;
Data_in_mem : in std_logic_vector (BitWidth... |
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary... |
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary... |
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary... |
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end functio... |
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end functio... |
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end functio... |
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end functio... |
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end functio... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sweep is
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
end sweep;
architecture arch of sweep is
signal q: std_logic_vector(11 downto 0);
begin
--clock divider
process(mclk)
begin
... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sweep is
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
end sweep;
architecture arch of sweep is
signal q: std_logic_vector(11 downto 0);
begin
--clock divider
process(mclk)
begin
... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Group 2: Gesture Control Interface top level file
-- Eric Smith, Chris Chmilar, Rajan Jassal
-- This file is a modified version of the top level file provided in lab 1
-- Nancy Minderman
-- nancy.minderman@ualberta.ca
-- This file makes extensive use of Altera template structures.
-- This file is the top-l... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
library verilog;
use verilog.vl_types.all;
entity finalproject_sdram_input_efifo_module is
port(
clk : in vl_logic;
rd : in vl_logic;
reset_n : in vl_logic;
wr : in vl_logic;
wr_data : in vl_logic_vecto... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Block1 IS
PORT(
D : IN STD_LOGIC;
C : IN STD_LOGIC;
B : IN STD_LOGIC;
A : IN STD_LOGIC;
E : OUT STD_LOGIC);
END Block1;
ARCHITECTURE logic OF Block1 IS
BEGIN
E <= (D AND C AND A) OR (NOT(C) AND NOT(A)) OR (A AND NOT(B));
END log... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity lifo_tb is
-- Generic declarations of the tested unit
generic(
m : INTEGER := 5;
n : INTEGER := 16 );
end lifo_tb;
architecture TB_A... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------
---- ----
---- iteration_synth.vhd ----
---- ----
---- This file is part of the turbo... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
|
package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
|
package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 20... |
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