content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FF_TagRam6... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2011 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
-------------------------------------------------------------------------------
-- Title : Instruction Cache L1
-- Project :
-------------------------------------------------------------------------------
-- File : Instruction_Cache.vhd
-- Author : Robert Jarzmik <robert.jarzmik@free.fr>
-- Company ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro3 is
port (
clk : std_logic;
led : out std_logic);
end;
architecture behav of repro3 is
constant LOOKUP_LEN : integer := 6;
constant LOOKUP_TABLE : unsigned(LOOKUP_LEN*8-1 downto 0) :=
x"010205" & x"060708";
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat Dec 24 01:08:44 2016
-- Host : KLight-PC running 64-bit major relea... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity m_eth is
generic(
RAM_RD_CYCLE : natural := 2;
RAM_WR_CYCLE : natural := 2;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural ... |
----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETE... |
----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETE... |
----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETE... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains... |
--------------------------------------------------------------------------------
-- DA2 Reference Component
--------------------------------------------------------------------------------
-- Author : Ioana Dabacan
-- CopyRight 2008 Digilent Ro.
-----------------------------------------------------------... |
-- $Id: simclkcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: simclkcnt - sim
-- Description: test bench syste... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87... |
library verilog;
use verilog.vl_types.all;
entity butter_2 is
generic(
RST_LVL : integer := 0
);
port(
clk : in vl_logic;
rst : in vl_logic;
butt2_real0 : in vl_logic_vector(15 downto 0);
butt2_imag0 : in vl_logi... |
-------------------------------------------------------------------------------
-- Title : Human Readable Name for the module in this file.
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : vhdl_file_template.vhd
-- Created : 201... |
-------------------------------------------------------------------------------
-- Title : ALU substracter
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Substracter.vhd
-- Author ... |
-- $Id: tb_tst_sram_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_n4
-- Description: Configur... |
architecture RTL of FIFO is
begin
process is
begin
end process;
process (a, b) is
begin
end process;
-- Violations below
process
begin
end process;
process (a, b)
begin
end process;
process(a,b)begin end process;
end architecture RTL;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.LIB.ALL;
ENTITY AP IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
-- AP Memory/Arbiter
MemDataIn : IN AP_data_width;
MemDataOut: OUT AP_data_width;
MemAddr ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
begin
LL: case test generate
when =>
end generate;
end architecture arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
begin
LL: case test generate
when =>
end generate;
end architecture arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- (C) Copyright 2013-2015 Authors and the Free Software Foundation.
--
-- This file is part of OpenRIO.
--
-- OpenRIO is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with MMC feature set
--
-- $Id: chip-mmc-a.vhd,v 1.7 2007-08-06 23:31:42 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gray_testbench is end gray_testbench;
architecture behavioral of gray_testbench is
signal input : std_logic_vector(3 downto 0);
signal output : std_logic_vector(3 downto 0);
component mux
port (
a ... |
library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLUP is
port (
O : out std_logic
);
attribute syn_not_a_driver : boolean;
attribute syn_not_a_driver of O : signal is true;
end entity PULLUP;
architecture bb of PULLUP is
attribute syn_black_box of bb : architect... |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record a : std_logic; b : std_logic; end record;
begin
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
carry : in std_logic;
... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
entity hwtireg is
generic
(
REG_WIDTH : integer := 32;
USE_HIGH : boolean := false;
C_AW... |
-- matrix_pixel_gen.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity matrix_pixel_gen is
port (
CLK : in std_logic;
RST : in std_logi... |
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
--------... |
----------------------------------------------------------------------------------
--
-- Lab session #4: Invaders testbech
--
-- Testing the block controlling the space invaders
--
-- Each invader has its power encoded in 2 bits:
-- 00 -> no invader
-- 01 -> easy invader (1 shot) [green]
-- 10 -> medium invader ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--
-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade
--
-- MODULE: Utility package
--
-- ELEMENT: -
--
-- DESCRIPTION: several utility types and functions
--
-- AUTHOR: D. Calvet calvet@hep.saclay.cea.fr
--
-- DATE AND HISTORY:
-- Ja... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
package wishbone_pkg2 is
subtype my_vector is std_logic_vector;
type t_wishbone_master_out is record
dat : my_vector;
end record;
subtype t_wishbone_slave_in is t_wishbone_master_out;
end wishbone_pkg2;
library work;
use work.wishbone_pkg2.all;
library ieee;
use iee... |
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later v... |
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file ... |
entity tc16 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc16 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if ?? tg and falling_edge(clk) then
null;
end if;
end process;
end behav;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
-----------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
-----------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
-----------------------------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Multipelexer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Multiplexer... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testcase1 is
port (
sel : in unsigned(1 downto 0);
det : out std_logic
);
end testcase1;
architecture behavior of testcase1 is
begin
tc: process(sel)
begin
case to_integer(sel) is
when 0 to 1 =>
det <= '0';... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCAM_Cell is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
cell_search_bit : in STD_LOGIC;
cell_dont_care_bit : in STD_LOGIC;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity signextend is
Port (
clk : in std_logic;
in16 : in std_logic_vector(15 downto 0);
out32 : out std_logic_vector(31 downto 0)
);
End;
Architecture RTL of signextend is
begin
pr... |
-------------------------------------------------------------------------------
-- axi_vdma_regdirect
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All righ... |
-------------------------------------------------------------------------------
-- axi_vdma_regdirect
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All righ... |
-- $Id: rlink_sp1c.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ab
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Entity: usb_trace_adapter
-- Date:2018-07-15
-- Author: Gideon
--
-- Description: Encodes USB data into 1480A compatible data format
--------------------------------------------------------------------------------
library ieee;
u... |
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be ... |
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be ... |
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be ... |
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be ... |
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be ... |
-------------------------------------------------------------------------------
--! @file phyActGen-rtl-ea.vhd
--
--! @brief Phy activity generator
--
--! @details The phy activity generator generates a free-running clock-synchronous
--! packet activity signal. This signal can be used to drive an LED.
--------... |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE ... |
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