content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of FIFO is
begin
process
begin
loop
a <= b;
end loop;
-- Violations below
loop
a <= b;
end loop;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
package test_pkg is
signal glob_sig : std_logic := '1';
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.test_pkg.all;
entity issue483 is
end entity;
architecture rtl of issue483 is
begin
p_proc : process
constant C_CONST : std_logic := glob_sig;
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
--------------------------------------------------------... |
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : ADC Model
-- Last update : 27.04.2015
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
us... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms o... |
architecture RTl of FIFO is
component fifo is
port (
a : in std_logic
);
end component fifo;
-- Failures below
component fifo is
port (
a : in std_logic
);
end component fifo;
component fifo is
port (
a : in std_logic
);
end component fifo;
begin
en... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity testbench is
end testbench;
architecture final_testbench of testbench is
component project2
port (
clock : in std_logic;
reset : in std_logic;
valid : in std_logic;
hold_me : in std_logic;
data_in : in std_logic_vector (7 downto 0... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.11.2012 05:36:01
-- Design Name:
-- Module Name: cam_pkg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_2_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * ... |
-- --------------------------
-- TIMING
-- --------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------
Entity timing is
-- ----------------------------------------------------
generic (
F : na... |
library ieee;
use ieee.std_logic_1164.all;
entity verzoegerung_tb is
end verzoegerung_tb;
architecture behavior of verzoegerung_tb is
component verzoegerung
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end component;
... |
library ieee;
use ieee.std_logic_1164.all;
entity verzoegerung_tb is
end verzoegerung_tb;
architecture behavior of verzoegerung_tb is
component verzoegerung
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end component;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:44:15 11/21/2012
-- Design Name:
-- Module Name: BancoDeRegistros - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depende... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity conv_7seg_int is
port(digit: in integer;
seg: out std_logic_vector(6 downto 0));
end conv_7seg_int;
architecture Behavior of conv_7seg_int is
begin
with digit select
seg <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity test is
end test;
architecture rtl of test is
component top is
port( clk : in std_logic;
reset : in std_logic;
vs : out std_logic;
hs : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity mul32const is
port(
in1: in std_logic_vector(31 downto 0);
out1: out std_logic_vector(34 downto 0)
);
end mul32const;
architecture rtl of mul32const is
begin
out1<= ((in1 & "000") + (in1) + (in1)); ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity taps2 is
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_lo... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:13:29 11/08/2013
-- Design Name:
-- Module Name: cerrojoElectronico - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std... |
------------------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ******************************************... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity zero_counter_t is
end zero_counter_t;
architecture Beh of zero_counter_t is
component ZeroCounter
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end component;
signal clk: std_logic := '0';
signal rst: st... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
-------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_std.all;
entity divider_TB is
end divider_TB;
architecture Behavioral of divider_TB is
component divider_sequential
port (
Enable : in std_logic;
Ready : out std_logic;
CLK : in std_logic;
Overflow : out std_lo... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
entity b is end entity;
entity foo is
generic ( a : integer );
port ( b : in integer );
end entity;
architecture arch of foo is
begin
end architecture;
configuration yah of foo is
use work.foo;
for arch
end for;
end configuration;
architecture a of b is
component y is end component;
com... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNCKXZT4CF is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
-------------------------------------------------------------------------------
-- $Id: checkbit_handler.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file ... |
ARCHITECTURE behavior OF tb_ClkDiv IS
CONSTANT HalfClkPer : time := 62.5 ns; -- 62.5ns => 8 MHz
-- Component Declaration
COMPONENT ClkDiv IS
Generic (DividerWidth_g : integer range 4 to 32 := 16);
Port ( F100_400_n_i : in STD_LOGIC;
Divider800_i : in std_... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.Font.all;
entity top is
Port (
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- --------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
---------------... |
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
---------------... |
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
---------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- This hooks up to the bus, LED display, LEDs, switches and buttons and allows
-- control of the processor. It allows single-stepping of the processor, and
-- when not in deb... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file ... |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity K7SerialInterfaceOut is
Generic (
GATE_DELAY_G : time := 1 ns
);
Port (
-- Parallel clock and reset
sstClk ... |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
entity t5 is
end t5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of t5 is
signal s : std_logic := '0';
begin
b: block
port (p : out std_logic := 'Z');
port map (p => s);
begin
end block;
b2: block
port (p : out std_logic := '1');
port map (p => s);
begin
end block;
... |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont10.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of t... |
-------------------------------------------------------------------------------
--! @file xf_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-11
--! @brief Auxiliary FPGA package.
-------------------------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the 'starter' module.
--! @details Everytime after hard reset Rocket cor... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Implementation of the 'starter' module.
--! @details Everytime after hard reset Rocket cor... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
entity shiftLeftImm is
port (
imm: in std_logic_vector (31 downto 0);
output: out std_logic_vector (31 downto 0)
);
end entity;
architecture behav of shiftLeftImm is
begin
output <= ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
package mouse_ref_pkg is
component MouseRefComp
port (
clk : in std_logic;
resolution : in std_logic;
rst : in std_logic;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
package pkgc is
constant width : natural;
end pkgc;
package body pkgc is
constant width : natural := 4;
end pkgc;
use work.pkgc.all;
package pkgcomp is
component comp is
generic (val : bit_vector (width -1 downto 0));
port (b : out bit);
end component;
end pkgcomp;
use work.pkgc.all;
entity comp is
... |
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should chec... |
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