content stringlengths 1 1.04M ⌀ |
|---|
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should chec... |
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should chec... |
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should chec... |
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should chec... |
-- new_component.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should chec... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x4time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x4time;
-- Architecture of the Component
architecture a_x4time of x4time is
begin
b_out(7) <= b_in(... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x4time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x4time;
-- Architecture of the Component
architecture a_x4time of x4time is
begin
b_out(7) <= b_in(... |
-------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_... |
-------------------------------------------------------------------------------
-- bfm_memory_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_slave_bfm_v1_00_a;
use plbv46_... |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package MyWork is
-- type <new_type> is
-- recor... |
-- control module (implements MIPS control unit)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY control IS
PORT(
Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
flush : OUT STD_LOGIC;
flushP : IN STD_LOGIC;
Zero : IN STD_LO... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
package foo is
-- enum_type_def
type foo;
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type BIT is ('0','1');
type SWITCH_LEVEL is ('0','1','X');
-- integer_type_def
type TWOS_COMPLEMENT_INTEGER is range -32768 to 32767;
type BYTE_LENGTH_INTEGER is range 0 to 255;
type WORD_INDEX is rang... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pio_n is
generic (
RegCnt : positive := 256;
ByteEnable: boolean := false
);
port (
clk : in std_logic := '0'; -- clk.clk
reset ... |
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Deglitches async inputs
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.a... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Deglitches async inputs
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.a... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 22 15:29:26 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:12:12 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end;
architecture a of ent is
begin
assert false
report "Just a note"
severity note;
assert false
report "Test assertion failed"
severity failure;
end;
|
architecture ARCH of FIFO is
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
signal sig1 : std_logic; -- comment
-- This comment should be left alone
signal sig1 : std_logic; -- comment... |
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity memory_no_clk is
generic ( N : integer := 1);
port ( clk : in std_logic;
write_en: in std_logic;
addr_1 : in std_logic_vector (31 downto 0);
addr_2 : in ... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counters is
port(
sysclk : in std_logic;
foo_card : in std_logic;
wfoo0_baz : in std_logic;
wfoo0_blrb : in std_logic;
wfoo0_zz1pb : in std_logic;
wfoo0_turn : in std_logic_vector(31 downto 0);
debct_baz : ... |
----------------------------------------------------------------------
-- Created by SmartDesign Thu Jun 22 17:22:48 2017
-- Version: v11.8 11.8.0.26
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
--------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: fpgaddicted (Stefan Naco)
--
-- Create Date: 17:26:19 04/27/2017
-- Design Name:
-- Module Name: animation_engine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Desc... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
--!
--! \file dcrfifo.vhd
--!
--! Implementation of a FIFO with DCR bus attachment.
--!
--! control register : BASE_ADDR
--! when read:
--! bit 31 = underrun indicator (initial: 0)
--! bit 30 = overflow indicator (initial: 0)
--! bit 28 = write only indicator (initial: ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_prac4 IS
END test_fsm_prac4;
ARCHITECTURE behavior OF test_fsm_prac4 IS
COMPONENT fsm_prac4
PORT(
X : IN std_logic;
RESET : IN std_logic;
clk100mhz : IN std_logic;
Z : OUT std_logic
);
... |
-------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t4... |
package p1 is
constant k : integer := 1;
constant j : integer := 5;
type t is (FOO, BAR);
end package;
package p2 is
constant k : integer := 2;
constant j : integer := 7;
type t is (BAR, BAZ);
end package;
use work.p1.all;
use work.p2.all;
package p3 is
constant x : integer := k; ... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: clock1hz.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =================================... |
--!
--! \file mem_plb34.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (ht... |
-- bitonic_sort9.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bitonic_sort9 is
generic (
LEVEL : integer := -1
);
port (
CLK : in std_logic;
CE : in std... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
-- count number of '1'.
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
sel : in std_ulogic;
din : in std_ulogic_vector(15 downto 0);
dout : out std_ulogic
);
end;
architecture rtl of ent is
begin
comb : process (sel, din)
variable v : std_ulogic;
begin
v := '0';
... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY UNISIM;
USE UNISIM.vcomponents.ALL;
ENTITY CLK IS
PORT
(
reset, clk_input : IN STD_LOGIC;
clk_output : OUT STD_LOGIC
);
END CLK;
ARCHITECTURE Behavioral OF clk IS
SIGNAL sig_clk, clkfb : STD_LOGIC;
BEGIN
-- force sig_CLK_108... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:58:07 09/10/2009
-- Design Name:
-- Module Name: /home/abaez/ise_projects/complete_pic/src//complete_pic_test.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block4.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
-- Date : Sun Oct 25 15:45:18 2015
-- Host : arthas-ubuntu running 64-bit Ubuntu ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:12:46 09/15/2014
-- Design Name:
-- Module Name: H:/Documents/md5_test/tb_md5.vhd
-- Project Name: md5_test
-- Target Device:
-- Tool versions:
-- Description:
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_uart_pack.all;
entity generic_fifo is
generic (
FIFO_WIDTH : positive := 32;
FIFO_DEPTH : positive := 1024
);
port (
clock : in std_logic;
nreset : in std_logic;
... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
-- Date : Wed Apr 8 23:17:20 2015
-- Host : parallella running 64-bit Ubuntu 1... |
entity issue436 is
end entity;
architecture MODEL of issue436 is
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable v : VEC_RANGE_TYPE;
begin
... |
library ieee;
use ieee.std_logic_1164.all;
package miscellaneous is
component ClockGenerator
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic;
oBCLK : out std_ulogic;
oSCLK : out std_ulogic;
oLRCOUT : out std_ulogic);
end ... |
library ieee;
use ieee.std_logic_1164.all;
package miscellaneous is
component ClockGenerator
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic;
oBCLK : out std_ulogic;
oSCLK : out std_ulogic;
oLRCOUT : out std_ulogic);
end ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split7 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_posit... |
--!
--! \file just_wait.vhd
--!
--! Benchmark for cooperative multithreading
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 13.03.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LO... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LO... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LO... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_impl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_impl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_impl... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_impl... |
entity bounds7 is
end entity;
architecture test of bounds7 is
type my_int is range 1 to 10;
begin
process is
variable x : my_int;
variable y : integer;
begin
x := 6;
y := integer(x);
x := 10;
x := 11;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : async_fifo_dist_inst.vhd
-- Author : ghanash
-- Company : Xilinx, Inc.
-- Created ... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CI_4511 is
Port ( Ai, Bi, Ci, Di : in STD_LOGIC;
Ao, Bo, Co, Do, Eo, Fo, Go : out STD_LOGIC
);
end CI_4511;
architecture Behavioral of CI_4511 is
begin
process(Ai, Bi, Ci, Di)
begin
if (Ai = '1') and (Bi = '0') and (Ci = '0... |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vh... |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vh... |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vh... |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vh... |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vh... |
-------------------------------------------------------------------------------
-- ac97_core.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_acore.vh... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplex_1_tb is
end entity;
architecture behav of multiplex_1_tb is
component multiplex_1
port (
smi : in std_logic_vector(6 downto 0);
smo : out std_logic;
se : in std_logic_vector(2 downto 0)
);
end component;
for multiplex_1... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
---po_i2c_status(3): '1' = bus transfering, '0' = stopped.
---po_i2c_status(2): '1' = read, '0' = write.
---po_i2c_status(1): '1' = data acknowleged, ... |
entity one is
end entity;
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.