content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
--! @file mmSlaveConv-rtl-ea.vhd
--
--! @brief Memory mapped slave interface converter
--
--! @details The slave interface converter is fixed to a 16 bit memory mapped
--! slave, connected to a 32 bit master. The conversion also co... |
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.OISC_SUBLEQ_PKG.all;
entity BENCH_OISC_SUBLEQ is
begin
end entity BENCH_OISC_SUBLEQ;
architecture BENCH of BENCH_OISC_SUBLEQ is
signal sPCLK : std_logic := '0';
signal sDCLK : std_logic := '0';
signal sCLK : std_logic := '0';
signal s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.OISC_SUBLEQ_PKG.all;
entity BENCH_OISC_SUBLEQ is
begin
end entity BENCH_OISC_SUBLEQ;
architecture BENCH of BENCH_OISC_SUBLEQ is
signal sPCLK : std_logic := '0';
signal sDCLK : std_logic := '0';
signal sCLK : std_logic := '0';
signal s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.OISC_SUBLEQ_PKG.all;
entity BENCH_OISC_SUBLEQ is
begin
end entity BENCH_OISC_SUBLEQ;
architecture BENCH of BENCH_OISC_SUBLEQ is
signal sPCLK : std_logic := '0';
signal sDCLK : std_logic := '0';
signal sCLK : std_logic := '0';
signal s... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_rc
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_soc is
end tb_soc;
architecture behav of tb_soc is
signal rst : std_logic := '1';
signal clk : std_logi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
-- Twofish.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This pr... |
entity tb_sram05 is
end tb_sram05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram05 is
signal rst : std_logic;
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : ... |
library ieee;
use ieee.numeric_bit.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.numeric_bit.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Ce bloc est un multiplexeur
--
-- Il selectionne une configuration de serpentin parmis les 4 en entrées,
-- a partir des 2 interrupteurs en entrée
--
-- En sortie, on a la configuration selectionnée
--
-----------------------------------... |
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL - Michigan
-- Engineer: Panagiotis Gkountoumis & Reid Pinkham & Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis & Reid Pinkham & Paris Moschovakos
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--! @file synchronizerRtl.vhd
--
--! @brief Synchronizer
--
--! @details This is a synchronizer with configurable stage size.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Re... |
----------------------------------------------------------------------------------
-- Create Date: 21:52:35 04/10/2017
-- Module Name: XOR_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XOR_BitABit is
... |
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.io.all;
--------------------------------------------------------------------------------
-- I/O PACKAGE
--------------------------------------------------------------------------------
package io is
constant A... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------... |
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- Thi... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:03:26 02/20/2011
-- Design Name:
-- Module Name: hamming_encoder_26bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is'... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Generate predefined values for filter input bit streams.
--------------------------------------------------------------------------------
lib... |
architecture rtl of fifo is
alias designator is name;
signal sig1 : std_logic;alias designator is name;
signal sig1 : std_logic; alias designator is name;
begin
end architecture rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
entity router_channel is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 5;
Rxy_rst : integer :=... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: TMDS Encoder
-- 8 bits colour, 2 control bits and one blanking bits in
-- 10 bits of TMDS encoded data out
-- Clocked at the pixel clock
--
----------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: TMDS Encoder
-- 8 bits colour, 2 control bits and one blanking bits in
-- 10 bits of TMDS encoded data out
-- Clocked at the pixel clock
--
----------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:19 04/24/2017
-- Design Name:
-- Module Name: benes8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:19 04/24/2017
-- Design Name:
-- Module Name: benes8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:45:14 03/06/2016
-- Design Name:
-- Module Name: C:/Users/Yakov/OneDrive/School/University Stuff/ENEL500/test232/tb_rs232.vhd
-- Project Name: test232
-- Target Device:
-- Tool vers... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--!
--! Copyright 2020 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- This -*- vhdl -*- file was generated from std_logic_1164-body.proto
-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-------------------------------------------------------------------------------
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers fo... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
ram_init_inst : ram_init PORT MAP (
clock => clock_sig,
init => init_sig,
dataout => dataout_sig,
init_busy => init_busy_sig,
ram_address => ram_address_sig,
ram_wren => ram_wren_sig
);
|
ram_init_inst : ram_init PORT MAP (
clock => clock_sig,
init => init_sig,
dataout => dataout_sig,
init_busy => init_busy_sig,
ram_address => ram_address_sig,
ram_wren => ram_wren_sig
);
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_agent is
generic(
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_DATA_SIDEBAND_H: integer := 105;
PKT_DATA_SIDEBAND_L: integer := 98;
PKT_ADDR_SIDEBAND_H: integer := 97;
PK... |
--! @file dataLatch-syn-a.vhd
--! @brief Data latch generated architecture
-------------------------------------------------------------------------------
-- Architecture : syn
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redi... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc_v2
-- Module Name: Stage_Polynomial_Calc_v2
-- Project Na... |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eithe... |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eithe... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310_tb is
end ADT7310_tb;
architecture behavior of ADT7310_tb is
component ADT7310
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- company:
-- engineer:
--
-- vhdl test bench created by ise for module: random_number
--
-- dependencies:
--
-- revision:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_lo... |
-- File: bin2gray.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon May 23 16:09:27 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end en... |
-- File: bin2gray.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon May 23 16:09:27 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end en... |
-- File: bin2gray.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon May 23 16:09:27 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end en... |
-- File: bin2gray.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon May 23 16:09:27 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end en... |
-- File: bin2gray.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon May 23 16:09:27 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end en... |
-- File: bin2gray.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon May 23 16:09:27 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity bin2gray is
port (
B: in unsigned(7 downto 0);
G: out unsigned(7 downto 0)
);
end en... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
... |
-- SHA256 Hashing Module - Functions
-- Kristian Klomsten Skordal <kristian.skordal@wafflemail.net>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha256_types.all;
use work.sha256_constants.all;
package sha256_functions is
-- Function used to index arrays using std_logic_vector:
fu... |
-- VHDL do controlador de impressao do tabuleiro
library ieee;
use ieee.std_logic_1164.all;
entity controlador_impressao is
port(
clock : in std_logic;
reset : in std_logic;
comeca_impressao : in std_logic;
uart_livre : in std_logic;
posica... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
package wed is
type wed_type is record
status : std_logic_vector(7 downto 0); -- 7 downto 0
wed00_a : std_logic_vector(7 downto 0); -- 15 downto 8
... |
library ieee;
use ieee.std_logic_1164.all;
entity dut is
port (
sig_i : in std_logic_vector;
sig_o : out std_logic_vector
);
end entity;
architecture arch of dut is
begin
sig_o <= (sig_o'range => 'X') after 1 ns, sig_i after 2 ns;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end ent... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shr_141 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shr_141;
architecture augh of shr_141 i... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shr_141 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shr_141;
architecture augh of shr_141 i... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.