content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- William Fan
-- 02/14/2011
-- Signed Counter RTL
package sgncounter is
component counter is
port (j,k: in std_logic;
out_bin: out std_logic);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.sgncounter.all;
entity scounter is
generic (N: int... |
library IEEE;
use IEEE.std_logic_1164.all;
entity inv is
port(inb: in STD_logic;
outb: out STD_Logic);
end inv;
architecture structure of inv is
begin
outb <= not (inb);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity nand2 is
port(a, b: in STD_logic;
outb: out STD_Logic);
end nand2;
architect... |
--Copyright (c) 2005 National Center For Atmospheric Research All rights reserved;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity mux is
port(
add_bus_hi:in std_logic;
add_bus_lo:in std_logic_vector(3 downto 0);
data_bus:i... |
-- Nancy Minderman
-- nancy.minderman@ualberta.ca
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward dec... |
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Generic version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo_std.vhd
-... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may ... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:28:20 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:02:04 10/11/2013
-- Design Name:
-- Module Name: C:/Users/mblott/Desktop/SmartCAM/toe_sessionLup/SmartCamTest.vhd
-- Project Name: toe_sessionLup
-- Target Device:
-- Tool versions:... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:02:04 10/11/2013
-- Design Name:
-- Module Name: C:/Users/mblott/Desktop/SmartCAM/toe_sessionLup/SmartCamTest.vhd
-- Project Name: toe_sessionLup
-- Target Device:
-- Tool versions:... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ebb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !... |
entity sub is
port (
x : in integer );
end entity;
entity top is
end entity;
architecture test of top is
begin
end architecture;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrica... |
-- Dual port Video RAM
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vram is
port(
clk_a : in std_l... |
library verilog;
use verilog.vl_types.all;
entity InstruMemory is
generic(
DATA_WIDTH : integer := 32;
DATA_LENGTH : integer := 128;
ADX_LENGTH : integer := 7
);
port(
clk : in vl_logic;
adx : in vl_logic_vector;
W... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity mem_regs is
generic (
SIZE : integer := 32
);
port (
W_i : in std_logic_vector(SIZE - 1 downto 0);
D3_i : in std_logic_vector(4 downto 0);
W_o : out std_logic_vector(SIZE - 1 downto 0);
D3_o : out std_logic_... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY... |
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY... |
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY... |
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY... |
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Stack Using Single Port Distributed RAM
----------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Stack Using Single Port Distributed RAM
----------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Stack Using Single Port Distributed RAM
----------------------... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eaa_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g... |
library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
"xxx" . null;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity conv_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * ... |
-- The order of design units in the file is significant
package pack1 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
---------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DoubleSingleWordVoter is
port(
clk :... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
library verilog;
use verilog.vl_types.all;
entity Control_unit is
port(
IRset : in vl_logic_vector(0 to 8);
IRin : out vl_logic;
Riout : out vl_logic_vector(0 to 7);
Gout : out vl_logic;
DINout : out vl_logic;... |
-- NEED RESULT: ARCH00138.P1: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00138.P2: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00138.P3: Multi inertial transactions occurred on signal asg with indexe... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:58:12 2019
-- Host : varun-laptop running 64-bit Service ... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:58:12 2019
-- Host : varun-laptop running 64-bit Service ... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:58:12 2019
-- Host : varun-laptop running 64-bit Service ... |
--
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either ve... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComFlow_pkg.all;
-- Top level du driver USB
-- 4 output flows max
-- 2 input flow max
-- TODO
-- PASSER LES Identifiants de FLOW en générique du driver:
-- ca permettrait de specifier les valeurs des identifiants des trames par GPStudio
-... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- /... |
--------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 07-04-2017
-- Package Name: alu/components
-- Module Name: FULL_ADDER
------------... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
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