content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--!
--! @file: exercise8_3.vhd
--! @brief: circuilar shift with compenet #1 constant stages
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_components.all;
-- Main code
-----... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * ... |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
entity outputModule is
generic(
address: regflit
);
port(
clock: in std_logic;
tx: in std_logic;
data: in regflit;
currentTime: std_logic_ve... |
----------------------------------------------------------------------------------
-- Module Name: link_signal_mgmt - Behavioral
--
-- Description: Controls the settings and state of the GTX transceivers based on
-- The registers that are read from the host.
--
--------------------------------------... |
---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as ... |
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC AD7266
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2013
----------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC AD7266
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2013
----------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
package xtccomppkg is
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $RCSfile: mult_gen_v11_2_xst_comp.vhd,v $ $Revision: 1.4 $ $Date: 2010/03/19 10:56:59 $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. ... |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rpm_counter_tb is
generic
(
BITS_N : natural := 20;
MIN_RPM_LIM : natural := 2**18;
TEST_RPM : natural := 2**16
);
end entity;
architecture rtl of rpm_cou... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_b_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity flag is
port(
busOut : in vl_logic_vector(31 downto 0);
busA : in vl_logic_vector(31 downto 0);
busB : in vl_logic_vector(31 downto 0);
carryOut : in vl_logic;
z ... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidentia... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_cor... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_cor... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_cor... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_cor... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
--
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versi... |
-- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- -------... |
-- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- -------... |
-------------------------------------------------------------------------------
-- Title : Abstract Memory-Mapped Interface
-- Project :
-------------------------------------------------------------------------------
-- File : AbstractMmPkg.vhd
-- Author : Rob Gaddi <rgaddi@highlandtechnology.com>
-... |
library IEEE;
use IEEE.std_logic_1164.all;
-- Barrel shifter de N bits (default = 4)
entity barrel_shifterNb is
-- Cantidad de bits
generic (N: NATURAL := 4);
port (
to_left : in std_logic;
M : in natural;
a : in std_logic_vector(N-1 downto 0);
o : out std_logic_vector(N-1 downto... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
-- -------------------------------------------------------------
--
-- Generated Configuration for di_tnrc
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/17/2013 07:39:31 PM
-- Design Name:
-- Module Name: sdram_buffer_fifo_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity STEP_MOD is
generic (
-- IO-REQ: 19 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(1... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and propr... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: John Bieling ----
---- ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Top level for the OV7670 camera project.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSL is port(
S : in std_logic;
R : in std_logic;
Q : out std_logic;
nQ : out std_logic
);
end RSL;
architecture structual of RSL is
component NOR2 is port(
a, b: in std_logic;
z: out std_logic);
end component;
component REP is port(
a: in std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
us... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-----------------------------------------------------------------------------------------------------------
--
-- REGISTER FILE
--
-- The register file is a read/write memory, made up of 8 32-bit general purpose registers.
-- It can be addressed by different resource... |
entity tb_insert01 is
end tb_insert01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_insert01 is
signal a : std_logic_vector (3 downto 0);
signal b : std_logic;
signal o0, o1, o2, o3 : std_logic_vector (3 downto 0);
begin
dut: entity work.insert01
port map (a, b, o0, o1, o2, o3);
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 2;
NRP : integer := 3;
AW : integer := 10;
DW : integer := 16
);
port... |
entity wait20 is
end entity;
architecture test of wait20 is
signal x : bit_vector(1 to 3);
begin
main: process is
begin
x <= "010" after 2 ns, "101" after 4 ns, "111" after 6 ns;
wait on x(2) for 10 ns; -- Splits the nexus
assert now = 2 ns;
assert x = "010";
... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
package ARITHMETIC is
-- integer definitions
type t_int is ra... |
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
... |
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
... |
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
... |
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY BSA16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC
);
END BSA16bits;
archit... |
entity tb_memmux04 is
end tb_memmux04;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux04 is
signal wen : std_logic;
signal waddr : std_logic_vector (3 downto 0);
signal wdat : std_logic_vector (31 downto 0);
signal raddr : std_logic_vector (3 downto 0);
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may b... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity screen_position_gen is
port (
-- inputs
nrst : in std_logic;
clk108 : in std_logic;
vblank : in std_logic;
in_line_change : in st... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
USE ieee.numeric_std.all;
entity memory is
port(
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
new_data: IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(17 downto 0); -- data input
data_out... |
entity crash_entity is end entity;
architecture default of crash_entity is
type rec is record
v : natural;
end record;
attribute s : rec;
function func return boolean is
begin
return s.v = 0;
end function;
begin
end architecture;
|
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