content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ToPixelWinner is
Port (
DataIn : in STD_LOGIC_VECTOR (107 downto 0);
Column : in STD_LOGIC_VECTOR (6 downto 0);
PixelOut : out STD_LOGIC
);
end ToPixelWinner;
architecture Behavioral of ToPixelWinner is
begin
--Select pixel data in accor... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--*********************************************************************************... |
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--*********************************************************************************... |
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--*********************************************************************************... |
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--*********************************************************************************... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- M... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- M... |
-----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;... |
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlost... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
type T;
DEPTH : positive );
port (
clk : in std_logic;
pop : in std_logic;
push : in std_logic;
full : out std_logic;
valid : out std_logic;
din ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_4_e-... |
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.... |
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.... |
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.... |
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nor2to1 is
port (
A: in std_logic;
B: in std_logic;
Z: out std_logic
);
end nor2to1;
architecture behavioral of nor2to1 is
begin
Z <= A nor B;
end behavioral; |
entity tb_arr06 is
end tb_arr06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr06 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr06
port map (clk => clk, val => va... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
li... |
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
li... |
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
li... |
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
li... |
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated doc... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
library verilog;
use verilog.vl_types.all;
entity quanta_vlg_check_tst is
port(
hex0 : in vl_logic_vector(6 downto 0);
hex1 : in vl_logic_vector(6 downto 0);
hex2 : in vl_logic_vector(6 downto 0);
hex3 : in vl_logic_vector(6... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:18 05/29/2014
-- Design Name:
-- Module Name: FSM3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_xor is
port (
bit1_in: in std_logic := '0';
bit2_in: in std_logic := '0';
result: out std_logic := '0'
);
end;
architecture bit_xor_arq of bit_xor is
begin
process(bit1_in, bit2_in)
begin
result <= bit1_in xor bit2_in;
en... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_l... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_signal is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
store, update, clear, clock : in std_logic;
output : out std_logic_vector((width + 1) downto 0)
);
end c_signal;
architect... |
package my_package is
type my_type_t is record
state : bit_vector;
aux : bit_vector;
end record my_type_t;
type my_array_t is array (natural range <>) of my_type_t;
end package my_package;
-------------------------------------------------------------------------------
entity record38 is
e... |
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY bcd_adder IS
PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END bcd_adder;
ARCHITECTURE Behavi... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: ibdr_rk11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rk11 - syn
-- Description: ibus dev(rem... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ae_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tl_car_field is
port(
osc_out: out std_logic;
osc_in: in std_logic;
ext_clk_in: in std_logic;
--
l_lvds_io: inout std_logic;
r_lvds_io: inout std_logic;
--
i2s1_sck: out std_logic;
i2s1_ws: out std_logic;
i2s1_d0: in s... |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity testina is
end entity;
architecture beh of testina is
component mezzanotte is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_... |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity testina is
end entity;
architecture beh of testina is
component mezzanotte is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Fri Oct 16 15:22:50 2015
-- Host : cascade.andrew.cmu.edu running 64-bi... |
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux01 is
port (
wen : std_logic;
addr : std_logic_vector (3 downto 0);
wdat : std_logic;
rdat : out std_logic_vector (15 downto 0);
clk : std_logic;
rst : std_logic);
end memmux01;
architecture rtl of memmux01 is
... |
library ieee, altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use altera.altera_syn_attributes.all;
entity PZP_MIF is
port (clk: in std_logic;
addr: in natural range 0 to 63;
q: out std_logic_vector (7 downto 0));
end entity;
architecture rtl of PZP_MIF is
type PZP_MIF_t is array (63 downto 0) of... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5 is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); ... |
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESU... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RxIn_Delay... |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Ha... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
entity MaliDek2 is port (
a0, e: in std_logic;
i0, i1: out std_logic);
end MaliDek2;
architecture arch of MaliDek2 is
begin
i0 <= e and not a0;
i1 <= e and a0;
end arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
architecture RTL of TxDataStateMachine is
-- States of the TxDataStateMachine
type StatesTX is(stIdle, stLoad, stShift, stParityWrite, stStopWrite);
-- Signal Declartation
-- Signal for the States
signal CurrentState : StatesTX;
signal NextState : StatesTX;
-- Signal for the DataBits
signal DataBit... |
library verilog;
use verilog.vl_types.all;
entity clock is
port(
clk : out vl_logic
);
end clock;
|
library verilog;
use verilog.vl_types.all;
entity clock is
port(
clk : out vl_logic
);
end clock;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; e... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.