content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
... |
package range1 is
subtype preal is real range 1.0 to real'high;
function as_positive (x : integer) return positive;
function as_positive (x : real) return preal;
end package;
package body range1 is
function as_positive (x : integer) return positive is
variable p : positive;
begin
... |
--
-- OutputGenerator.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copy... |
entity test is
subtype t is ((bar baz, qux zzz)) foo;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_imme... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_imme... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_imme... |
-------------------------------------------------------------------------------
--
-- Title : absdb
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\E... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity PreScale is
generic (BIT_WIDTH : integer := 19);
Port(inclock: IN std_logic;
outclock: OUT std_logic);
End PreScale;
--generic map (BIT_WIDTH=>6) port map ()
Architecture structure of PreScale is
signal Q: unsigned (BIT_WIDTH-1 downto 0... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--*****************************************************************************
--*****************************************************************************
-- Model: testbench for a uniaxial MEMS accelerometer accelZa_02.vhd in hAMSter
--
--
-- Author: <vladimir.kolchuzhin@ieee.org>
-- Date: 30.09.2021
-- ... |
--!
--! Copyright 2020 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
library verilog;
use verilog.vl_types.all;
entity control_vlg_check_tst is
port(
lose : in vl_logic;
roll : in vl_logic;
sp : in vl_logic;
win : in vl_logic;
sampler_rx : in vl_logic
);
end control_vl... |
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- =========================... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @details PLL instance for the behaviour simulation
--!
--! "Output Output Phase Duty Pk-... |
use Std.Textio.all;
library IEEE;
library worklib;
use ieee.std_logic_1164.ALL;
entity test_c_and
is end;
architecture test_c_and of test_c_and is
component c_and
generic (width : integer := 1);
port (input1 : std_logic_vector((width -1) downto 0);
input2 : std_logic_vector((width -1) downto 0);
... |
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better reso... |
-------------------------------------------------------------------------------
--
-- File: LM.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilen... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY pulselut_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top_capture_cotnrol_test.vhd
-- Created : 2016-02-22
-- Last up... |
entity bar is
end entity bar;
entity \foo\ is
port (test : in bit);
end entity \foo\;
architecture structural of \foo\ is
begin -- architecture structural
end architecture structural;
architecture structural of bar is
signal test : bit;
begin -- architecture structural
foo_1: entity work.\foo\
port map (tes... |
entity bar is
end entity bar;
entity \foo\ is
port (test : in bit);
end entity \foo\;
architecture structural of \foo\ is
begin -- architecture structural
end architecture structural;
architecture structural of bar is
signal test : bit;
begin -- architecture structural
foo_1: entity work.\foo\
port map (tes... |
entity bar is
end entity bar;
entity \foo\ is
port (test : in bit);
end entity \foo\;
architecture structural of \foo\ is
begin -- architecture structural
end architecture structural;
architecture structural of bar is
signal test : bit;
begin -- architecture structural
foo_1: entity work.\foo\
port map (tes... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:47:09 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CAM_Wrapper is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 8 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECT... |
library verilog;
use verilog.vl_types.all;
entity Addsub is
port(
a : in vl_logic_vector(15 downto 0);
b : in vl_logic_vector(15 downto 0);
select_add_sub : in vl_logic;
result : out vl_logic_vector(15 downto 0)
);
end Addsub;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cpu_1x3 is
generic (
PROGRAM_00 : string := "input.prg";
PROGRAM_01 : string := "passthrough.prg";
PROGRAM_02 : string := "output.prg");
port (
I_clk : in std_logic;
I_reset : in std_logic);
end cpu_1x3;
architecture Behavioral of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
ENTITY INTERFACE_COMB_1 IS
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END;
ARCHITECTURE RTL OF INTERFACE_COMB_1 IS
----------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:44:56 06/01/2014
-- Design Name:
-- Module Name: toplevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 17:04:32 2015
-- Host : Vangelis-PC running 64-bit major rel... |
--------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Kovacs Laszlo - Attila
--
-- Create Date: 12:53:59 01/11/08
-- Module Name: Memory - Behavioral
-- Project Name: StreamIO
-- Description:
-- Implements dualport synchronous memory ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
---------------------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
---------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reconos_hwt_idle is
port (
-- OSIF FIFO ports
OSIF_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_Sw2Hw_Empty : in std_logic;
OSIF_Sw2Hw_RE : out std_logic;
OSIF_Hw2Sw_Data : out std_logic_vector(31 downto 0);
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- After input has been loaded, run calcs to fill up entire message digest
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Ge... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
type t_int1 is range 0 to 100 ;
subtype st_int1 is t_int1 range 8 to 60 ;
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr2_range1 is integer ran... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity VGA3BitTestPattern is
port (
RstN : in bit1;
Clk : in bit1;
--
Button : in word(3-1 downto 0);
--
HSync : out bit1;
VSync : out bit1;
VgaRed : out word(3-1 d... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:09:59 09/30/2014
-- Design Name:
-- Module Name: ADCS7476_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:09:59 09/30/2014
-- Design Name:
-- Module Name: ADCS7476_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:04 05/20/2016
-- Design Name:
-- Module Name: ADDR_calculator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your opti... |
-- NEED RESULT: ARCH00412.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00412: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00412: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00412: One i... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- (c) EMARD
-- LICENSE=BSD
-- generic (vendor-agnostic) serializer
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY serializer_generic IS
GENERIC
(
C_channel_bits: integer := 10; -- number of bits per channel
C_output_bits: integer := 1; -- output bits per channel
C_channels: integer := 3 -- number of channe... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 16-03-2017
-- Module Name: memory.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.a... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_xadc_core_drp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLA... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any ... |
----------------------------------------------------------------------------------
-- Company: RAT Technologies (a subdivision of Cal Poly CENG)
-- Engineer: Various RAT rats
--
-- Create Date: 02/03/2017
-- Module Name: RAT_wrapper - Behavioral
-- Target Devices: Basys3
-- Description: Wrapper for RAT ... |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_test_1.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
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