content stringlengths 1 1.04M ⌀ |
|---|
-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity subtract is
port (
a : in unsigned(3 downto 0);
b : in unsigned(3 downto 0);
out_sig : out unsigned(... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:24:15 07/31/2014
-- Design Name:
-- Module Name: C:/Documents and Settings/paulmoon/Desktop/SENG440/huffman/huffman_testbench.vhd
-- Project Name: huffman
-- Target Device:
... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contai... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 1;
NRP : integer := 1;
AW : integer := 11;
DW : integer := 32
);
port... |
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
port (
writedata : in std_logic_vector(31 downto 0... |
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
port (
writedata : in std_logic_vector(31 downto 0... |
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architectu... |
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architectu... |
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architectu... |
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architectu... |
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architectu... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee; context c1, c1a, c1b;
library ieee; context con1; context con2; context con3;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Math extension package.
--
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
-------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_lo... |
package pkg is
type type_t is (a,b,c,d);
function type_t_image(data : type_t) return string;
end package;
package body pkg is
function type_t_image(data : type_t) return string is
begin
return type_t'image(data);
end;
end;
use work.pkg.all;
entity bug is
end entity;
architecture arch of bug is
begin
... |
package pkg is
type type_t is (a,b,c,d);
function type_t_image(data : type_t) return string;
end package;
package body pkg is
function type_t_image(data : type_t) return string is
begin
return type_t'image(data);
end;
end;
use work.pkg.all;
entity bug is
end entity;
architecture arch of bug is
begin
... |
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
m : out std_logic);
end mux;
architecture behavioral of mux is
begin
process(a,b,c,d... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to us... |
-------------------------------------------------------------------------------
-- full_axi.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_l... |
library IEEE;
use IEEE.std_logic_1164.all;
entity UC_receptor is
port(
CLOCK, RESET, LIGA, CD : in std_logic;
DTR, enable_recepcao : out std_logic;
dep_estado : out std_logic_vector(1 downto 0)
);
end UC_receptor;
architecture estados of UC_receptor is
type ti... |
library verilog;
use verilog.vl_types.all;
entity SeqSideEightBitAdder_vlg_check_tst is
port(
HEX0 : in vl_logic_vector(6 downto 0);
HEX1 : in vl_logic_vector(6 downto 0);
LEDR : in vl_logic_vector(8 downto 0);
sampler_rx : in vl_... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
use work.pico_cpu.all;
entity PicoCPUTestBench is
end PicoCPUTestBench;
architecture Bench of PicoCPUTestBench is
--Component declaration for ALU
signal clk: std_logic:= '0';
signal rst: std_logic:= '0';
signal IO: std_logic_vector(CP... |
------------------------------------------------------------------------------
-- qmfir.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHA... |
------------------------------------------------------------------------------
-- qmfir.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHA... |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package breakout_config is
type control_signal_out is (go_up, go_down, go_left, go_right, pause, end_game, launch, none);
constant SCREEN_Y_BEGIN : integer := 64;
constant SCREEN_Y_END : integer := 80;
constant SCREEN_BRICK_BEGIN :... |
-- modified 2006-05-13 (Line 404)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_async is
generic(
DEPTH : natural;
AWIDTH : natural;
DWIDTH : natural;
RAM_TYPE : string -- "BLOCK_RAM" or "DIS_RAM"
);
port(
reset : in std_logic;
clr : in... |
architecture Struct of TbdAudioCodecAvalon is
component Audio is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
audio_clk_clk : out std_logic; -- clk
i2s_adcdat : in std_logic := 'X'; -- adcdat
i2s_adclrck ... |
entity should_fold is
generic ( X : boolean );
end entity;
architecture test of should_fold is
begin
g: if not X generate -- Error if not constant folded
assert X;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity... |
entity should_fold is
generic ( X : boolean );
end entity;
architecture test of should_fold is
begin
g: if not X generate -- Error if not constant folded
assert X;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity... |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Rea... |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Rea... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- NEED RESULT: ARCH00677: Attributes inherited by aliases passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
------------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForwardingUnit is
Port ( EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VEC... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForwardingUnit is
Port ( EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VEC... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity vhdl2008 is
end entity;
architecture test of vhdl2008 is
begin
process is
variable x, y : integer;
begin
x := 1 when y > 2 else 5; -- OK
x := 5 when x; -- Error
x := 1 when x < 1 else false; -- Error
end process;
-- Changes to locally st... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : eth_filter
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------... |
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:45 01/24/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/analogue/vhdl/analogue_tb.vhd
-- Project Name: analogue
-- Target Device:
-- Tool versions:
-- Descr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- axi_sg_ftch_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights re... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_971;
architecture augh of cmp_971 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_971;
architecture augh of cmp_971 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;
architecture behavior of gates is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal notA : std_logic;
signal notB : std_logic;
signal notC : std_logic;
signal notD : std_... |
library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;
architecture behavior of gates is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal notA : std_logic;
signal notB : std_logic;
signal notC : std_logic;
signal notD : std_... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- dummy entity
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum ... |
component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0); ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
library unisim;
use unisim.vcomponents.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce :... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
library unisim;
use unisim.vcomponents.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce :... |
entity main is
end entity main ;
architecture arch of main is
-- type t is range -1 to 10;
-- type t is integer;
signal s1 : integer;
signal s2 : integer;
signal s : integer;
begin
s <= s1 + s2;
main: process(s)
begin
report integer'image(s);
end process;
end;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis transl... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis transl... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO... |
-- This is valid
architecture RTL of ENTITY1 is
begin
end architecture RTL;
-- This is not valid
architecture ENTITY1 of entity1 is
begin
end architecture ENTITY1;
-- This is valid
architecture BLUE of ENTITY1 is
begin
end architecture BLUE;
-- This is not valid
architecture CDC of ENTITY1 is
begin
end arch... |
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNH6PQLQQ2 is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad_ctrl.vhd,v 1.3 2005-09-15 17:28:17 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:27 2017
-- Host : DarkCube running 64-bit major re... |
entity ieee7 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
architecture test of ieee7 is
begin
main: process is
variable x, y, z : ufixed(7 downto -3) := (others => '0');
begin
z := to_ufixed(0, 7, -3);
assert x + y = z;
x := to_ufixed(5, 7,... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
a, b : in std_logic_vector(31 downto 0);
control : in std_logic_vector(2 downto 0);
output : out std_logic_vector(31 downto 0);
zero : out std_logic);
end alu;
architecture behave of alu is
begin
end b... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may ... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_core.vhd
-... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatch is
port(SW : in std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(2 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downt... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- N TO 16 BITS Adaptateur
-- valeurs possibles entrée 8,16,32
-- tester avec 1, 2, 4 avec le code en 8to16, devrait fonctionner ou presque ...
-- ALtera libray used for 32 to 16 bits scfifo component
LIBRARY altera_mf;
USE altera_mf.al... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.