content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilin... |
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary i... |
-------------------------------------------------------------------------------
-- Title : Infrared Receiver Package
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_pkg.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform ... |
-------------------------------------------------------------------------------
-- Title : Infrared Receiver Package
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_pkg.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your opti... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
EN... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:03:41 02/06/2015
-- Design Name:
-- Module Name: adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:03:41 02/06/2015
-- Design Name:
-- Module Name: adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
--
-- Author: Adam Howard - ahowar31@utk.edu, Ben Olson - molson5@utk.edu
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Button debouncing and control logic
--
----------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Bus_Arbitter is
port(clk: in std_logic;
rst: in std_logic;
correq: in std_logic;
cordone: in std_logic;
req_1: in std_logic;
req_2: in std_logic;
req_3: in std_logic;
req_4: in std_logic;
grant_1: out std_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
package main_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 1935;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package bod... |
------------------------------------------------------------
-- Notes:
-- Clock on FALLING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dsp_mul is
port(
clk: in std_ulogic;
a_i: in std_ulogic_vector(23 downto 0);
b_i: in std_ulogic_vector(16 downto 0);
p_o: out std_ulogic_vector(40 downto 0)
);
end dsp_... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(
clk, reset: in std_logic;
data_1, data_2: in std_logic;
clk_out: out std_logic;
ps_control: out std_logic;
LED: out std_logic_vector(7 downto 0)
);
end test;
architecture be... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/21/2015 12:17:45 PM
-- Design Name:
-- Module Name: SRAM16Bytes - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is... |
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is... |
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is... |
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is... |
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
----------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
----------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_... |
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ae
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerate... |
-- NEED RESULT: ARCH00354.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00354.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00354.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: A... |
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_e... |
entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
functi... |
entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
functi... |
entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
functi... |
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : portbin.vhd
-- PROJECT : Altera A8255 Peripheral Interface Adapter
-- PURPOSE : This file contains the entity and architecture
-- for the Port B Input R... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_seq_generator - Behavioral
--
-- Description: A very bad random SYN number generator
--
-----------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 ... |
-- file: clk_wiz_v3_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This di... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -----------------------------------------------... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY genAdderUnsgndSat IS
GENERIC(
value_len : integer
);
PORT(
value0 : IN std_logic_vector(value_len-1 downto 0);
value1 : IN std_logic_vector(value_len-1 downto 0);
output : OUT std_logic_vector(value_len-1 downto 0)
);
END genAdderUnsgndSat;
A... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity add is
port (
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
c_i: in std_logic;
s: out std_logic_vector(3 downto 0);
c_o: out std_logic );
end add;
architecture add_arch of add is
signa... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_559 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_559;
architecture augh of mul_559 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_559 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_559;
architecture augh of mul_559 is
signal tmp_res : signed(... |
architecture RTL of ENTITY_NAME is
begin
process
begin
FORCE_LABEL : sig1 <= transport a and c;
FORCE_LABEL : sig1 <= a and c;
sig1 <= a and c;
check_value(to_integer(unsigned(v_normalized_chan)) <= config.max_channel, TB_FAILURE, "Sanity check: Check that channel number is supported.", scope... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
entity test_ is end;
|
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity Binary_7_Segment is
port (bin : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end Binary_7_Segment;
architecture binToHex of Binary_7_Segment is
begin
with bin select
seg <= "1000000" when "0000... |
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity Binary_7_Segment is
port (bin : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end Binary_7_Segment;
architecture binToHex of Binary_7_Segment is
begin
with bin select
seg <= "1000000" when "0000... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
package fifo_pkg is
end package;
library ieee;
package fifo_pkg is
end package;
-- Comment
package fifo_pkg is
end package;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
entity tb_var04 is
end tb_var04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var04 is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (15 downto 0);
signal res : std_logic_vector (15 downto 0);
begin
dut: entity work.var04
port m... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004-2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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