content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- From OSVVM
--
use std.textio.all ;
package NamePkg is
type NamePType is protected
procedure Set (NameIn : String) ;
impure function Get (DefaultName : string := "") return string ;
impure function GetOpt return string ;
impure function IsSet return boolean ;
procedure Clear ; -- clear name
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cache is
Generic (WIDTH : natural := 13; -- Length of address
DWIDTH : natural := 13; -- Length of one entry
CACHE_SIZE : natural := 4); -- Log2 of number of entries in the cache
Port ( clk, reset : in STD_LO... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:50 07/14/2014
-- Design Name:
-- Module Name: key_expansion_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:01:55 11/20/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/Desktop/Nibble_Knowledge_CPU(1)/tb_io_mapping.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool ve... |
architecture RTL of FIFO is
SIGNAL sig1 : std_logic;
SIGNAL sig2 : std_logic;
-- Violations below
SIGNAL sig1 : std_logic;
SIGNAL sig2 : std_logic;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rs232_tb IS
END rs232_tb;
ARCHITECTURE behavior OF rs232_tb IS
COMPONENT RS232
PORT(
clk : IN std_logic;
Entrada_8bits : IN std_logic_vector(7 downto 0);
Activador_Envio_Mensaje : IN std_logic;
Salida_1bit : OUT ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- Serial reset for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
-------------------------------------------------------------------------------
-- $Id$
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilin... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity uart_bridge is
port (
-- UART Interface
uart_clock : in std_logic ;
uart_reset : in std_logic ;
uart_enable : in std_logic ;
uart_rxd : out std_logic ;
uart_txd : out std_log... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.flink_definitions.ALL;
--USE work.UART_pkg.ALL;
entity uartDevice_S00_AXI is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_uarts: INTEGER RANGE 0 TO 16 :=... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR :... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR :... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR :... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR :... |
------------------------------------------------------------------------------
--
-- Design : Branch Predicton Buffer
-- Project : Tomasulo Processor
-- Entity : bpb
-- Author : kapil
-- Company : University of Southern California
-- Last Updated : June 24, 2010
--... |
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_dclk : out std_logic; -- dclk
epcs_flash_sce : out std_logic; -- sce
epcs_flash_sdo ... |
library ieee;
use ieee.std_logic_1164.all;
use work.rec10_pkg.all;
entity rec10 is
port (inp : std_logic;
o : out myrec);
end rec10;
architecture behav of rec10 is
begin
o.b (1) <= not inp;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.std_logic_misc.all;
package RWCACHE_PKG is
constant RWCACHE_WAYS : natural := 2;
constant RWCACHE_NUMSETS : natural := 4; --Depth of ICache
constant RWCACHE_WORDS : natural := 2;
constant DATA_SIZE : natural := 32;
constant RWCA... |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
----... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
a... |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: add_flt_stratix5_speed.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- =============... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
package myutils is
subtype dfu_opcode_t is std_logic_vector(4 downto 0);
subtype dfu_veclen_t is std_logic_vector(9 downto 0);
subtype raw_dfu_config_t is std_logic_vector(14 downto 0);
type dfu_config_t is record... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00662
--
-- AUTHOR:
--
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revi... |
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis (christos.bakalis@cern.ch)
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-B... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
library IEEE;
use ieee.std_logic_1164.all;
-- ENTITY
entity FSMctrl is
port(
CLK, RST, ENTER: in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Selecao: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end FSMctrl;
--ARCHITECTURE
architecture FSM_beh of FSMctrl is
type states is(... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
library work;
use work.i2c_arb_pkg.all;
ENTITY testbench_i2c_arbiter IS
END testbench_i2c_arbiter;
ARCHITECTURE behavior OF testbench_i2c_arbiter IS
signal clk : std_logic := '0';
signal reset : std_logic := '1'; -- low-level active
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow ----... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
-------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
-------------------------------------------------------------------... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generat... |
-------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generat... |
-------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generat... |
--------------------------------------------------------------------------------------------------
-- Sparse FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
----------------------------------------------------... |
----------------------------------------------------------------------------
-- debouncer.vhd -- Signal Debouncer
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
-------------------------------------------------------------... |
entity test is
end entity test;
architecture test of test is
-- next line should fail to compile because it's not legal to assign a default value to a signal parameter
procedure proc(signal a : integer := 1) is
begin
end procedure proc;
begin
end architecture test;
architecture test2 of test is
pr... |
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.26.17:32:01
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par is
port (
vertex_col : out std_logic_vector(15 downto 0); ... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Versi... |
--
-- VHDL Architecture lab8_new_lib.Decoder.Structure
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 12:10:03 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Decode_stage IS
GENERIC( n... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
-------------------------------------------------------------------------------
--
-- The testbench for t8048.
--
-- $Id: tb_t8048.vhd,v 1.8 2008-04-28 22:10:13 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised fo... |
-- fft16_tb.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- This testbench simulates a 16-Point FFT for manual testing. Pipelining
-- and synchronisation can be tested.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity fft16_tb is
... |
architecture RTL of ENTITY1 is
type memory is array (DEPTH - 1 downto 0) of STD_LOGIC_VECTOR(WIDTH-1 downto 0);
type memory is array (DEPTH - 1 downto 0) of
STD_LOGIC_VECTOR(WIDTH-1 downto 0);
begin
end architecture RTL;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_mux_2x1_busInput IS END tb_mux_2x1_busInput;
ARCHITECTURE test OF tb_mux_2x1_busInput IS
CONSTANT size: I... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 15:55:33 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(
clk, res_as, up : in std_logic;
count : out std_logic_vector (3 downto 0)
);
end entity;
architecture behav of counter is
signal Q : std_logic_vector (3 downto 0) := "0000";
signal N... |
library ieee;
use ieee.std_logic_1164.all;
entity gpio is
port( clk : in std_logic;
rst : in std_logic;
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
wr : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(7 downto 0)... |
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
... |
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
... |
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
... |
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C1 is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
F: out std_logic
);
end C1;
architecture c1_estr of C1 is
begin
F <= A or B or C;
end c1_estr; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity cronometro is
port (
-- Entradas
startStop: in std_logic;
puestaCero: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
rightSegs: out std_logic_vector(7 d... |
-- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, incl... |
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