content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- zobrazi 4 hexa cislice (DATA) na 4 mistnem 7segmentovem displeji (SEGMENT, DP, DIGIT)
entity HEX2SEG is
port (
DATA : in STD_LOGIC_VECTOR (15 downto 0); -- vstupni data k zobrazeni (4 sestnactkove cislice)
CLK : ... |
library verilog;
use verilog.vl_types.all;
entity Counter16anDisplay_vlg_vec_tst is
end Counter16anDisplay_vlg_vec_tst;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ex... |
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ex... |
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ex... |
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ex... |
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ex... |
-----------------------------------------------------------------------------------------------------
-- Mux Stall
-- This mux is controlled by the Hazard Detection Unit. The control signal is mux_op, when asserted
-- the mux force a Control Word of a NOP (Control Word + ALU Opcode), otherwise the Control Word
-- p... |
-----------------------------------------------------------------------------------------------------
-- Mux Stall
-- This mux is controlled by the Hazard Detection Unit. The control signal is mux_op, when asserted
-- the mux force a Control Word of a NOP (Control Word + ALU Opcode), otherwise the Control Word
-- p... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_k1_k4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Autho... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
entity e is
end entity;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Met... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
entity e is
end entity;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Met... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_cmd_demux is
port(
sink_valid : in vl_logic_vector(0 downto 0);
sink_data : in vl_logic_vector(104 downto 0);
sink_channel : in vl_logic_vector(5 downto 0);
sink_startofpacket: in... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux19x1 is
port (H1, T1, U1, H2, T2, U2, H3, T3, U3, CTRL1, CTRL2, CTRL3: in std_logic_vector(7 downto 0);
mais, menos, vezes, barra, igual, dois, CTRLf: in std_logic_vector(7 downto 0);
s: in std_logic_vector(4 downto 0);
m: out std_logic_vector(7 downto 0)
... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
entity test is
end test;
architecture only of test is
type int_array is array (3 downto 0) of integer;
begin -- only
p: process
variable w, x, y, z : integer := 0;
variable q : int_array := (3, 2, 1, 0);
begin -- process p
(w, x, y, z) := q;
assert w = 3 report "TEST FAILED" severity FAILURE;
... |
entity test is
end test;
architecture only of test is
type int_array is array (3 downto 0) of integer;
begin -- only
p: process
variable w, x, y, z : integer := 0;
variable q : int_array := (3, 2, 1, 0);
begin -- process p
(w, x, y, z) := q;
assert w = 3 report "TEST FAILED" severity FAILURE;
... |
entity test is
end test;
architecture only of test is
type int_array is array (3 downto 0) of integer;
begin -- only
p: process
variable w, x, y, z : integer := 0;
variable q : int_array := (3, 2, 1, 0);
begin -- process p
(w, x, y, z) := q;
assert w = 3 report "TEST FAILED" severity FAILURE;
... |
entity tb_assert2 is
end tb_assert2;
architecture behav of tb_assert2 is
signal v, res : natural;
signal en : boolean := false;
begin
dut: entity work.assert2
port map (v, en, res);
process
begin
en <= True;
v <= 2;
wait for 1 ns;
assert res = 3 severity failure;
v <= 11;
en <= ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add32_tb is
end add32_tb;
architecture TB of add32_tb is
component add32
port(
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
cin : in std_logic;
cout : out ... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 12/13/2013 07:56:40 PM
-- Design Name:
-- Module Name: global_clock_reset - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- This module encapsula... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major relea... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
component wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_slave_0_abus_read ... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
package std is end;
|
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_log... |
-------------------------------------------------------------------------------
-- axi_sg_ftch_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights r... |
-- -------------------------------------------------------------
--
-- Entity Declaration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $I... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
---------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
---------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
---------------------... |
-------------------------------------------------------------------------------
-- microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_00_a;
use microblaze_... |
-- Top level of the com block, contains the flow to com and com to flow mux.
-- Also instantiates the flow to com and com to flow block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com_package.all;
entity com is
generic (
FIFO_IN_N : integer := 4;
FIF... |
architecture rtl of fifo is
begin
process begin
report "hello";
report "hello";
end process;
end architecture rtl;
|
----------------------------------------------------------------------
-- brdConst_pkg (for SmartFusion(1) Evaluation Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constan... |
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step ... |
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step ... |
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step ... |
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.array32.all;
entity mul32booth is
port(
mr,md : in std_logic_vector(31 downto 0);
out1 : out std_logic_vector(63 downto 0)
);
end mul32booth;
architecture rtl of mul32booth is
signal outDecod... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VH... |
library ieee;
use ieee.s_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav... |
--Practica5 de Diseño Automatico de Sistemas
--Piano Electronico.
--Altavoz.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity speaker is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector (7 downto 0);
new_data : in std_log... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:42 2019
-- Host : varun-laptop running 64-bit Serv... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:05 07/16/2014
-- Design Name:
-- Module Name: cipher_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ok_1_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath_line IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
RESETX, RESETY, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 do... |
----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_log... |
----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_log... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Devel... |
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect ke... |
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`protect ke... |
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect begin_protected
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`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect ke... |
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Simple testbench for playing around with the CRC calculation code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.al... |
library IEEE, STD;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_1164.all;
entity ledramp_tb is
end ledramp_tb;
architecture tb_arch of ledramp_tb is
-- UUT component
component ledramp
generic (
PWM_RANGE_MAX : integer := 5000000
);
port (
clk : in std_logic;
... |
-- This is the implementation of a constant delay
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program ... |
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port (
a_31 : in std_logic;
b_31 : in std_logic;
diff_31 : in std_logic;
carry : in std_logic;
zero : in std_logic;
op ... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Mar 20 20:54:09 2017
--Host : N73-PC running 64-bit major release (bui... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published... |
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