content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:53 04/11/2016
-- Design Name:
-- Module Name: PCStack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:53 04/11/2016
-- Design Name:
-- Module Name: PCStack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
... |
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
... |
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
... |
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
... |
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
--------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
--------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
--------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
--------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
--------------------------------------------------... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_in_8b_sync_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.a... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
entity STOP_32b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of STOP_32b is
begin
-------------... |
----------------------------------------------------------------------------------
-- Company: PWr
-- Engineer: Kacper Witkowski
-- Module Name: Serializer
-- Project Name: Nadajnik i odbiornik szeregowy z kontrolą poprawności przesyłu CRC16
-----------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Deadtime generation
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'93/02
------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Deadtime generation
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'93/02
------------------------------------------------... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:09:13 2017
-- Host : EffulgentTome running 64-bit maj... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/07/2015 10:17:42 PM
-- Design Name:
-- Module Name: Increment16Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; --... |
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; --... |
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; --... |
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; --... |
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; --... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_... |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 14:22:20
-- Design Name: rx_path_lookup_memory.vhd
-- Module Name: rx_path_lookup_memory - structural
-- Project Name: automotive ethernet gateway
-- Targe... |
-- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LED blinking module
entity ledblinker is
port (clk: in std_logic; -- clock, rising edge
... |
--
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-... |
-- Revision history:
-- 07.08.2015 Carlos Minamisava Faria created
-- 07.08.2015 Carlos Minamisava Faria entity
-- 07.08.2015 Carlos Minamisava Faria moore state machine states definition
-- 10.08.2015 Carlos Minamisava Faria & Patrick Appenheimer Instructions added
-- 10.08.2015 Patrick A... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- ion_wishbone_bridge.vhdl -- Connects an ION bus master to a Wishbone bus.
--------------------------------------------------------------------------------
-- ION_WISHBONE_BRIDGE
-- This bridge converts ION-bus signals to Wishbone signa... |
library ieee;
use ieee.numeric_bit.all;
entity View2 is
port(
Rb, Reset, CLK: in bit;
Win, Lose:out bit;
hex0,hex1:out unsigned(7 downto 0)
);
end entity View2;
architecture Sys of View2 is
component Segment7Decoder
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(... |
-- ps2_rx_tb.vhd - TB modulu pro prijem signalu z portu PS2
-- Autori: Jakub Cabal
-- Posledni zmena: 04.10.2014 21:24
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY TB_... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
library ieee;
use ieee.std_logic_1164.all;
entity anod_enabler_decoder_tb is
end;
architecture anod_enabler_decoder_tb_func of anod_enabler_decoder_tb is
signal data_in: std_logic_vector(1 downto 0) := (others => '0');
signal data_out: std_logic_vector(3 downto 0) := (others => '0');
component ano... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
begin
end architecture RTL;
|
-------------------------------------------------------------------------------
-- Design : Instruction Fetch Queue i_fetch_q
-- Project : Tomasulo Processor
-- Author : Gandhi Puvvada
-- Company : University of Southern California
-- Date : 07/25/2008 , 7/15/2009, 6/29/2010
-- This file is same as the fil... |
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ***********************************************... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:09:00 01/06/2016
-- Design Name:
-- Module Name: my_alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CLAH8bits;
ARCHITECTURE strc_CLAH8bits of CLAH8bits is
SIGNA... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
------------------------------------------------------------... |
package error2 is
subtype char128 is character range (NUL to DEL); -- Error
-- Crash here
constant k : string := IfElse(false, "Status: " & IfElse(true, "PASSED", "FAILED") & LF, "");
end package;
|
--
-- synthesis test 3:
-- * with clock enable
-- * fast
--
--
-- Altera EP2C-8, Quartus 8.0: 286 LEs,0 bits mem, fmax = 295 MHz (320 requested)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw3_grain128 is
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I ... |
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_scheduler_tb_v1_00_a;
use plb_schedu... |
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_scheduler_tb_v1_00_a;
use plb_schedu... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/11/2018 04:18:22 PM
-- Module Name: writeback - Behavioral
-- Description: Writeback shift register
--
-- Additional Comments:
-- This is an output buffer for the ALU stage for the control ... |
--*****************************************************************************
-- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved.
-- Module name : ADS58C48
-- Call by :
-- Description : this module is the top module of ADS58C48.
-- IC : 5CGXFC7D7F31C8N
-- Version ... |
--ovo su komentari
--trebali bi biti zanemareni
ENTITY Adder_4_bit IS PORT(
x: in std_logic_vector(3 downto 0); --prvi broj
y: in std_logic_vector(3 downto 0); -- drugi broj
cin: in std_logic;
sum: out std_logic_vector(3 downto 0);
cout: out std_logic
);
END Adder_4_bit;
architecture arch OF Adder_4_bit IS
sign... |
-------------------------------------------------------------------------------
-- Title : Strobe generator
-- Project :
-------------------------------------------------------------------------------
-- File : strobe_gen.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03... |
architecture RTL of FIFO is
attribute coordinate of OTHERS : component is (0.0, 17.5);
attribute coordinate of OTHERS :component is (0.0, 17.5);
begin
end architecture RTL;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
LIBRARY RS232_test;
USE RS232_test.RS232_test.all;
entity PICtop_tb is
end PICtop_tb;
architecture TestBench of PICtop_tb is
component PICtop
port (
Reset ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
... |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Top-level description of a simple von-Neumann MCU.
-- All top-level compone... |
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xil... |
entity ieee8 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.fixed_pkg.all;
architecture test of ieee8 is
procedure check(value : in float32; expect : in real) is
variable r : real;
begin
r := to_real(value);
assert value > expect - 0.00001;
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vactcapdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:03 2017
-- Host : EffulgentTome running 64-bit major... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
-- $Id: pdp11_ounit.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ounit - syn
-- Description: pdp11: a... |
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