content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://gith... |
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://gith... |
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_e... |
-- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_mips32/ALU_control.sch - Mon May 14 15:21:40 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx reco... |
library ieee;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity spi_reader is
port (
clock : in std_logic ;
sclk : out std_logic ;
miso : in std_logic ;
mosi : out std_logic ;
enx : out std_logic ;
reset_out : out std_logic
) ;
end entit... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ======================================================================
-- CBC-DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistri... |
-------------------------------------------------------------------------------
-- Title : Entity for simulation model of MAX6682 temperature sensor
-- Project :
-------------------------------------------------------------------------------
-- File : max6682-e.vhd
-- Author : Johann Glaser
-- Compan... |
-------------------------------------------------------------------------------
-- Title : Entity for simulation model of MAX6682 temperature sensor
-- Project :
-------------------------------------------------------------------------------
-- File : max6682-e.vhd
-- Author : Johann Glaser
-- Compan... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare15.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================... |
--
-- LinearTableMul.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki (brezza@pokipoki.org)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyr... |
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
... |
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
... |
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
... |
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
... |
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
-- for LHI instr. which loads the 16 bit immediate values imm16 into the most significant
-- half of an integer register and clears the least significant half (i.e. imm16 ## 0^16)
entity concat16 is
port(
-- inputs
string16 : in std_logic_vector(15 downto 0);... |
-- NEED RESULT: ARCH00422: Dynamic elaboration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_multiplexer is
generic(
PORT_SIZE: natural := 1;
PORT_QUANT: natural := 2); --Port quantity, la cantidad de puertos de entrada
port (
data_in: in
data_out: out std_logic_vector(PORT_SIZE-1 downto 0);
);
end;
a... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux04 is
port (ad : std_logic_vector (1 downto 0);
val : std_logic;
dat : std_logic_vector (3 downto 0);
res : out std_logic_vector (3 downto 0));
end memmux04;
architecture behav of memmux04 is
begin
process (a... |
library IEEE;
use ieee.std_logic_1164.all;
entity registers is
port(
readRegister1, readRegister2, writeRegister : in std_logic_vector(4 downto 0);
writeData : in std_logic_vector(31 downto 0);
clk, rst, pre, regWrite : in std_logic;
readData1, readData2 : out std_logic_vector(31 downto 0)
);
end registers;... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--------------------------------------------------------------------------------
-- file name : glb_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity
-- arch_itecture
--
-- language : vhdl
--
------------------------... |
--------------------------------------------------------------------------------
-- Generated from template tb_template.vhdl by hexconv.pl
--------------------------------------------------------------------------------
-- Light8080 simulation test bench.
----------------------------------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e, f : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END ENTITY mux;
ARCHITECTURE Behavior OF mux IS
SIGNAL Qs : STD_LOGIC_VECTOR(N-1 DOWN... |
-- NEED RESULT: ARCH00690: Allocators with generic scalar qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
----------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity slice03 is
port (di : std_logic_vector(7 downto 0);
do : out std_logic_vector (3 downto 0));
end slice03;
architecture behav of slice03 is
begin
do <= di (7 downto 4)(7 downto 4);
end behav;
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyrig... |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyrig... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use... |
-------------------------------------------------------------
-- MSS copyright 2011-2014
-- Filename: COM5402.VHD
-- Author: Alain Zarembowitch / MSS
-- Version: 6
-- Date last modified: 1/31/14
-- Inheritance: N/A
--
-- description: Internet IP stack: IP/TCP/UDP/ARP/PING.
-- The IP stack... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shiftr00 is
port(
clkcshr: in std_logic ;
codopcshr: in std_logic_vector ( 3 downto 0 );
portAcshr: in std_logic_vector ( 7 downto 0 );
inFlagcshr: in std_logic;
outcshr: out std_logic_ve... |
library verilog;
use verilog.vl_types.all;
entity MeioSomador4Bits_vlg_vec_tst is
end MeioSomador4Bits_vlg_vec_tst;
|
-- $Id: bp_rs232_2l4l_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description:... |
--------------------------------------------------------------------------
-- package com tipos basicos
--------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
package PhoenixP... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG24 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(23 downto 0);
CLR : in vl_logic_vector(23 downto 0);
FLAG ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG24 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(23 downto 0);
CLR : in vl_logic_vector(23 downto 0);
FLAG ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG24 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(23 downto 0);
CLR : in vl_logic_vector(23 downto 0);
FLAG ... |
library ieee;
use ieee.std_logic_1164.all;
entity foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of foo_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a and b;
y <= a or b;
end if... |
library ieee;
use ieee.std_logic_1164.all;
entity foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of foo_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a and b;
y <= a or b;
end if... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/27/2016 04:46:45 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_dma is
port (
rst : in st... |
------------------------------------------------------------------------------
-- File name: top_cpu.vhd
-- Function : Top file for the Tomasulo CPU project with file i/o
-- Modified by : Prasanjeet Das
-- Date : 7/20/09, 7/24/09, 7/25/09
-----------------------------------------------------------------------... |
--
-- FeedbackMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This module represents a store for feedback data of all OPLL channels. The feedback
-- data is written by the OutputGenerator module. Then the value written is
-- read from ... |
--
-- FeedbackMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This module represents a store for feedback data of all OPLL channels. The feedback
-- data is written by the OutputGenerator module. Then the value written is
-- read from ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:51:15 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
begin
END;
end generate;
IF_LABEL : if a = '1' generate
begin
END;
end generate;
CASE_LABEL : case data generate
when choice =>
begin
END;
end generate;
-- Violations below
FOR_LABEL : for i in ... |
--------------------------------------------------------------------------------
--
-- Title : fp23_mult
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : floating point multiplier
--... |
-------------------------------------------------------------------------------
-- Title : Rotation-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_rotate_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company ... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
---------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
---------------------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: VGA_SYNC
-- AUTHORS: Vojtěch Jeřábek <xjerab17@stud.feec.vutbr.cz>
-- Jakub Cabal <xcabal05@st... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:11 01/04/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/dma/tb_dma_bus_controller.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Descriptio... |
-----------------------------------------------------------------------------------
-- Odsek za racunarsku tehniku i medjuracunarske komunikacije --
-- Copyright © 2009 All Rights Reserved --
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_axis_dwidth_converter
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xili... |
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_axis_dwidth_converter
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xili... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.koc_lock_pack.all;
entity koc_lock_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_defa... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\CPU_Subsystem_8_bit_pkg.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1... |
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
library IEEE;
use IEEE.std_logic_1164.all;
entity SCIT4 is
port (
A, B : in std_logic_vector ( 3 downto 0 );
Cin : in std_logic;
S : out std_logic_vector ( 4 downto 0 )
);
end entity SCIT4;
architecture SCIT4_BODY of SCIT4 is
signal C : std_logic_vector ( 4 downto 0 );
begin
-- VSTUP : process (Cin)... |
-- Project: VHDL to Verilog RTL translation
-- Revision: 1.0
-- Date of last Revision: February 27 2001
-- Designer: Vincenzo Liguori
-- vhd2vl test file
-- This VHDL file exercises vhd2vl
LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity test is port(
-- ... |
architecture rtl of fifo is
constant AVMM_SLAVE_NULL : t_avmm_slave :=
(
(others => '0'),
'0',
'0'
);
constant cons1 : t_type :=
(
(others => '0'),
(1 => '0', others => '1'),
(others => '0')
);
constant cons2 : t_type :=
(
(others => (valid => '0', data => (others => '0'))),
(others ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xil... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:16:06 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
entity TESTONE is
end TESTONE;
architecture beh of TESTONE is
component sedici_bit is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out ... |
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