content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
entity TESTONE is
end TESTONE;
architecture beh of TESTONE is
component sedici_bit is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:17 02/10/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/Source/AudioIO/DAPwm_tb.vhd
-- Project Name: SoundboxProject
-- Target Device:
-- Tool versi... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in char... |
architecture RTL of FIFO is
begin
process
begin
for x in (0 to 30) loop
end loop;
loop
end loop;
-- Violations below
for x in (0 to 30) loop
end loop;
for x in (0 to 30) loop
end loop;
end process;
end;
|
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
------------------------------------------------------------------------------... |
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
------------------------------------------------------------------------------... |
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
------------------------------------------------------------------------------... |
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
------------------------------------------------------------------------------... |
-- lib2
package pkg2 is
constant const2 : integer := 1;
end package;
package body pkg2 is
end package body;
use work.pkg2.all;
package pkg is
constant const : integer := const2 + 1;
end package;
package body pkg is
end package body;
------------------------------------------------------------------------------... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux32b is
PORT( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
Sel: in STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0));
end mux32b;
architecture arqMux32b of mux32b is
begin
process(A, B, Sel)
begin
if (Sel = '... |
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity Example0 is port(
clk_clk, clk_reset_n... |
--------------------------------------------------------------------
-- Package: MultiIO
-- File: MultiIO.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by Manfred.Helzle@embedd.it
--
-- Description: APB Multiple digital I/O Types and Components
... |
--------------------------------------------------------------------
-- Package: MultiIO
-- File: MultiIO.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by Manfred.Helzle@embedd.it
--
-- Description: APB Multiple digital I/O Types and Components
... |
----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 16:38:03 06 Oct 2008
-- Design Name:
-- Module Name: DDR_Blink - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vor
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:56:34 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vor-rtl-conf-c.v... |
library verilog;
use verilog.vl_types.all;
entity altparallel_flash_loader is
generic(
EXTRA_ADDR_BYTE : integer := 0;
FEATURES_CFG : integer := 1;
PAGE_CLK_DIVISOR: integer := 1;
BURST_MODE_SPANSION: integer := 0;
ENHANCED_FLASH_PROGRAMMING: integer := 0;
FLASH_EC... |
library ieee;
library ieee;
library ieee;
library ieee;
library ieee;
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:08:51 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_RegFile_TB.vhd
-- Project Name: TestCPU1
... |
package body fifo_pkg is
end package body;
package body fifo_pkg --comment
is
end package body;
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** ... |
-------------------------------------------------------------------------------
-- Title : includeModuleBVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleBVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-0... |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
data_en : out std_logic; ... |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL is
port (
data_en : out std_logic; ... |
-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005 HT-LAB ... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific RAM selector
---------------------------------------------------------------... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 07-05-2016
-- Module Name: p4-2.vhd
--------------------------------------------------------------------------------
-- next state logic for a FSM
process (... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
--!
--! @file: exercise5_10.vhd
--! @brief: arithmetic circuit with integer
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mini_alu is
generic (N: integer ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity spi is
port(
clk: in std_logic;
data: in std_logic_vector(31 downto 0);
ready: out std_logic;
valid: in std_logic;
clatch: out std_logic;
cclk: out std_logic;
cdata: out std_logic
);
e... |
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Configuration for using the testbench in post-synthesis simulation
-- Start work.post_synthesis_spartan6 in your simulator of choice
... |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.std_LOGIC_1164.all;
entity Counter9999Tb is
end Counter9999Tb;
-- Teste unitário para contador de 0 a 9999.
architecture Stimulus of Counter9999Tb is
signal s_clk, s_reset, s_enable : std_logic;
signal s_count... |
package pkg is
generic ( gen: natural );
constant test: natural:=gen;
end package;
package body pkg is
end pkg;
package mygpkg is new work.pkg generic map ( gen => 17 );
|
package pkg is
generic ( gen: natural );
constant test: natural:=gen;
end package;
package body pkg is
end pkg;
package mygpkg is new work.pkg generic map ( gen => 17 );
|
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
... |
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
... |
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
... |
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
... |
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
p... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
p... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
p... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic ( widthB : natural := 8;
widthA : natural := 16);
p... |
library ieee;
use ieee.std_logic_1164.all;
entity init is
port (o : out std_logic);
end init;
architecture behav of init is
begin
o <= '0';
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity forgen02 is
port (a : out std_logic_vector (7 downto 0));
end;
architecture behav of forgen02 is
-- constan... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_hardware_interface_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ... |
-- NEED RESULT: ARCH00016: Associated composite generics with globally static subtype passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
---------------------------------------------... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_eba_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: w... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sign_ext_unit is
Port( entrada : in STD_LOGIC_VECTOR (12 downto 0);
salida : out STD_LOGIC_VECTOR (31 downto 0)
);
end sign_ext_unit;
architecture ArqSignExt of sign_ext_unit is
begin
process(entrada)
begin
if (entrada(1... |
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
----... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
-- $Id: tbd_serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, ei... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated Please do not change!
-- Here are the parameters:
-- network size x:2
-- network size y:2
-- data width:32-- traffic pattern:------------------------------------------... |
-- $Id: sys_tst_snhumanio_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either ... |
entity test is
subtype t is foo(bar)(open);
end;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:58)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library lib;
use lib.controller.all;
use lib.general.all;
use lib.io.all;
entity spaceinvaders is
generic
(
rx : integer := 160; -- H resolution
ry : integer := 120; -- W resolutio... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY FlashReader IS
PORT (
KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:34 12/02/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/jummmmmmmm/tbfetchhhh.vhd
-- Project Name: jummmmmmmm
-- Target Device:
-- Tool versions:
-- Desc... |
constant SensorFSMLength : integer := 1180;
constant SensorFSMCfg : std_logic_vector(SensorFSMLength-1 downto 0) := "1111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000000000000000001010000000100100000000000000000011000101001000100000001000000010001000010010010000... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock... |
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