content stringlengths 1 1.04M ⌀ |
|---|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the F... |
library ieee;
use ieee.std_logic_1164.all;
entity MUX5X1 is
port(
clk: in std_logic;
distortion: in std_logic_vector(15 downto 0);
reverb: in std_logic_vector(15 downto 0);
AUDIO_IN: in std_logic_vector(15 downto 0);
audio_loop : in std_logic_vector(15 downto 0);
OUTPUT: out std_logic_vector(15 downto 0);... |
-- NEED RESULT: ARCH00273: Conformance checking passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--... |
-------------------------------------------------------------------------------
-- proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v2_00_a;
use pro... |
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 19:44:54 04/12/2011
-- Design Name:
-- Module Name: PWM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Pulse-Width Modul... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram3 is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA ... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : gen_counter.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Syste... |
-- NEED RESULT: ARCH00424: Identifiers passed
--
-- TEST NAME:
--
-- CT00424
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.3 (1)
-- 13.3 (2)
-- 13.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00424)
-- ENT00424_Test_Bench(ARCH00424_Test_Bench)
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
LIBRARY lib;
USE lib.general.all;
entity score is
port(
clock_i,reset_i: in std_logic;
score_o: out std_logic_vector(27 downto 0)
);
end score;
architecture Behavior of score is
signal unidade, dezena, centena, milhar: integer :=... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 00:51:00 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use std.textio.all;
package rom is
generic (
word_bits: positive;
address_bits: positive;
rom_filename: string
);
subtype word_type is std_logic_vector(word_bits-1 downto 0);
... |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity Bcd2digitAdder_vlg_vec_tst is
end Bcd2digitAdder_vlg_vec_tst;
|
-- VHDL da Unidade de Controle da transmissão
library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_modem_recepcao is
port(clock : in std_logic;
reset : in std_logic;
liga : in std_logic;
CD : in std_logic;
R... |
--!
--! @file: example10_1.vhd
--! @brief: writing values to a file
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
use std.textio.all;
--------------------------------------
entity write_to_file is
end entity write_to_file;
--------------------------------------
arch... |
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2021 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.synt... |
entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedu... |
entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedu... |
entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedu... |
entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedu... |
entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedu... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library verilog;
use verilog.vl_types.all;
entity Forward is
port(
RegDst : in vl_logic_vector(1 downto 0);
Rt_From_ID_EX : in vl_logic_vector(4 downto 0);
Rs_From_ID_EX : in vl_logic_vector(4 downto 0);
Rd_From_EX_MEM : in vl_logic_vector(4 downto 0);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity alu_tb is
end alu_tb;
architecture alu_test of alu_tb is
component alu is
port (
clk : in std_logic;
reset : in std_logic;
opcode : in opcode_t;
opa : in word_t;
opb : in word_t;
result : out word_t... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
Rst : in STD_LOGIC;
clk : in STD_LOGIC;
Ncwp : in STD_LOGIC_VECTOR (4 downto 0);
Carry : out STD_LOGIC;
Cwp : out STD_LOGIC_VECTOR (4 downto 0);
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:33:05 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bi... |
-- cb20.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20 is
port (
clk_clk : in std_logic := '0'; -- ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package wishbone_types is
type wb_slave_out_t is record
dat : bit_vector;
ack : bit;
stall : bit;
end record;
-- Common subtypes
constant wb_cpu_data_bits : integer := 64;
subtype wb_cpu_in_t is wb_slave_out_t(dat(wb_cpu_data_bits-1 downto 0));
-- GHDL: Works
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
library verilog;
use verilog.vl_types.all;
entity MF_pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
d : in vl_logic;
clrn : in vl_logic;
prn : in ... |
-- Luz uC memory mapper - connects the internal Wishbone bus
-- between the CPU, user memory, and the various peripherals.
-- Serves as a crossbar, routing bus transactions from the CPU
-- to different modules depending on address mapping.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
... |
-- Luz uC memory mapper - connects the internal Wishbone bus
-- between the CPU, user memory, and the various peripherals.
-- Serves as a crossbar, routing bus transactions from the CPU
-- to different modules depending on address mapping.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package pkg is
procedure other_proc(value : boolean);
procedure other_proc(value : integer);
procedure proc(other_proc : integer);
procedure proc;
end package;
package body pkg is
procedure proc2 is
begin
proc(other_proc => 0);
end;
end package body;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- **********************************************
-- Banco de prueba para Circuitos combinacionales
-- **********************************************
-- En inglés se llama testbench
library ieee;
use ieee.std_logic_1164.all;
entity ig2_bp is
end ig2_bp;
architecture arq_bp of ig2_bp is
signal prueba_e1, prueba_e2:... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Codeword Generator 1
-- Module Name: Tb_Codeword_Generator_1
-- Project Name... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 4/2;
assert x = 2 report "TEST FAILED - x does not equal 2" severity failure;
assert x /= 2 report "TEST PASSED" severity note;
wait;
end process;
e... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 4/2;
assert x = 2 report "TEST FAILED - x does not equal 2" severity failure;
assert x /= 2 report "TEST PASSED" severity note;
wait;
end process;
e... |
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 4/2;
assert x = 2 report "TEST FAILED - x does not equal 2" severity failure;
assert x /= 2 report "TEST PASSED" severity note;
wait;
end process;
e... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 09:41:53 AM
-- Design Name:
-- Module Name: mmc_clk_manager - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
-- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associat... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C4 is
port (A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
F: out std_logic_vector(7 downto 0)
);
end C4;
architecture circuito of C4 is
begin
F <= not(A);
end circuito; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- ... |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad_ctrl.vhd,v 1.3 2005/09/15 17:28:17 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: FALLING_EDGE_DETECTOR
-- AUTHORS: Jakub Cabal <xcabal05@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, pl... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 30-05-2016
-- Module Name: p6-2.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_nand_gate_busInput IS END tb_nand_gate_busInput;
ARCHITECTURE test OF tb_nand_gate_busInput IS
CONSTANT s... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee ;
use ieee.numeric_bit.all;
entity DiceGame_controller is
port(Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
end DiceGame_controller;
architecture DiceGameControl of DiceGame_controller is
signal State, Nextstate: integer range 0 to 5:=0;
signal Poin... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity RomBasic2 is
port (
clk : in std_logic;
addr : in std_logic_vector(13 downto 0);
data : out std_logic_vector(7 downto 0)
);
en... |
-- File: clock.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sat May 28 18:39:08 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_081.all;
entity clock is
port (
clk: in std_logic;
reset: in std_logic;
en: in std_logic;
c... |
--+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
... |
--+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
ARCHITECTURE struct OF i2c_master IS
-- Component Declaration
COMPONENT i2ccore
Generic ( DividerWidth_g : integer range 4 to 32);
Port ( Reset_i : in STD_LOGIC;
Clk_i : in STD_LOGIC;
Data_i : in STD_LOGIC_VECTOR (7 downto 0);
Data_o... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:03:44 11/22/2012
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:18:48 06/05/2016
-- Design Name:
-- Module Name: C:/Users/AlvaroMoreno/Desktop/proooc/sacagawea_copy/test_clock_counter_cntrl.vhd
-- Project Name: Sacagawea
-- Target Device: ... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
entity FIFO is
end entity FIFO;
entity --Comment
--Comment
--Comment
FIFO is
end entity FIFO
;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagene01.all;
entity topgeneric01 is
port(
clk0: in std_logic ;
codop00: in std_logic_vector ( 3 downto 0 );
enable00: in std_logic ;
en20: in std_logic ;
PortA00: in std_logic_vector ( 7 ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AU is
port(
a_in : in unsigned(3 downto 0);
b_in : in unsigned(3 downto 0);
control_in : in unsigned(3 downto 0);
control_out : out unsigned(3 downto 0);
data_out : out unsigned(3 downto 0);
com... |
-- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_Display is
Port (
Hex_IN : in STD_LOGIC_VECTOR (15 downto 0);
iCLK : in STD_LOGIC;
MOSI : out STD_LOGIC;
CSN : out STD_LOGIC;
SCK : out STD_LOGIC);
end SPI_Di... |
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity test;
architecture behaviour of test is
type arecordtype is record
valid : std_ulogic;
write_data : std_ulogic_vector(63 downto 0);
end record;
signal a : arecordtype;
subtype byte_index_t ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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