content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Model: dc voltage source
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <vladimir.kolchuzhin@etit.tu-chemnitz.de>
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-----------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Model: dc voltage source
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <vladimir.kolchuzhin@etit.tu-chemnitz.de>
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-----------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb is
end;
architecture arch of tb is
signal clk: std_logic := '0';
signal lclk: std_ulogic;
signal stop: boolean := false;
signal lclk_count: integer := 0;
component acomp is
port (x: in std_ulogic; y: ... |
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb is
end;
architecture arch of tb is
signal clk: std_logic := '0';
signal lclk: std_ulogic;
signal stop: boolean := false;
signal lclk_count: integer := 0;
component acomp is
port (x: in std_ulogic; y: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out S... |
-- Copyright (c) 2013, Jahanzeb Ahmad
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of condition... |
-- Copyright (c) 2013, Jahanzeb Ahmad
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of condition... |
-- Copyright (c) 2013, Jahanzeb Ahmad
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of condition... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License a... |
--------------------------------------------------------------------------------
-- Title : Definitions and Constants for WBB2VME
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_pkg.vhd
-- Author : michael.miehling@men.d... |
library ieee;
use ieee.std_logic_1164.all;
entity issue2 is
end issue2;
architecture beh of issue2 is
type t_rec is
record
elem : std_logic_vector (3 downto 0);
end record;
function fun (arg : std_logic_vector) return t_rec is
begin
return t_rec'(elem => arg);
end ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_nov is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_nov;
architecture behaviour of scf_nov is
constant state1: std_logic_vector(6 downto 0) :=... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
-... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
-... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
-... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
-... |
-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.8
-- Thu May 9 17:13:50 2019
-- parameterized module component declaration
component fmexg_fifo_5
port (Data: in std_logic_vector(11 downto 0);
WrClock: in std_logic; RdClock: in std_logic;
WrE... |
-- fichier testenv.vhdl (C) Yann Guidon 2010
-- version jeu. sept. 2 06:38:43 CEST 2010
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
entity test is
package a is new b generic map(c => (bar) foo);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:30:27 10/04/2016
-- Design Name:
-- Module Name: instruction_memory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
library verilog;
use verilog.vl_types.all;
entity FSM_core_vlg_sample_tst is
port(
CLK : in vl_logic;
reset : in vl_logic;
X : in vl_logic;
sampler_tx : out vl_logic
);
end FSM_core_vlg_sample_tst;
|
library verilog;
use verilog.vl_types.all;
entity FSM_core_vlg_sample_tst is
port(
CLK : in vl_logic;
reset : in vl_logic;
X : in vl_logic;
sampler_tx : out vl_logic
);
end FSM_core_vlg_sample_tst;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of ent_a
--
-- Generated
-- by: wig
-- on: Thu Oct 20 06:53:04 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2a1 is
port( i0, i1, s : in std_logic;
o : out std_logic
);
end mux2a1;
architecture flow of mux2a1 is
begin
o <= i0 when s='0' else i1;
end flow;
-- 2 to 1 mux with XLEN number of inputs and outputs.
library IEEE;
use IE... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AB_TB IS
END LatchSR_AB_TB;
ARCHITECTURE behavior OF LatchSR_AB_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AB
PORT(
Sn : IN std_logic;
Rn : IN std_logic;
Q : OUT std_logic;
... |
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_receiver_async2sync is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iSIGNAL : in vl_logic_vector;
oSIGNAL : ... |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ----------------------------... |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ----------------------------... |
library verilog;
use verilog.vl_types.all;
entity CMMaster1Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster1Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster1Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_10_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- a... |
library ieee;
use ieee.std_logic_1164.all;
entity assert3 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
res : out natural);
end;
architecture behav of assert3 is
begin
process (v, en)
begin
res <= 0;
if en = '1' then
for i in v'range loop
if v (i) = '1' then
... |
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)... |
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)... |
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 08:22:22 PM
-- Design Name:
-- Module Name: decryptionLoopCore_V1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
... |
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- Thi... |
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- Thi... |
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- Thi... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MAXIMUM_32b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of ... |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Timing the entire decoding sequence blocks.
-- provide a proper speed data clock for the interceptor to output data at the same speed as USB.
ENTITY timer is
port(clk, rst:IN STD_LOGIC;
egde_det, f_egde_det, EOP:IN STD_LOGIC; -- edge use to re-synchronize the timer, f... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity o_ALU_Control is
Port (
-- inputs
i_ALUOp : in STD_LOGIC_VECTOR(1 downto 0); -- From Main Control Unit
i_Inst_Funct : in STD_LOGIC_VECTOR(5 downto 0); -- From Instruction memory
-- outputs
o_ALU_Co... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity o_ALU_Control is
Port (
-- inputs
i_ALUOp : in STD_LOGIC_VECTOR(1 downto 0); -- From Main Control Unit
i_Inst_Funct : in STD_LOGIC_VECTOR(5 downto 0); -- From Instruction memory
-- outputs
o_ALU_Co... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOT1 is port(
a: in std_logic;
z: out std_logic
);
end NOT1;
--
architecture NOT1 of NOT1 is
begin
z <= not a;
end NOT1; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOT1 is port(
a: in std_logic;
z: out std_logic
);
end NOT1;
--
architecture NOT1 of NOT1 is
begin
z <= not a;
end NOT1; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.02.2016 21:28:53
-- Design Name:
-- Module Name: DataSequencer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity freq_man is
port
(
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
clk_out1 : out std_l... |
architecture RTL of FIFO is
ATTRIBUTE max_delay : time;
ATTRIBUTE MAX_DELAY : TIME;
begin
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity OR2 is port(
a,b: in std_logic;
z: out std_logic
);
end OR2;
--
architecture OR2 of OR2 is
begin
z <=a or b;
end OR2; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- NEED RESULT: *** An assertion violation should follow
-- NEED RESULT: ARCH00026: Assertion Violation only occurs when condition is false passed
-- NEED RESULT: *** No assertion violation should follow
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: pre-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: pre-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: pre-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000... |
entity tb_block02 is
end tb_block02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_block02 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.block02
port map (
q => dout,
d => din,
clk => clk);
process
procedur... |
library ieee;
use ieee.std_logic_1164.all;
entity clear_video_ram is
generic(
N_bits_row: natural := 2;
N_bits_col: natural := 2;
N_ROWS: natural := 2;
N_COLS: natural := 2
);
port(
clock: in std_logic;
reset: in std_logic;
enable: in std_logic;
... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
PACKAGE int_to_7seg_pack IS
TYPE logic_vector_array IS ARRAY (0 TO 9) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
END PACKA... |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_im is
port(
clk : in vl_logic;
jdo : in vl_logic_vector(37 downto 0);
jrst_n : in vl_logic;
reset_n : in vl_logic;
take_action_tracectrl: in ... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- http... |
--
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your op... |
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
----------------------------------------... |
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler (cjt@users.sourceforge.net)
-- Standard : VHDL'93/02
----------------------------------------... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
--------------------------------... |
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
--------------------------------... |
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
--------------------------------... |
entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav... |
entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav... |
entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
termi... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : top_test_uart
-- Date : 07/25/2016
--
-- Description :
--
-- --------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sat Mar 19 19:16:24 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major... |
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