content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc682.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00682ent IS
END c03s04b01x00p23n01i00682ent;
ARCHITECTURE c03s04b01x00p23n01i00682arch OF c03s04b01x00p23n01i00682ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
variable i3, i2, i1: INTEGER;
file S1: FT open read_mode is "iofile.47";
BEGIN
wait for 10 ns;
READ(S1,i3);
READ(S1,i2);
READ(S1,i1);
wait for 10 ns;
assert NOT( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***PASSED TEST: c03s04b01x00p23n01i00682"
severity NOTE;
assert ( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***FAILED TEST: c03s04b01x00p23n01i00682 - Procedure READ retrieves the next value from a file."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00682arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc682.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00682ent IS
END c03s04b01x00p23n01i00682ent;
ARCHITECTURE c03s04b01x00p23n01i00682arch OF c03s04b01x00p23n01i00682ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
variable i3, i2, i1: INTEGER;
file S1: FT open read_mode is "iofile.47";
BEGIN
wait for 10 ns;
READ(S1,i3);
READ(S1,i2);
READ(S1,i1);
wait for 10 ns;
assert NOT( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***PASSED TEST: c03s04b01x00p23n01i00682"
severity NOTE;
assert ( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***FAILED TEST: c03s04b01x00p23n01i00682 - Procedure READ retrieves the next value from a file."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00682arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc682.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00682ent IS
END c03s04b01x00p23n01i00682ent;
ARCHITECTURE c03s04b01x00p23n01i00682arch OF c03s04b01x00p23n01i00682ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
variable i3, i2, i1: INTEGER;
file S1: FT open read_mode is "iofile.47";
BEGIN
wait for 10 ns;
READ(S1,i3);
READ(S1,i2);
READ(S1,i1);
wait for 10 ns;
assert NOT( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***PASSED TEST: c03s04b01x00p23n01i00682"
severity NOTE;
assert ( (i3 = 3) and (i2 = 2) and (i1 = 1) )
report "***FAILED TEST: c03s04b01x00p23n01i00682 - Procedure READ retrieves the next value from a file."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00682arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Feb 15 09:42:21 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE -nodelta ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2006/03/14 08:13:24 wig Exp $
-- $Date: 2006/03/14 08:13:24 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/03/14 08:13:24 wig
-- Adding testcase macro/splice: started development for macros iterating over signal bits
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.76 2006/01/19 08:49:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
for inst_splice : inst_splice_e_s
use configuration work.inst_splice_rtl_conf;
end for;
for inst_splice_1_0 : inst_splice_1_0_e_s
use configuration work.inst_splice_1_0_rtl_conf;
end for;
for inst_splice_1_1 : inst_splice_1_1_e_s
use configuration work.inst_splice_1_1_rtl_conf;
end for;
for inst_splice_1_2 : inst_splice_1_2_e_s
use configuration work.inst_splice_1_2_rtl_conf;
end for;
for inst_splice_1_3 : inst_splice_1_3_e_s
use configuration work.inst_splice_1_3_rtl_conf;
end for;
for inst_splice_2_0 : inst_splice_2_0_e_s
use configuration work.inst_splice_2_0_rtl_conf;
end for;
for inst_splice_2_1 : inst_splice_2_1_e_s
use configuration work.inst_splice_2_1_rtl_conf;
end for;
for inst_splice_2_2 : inst_splice_2_2_e_s
use configuration work.inst_splice_2_2_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phi is
port(x_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end phi;
architecture Behavioral of phi is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
begin
op_1_s <= std_logic_vector(rotate_left(unsigned(x_in), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(x_in), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(x_in), 8));
x_out <= (op_1_s and op_8_s) xor op_2_s;
end Behavioral; |
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phi is
port(x_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end phi;
architecture Behavioral of phi is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
begin
op_1_s <= std_logic_vector(rotate_left(unsigned(x_in), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(x_in), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(x_in), 8));
x_out <= (op_1_s and op_8_s) xor op_2_s;
end Behavioral; |
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phi is
port(x_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end phi;
architecture Behavioral of phi is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
begin
op_1_s <= std_logic_vector(rotate_left(unsigned(x_in), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(x_in), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(x_in), 8));
x_out <= (op_1_s and op_8_s) xor op_2_s;
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1661.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01661ent IS
END c09s01b00x00p02n01i01661ent;
ARCHITECTURE c09s01b00x00p02n01i01661arch OF c09s01b00x00p02n01i01661ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end block -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01661 - Semicolon expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01661arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1661.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01661ent IS
END c09s01b00x00p02n01i01661ent;
ARCHITECTURE c09s01b00x00p02n01i01661arch OF c09s01b00x00p02n01i01661ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end block -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01661 - Semicolon expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01661arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1661.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01661ent IS
END c09s01b00x00p02n01i01661ent;
ARCHITECTURE c09s01b00x00p02n01i01661arch OF c09s01b00x00p02n01i01661ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end block -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01661 - Semicolon expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01661arch;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The ReadIoInstructionExecutor entity
entity ReadIoInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic;
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress;
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData;
-- the operation to perform on the memory
memory_operation: out MemoryOperation;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic := '0';
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress;
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData;
-- the processor register operation signal
register_operation: out RegisterOperation;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic;
------------------------------------------
-- IO ports
------------------------------------------
-- io port: port0
port0: in IOPortData
);
end ReadIoInstructionExecutor;
architecture ReadIoInstructionExecutorImpl of ReadIoInstructionExecutor is
type state_type is (
execute,
store_result,
complete
);
signal state: state_type := execute;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when execute =>
result <= port0;
state <= store_result;
when store_result =>
register_address <= arg0_address;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
state <= complete;
when complete =>
if register_ready = '1' then
instruction_ready <= '1';
end if;
state <= complete;
end case;
else
register_enable <= '0';
register_operation <= OP_REG_GET;
instruction_ready <= '0';
state <= execute;
end if;
end if;
end process;
end ReadIoInstructionExecutorImpl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_ov7670_vga_1_0 -prefix
-- system_ov7670_vga_1_0_ system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_1_0 is
Port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_1_0;
architecture stub of system_ov7670_vga_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "pclk,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
for i in 1 to x loop
null;
end loop;
x := 4;
for i in 5 to x loop
null;
end loop;
wait;
end process;
end architecture;
|
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
for i in 1 to x loop
null;
end loop;
x := 4;
for i in 5 to x loop
null;
end loop;
wait;
end process;
end architecture;
|
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
for i in 1 to x loop
null;
end loop;
x := 4;
for i in 5 to x loop
null;
end loop;
wait;
end process;
end architecture;
|
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
for i in 1 to x loop
null;
end loop;
x := 4;
for i in 5 to x loop
null;
end loop;
wait;
end process;
end architecture;
|
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
for i in 1 to x loop
null;
end loop;
x := 4;
for i in 5 to x loop
null;
end loop;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity and6 is
port (i0, i1, i2, i3, i4, i5 : std_logic;
o : out std_logic);
end and6;
architecture behav of and6 is
component and3 is
port (a, b, c : std_logic;
o : out std_logic);
end component;
signal t1, t2 : std_logic;
begin
a1: and3
port map (i0, i1, i2, t1);
a2: and3
port map (i3, i4, i5, t2);
o <= t1 and t2;
end behav;
|
------------------------------------------------------------------------------
--! Copyright (C) 2017 , Emmanuel Amadio
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg_package.vhd
--!
--! @brief fpgaMSP430 Debug Package
--
--! @author Emmanuel Amadio, emmanuel.amadio@gmail.com
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
package fmsp_dbg_package is
component fmsp_dbg_uart is
generic (
DBG_UART_AUTO_SYNC : boolean := true; --! Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; --! Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000; --! Debug DCO_CLK frequency
DBG_HWBRK_RANGE : boolean := true; --! Enable/Disable the hardware breakpoint RANGE mode
SYNC_DBG_UART_RXD : boolean := true --! Synchronize RXD inputs
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
dbg_dout : in std_logic_vector(15 downto 0); --! Debug register data output
dbg_rd_rdy : in std_logic; --! Debug register data is ready for read
dbg_uart_rxd : in std_logic; --! Debug interface: UART RXD
mem_burst : in std_logic; --! Burst on going
mem_burst_end : in std_logic; --! End TX/RX burst
mem_burst_rd : in std_logic; --! Start TX burst
mem_burst_wr : in std_logic; --! Start RX burst
mem_bw : in std_logic; --! Burst byte width
--! OUTPUTs
dbg_addr : out std_logic_vector(5 downto 0); --! Debug register address
dbg_din : out std_logic_vector(15 downto 0); --! Debug register data input
dbg_rd : out std_logic; --! Debug register data read
dbg_uart_txd : out std_logic; --! Debug interface: UART TXD
dbg_wr : out std_logic --! Debug register data write
);
end component fmsp_dbg_uart;
component fmsp_dbg_i2c is
generic (
DBG_I2C_BROADCAST_EN : boolean := false --! Enable the I2C broadcast address
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
dbg_dout : in std_logic_vector(15 downto 0); --! Debug register data output
dbg_i2c_addr : in std_logic_vector(6 downto 0); --! Debug interface: I2C ADDRESS
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; --! Debug interface: I2C SDA IN
mem_burst : in std_logic; --! Burst on going
mem_burst_end : in std_logic; --! End TX/RX burst
mem_burst_rd : in std_logic; --! Start TX burst
mem_burst_wr : in std_logic; --! Start RX burst
mem_bw : in std_logic; --! Burst byte width
--! OUTPUTs
dbg_addr : out std_logic_vector(5 downto 0); --! Debug register address
dbg_din : out std_logic_vector(15 downto 0); --! Debug register data input
dbg_i2c_sda_out : out std_logic; --! Debug interface: I2C SDA OUT
dbg_rd : out std_logic; --! Debug register data read
dbg_wr : out std_logic --! Debug register data write
);
end component fmsp_dbg_i2c;
component fmsp_dbg is
generic (
DBG_UART : boolean := false; -- Enable UART (8N1) debug interface
DBG_I2C : boolean := true; -- Enable I2C debug interface
DBG_I2C_BROADCAST_EN : boolean := false; --! Enable the I2C broadcast address
DBG_RST_BRK_EN : boolean := false; --! CPU break on PUC reset
DBG_HWBRK_0_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_1_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_2_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_3_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_RANGE : boolean := true; --! Enable/Disable the hardware breakpoint RANGE mode
DBG_UART_AUTO_SYNC : boolean := true; --! Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; --! Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000; --! Debug DCO_CLK frequency
SYNC_DBG_UART_RXD : boolean := true --! Synchronize RXD inputs
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
cpu_en_s : in std_logic; --! Enable CPU code execution (synchronous)
cpu_id : in std_logic_vector(31 downto 0); --! CPU ID
cpu_nr_inst : in std_logic_vector(7 downto 0); --! Current fmsp instance number
cpu_nr_total : in std_logic_vector(7 downto 0); --! Total number of fmsp instances-1
dbg_en_s : in std_logic; --! Debug interface enable (synchronous)
dbg_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_i2c_addr : in std_logic_vector(6 downto 0); --! Debug interface: I2C Address
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; --! Debug interface: I2C SDA IN
dbg_mem_din : in std_logic_vector(15 downto 0); --! Debug unit Memory data input
dbg_reg_din : in std_logic_vector(15 downto 0); --! Debug unit CPU register data input
dbg_uart_rxd : in std_logic; --! Debug interface: UART RXD (asynchronous)
decode_noirq : in std_logic; --! Frontend decode instruction
eu_mab : in std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : in std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
fe_mdb_in : in std_logic_vector(15 downto 0); --! Frontend Memory data bus input
pc : in std_logic_vector(15 downto 0); --! Program counter
puc_pnd_set : in std_logic; --! PUC pending set for the serial debug interface
--! OUTPUTs
dbg_cpu_reset : out std_logic; --! Reset CPU from debug interface
dbg_freeze : out std_logic; --! Freeze peripherals
dbg_halt_cmd : out std_logic; --! Halt CPU command
dbg_i2c_sda_out : out std_logic; --! Debug interface: I2C SDA OUT
dbg_mem_addr : out std_logic_vector(15 downto 0); --! Debug address for rd/wr access
dbg_mem_dout : out std_logic_vector(15 downto 0); --! Debug unit data output
dbg_mem_en : out std_logic; --! Debug unit memory enable
dbg_mem_wr : out std_logic_vector(1 downto 0); --! Debug unit memory write
dbg_reg_wr : out std_logic; --! Debug unit CPU register write
dbg_uart_txd : out std_logic --! Debug interface: UART TXD
);
end component fmsp_dbg;
component fmsp_dbg_hwbrk is
generic (
DBG_HWBRK_EN : boolean := false -- Include hardware breakpoints unit
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
brk_reg_rd : in std_logic_vector(3 downto 0); --! Hardware break/watch-point register read select
brk_reg_wr : in std_logic_vector(3 downto 0); --! Hardware break/watch-point register write select
dbg_din : in std_logic_vector(15 downto 0); --! Debug register data input
decode_noirq : in std_logic; --! Frontend decode instruction
eu_mab : in std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : in std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
pc : in std_logic_vector(15 downto 0); --! Program counter
--! OUTPUTs
brk_halt : out std_logic; --! Hardware breakpoint command
brk_pnd : out std_logic; --! Hardware break/watch-point pending
brk_dout : out std_logic_vector(15 downto 0) --! Hardware break/watch-point register data input
);
end component fmsp_dbg_hwbrk;
--! Debug interface
constant C_DBG_UART_WR : integer := 18;
constant C_DBG_UART_BW : integer := 17;
-- constant C_DBG_UART_ADDR : integer := 16:11
--! Debug interface CPU_CTL register
constant C_HALT : integer := 0;
constant C_RUN : integer := 1;
constant C_ISTEP : integer := 2;
constant C_SW_BRK_EN : integer := 3;
constant C_FRZ_BRK_EN : integer := 4;
constant C_RST_BRK_EN : integer := 5;
constant C_CPU_RST : integer := 6;
--! Debug interface CPU_STAT register
constant C_HALT_RUN : integer := 0;
constant C_PUC_PND : integer := 1;
constant C_SWBRK_PND : integer := 3;
constant C_HWBRK0_PND : integer := 4;
constant C_HWBRK1_PND : integer := 5;
--! Debug interface BRKx_CTL register
constant C_BRK_MODE_RD : integer := 0;
constant C_BRK_MODE_WR : integer := 1;
-- constant C_BRK_MODE : integer := 1:0
constant C_BRK_EN : integer := 2;
constant C_BRK_I_EN : integer := 3;
constant C_BRK_RANGE : integer := 4;
--! Basic clock module: BCSCTL1 Control Register
-- constant C_DIVAx 5:4
constant C_DMA_CPUOFF : integer := 0;
constant C_DMA_OSCOFF : integer := 1;
constant C_DMA_SCG0 : integer := 2;
constant C_DMA_SCG1 : integer := 3;
--! Basic clock module: BCSCTL2 Control Register
constant C_SELMx : integer := 7;
constant C_SELS : integer := 3;
-- constant C_DIVSx 2:1
--
--! DEBUG INTERFACE EXTRA CONFIGURATION
--======================================
--! Debug interface: CPU version
--! 1 - FPGA support only (Pre-BSD licence era)
--! 2 - Add ASIC support
--! 3 - Add DMA interface support
constant C_CPU_VERSION : integer range 0 to 7 := 1;
--! Debug interface: Software breakpoint opcode
constant C_DBG_SWBRK_OP : std_logic_vector(15 downto 0) := x"4343";
--! Debug UART interface auto data synchronization
--! If the following define is commented out, then
--! the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
--! defined.
-- constant C_DBG_UART_AUTO_SYNC
--! Debug UART interface data rate
--! In order to properly setup the UART debug interface, you
--! need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
--! the chosen BAUD rate from the UART interface.
--
-- constant C_DBG_UART_BAUD 9600
-- constant C_DBG_UART_BAUD 19200
-- constant C_DBG_UART_BAUD 38400
-- constant C_DBG_UART_BAUD 57600
-- constant C_DBG_UART_BAUD 115200
-- constant C_DBG_UART_BAUD 230400
-- constant C_DBG_UART_BAUD 460800
-- constant C_DBG_UART_BAUD 576000
-- constant C_DBG_UART_BAUD 921600
-- constant C_DBG_UART_BAUD 2000000
-- constant C_DBG_DCO_FREQ 20000000
-- constant C_DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
--! Debug interface selection
--! constant C_DBG_UART -> Enable UART (8N1) debug interface
--! constant C_DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
--
-- constant C_DBG_UART
-- constant C_DBG_JTAG
end fmsp_dbg_package; --! fmsp_package
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_0, CTS_L_0: out std_logic;
DRTS_L_0, DCTS_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_1, CTS_L_1: out std_logic;
DRTS_L_1, DCTS_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_2, CTS_L_2: out std_logic;
DRTS_L_2, DCTS_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_3, CTS_L_3: out std_logic;
DRTS_L_3, DCTS_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal RTS_L_0, DRTS_L_0, CTS_L_0, DCTS_L_0: std_logic;
--------------
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal RTS_L_1, DRTS_L_1, CTS_L_1, DCTS_L_1: std_logic;
--------------
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal RTS_L_2, DRTS_L_2, CTS_L_2, DCTS_L_2: std_logic;
--------------
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal RTS_L_3, DRTS_L_3, CTS_L_3, DCTS_L_3: std_logic;
--------------
--fault injector signals
signal FI_Add_2_0, FI_Add_0_2: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: std_logic :='0';
signal FI_Add_3_1, FI_Add_1_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: std_logic :='0';
signal FI_Add_1_0, FI_Add_0_1: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: std_logic :='0';
signal FI_Add_3_2, FI_Add_2_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: std_logic :='0';
constant clk_period : time := 1 ns;
signal reset,clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32)
PORT MAP (reset, clk,
RX_L_0, RTS_L_0, CTS_L_0, DRTS_L_0, DCTS_L_0, TX_L_0,
RX_L_1, RTS_L_1, CTS_L_1, DRTS_L_1, DCTS_L_1, TX_L_1,
RX_L_2, RTS_L_2, CTS_L_2, DRTS_L_2, DCTS_L_2, TX_L_2,
RX_L_3, RTS_L_3, CTS_L_3, DRTS_L_3, DCTS_L_3, TX_L_3,
--fault injector signals
FI_Add_2_0, FI_Add_0_2,
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0,
FI_Add_3_1, FI_Add_1_3,
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1,
FI_Add_1_0, FI_Add_0_1,
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0,
FI_Add_3_2, FI_Add_2_3,
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2);
-- connecting the packet generators
gen_random_packet(100, 0, 7, 8, 8, 10000 ns, clk, CTS_L_0, DRTS_L_0, RX_L_0);
gen_random_packet(100, 1, 42, 8, 8, 10000 ns, clk, CTS_L_1, DRTS_L_1, RX_L_1);
gen_random_packet(100, 2, 3, 8, 8, 10000 ns, clk, CTS_L_2, DRTS_L_2, RX_L_2);
gen_random_packet(100, 3, 15, 8, 8, 10000 ns, clk, CTS_L_3, DRTS_L_3, RX_L_3);
-- connecting the packet receivers
-- Arguments are:
-- data_width, inital delay, node_id, clk, DCTS, RTS, TX
get_packet(32, 5, 0, clk, DCTS_L_0, RTS_L_0, TX_L_0);
get_packet(32, 5, 1, clk, DCTS_L_1, RTS_L_1, TX_L_1);
get_packet(32, 5, 2, clk, DCTS_L_2, RTS_L_2, TX_L_2);
get_packet(32, 5, 3, clk, DCTS_L_3, RTS_L_3, TX_L_3);
-- connecting the fault generators
gen_fault(sta0_1_0, sta1_1_0, FI_Add_1_0, 159,630740728,1463377560);
gen_fault(sta0_0_1, sta1_0_1, FI_Add_0_1, 183,299885916,604299435);
gen_fault(sta0_2_0, sta1_2_0, FI_Add_2_0, 113,1672277857,1698333909);
gen_fault(sta0_0_2, sta1_0_2, FI_Add_0_2, 135,307701509,1786630064);
gen_fault(sta0_3_1, sta1_3_1, FI_Add_3_1, 153,1552781373,879739902);
gen_fault(sta0_1_3, sta1_1_3, FI_Add_1_3, 148,1204692760,1152973055);
gen_fault(sta0_3_2, sta1_3_2, FI_Add_3_2, 197,1442556552,530752640);
gen_fault(sta0_2_3, sta1_2_3, FI_Add_2_3, 118,1013417135,168462331);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_0, CTS_L_0: out std_logic;
DRTS_L_0, DCTS_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_1, CTS_L_1: out std_logic;
DRTS_L_1, DCTS_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_2, CTS_L_2: out std_logic;
DRTS_L_2, DCTS_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_L_3, CTS_L_3: out std_logic;
DRTS_L_3, DCTS_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal RTS_L_0, DRTS_L_0, CTS_L_0, DCTS_L_0: std_logic;
--------------
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal RTS_L_1, DRTS_L_1, CTS_L_1, DCTS_L_1: std_logic;
--------------
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal RTS_L_2, DRTS_L_2, CTS_L_2, DCTS_L_2: std_logic;
--------------
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal RTS_L_3, DRTS_L_3, CTS_L_3, DCTS_L_3: std_logic;
--------------
--fault injector signals
signal FI_Add_2_0, FI_Add_0_2: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: std_logic :='0';
signal FI_Add_3_1, FI_Add_1_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: std_logic :='0';
signal FI_Add_1_0, FI_Add_0_1: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: std_logic :='0';
signal FI_Add_3_2, FI_Add_2_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: std_logic :='0';
constant clk_period : time := 1 ns;
signal reset,clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32)
PORT MAP (reset, clk,
RX_L_0, RTS_L_0, CTS_L_0, DRTS_L_0, DCTS_L_0, TX_L_0,
RX_L_1, RTS_L_1, CTS_L_1, DRTS_L_1, DCTS_L_1, TX_L_1,
RX_L_2, RTS_L_2, CTS_L_2, DRTS_L_2, DCTS_L_2, TX_L_2,
RX_L_3, RTS_L_3, CTS_L_3, DRTS_L_3, DCTS_L_3, TX_L_3,
--fault injector signals
FI_Add_2_0, FI_Add_0_2,
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0,
FI_Add_3_1, FI_Add_1_3,
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1,
FI_Add_1_0, FI_Add_0_1,
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0,
FI_Add_3_2, FI_Add_2_3,
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2);
-- connecting the packet generators
gen_random_packet(100, 0, 7, 8, 8, 10000 ns, clk, CTS_L_0, DRTS_L_0, RX_L_0);
gen_random_packet(100, 1, 42, 8, 8, 10000 ns, clk, CTS_L_1, DRTS_L_1, RX_L_1);
gen_random_packet(100, 2, 3, 8, 8, 10000 ns, clk, CTS_L_2, DRTS_L_2, RX_L_2);
gen_random_packet(100, 3, 15, 8, 8, 10000 ns, clk, CTS_L_3, DRTS_L_3, RX_L_3);
-- connecting the packet receivers
-- Arguments are:
-- data_width, inital delay, node_id, clk, DCTS, RTS, TX
get_packet(32, 5, 0, clk, DCTS_L_0, RTS_L_0, TX_L_0);
get_packet(32, 5, 1, clk, DCTS_L_1, RTS_L_1, TX_L_1);
get_packet(32, 5, 2, clk, DCTS_L_2, RTS_L_2, TX_L_2);
get_packet(32, 5, 3, clk, DCTS_L_3, RTS_L_3, TX_L_3);
-- connecting the fault generators
gen_fault(sta0_1_0, sta1_1_0, FI_Add_1_0, 159,630740728,1463377560);
gen_fault(sta0_0_1, sta1_0_1, FI_Add_0_1, 183,299885916,604299435);
gen_fault(sta0_2_0, sta1_2_0, FI_Add_2_0, 113,1672277857,1698333909);
gen_fault(sta0_0_2, sta1_0_2, FI_Add_0_2, 135,307701509,1786630064);
gen_fault(sta0_3_1, sta1_3_1, FI_Add_3_1, 153,1552781373,879739902);
gen_fault(sta0_1_3, sta1_1_3, FI_Add_1_3, 148,1204692760,1152973055);
gen_fault(sta0_3_2, sta1_3_2, FI_Add_3_2, 197,1442556552,530752640);
gen_fault(sta0_2_3, sta1_2_3, FI_Add_2_3, 118,1013417135,168462331);
end;
|
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity Long2Double is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_Long2Double of Long2Double is
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(2 downto 0);
signA : std_logic;
absA : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
op_signed : std_logic;
mantAlign : std_logic_vector(63 downto 0);
lshift : integer range 0 to 63;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
'0', (others => '0'), (others => '0'), -- signA, absA, result
'0', (others => '0'), 0 -- op_signed, mantAlign, lshift
);
signal r, rin : RegistersType;
begin
-- registers:
comb : process(i_nrst, i_ena, i_signed, i_w32, i_a, r)
variable v : RegistersType;
variable mantAlign : std_logic_vector(63 downto 0);
variable lshift : integer range 0 to 63;
variable expAlign : std_logic_vector(10 downto 0);
variable mantEven : std_logic;
variable mant05 : std_logic;
variable mantOnes : std_logic;
variable rndBit : std_logic;
variable v_signA : std_logic;
variable vb_A : std_logic_vector(63 downto 0);
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena := r.ena(1 downto 0) & (i_ena and not r.busy);
if i_w32 = '0' then
v_signA := i_a(63);
vb_A := i_a;
elsif i_signed = '1' and i_a(31) = '1' then
v_signA := '1';
vb_A(63 downto 32) := (others => '1');
vb_A(31 downto 0) := i_a(31 downto 0);
else
v_signA := '0';
vb_A(31 downto 0) := i_a(31 downto 0);
vb_A(63 downto 32) := (others => '0');
end if;
if i_ena = '1' then
v.busy := '1';
if i_signed = '1' and v_signA = '1' then
v.signA := '1';
v.absA := not vb_A + 1;
else
v.signA := '0';
v.absA := vb_A;
end if;
v.op_signed := i_signed;
end if;
-- multiplexer, probably if/elsif in rtl:
mantAlign := (others => '0');
lshift := 63;
if r.absA(63) = '1' then
mantAlign := r.absA;
else
for i in 1 to 63 loop
if lshift = 63 and r.absA(63 - i) = '1' then
mantAlign := r.absA(63-i downto 0) & zero64(i-1 downto 0);
lshift := i;
end if;
end loop;
end if;
if r.ena(0) = '1' then
v.mantAlign := mantAlign;
v.lshift := lshift;
end if;
if r.absA = zero64 then
expAlign := (others => '0');
else
expAlign := conv_std_logic_vector(1086 - r.lshift, 11);
end if;
mantEven := r.mantAlign(11);
mant05 := '0';
if r.mantAlign(10 downto 0) = "11111111111" then
mant05 := '1';
end if;
rndBit := r.mantAlign(10) and not(mant05 and mantEven);
mantOnes := '0';
if r.mantAlign(63) = '1' and r.mantAlign(62 downto 11) = X"fffffffffffff" then
mantOnes := '1';
end if;
-- Result multiplexers:
res(63) := r.signA and r.op_signed;
res(62 downto 52) := expAlign + ("0000000000" & (mantOnes and rndBit));
res(51 downto 0) := r.mantAlign(62 downto 11) + rndBit;
if r.ena(1) = '1' then
v.result := res;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_valid <= r.ena(2);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
-- Title : On Board Programer (OBP, WB-debuger simplification)
-- Project : OBP
-------------------------------------------------------------------------------
-- File : obp.vhd
-- Author : Jose Jimenez Montañez, Miguel Jimenez Lopez
-- Company : University of Granada (UGR)
-- Created : 2014-06-12
-- Last update: 2014-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- OBP is a HDL module implementing a On Board Programer component that allows
-- to program the LM32 inside the WRPC via USB port. In addition, some debug
-- functions have been added (to read/write WB registers, show the SDB structure, etc).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, University of Granada (UGR)
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-12 1.0 JJimenez,klyone Created and first version
-------------------------------------------------------------------------------
-- Memory map:
-- Master interconnect:
-- 0x00000000: OBP RAM Memory (Firmware)
-- 0x00400000 Sec Crossbar
-- 0x00A00000: To-external device bridge (Main)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wrcore_pkg.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.softpll_pkg.all;
use work.obp_pkg.all;
use work.obp_wbgen2_pkg.all;
entity OBP is
generic(
g_dpram_initf : string := "obp.ram";
g_dpram_size : integer;
g_cram_size : integer;
g_bridge_sdb : t_sdb_bridge
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
enable_obp : in std_logic;
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
wbm_i : in t_wishbone_master_in;
wbm_o : out t_wishbone_master_out
);
end OBP;
architecture Behavioral of OBP is
component obp_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_obp_in_registers;
regs_o : out t_obp_out_registers
);
end component;
constant c_secobp_layout : t_sdb_record_array(1 downto 0) := f_secobp_layout(g_cram_size);
constant c_secobp_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secobp_layout, c_secobp_sdb_address);
constant c_mobp_layout : t_sdb_record_array(2 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram_obp(g_dpram_size), x"00000000"),
1 => f_sdb_embed_bridge(c_secobp_bridge_sdb, x"00200000"),
2 => f_sdb_embed_bridge(g_bridge_sdb, x"00400000"));
constant c_mobp_sdb_address : t_wishbone_address := x"01000000";
signal cbar2_slave_i : t_wishbone_slave_in_array (1 downto 0);
signal cbar2_slave_o : t_wishbone_slave_out_array(1 downto 0);
signal cbar2_master_i : t_wishbone_master_in_array(1 downto 0);
signal cbar2_master_o : t_wishbone_master_out_array(1 downto 0);
signal cbar_slave_i : t_wishbone_slave_in_array (1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(2 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(2 downto 0);
signal dpram_wbb_i_dummy : t_wishbone_slave_in;
signal dpram_wbb_o_dummy : t_wishbone_slave_out;
signal rst_n_obp : std_logic;
signal cnt_words : unsigned(31 downto 0);
signal recv_ok : std_logic;
signal obp_regs_in : t_obp_in_registers := c_obp_in_registers_init_value;
signal obp_regs_out : t_obp_out_registers := c_obp_out_registers_init_value;
signal lm32_irqs : std_logic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- LM32
-----------------------------------------------------------------------------
LM32_CORE : xwb_lm32
generic map(g_profile => "medium_icache_debug")
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_obp,
irq_i => lm32_irqs,
dwb_o => cbar_slave_i(0),
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1),
iwb_i => cbar_slave_o(1)
);
-----------------------------------------------------------------------------
-- Dual-port RAM
-----------------------------------------------------------------------------
DPRAM : xwb_dpram
generic map(
g_size => g_dpram_size,
g_init_file => g_dpram_initf,
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_obp,
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
slave2_i => dpram_wbb_i_dummy,
slave2_o => dpram_wbb_o_dummy
);
-----------------------------------------------------------------------------
-- Dual-port Configuration RAM
-----------------------------------------------------------------------------
CRAM : xwb_dpram
generic map(
g_size => g_cram_size,
--g_init_file => g_dpram_initf,
--g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_obp,
slave1_i => cbar2_master_o(0),
slave1_o => cbar2_master_i(0),
slave2_i => dpram_wbb_i_dummy,
slave2_o => dpram_wbb_o_dummy
);
-- Recv counter
cnt_recv_words: process (clk_sys_i)
begin
if (rising_edge(clk_sys_i)) then
if (rst_n_obp = '0') then
cnt_words <= to_unsigned(0,32);
elsif (enable_obp = '1') then
if (cbar2_master_o(0).cyc = '1' and cbar2_master_o(0).stb = '1') then
cnt_words <= cnt_words+1;
end if;
end if;
end if;
end process;
-- This bit must be read by LM32 in order to decide if the program operation must be performed
recv_ok <= '1' WHEN cnt_words = 2*obp_regs_out.n_prog_w_n_prog_w_o ELSE '0';
OBP_WB_REGS: obp_wb_slave
port map (
rst_n_i => rst_n_obp,
clk_sys_i => clk_sys_i,
wb_adr_i => cbar2_master_o(1).adr(0 downto 0),
wb_dat_i => cbar2_master_o(1).dat,
wb_dat_o => cbar2_master_i(1).dat,
wb_cyc_i => cbar2_master_o(1).cyc,
wb_sel_i => cbar2_master_o(1).sel,
wb_stb_i => cbar2_master_o(1).stb,
wb_we_i => cbar2_master_o(1).we,
wb_ack_o => cbar2_master_i(1).ack,
wb_stall_o => cbar2_master_i(1).stall,
regs_i => obp_regs_in,
regs_o => obp_regs_out
);
-----------------------------------------------------------------------------
-- WB intercon
-----------------------------------------------------------------------------
WB_CON : xwb_sdb_crossbar
generic map(
g_num_masters => 2,
g_num_slaves => 3,
g_registered => true,
g_wraparound => true,
g_layout => c_mobp_layout,
g_sdb_addr => c_mobp_sdb_address
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_obp,
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
master_i => cbar_master_i,
master_o => cbar_master_o
);
cbar_master_i(2) <= wbm_i;
wbm_o <= cbar_master_o(2);
-----------------------------------------------------------------------------
-- WB intercon (Secondary)
-----------------------------------------------------------------------------
WB_CON_SEC : xwb_sdb_crossbar
generic map(
g_num_masters => 2,
g_num_slaves => 2,
g_registered => true,
g_wraparound => true,
g_layout => c_secobp_layout,
g_sdb_addr => c_secobp_sdb_address
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_obp,
slave_i => cbar2_slave_i,
slave_o => cbar2_slave_o,
master_i => cbar2_master_i,
master_o => cbar2_master_o
);
cbar2_slave_i(0) <= cbar_master_o(1);
cbar2_slave_o(0) <= cbar_master_i(1);
wbs_o <= cbar2_slave_o(1);
cbar2_slave_i(1) <= wbs_i;
lm32_irqs(31 downto 1) <= (others => '0');
lm32_irqs(0) <= obp_regs_out.cflags_stp_o;
rst_n_obp <= (enable_obp and rst_n_i);
end Behavioral;
|
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|
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xtGNz+MJbR3qwqPvk8+dVkkT1kJbd3tReNDTr/nDGPDXlDwCpbYgMqIPYB4rQRNZ0eX/HM+p+3fm
mvDqF/4WanFw75RPj3lvcE82MZ18RvLq9JWC9CD4WQQUWfdB3L+ck7DH/KkcrsRSpqmzK/Ake7ss
vW+jDvHoNYFWzney2QbBOATrWgqG0qlZPDbiyfDUUHbYrukcLPSviDZcs8mVrPROom4GBchiusYG
Ra6/PT4fzj7Vu5d3W7SEXqgf6NzzfoGb89JGznwCzEvklko+Y4wTM/Hvxuf9MniM4hwyG+b8bs5l
cET/mkY62l1WrXCf2eSfZ28K+1rDfDC0aIx/RTVEYnq7tV263sdcNzWEVl8eTGAw1nXk7of+28Dy
jqy2A5m1kIAZELgIzr43+3bcg/lgSP4bX+9VKOZY5UvOlhaeHODwv9rJtWcKC7xkpXRSmjvcxyId
rq4XW5lNCcTfnt8MvdA6272VbV7Z7HSdGhy5wtiu5xG9fasLTShQD6i5z8TB+YIpK21i3Jwpqt6K
n1hQkZ/aJCIuB5VQpqjrJkPEZErkpH00jbR4dr/YNrnFf2GHTwyYRA==
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity MeioSomador4Bits is
port(
HEX0 : out vl_logic_vector(6 downto 0);
HEX1 : out vl_logic_vector(6 downto 0);
LEDR : out vl_logic_vector(4 downto 0);
SW : in vl_logic_vector(8 downto 1)
);
end MeioSomador4Bits;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:20 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_sim_netlist.vhdl
-- Design : system_axi_gpio_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[15]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_1_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_1_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[15]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair3";
begin
\Not_Dual.gpio_Data_Out_reg[15]\ <= \^not_dual.gpio_data_out_reg[15]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[15]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(15),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(15),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(5),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[15]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(14),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(14),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(13),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(13),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(12),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(12),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(11),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(10),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(9),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(8),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(7),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(6),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[15]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(31),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(15),
O => D(15)
);
\Not_Dual.gpio_Data_Out[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(21),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(5),
O => D(5)
);
\Not_Dual.gpio_Data_Out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(20),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(19),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(18),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(17),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(16),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(30),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(14),
O => D(14)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(29),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(13),
O => D(13)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(28),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(12),
O => D(12)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(27),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(11),
O => D(11)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(26),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(10),
O => D(10)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(25),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(9),
O => D(9)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(24),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(8),
O => D(8)
);
\Not_Dual.gpio_Data_Out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(23),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(7),
O => D(7)
);
\Not_Dual.gpio_Data_Out[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(22),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(6),
O => D(6)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[15]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_1_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_1_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_12 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_13 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_14 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_15 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_12 : STD_LOGIC;
signal s_level_out_bus_d2_13 : STD_LOGIC;
signal s_level_out_bus_d2_14 : STD_LOGIC;
signal s_level_out_bus_d2_15 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_12 : STD_LOGIC;
signal s_level_out_bus_d3_13 : STD_LOGIC;
signal s_level_out_bus_d3_14 : STD_LOGIC;
signal s_level_out_bus_d3_15 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(15 downto 0) <= \^scndry_vect_out\(15 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_12,
Q => s_level_out_bus_d2_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_13,
Q => s_level_out_bus_d2_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_14,
Q => s_level_out_bus_d2_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_15,
Q => s_level_out_bus_d2_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_12,
Q => s_level_out_bus_d3_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_13,
Q => s_level_out_bus_d3_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_14,
Q => s_level_out_bus_d3_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_15,
Q => s_level_out_bus_d3_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => \^scndry_vect_out\(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => \^scndry_vect_out\(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_12,
Q => \^scndry_vect_out\(12),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_13,
Q => \^scndry_vect_out\(13),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_14,
Q => \^scndry_vect_out\(14),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_15,
Q => \^scndry_vect_out\(15),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => \^scndry_vect_out\(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => \^scndry_vect_out\(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => \^scndry_vect_out\(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => \^scndry_vect_out\(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => \^scndry_vect_out\(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(12),
Q => s_level_out_bus_d1_cdc_to_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(13),
Q => s_level_out_bus_d1_cdc_to_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(14),
Q => s_level_out_bus_d1_cdc_to_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(15),
Q => s_level_out_bus_d1_cdc_to_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(15),
I1 => \^scndry_vect_out\(15),
O => D(15)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => \^scndry_vect_out\(5),
O => D(5)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(14),
I1 => \^scndry_vect_out\(14),
O => D(14)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(13),
I1 => \^scndry_vect_out\(13),
O => D(13)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(12),
I1 => \^scndry_vect_out\(12),
O => D(12)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(11),
I1 => \^scndry_vect_out\(11),
O => D(11)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(10),
I1 => \^scndry_vect_out\(10),
O => D(10)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(9),
I1 => \^scndry_vect_out\(9),
O => D(9)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => \^scndry_vect_out\(8),
O => D(8)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => \^scndry_vect_out\(7),
O => D(7)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => \^scndry_vect_out\(6),
O => D(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_interrupt_control : entity is "interrupt_control";
end system_axi_gpio_1_0_interrupt_control;
architecture STRUCTURE of system_axi_gpio_1_0_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[15]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[14]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[13]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[12]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[11]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[10]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[9]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[8]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[7]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[6]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[5]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 15 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_1_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_1_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 15 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 15 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(15 downto 0) <= \^q\(15 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_12_in,
I1 => p_11_in,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\,
I3 => p_13_in,
I4 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\,
I5 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\,
O => or_ints
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I2 => p_2_in,
I3 => p_1_in,
I4 => p_3_in,
I5 => p_4_in,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_6_in,
I1 => p_5_in,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
I4 => p_9_in,
I5 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(10),
Q => p_9_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(11),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(12),
Q => p_11_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(13),
Q => p_12_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(14),
Q => p_13_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(15),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => p_3_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(5),
Q => p_4_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(6),
Q => p_5_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(7),
Q => p_6_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(8),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(9),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.system_axi_gpio_1_0_cdc_sync
port map (
D(15) => gpio_data_in_xor(0),
D(14) => gpio_data_in_xor(1),
D(13) => gpio_data_in_xor(2),
D(12) => gpio_data_in_xor(3),
D(11) => gpio_data_in_xor(4),
D(10) => gpio_data_in_xor(5),
D(9) => gpio_data_in_xor(6),
D(8) => gpio_data_in_xor(7),
D(7) => gpio_data_in_xor(8),
D(6) => gpio_data_in_xor(9),
D(5) => gpio_data_in_xor(10),
D(4) => gpio_data_in_xor(11),
D(3) => gpio_data_in_xor(12),
D(2) => gpio_data_in_xor(13),
D(1) => gpio_data_in_xor(14),
D(0) => gpio_data_in_xor(15),
Q(15 downto 0) => \^q\(15 downto 0),
gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(15) => gpio_io_i_d2(0),
scndry_vect_out(14) => gpio_io_i_d2(1),
scndry_vect_out(13) => gpio_io_i_d2(2),
scndry_vect_out(12) => gpio_io_i_d2(3),
scndry_vect_out(11) => gpio_io_i_d2(4),
scndry_vect_out(10) => gpio_io_i_d2(5),
scndry_vect_out(9) => gpio_io_i_d2(6),
scndry_vect_out(8) => gpio_io_i_d2(7),
scndry_vect_out(7) => gpio_io_i_d2(8),
scndry_vect_out(6) => gpio_io_i_d2(9),
scndry_vect_out(5) => gpio_io_i_d2(10),
scndry_vect_out(4) => gpio_io_i_d2(11),
scndry_vect_out(3) => gpio_io_i_d2(12),
scndry_vect_out(2) => gpio_io_i_d2(13),
scndry_vect_out(1) => gpio_io_i_d2(14),
scndry_vect_out(0) => gpio_io_i_d2(15)
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(15),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[10]_0\,
Q => ip2bus_data(5),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[11]_0\,
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[12]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[13]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[14]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[15]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(14),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(13),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(12),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(11),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[5]_0\,
Q => ip2bus_data(10),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[6]_0\,
Q => ip2bus_data(9),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[7]_0\,
Q => ip2bus_data(8),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[8]_0\,
Q => ip2bus_data(7),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[9]_0\,
Q => ip2bus_data(6),
R => Read_Reg_Rst
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(15),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(10),
Q => \^q\(5),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(11),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(12),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(13),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(14),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(15),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(14),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(13),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(12),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(11),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(5),
Q => \^q\(10),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(6),
Q => \^q\(9),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(7),
Q => \^q\(8),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(8),
Q => \^q\(7),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(9),
Q => \^q\(6),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(15),
Q => gpio_io_o(15),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => gpio_io_o(5),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(14),
Q => gpio_io_o(14),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(13),
Q => gpio_io_o(13),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(12),
Q => gpio_io_o(12),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(11),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(10),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(9),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(8),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => gpio_io_o(7),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => gpio_io_o(6),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(15),
Q => gpio_io_t(15),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(5),
Q => gpio_io_t(5),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(14),
Q => gpio_io_t(14),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(13),
Q => gpio_io_t(13),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(12),
Q => gpio_io_t(12),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(11),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(10),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(9),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(8),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(7),
Q => gpio_io_t(7),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(6),
Q => gpio_io_t(6),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[15]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 16 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_1_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_1_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_1_0_address_decoder
port map (
D(15 downto 0) => D(15 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\,
\Not_Dual.gpio_Data_In_reg[0]\(15 downto 0) => Q(15 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[15]\ => \Not_Dual.gpio_Data_Out_reg[15]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(10),
Q => s_axi_rdata(10),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(11),
Q => s_axi_rdata(11),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(12),
Q => s_axi_rdata(12),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(13),
Q => s_axi_rdata(13),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(14),
Q => s_axi_rdata(14),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(15),
Q => s_axi_rdata(15),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(16),
Q => s_axi_rdata(16),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(6),
Q => s_axi_rdata(6),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(7),
Q => s_axi_rdata(7),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(8),
Q => s_axi_rdata(8),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(9),
Q => s_axi_rdata(9),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 16 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_1_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_1_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_1_0_slave_attachment
port map (
D(15 downto 0) => D(15 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[15]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(15 downto 0) => Q(15 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(16 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(16 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(16 downto 0) => s_axi_rdata(16 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_1_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 16;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_1_0_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_1_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_1_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_1_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_1_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_1_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_1_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_51 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_53 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_54 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 15 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 16 to 16 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 15 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 16 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(15 downto 0) <= \^gpio_io_t\(15 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15 downto 0) <= \^s_axi_rdata\(15 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_1_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(15) => DBus_Reg(0),
D(14) => DBus_Reg(1),
D(13) => DBus_Reg(2),
D(12) => DBus_Reg(3),
D(11) => DBus_Reg(4),
D(10) => DBus_Reg(5),
D(9) => DBus_Reg(6),
D(8) => DBus_Reg(7),
D(7) => DBus_Reg(8),
D(6) => DBus_Reg(9),
D(5) => DBus_Reg(10),
D(4) => DBus_Reg(11),
D(3) => DBus_Reg(12),
D(2) => DBus_Reg(13),
D(1) => DBus_Reg(14),
D(0) => DBus_Reg(15),
E(0) => AXI_LITE_IPIF_I_n_40,
GPIO_DBus_i(0) => GPIO_DBus_i(16),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_49,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_51,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_27,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_26,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_25,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_24,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => AXI_LITE_IPIF_I_n_38,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_30,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_41,
Q(15) => gpio_Data_In(0),
Q(14) => gpio_Data_In(1),
Q(13) => gpio_Data_In(2),
Q(12) => gpio_Data_In(3),
Q(11) => gpio_Data_In(4),
Q(10) => gpio_Data_In(5),
Q(9) => gpio_Data_In(6),
Q(8) => gpio_Data_In(7),
Q(7) => gpio_Data_In(8),
Q(6) => gpio_Data_In(9),
Q(5) => gpio_Data_In(10),
Q(4) => gpio_Data_In(11),
Q(3) => gpio_Data_In(12),
Q(2) => gpio_Data_In(13),
Q(1) => gpio_Data_In(14),
Q(0) => gpio_Data_In(15),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(15 downto 0) => \^gpio_io_t\(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(16) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(15) => ip2bus_data_i_D1(16),
\ip2bus_data_i_D1_reg[0]_0\(14) => ip2bus_data_i_D1(17),
\ip2bus_data_i_D1_reg[0]_0\(13) => ip2bus_data_i_D1(18),
\ip2bus_data_i_D1_reg[0]_0\(12) => ip2bus_data_i_D1(19),
\ip2bus_data_i_D1_reg[0]_0\(11) => ip2bus_data_i_D1(20),
\ip2bus_data_i_D1_reg[0]_0\(10) => ip2bus_data_i_D1(21),
\ip2bus_data_i_D1_reg[0]_0\(9) => ip2bus_data_i_D1(22),
\ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(23),
\ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24),
\ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_53,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_54,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(16) => \^s_axi_rdata\(31),
s_axi_rdata(15 downto 0) => \^s_axi_rdata\(15 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.system_axi_gpio_1_0_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_54,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_53,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_49,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_51,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.system_axi_gpio_1_0_GPIO_Core
port map (
D(15) => DBus_Reg(0),
D(14) => DBus_Reg(1),
D(13) => DBus_Reg(2),
D(12) => DBus_Reg(3),
D(11) => DBus_Reg(4),
D(10) => DBus_Reg(5),
D(9) => DBus_Reg(6),
D(8) => DBus_Reg(7),
D(7) => DBus_Reg(8),
D(6) => DBus_Reg(9),
D(5) => DBus_Reg(10),
D(4) => DBus_Reg(11),
D(3) => DBus_Reg(12),
D(2) => DBus_Reg(13),
D(1) => DBus_Reg(14),
D(0) => DBus_Reg(15),
E(0) => AXI_LITE_IPIF_I_n_41,
GPIO_DBus_i(0) => GPIO_DBus_i(16),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[10]_0\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.gpio_OE_reg[11]_0\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.gpio_OE_reg[12]_0\ => AXI_LITE_IPIF_I_n_27,
\Not_Dual.gpio_OE_reg[13]_0\ => AXI_LITE_IPIF_I_n_26,
\Not_Dual.gpio_OE_reg[14]_0\ => AXI_LITE_IPIF_I_n_25,
\Not_Dual.gpio_OE_reg[15]_0\ => AXI_LITE_IPIF_I_n_24,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_38,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.gpio_OE_reg[5]_0\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.gpio_OE_reg[6]_0\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.gpio_OE_reg[7]_0\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.gpio_OE_reg[8]_0\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.gpio_OE_reg[9]_0\ => AXI_LITE_IPIF_I_n_30,
Q(15) => gpio_Data_In(0),
Q(14) => gpio_Data_In(1),
Q(13) => gpio_Data_In(2),
Q(12) => gpio_Data_In(3),
Q(11) => gpio_Data_In(4),
Q(10) => gpio_Data_In(5),
Q(9) => gpio_Data_In(6),
Q(8) => gpio_Data_In(7),
Q(7) => gpio_Data_In(8),
Q(6) => gpio_Data_In(9),
Q(5) => gpio_Data_In(10),
Q(4) => gpio_Data_In(11),
Q(3) => gpio_Data_In(12),
Q(2) => gpio_Data_In(13),
Q(1) => gpio_Data_In(14),
Q(0) => gpio_Data_In(15),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_40,
gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0),
gpio_io_o(15 downto 0) => gpio_io_o(15 downto 0),
gpio_io_t(15 downto 0) => \^gpio_io_t\(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(15) => ip2bus_data(16),
ip2bus_data(14) => ip2bus_data(17),
ip2bus_data(13) => ip2bus_data(18),
ip2bus_data(12) => ip2bus_data(19),
ip2bus_data(11) => ip2bus_data(20),
ip2bus_data(10) => ip2bus_data(21),
ip2bus_data(9) => ip2bus_data(22),
ip2bus_data(8) => ip2bus_data(23),
ip2bus_data(7) => ip2bus_data(24),
ip2bus_data(6) => ip2bus_data(25),
ip2bus_data(5) => ip2bus_data(26),
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(16),
Q => ip2bus_data_i_D1(16),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(17),
Q => ip2bus_data_i_D1(17),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(18),
Q => ip2bus_data_i_D1(18),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(19),
Q => ip2bus_data_i_D1(19),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(20),
Q => ip2bus_data_i_D1(20),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(21),
Q => ip2bus_data_i_D1(21),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(22),
Q => ip2bus_data_i_D1(22),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(23),
Q => ip2bus_data_i_D1(23),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_1_0 : entity is "system_axi_gpio_1_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_1_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_1_0;
architecture STRUCTURE of system_axi_gpio_1_0 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 16;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_1_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0),
gpio_io_o(15 downto 0) => gpio_io_o(15 downto 0),
gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debounce is
generic(non_sampling_clk_cycles_num : integer := 15000000); -- number of clock cycles that the button value is not sampled
-- for simulation use a smaller number e.g. 32
port(
clk : in std_logic;
reset : in std_logic;
button_in : in std_logic; -- bouncing button signal (input)
button_out : out std_logic -- debounced button signal (output)
);
end debounce;
architecture Behavioral of debounce is
-- counter value
signal cnt : std_logic_vector(31 downto 0);
-- number of clock cycles that switch value is not sampled
constant non_sampling_clk_cycles : std_logic_vector(31 downto 0) := conv_std_logic_vector(integer(non_sampling_clk_cycles_num), 32);
type button_state_type is (NO_SAMPLING, SAMPLING, WAIT_FOR_ZERO);
signal button_state : button_state_type;
begin
debounce_fsm_process:
process(clk, reset, button_in, cnt)
begin
if reset = '1' then
button_state <= SAMPLING;
button_out <= '0';
cnt <= non_sampling_clk_cycles;
elsif clk ' event and clk = '1' then
case button_state is
when SAMPLING =>
cnt <= non_sampling_clk_cycles;
if button_in = '1' then
button_state <= NO_SAMPLING;
button_out <= '1';
else
button_state <= SAMPLING;
button_out <= '0';
end if;
when NO_SAMPLING =>
cnt <= cnt - '1';
if cnt > "00000000000000000000000000000000" then
button_state <= NO_SAMPLING;
elsif button_in = '1' then
button_state <= WAIT_FOR_ZERO; -- if NON sampling interval has elapsed and input button is pressed go to WAIT_FOR_ZERO state to wait for button to be released
else
button_state <= SAMPLING; -- if NON sampling interval has elapsed and input button is released, go to SAMPLING state
end if;
button_out <= '1';
when others => -- WAIT_FOR_ZERO
cnt <= (others=>'0');
if button_in = '1' then
button_state <= WAIT_FOR_ZERO;
button_out <= '1';
else
button_state <= SAMPLING;
button_out <= '0';
end if;
end case;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
package bpm_cores_pkg is
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
subtype t_swap_mode is std_logic_vector(1 downto 0);
constant c_swmode_rffe_swap : t_swap_mode := "00";
constant c_swmode_static_direct : t_swap_mode := "01";
constant c_swmode_static_inverted : t_swap_mode := "10";
constant c_swmode_swap_deswap : t_swap_mode := "11";
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component downconv is
generic (
g_input_width : natural := 16;
g_mixed_width : natural := 24;
g_output_width : natural := 32;
g_phase_width : natural := 8;
g_sin_file : string := "./dds_sin.nif";
g_cos_file : string := "./dds_cos.nif";
g_number_of_points : natural := 6;
g_diff_delay : natural := 2;
g_stages : natural := 3;
g_decimation_rate : natural := 1000);
port (
signal_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
phase_i : in std_logic_vector(g_phase_width-1 downto 0);
I_o : out std_logic_vector(g_output_width-1 downto 0);
Q_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic);
end component downconv;
component hpf_adcinput
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0)
);
end component hpf_adcinput;
component input_gen is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_ksum : integer := 1);
port (
x_i : in std_logic_vector(g_input_width-1 downto 0);
y_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0));
end component input_gen;
component fixed_dds is
generic (
g_number_of_points : natural := 203;
g_output_width : natural := 16;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram");
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic);
end component fixed_dds;
component lut_sweep is
generic (
g_number_of_points : natural := 203;
g_bus_size : natural := 16);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0);
valid_o : out std_logic);
end component lut_sweep;
component dds_sin_lut
port (
clka : in std_logic;
addra : in std_logic_vector;
douta : out std_logic_vector);
end component dds_sin_lut;
component dds_cos_lut
port (
clka : in std_logic;
addra : in std_logic_vector;
douta : out std_logic_vector);
end component dds_cos_lut;
component sw_windowing_n_251_tukey_0_2
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(23 downto 0)
);
end component sw_windowing_n_251_tukey_0_2;
component mixer is
generic (
g_sin_file : string;
g_cos_file : string;
g_number_of_points : natural := 6;
g_input_width : natural := 16;
g_dds_width : natural := 16;
g_output_width : natural := 32;
g_tag_width : natural := 1;
g_mult_levels : natural := 7);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
I_out : out std_logic_vector(g_output_width-1 downto 0);
I_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0);
Q_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
valid_o : out std_logic);
end component mixer;
component input_conditioner is
generic (
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic;
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end component input_conditioner;
component counter is
generic (
g_mem_size : natural := 601;
g_bus_size : natural := 15);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
switch_en_i : in std_logic;
switch_o : out std_logic;
index_o : out std_logic_vector(g_bus_size-1 downto 0));
end component counter;
component position_calc is
generic (
g_with_downconv : boolean := true;
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
g_tbt_tag_desync_cnt_width : natural := 14;
g_tbt_cic_mask_samples_width : natural := 16;
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35;
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980;
g_fofb_decim_width : natural := 32;
g_fofb_decim_desync_cnt_width : natural := 14;
g_fofb_cic_mask_samples_width : natural := 16;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100;
g_monit1_cic_ratio : positive := 8;
g_monit1_tag_desync_cnt_width : natural := 14;
g_monit1_cic_mask_samples_width : natural := 16;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100;
g_monit2_cic_ratio : positive := 8;
g_monit2_tag_desync_cnt_width : natural := 14;
g_monit2_cic_mask_samples_width : natural := 16;
g_monit_decim_width : natural := 32;
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
g_k_width : natural := 25;
g_offset_width : natural := 32;
g_IQ_width : natural := 32);
port (
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_tag_i : in std_logic_vector(0 downto 0);
adc_tag_en_i : in std_logic := '0';
adc_valid_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
mix_ce_o : out std_logic;
tbt_tag_i : in std_logic_vector(0 downto 0);
tbt_tag_en_i : in std_logic := '0';
tbt_tag_desync_cnt_rst_i : in std_logic := '0';
tbt_tag_desync_cnt_o : out std_logic_vector(g_tbt_tag_desync_cnt_width-1 downto 0);
tbt_decim_mask_en_i : in std_logic := '0';
tbt_decim_mask_num_samples_beg_i : in unsigned(g_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
tbt_decim_mask_num_samples_end_i : in unsigned(g_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_decim_ce_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_amp_ce_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
tbt_pha_ce_o : out std_logic;
fofb_decim_desync_cnt_rst_i : in std_logic := '0';
fofb_decim_desync_cnt_o : out std_logic_vector(g_fofb_decim_desync_cnt_width-1 downto 0);
fofb_decim_mask_en_i : in std_logic := '0';
fofb_decim_mask_num_samples_i : in unsigned(g_fofb_cic_mask_samples_width-1 downto 0) := (others => '0');
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_decim_ce_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_amp_ce_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
fofb_pha_ce_o : out std_logic;
monit1_tag_i : in std_logic_vector(0 downto 0);
monit1_tag_en_i : in std_logic := '0';
monit1_tag_desync_cnt_rst_i : in std_logic := '0';
monit1_tag_desync_cnt_o : out std_logic_vector(g_monit1_tag_desync_cnt_width-1 downto 0);
monit1_decim_mask_en_i : in std_logic := '0';
monit1_decim_mask_num_samples_beg_i : in unsigned(g_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
monit1_decim_mask_num_samples_end_i : in unsigned(g_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit1_amp_ce_o : out std_logic;
monit_tag_i : in std_logic_vector(0 downto 0);
monit_tag_en_i : in std_logic := '0';
monit_tag_desync_cnt_rst_i : in std_logic := '0';
monit_tag_desync_cnt_o : out std_logic_vector(g_monit2_tag_desync_cnt_width-1 downto 0);
monit_decim_mask_en_i : in std_logic := '0';
monit_decim_mask_num_samples_beg_i : in unsigned(g_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
monit_decim_mask_num_samples_end_i : in unsigned(g_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
monit_amp_ce_o : out std_logic;
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
tbt_pos_ce_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
fofb_pos_ce_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit1_pos_ce_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
monit_pos_ce_o : out std_logic);
end component position_calc;
component swap_freqgen
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
sync_trig_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode;
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
swap_div_f_cnt_en_i : in std_logic := '1';
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end component;
component deswap_channels
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end component;
component swmode_sel
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
-- Swap master clock
clk_swap_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode
);
end component;
component bpm_swap
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic;
-- Swap mode setting
swap_mode_i : in std_logic_vector(1 downto 0);
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end component;
component wb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic
);
end component wb_bpm_swap;
component xwb_bpm_swap
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic
);
end component;
component position_calc_cdc_fifo is
generic (
g_data_width : natural;
g_size : natural);
port (
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic);
end component position_calc_cdc_fifo;
component wb_position_calc_core
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
g_monit_decim_width : natural := 32;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end component;
component xwb_position_calc_core
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
g_monit_decim_width : natural := 32;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end component;
component wb_orbit_intlk
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0);
wb_sel_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end component;
component xwb_orbit_intlk
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end component;
end bpm_cores_pkg;
package body bpm_cores_pkg is
end bpm_cores_pkg;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY scandouble_ram_infer IS
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (7 DOWNTO 0);
address: IN integer RANGE 0 to 1824;
we: IN std_logic;
q: OUT std_logic_vector (7 DOWNTO 0)
);
END scandouble_ram_infer;
ARCHITECTURE rtl OF scandouble_ram_infer IS
TYPE mem IS ARRAY(0 TO 1824) OF std_logic_vector(7 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
SIGNAL ram_block : mem;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(address) <= data;
END IF;
q <= ram_block(address);
END IF;
END PROCESS;
END rtl; |
-- NEED RESULT: ARCH00065.P1_1: Next with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00065.P1_1: Next with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00065.P1_1: Next statement does not effect outer loop passed
-- NEED RESULT: ARCH00065.P1_2: Next with a label and condition only effects labeled loop passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00065
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.9 (2)
-- 8.9 (3)
-- 8.9 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00065)
-- ENT00065_Test_Bench(ARCH00065_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00065 of E00000 is
signal Dummy : Boolean := false ;
begin
P1_1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
begin
L1 :
for i in boolean loop
--
correct := true ;
L2 :
for j in 1 to 3 loop
next L2 ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00065.P1_1" ,
"Next with a label and no condition only effects " &
"labeled loop",
correct ) ;
--
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00065.P1_1" ,
"Next statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_1 ;
--
P1_2 :
process ( Dummy )
variable correct : boolean := true ;
variable counter : integer := 0 ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= c_boolean_2 loop
--
v_boolean := c_boolean_2 ;
for j in 1 to 3 loop
next L1 when j = j ;
end loop ;
--
counter := counter + 1 ;
--
end loop L1 ;
--
correct := counter = 0 ;
test_report ( "ARCH00065.P1_2" ,
"Next with a label and condition only effects " &
"labeled loop",
correct ) ;
--
end process P1_2 ;
--
--
end ARCH00065 ;
--
entity ENT00065_Test_Bench is
end ENT00065_Test_Bench ;
--
architecture ARCH00065_Test_Bench of ENT00065_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00065 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00065_Test_Bench ;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: Counter3bMOD5.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Counter3bMOD5 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END Counter3bMOD5;
ARCHITECTURE SYN OF counter3bmod5 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(2 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 5,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 3
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "5"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL q[2..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 3 0 @q 0 0 3 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: Counter3bMOD5.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Counter3bMOD5 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END Counter3bMOD5;
ARCHITECTURE SYN OF counter3bmod5 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(2 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 5,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 3
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "5"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL q[2..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 3 0 @q 0 0 3 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Counter3bMOD5_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_bram - syn
-- Description: rbus dev: rbus bram test target
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2010-12-31 352 1.0.2 simplify irb_ack logic
-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
-- 2010-12-26 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbbb0 cntl r/w/- Control register
-- 15:10 nbusy r/w/- busy cycles
-- 9:00 addr r/w/- bram address (will auto-increment)
-- bbbbbbb1 15:00 data r/w/- Data register (read/write to bram via addr)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_bram is -- rbus dev: rbus bram test target
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11110100#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end entity rbd_bram;
architecture syn of rbd_bram is
constant rbaddr_cntl : slv1 := "0"; -- cntl address offset
constant rbaddr_data : slv1 := "1"; -- data address offset
subtype cntl_rbf_nbusy is integer range 15 downto 10;
subtype cntl_rbf_addr is integer range 9 downto 0;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
addr : slv10; -- addr register
nbusy : slv6; -- nbusy setting
cntbusy : slv6; -- busy timer
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- addr
(others=>'0'), -- nbusy
(others=>'0') -- cntbusy
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM_DO : slv16 := (others=>'0');
begin
BRAM : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 10,
DWIDTH => 16)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.addr,
DI => RB_MREQ.din,
DO => BRAM_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, BRAM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable isbusy : slbit := '0';
variable ibramen : slbit := '0';
variable ibramwe : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
ibramen := '0';
ibramwe := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 1)=RB_ADDR(7 downto 1) then
n.rbsel := '1';
ibramen := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
end if;
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(0 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
n.addr := RB_MREQ.din(cntl_rbf_addr);
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if isbusy = '0' then
if RB_MREQ.we = '1' then
ibramwe := '1';
end if;
if irbena = '1' then
n.addr := slv(unsigned(r.addr) + 1);
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(0 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_nbusy) := r.nbusy;
irb_dout(cntl_rbf_addr) := r.addr;
when rbaddr_data =>
irb_dout := BRAM_DO;
when others => null;
end case;
end if;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= '0';
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
|
-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_bram - syn
-- Description: rbus dev: rbus bram test target
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2010-12-31 352 1.0.2 simplify irb_ack logic
-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
-- 2010-12-26 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbbb0 cntl r/w/- Control register
-- 15:10 nbusy r/w/- busy cycles
-- 9:00 addr r/w/- bram address (will auto-increment)
-- bbbbbbb1 15:00 data r/w/- Data register (read/write to bram via addr)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_bram is -- rbus dev: rbus bram test target
-- complete rrirp_aif interface
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11110100#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end entity rbd_bram;
architecture syn of rbd_bram is
constant rbaddr_cntl : slv1 := "0"; -- cntl address offset
constant rbaddr_data : slv1 := "1"; -- data address offset
subtype cntl_rbf_nbusy is integer range 15 downto 10;
subtype cntl_rbf_addr is integer range 9 downto 0;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
addr : slv10; -- addr register
nbusy : slv6; -- nbusy setting
cntbusy : slv6; -- busy timer
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- addr
(others=>'0'), -- nbusy
(others=>'0') -- cntbusy
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM_DO : slv16 := (others=>'0');
begin
BRAM : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 10,
DWIDTH => 16)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.addr,
DI => RB_MREQ.din,
DO => BRAM_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, BRAM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable isbusy : slbit := '0';
variable ibramen : slbit := '0';
variable ibramwe : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
ibramen := '0';
ibramwe := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 1)=RB_ADDR(7 downto 1) then
n.rbsel := '1';
ibramen := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
end if;
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(0 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
n.addr := RB_MREQ.din(cntl_rbf_addr);
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if isbusy = '0' then
if RB_MREQ.we = '1' then
ibramwe := '1';
end if;
if irbena = '1' then
n.addr := slv(unsigned(r.addr) + 1);
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(0 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_nbusy) := r.nbusy;
irb_dout(cntl_rbf_addr) := r.addr;
when rbaddr_data =>
irb_dout := BRAM_DO;
when others => null;
end case;
end if;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= '0';
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Triplicate data on write.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity mem_data_triplicator_wr_only is
generic (
-- Memory depth
depth_g : positive := 1048576;
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g / 3)))) - 1 downto 0);
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Memory interface
mem_addr_o : out std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
mem_wr_en_o : out std_ulogic;
mem_data_o : out std_ulogic_vector(width_g - 1 downto 0);
mem_busy_i : in std_ulogic;
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_wr_only;
architecture rtl of mem_data_triplicator_wr_only is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal wr_busy : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= wr_busy or mem_busy_i;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Calculate addresses
mem_data_triplicator_addr_inst : entity work.mem_data_triplicator_addr
generic map (
depth_g => depth_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => addr_i,
rd_en_i => '0',
wr_en_i => wr_en_i,
mem_addr_o => mem_addr_o,
mem_done_i => mem_done_i);
-- Triplicate data on write
mem_data_triplicator_wr_inst : entity work.mem_data_triplicator_wr
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => wr_en_i,
data_i => data_i,
busy_o => wr_busy,
done_o => done_o,
mem_wr_en_o => mem_wr_en_o,
mem_data_o => mem_data_o,
mem_done_i => mem_done_i);
end architecture rtl;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Decoder
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Decoder is
generic(N: integer:=3);
port(
I: in std_logic_vector(n-1 downto 0);
E: in std_logic:= '1';
Q: out std_logic_vector(2**n-1 downto 0):=(Others => '0')
);
end Decoder;
architecture Structure of Decoder is
signal en: std_logic_vector(1 downto 0);
signal o0: std_logic_vector(2**(n-1)-1 downto 0);
signal o1: std_logic_vector(2**(n-1)-1 downto 0);
component decoderBasic is
port(
I: in std_logic;
E: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
component Decoder is
generic(N: integer);
port(
I: in std_logic_vector(n-1 downto 0);
E: in std_logic;
Q: out std_logic_vector(2**n-1 downto 0)
);
end component Decoder;
begin
dec0: decoderBasic port map(I=>I(n-1), E=>E, Q=>en);
cond: if n = 1 generate
o0(0) <= en(0);
o1(0) <= en(1);
end generate cond;
Build: if n>1 generate
decN0:component Decoder
generic map(N=>n-1)
port map(I=>I(n-2 downto 0), E=>en(0), Q=>o0);
decN1:component Decoder
generic map(N=>n-1)
port map(I=>I(n-2 downto 0), E=>en(1), Q=>o1);
end generate Build;
Q <= o1 & o0;
end Structure; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cmvalidbits
-- File: cmvalidbits.vhd
-- Author: Magnus Hjorth - Cobham Gaisler
-- Description: Separate valid bits for data cache implemented with registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cmvalidbits is
generic (
abits : integer;
nways : integer range 1 to 4
);
port (
clk : in std_ulogic;
caddr: in std_logic_vector(abits-1 downto 0);
cenable: in std_logic_vector(0 to nways-1);
cwrite: in std_logic_vector(0 to nways-1);
cwdata: in std_logic_vector(0 to nways-1);
crdata: out std_logic_vector(0 to nways-1);
saddr: in std_logic_vector(abits-1 downto 0);
sclear: in std_logic_vector(0 to nways-1);
flush: in std_ulogic
);
end;
architecture rtl of cmvalidbits is
type validbits_array_type is array(0 to 2**abits-1) of std_logic_vector(0 to nways-1);
type validbits_regs is record
valid: validbits_array_type;
pcaddr: std_logic_vector(abits-1 downto 0);
pcwrite: std_logic_vector(0 to nways-1);
pcwdata: std_logic_vector(0 to nways-1);
psaddr: std_logic_vector(abits-1 downto 0);
end record;
signal r,nr: validbits_regs;
begin
comb: process(r,caddr,cenable,cwrite,cwdata,saddr,sclear,flush)
variable vrdata: std_logic_vector(0 to nways-1);
variable v: validbits_regs;
variable wv: std_logic_vector(0 to nways-1);
variable av: std_logic_vector(abits-1 downto 0);
variable amask: std_logic_vector(0 to 2**abits-1);
begin
v := r;
v.pcaddr := caddr;
v.pcwrite := cenable and cwrite;
v.pcwdata := cwdata;
v.psaddr := saddr;
-- Note: sclear is asserted one cycle after saddr so no pipeline reg on that
vrdata := r.valid(to_integer(unsigned(r.pcaddr)));
for i in 0 to 2**abits-1 loop
wv := r.valid(i);
av := std_logic_vector(to_unsigned(i,abits));
if r.pcaddr=av then
for j in 0 to nways-1 loop
if r.pcwrite(j)='1' then
wv(j) := r.pcwdata(j);
end if;
end loop;
end if;
if r.psaddr=av then
for j in 0 to nways-1 loop
if sclear(j)='1' then
wv(j) := '0';
end if;
end loop;
end if;
if flush='1' then
wv := (others => '0');
end if;
v.valid(i) := wv;
end loop;
nr <= v;
crdata <= vrdata;
end process;
regs: process(clk)
begin
if rising_edge(clk) then r <= nr; end if;
end process;
end;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 94464)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 94464)
`protect data_block
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`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:50:37 04/01/2017
-- Design Name:
-- Module Name: shifregister_5bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftregister_5bit is
Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);
A : out STD_LOGIC_VECTOR (4 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
C : out STD_LOGIC;
I : in STD_LOGIC_VECTOR (4 downto 0));
end shiftregister_5bit;
architecture Behavioral of shiftregister_5bit is
COMPONENT dff
PORT(
d : IN std_logic;
clk : IN std_logic;
clear : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
COMPONENT mux8to1
PORT(
Y : OUT STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 downto 0);
I : IN STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT;
COMPONENT HA
PORT(
AI : in STD_LOGIC;
BI : in STD_LOGIC;
CO : out STD_LOGIC;
SUM : out STD_LOGIC);
END COMPONENT;
----bus
signal data_Q, mux_o : std_logic_vector(4 downto 0);
signal sI0,sI1,sI2,SI3,sI4 : std_logic_vector (7 downto 0);
signal comp1, comp2, carry : std_logic_vector (4 downto 0);
----single signal
signal nclear: std_logic;
begin
--------------------------------- 1st bit
mux0 : mux8to1 PORT MAP (
Y => mux_o(0),
sel => sel,
I => sI0
);
dff0: dff PORT MAP (
d => mux_o(0),
clk => clk,
clear => nclear,
q => data_Q(0)
);
ha_0 : HA PORT MAP (
AI => '1' ,
BI => comp1(0) ,
CO => carry(0) ,
SUM => comp2(0)
);
---------------------------------- 2nd bit
mux1 : mux8to1 PORT MAP (
Y => mux_o(1),
sel => sel,
I => sI1
);
dff1: dff PORT MAP (
d => mux_o(1),
clk => clk,
clear => nclear,
q => data_Q(1)
);
ha_1 : HA PORT MAP (
AI => carry(0),
BI => comp1(1),
CO => carry(1) ,
SUM => comp2(1)
);
----------------------------------- 3rd bit
mux2 : mux8to1 PORT MAP (
Y => mux_o(2),
sel => sel,
I => sI2
);
dff2: dff PORT MAP (
d => mux_o(2),
clk => clk,
clear => nclear,
q => data_Q(2)
);
ha_2 : HA PORT MAP (
AI => carry(1),
BI => comp1(2),
CO => carry(2),
SUM => comp2(2)
);
----------------------------------- 4th bit
mux3 : mux8to1 PORT MAP (
Y => mux_o(3),
sel => sel,
I => sI3
);
dff3: dff PORT MAP (
d => mux_o(3),
clk => clk,
clear => nclear,
q => data_Q(3)
);
ha_3 : HA PORT MAP (
AI => carry(2),
BI => comp1(3),
CO => carry(3),
SUM => comp2(3)
);
----------------------------------- 5th bit
mux4 : mux8to1 PORT MAP (
Y => mux_o(4),
sel => sel,
I => sI4
);
dff4: dff PORT MAP (
d => mux_o(4),
clk => clk,
clear => nclear,
q => data_Q(4)
);
ha_4 : HA PORT MAP (
AI => carry(3),
BI => comp1(4),
CO => carry(4),
SUM => comp2(4)
);
-----------------------------------
---------- SIGNAL MAPPING ---------
sI0 <= (data_Q(0),comp2(0),comp1(0),data_Q(4),data_Q(1),'0',data_Q(1),I(0));
sI1 <= (data_Q(1),comp2(1),comp1(1),data_Q(0),data_Q(2),data_Q(0),data_Q(2),I(1));
sI2 <= (data_Q(2),comp2(2),comp1(2),data_Q(1),data_Q(3),data_Q(1),data_Q(3),I(2));
sI3 <= (data_Q(3),comp2(3),comp1(3),data_Q(2),data_Q(4),data_Q(2),data_Q(4),I(3));
sI4 <= (data_Q(4),comp2(4),comp1(4),data_Q(3),data_Q(0),data_Q(3),'0',I(4));
--- 1's complementary signal mapping----
comp1(0) <= not data_Q(0);
comp1(1) <= not data_Q(1);
comp1(2) <= not data_Q(2);
comp1(3) <= not data_Q(3);
comp1(4) <= not data_Q(4);
----------------------------------------
A <= data_Q;
nclear <= not reset;
C <= carry(4);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gray_compare is
generic (
width : positive
);
port (
-- These gray counters are interpreted as the MSB being a looped indicator
-- and the rest being the actual value. Invert the MSB of the value
-- (that is, gray(width-2)) to get the real value when the looped
-- flag is set.
-- This gray counter is updated on our clock
gray : in std_logic_vector(width - 1 downto 0);
-- This gray counter is updated on another clock
other_gray : in std_logic_vector(width - 1 downto 0);
clk : in std_logic;
-- Set high when both values are equal
eq : out std_logic := '0';
-- Tet high when only one counter has looped
looped : out std_logic := '0'
);
end gray_compare;
architecture behavioral of gray_compare is
component bus_sync is
generic (
width : positive
);
port (
bus_in : in std_logic_vector(width - 1 downto 0);
bus_out : out std_logic_vector(width - 1 downto 0);
clk : in std_logic
);
end component;
signal gray_sync : std_logic_vector(width - 1 downto 0);
-- signal test1 : std_logic_vector(width - 2 downto 0);
-- signal test2 : std_logic_vector(width - 2 downto 0);
begin
sync : bus_sync
generic map (
width => width
)
port map (
bus_in => other_gray,
bus_out => gray_sync,
clk => clk
);
process(clk)
variable looped1 : std_logic := '0';
variable looped2 : std_logic := '0';
variable value1 : std_logic_vector(width - 2 downto 0) := (others => '0');
variable value2 : std_logic_vector(width - 2 downto 0) := (others => '0');
begin
if falling_edge(clk) then
looped1 := gray(width - 1);
if looped1 = '1' then
value1 := (not gray(width - 2)) & gray(width - 3 downto 0);
else
value1 := gray(width - 2 downto 0);
end if;
looped2 := gray_sync(width - 1);
if looped2 = '1' then
value2 := (not gray_sync(width - 2)) & gray_sync(width - 3 downto 0);
else
value2 := gray_sync(width - 2 downto 0);
end if;
-- test1 <= value1;
-- test2 <= value2;
if value1 = value2 then
eq <= '1';
else
eq <= '0';
end if;
if looped1 = looped2 then
looped <= '0';
else
looped <= '1';
end if;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gray_compare is
generic (
width : positive
);
port (
-- These gray counters are interpreted as the MSB being a looped indicator
-- and the rest being the actual value. Invert the MSB of the value
-- (that is, gray(width-2)) to get the real value when the looped
-- flag is set.
-- This gray counter is updated on our clock
gray : in std_logic_vector(width - 1 downto 0);
-- This gray counter is updated on another clock
other_gray : in std_logic_vector(width - 1 downto 0);
clk : in std_logic;
-- Set high when both values are equal
eq : out std_logic := '0';
-- Tet high when only one counter has looped
looped : out std_logic := '0'
);
end gray_compare;
architecture behavioral of gray_compare is
component bus_sync is
generic (
width : positive
);
port (
bus_in : in std_logic_vector(width - 1 downto 0);
bus_out : out std_logic_vector(width - 1 downto 0);
clk : in std_logic
);
end component;
signal gray_sync : std_logic_vector(width - 1 downto 0);
-- signal test1 : std_logic_vector(width - 2 downto 0);
-- signal test2 : std_logic_vector(width - 2 downto 0);
begin
sync : bus_sync
generic map (
width => width
)
port map (
bus_in => other_gray,
bus_out => gray_sync,
clk => clk
);
process(clk)
variable looped1 : std_logic := '0';
variable looped2 : std_logic := '0';
variable value1 : std_logic_vector(width - 2 downto 0) := (others => '0');
variable value2 : std_logic_vector(width - 2 downto 0) := (others => '0');
begin
if falling_edge(clk) then
looped1 := gray(width - 1);
if looped1 = '1' then
value1 := (not gray(width - 2)) & gray(width - 3 downto 0);
else
value1 := gray(width - 2 downto 0);
end if;
looped2 := gray_sync(width - 1);
if looped2 = '1' then
value2 := (not gray_sync(width - 2)) & gray_sync(width - 3 downto 0);
else
value2 := gray_sync(width - 2 downto 0);
end if;
-- test1 <= value1;
-- test2 <= value2;
if value1 = value2 then
eq <= '1';
else
eq <= '0';
end if;
if looped1 = looped2 then
looped <= '0';
else
looped <= '1';
end if;
end if;
end process;
end behavioral;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_data_pkg.all;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_replace_pkg.all;
entity cpu_l1mem_data_cache_ctrl is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_data_ctrl_in : out cpu_mmu_data_ctrl_in_type;
cpu_mmu_data_ctrl_out : in cpu_mmu_data_ctrl_out_type;
cpu_l1mem_data_cache_ctrl_in : in cpu_l1mem_data_cache_ctrl_in_type;
cpu_l1mem_data_cache_ctrl_out : out cpu_l1mem_data_cache_ctrl_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
cpu_l1mem_data_cache_ctrl_in_vram : in cpu_l1mem_data_cache_ctrl_in_vram_type;
cpu_l1mem_data_cache_ctrl_out_vram : out cpu_l1mem_data_cache_ctrl_out_vram_type;
cpu_l1mem_data_cache_ctrl_in_mram : in cpu_l1mem_data_cache_ctrl_in_mram_type;
cpu_l1mem_data_cache_ctrl_out_mram : out cpu_l1mem_data_cache_ctrl_out_mram_type;
cpu_l1mem_data_cache_ctrl_out_tram : out cpu_l1mem_data_cache_ctrl_out_tram_type;
cpu_l1mem_data_cache_ctrl_out_dram : out cpu_l1mem_data_cache_ctrl_out_dram_type;
cpu_l1mem_data_cache_dp_in_ctrl : out cpu_l1mem_data_cache_dp_in_ctrl_type;
cpu_l1mem_data_cache_dp_out_ctrl : in cpu_l1mem_data_cache_dp_out_ctrl_type;
cpu_l1mem_data_cache_replace_ctrl_in : out cpu_l1mem_data_cache_replace_ctrl_in_type;
cpu_l1mem_data_cache_replace_ctrl_out : in cpu_l1mem_data_cache_replace_ctrl_out_type
);
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Test_Pattern_Generator_example is
end entity;
architecture rtl of tb_Test_Pattern_Generator_example is
component tb_Test_Pattern_Generator
end component;
begin
tb_Test_Pattern_Generator_instance :
component tb_Test_Pattern_Generator
port map();
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Test_Pattern_Generator_example is
end entity;
architecture rtl of tb_Test_Pattern_Generator_example is
component tb_Test_Pattern_Generator
end component;
begin
tb_Test_Pattern_Generator_instance :
component tb_Test_Pattern_Generator
port map();
end architecture rtl;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_data_steer.vhd
-- Version: v1.10.a
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_data_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
-- BLT 5-13-2002 -- Added capability for peripherals larger
-- than bus, new optimizations
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH_BUS : integer := width of host databus attached to the IPIF
-- C_DWIDTH_IP : integer := width of IP databus attached to the IPIF
-- C_SMALLEST_MASTER : integer := width of smallest master (not access size)
-- attached to the IPIF
-- C_SMALLEST_IP : integer := width of smallest IP device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Data_Steer is
generic (
C_DWIDTH_BUS : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_IP : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_MASTER : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IP : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH_BUS-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH_IP-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_BUS/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH_IP-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH_BUS-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_IP/8-1)
);
end entity IPIF_Data_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Data_Steer is
component Steer_Module_Write is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end component Steer_Module_Write;
component Steer_Module_Read is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end component Steer_Module_Read;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
WRITE_I: Steer_Module_Write
generic map (
C_DWIDTH_IN => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Wr_Data_In, --[in]
BE_In => BE_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Wr_Data_Out, --[out]
BE_Out => BE_Out --[out]
);
READ_I: Steer_Module_Read
generic map (
C_DWIDTH_IN => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT => C_SMALLEST_MASTER, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Rd_Data_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Rd_Data_Out --[out]
);
end architecture IMP;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_data_steer.vhd
-- Version: v1.10.a
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_data_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
-- BLT 5-13-2002 -- Added capability for peripherals larger
-- than bus, new optimizations
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH_BUS : integer := width of host databus attached to the IPIF
-- C_DWIDTH_IP : integer := width of IP databus attached to the IPIF
-- C_SMALLEST_MASTER : integer := width of smallest master (not access size)
-- attached to the IPIF
-- C_SMALLEST_IP : integer := width of smallest IP device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Data_Steer is
generic (
C_DWIDTH_BUS : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_IP : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_MASTER : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IP : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH_BUS-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH_IP-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_BUS/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH_IP-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH_BUS-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_IP/8-1)
);
end entity IPIF_Data_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Data_Steer is
component Steer_Module_Write is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
BE_In : in std_logic_vector(0 to C_DWIDTH_IN/8-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH_OUT/8-1)
);
end component Steer_Module_Write;
component Steer_Module_Read is
generic (
C_DWIDTH_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN : integer; -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH : integer
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end component Steer_Module_Read;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
WRITE_I: Steer_Module_Write
generic map (
C_DWIDTH_IN => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_DWIDTH_OUT => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_SMALLEST_OUT => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Wr_Data_In, --[in]
BE_In => BE_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Wr_Data_Out, --[out]
BE_Out => BE_Out --[out]
);
READ_I: Steer_Module_Read
generic map (
C_DWIDTH_IN => C_DWIDTH_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_DWIDTH_OUT => C_DWIDTH_BUS, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_OUT => C_SMALLEST_MASTER, -- 8, 16, 32, 64, 128, 256, or 512 -- HOST
C_SMALLEST_IN => C_SMALLEST_IP, -- 8, 16, 32, 64, 128, 256, or 512 -- IP
C_AWIDTH => C_AWIDTH )
port map (
Data_In => Rd_Data_In, --[in]
Addr => Addr, --[in]
Decode_size => Decode_size, --[in]
Data_Out => Rd_Data_Out --[out]
);
end architecture IMP;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clock_50 : in std_logic;
sma_clkout : out std_ulogic;
errorn : out std_logic;
fl_addr : out std_logic_vector(22 downto 0);
fl_dq : inout std_logic_vector(7 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dq : inout std_logic_vector(31 downto 0);
dram_clk : out std_logic;
dram_cke : out std_logic;
dram_cs_n : out std_logic;
dram_we_n : out std_logic; -- sdram write enable
dram_ras_n : out std_logic; -- sdram ras
dram_cas_n : out std_logic; -- sdram cas
dram_dqm : out std_logic_vector (3 downto 0); -- sdram dqm
uart_txd : out std_logic; -- DSU tx data
uart_rxd : in std_logic; -- DSU rx data
dsubre : in std_logic;
dsuact : out std_logic;
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
fl_rst_n : out std_logic;
fl_wp_n : out std_logic;
fl_ce_n : out std_logic;
-- gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpio : inout std_logic_vector(35 downto 0); -- I/O port
enet0_mdio : inout std_logic; -- ethernet PHY interface
enet0_gtx_clk : in std_logic;
enet0_rx_clk : in std_logic;
enet0_tx_clk : in std_logic;
enet0_rx_data: in std_logic_vector(3 downto 0);
enet0_rx_dv : in std_logic;
enet0_rx_er : in std_logic;
enet0_rx_col : in std_logic;
enet0_rx_crs : in std_logic;
enet0_int_n : in std_logic;
enet0_rst_n : out std_logic;
enet0_tx_data: out std_logic_vector(3 downto 0);
enet0_tx_en : out std_logic;
enet0_tx_er : out std_logic;
enet0_mdc : out std_logic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1);
sw : in std_logic_vector(0 to 2) := "000"
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal dsubren : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ, clk2xen => 1)
port map (clkin => clock_50, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => sma_clkout, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dui.rxd <= uart_rxd when sw(0) = '0' else '1';
-- dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= '0'; memi.bwidth <= "00";
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL, iomask => 0,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (fl_addr, memo.address(22 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (fl_oe_n, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (fl_we_n, memo.writen);
fl_rst_pad : outpad generic map (tech => padtech)
port map (fl_rst_n, rstn);
fl_wp_pad : outpad generic map (tech => padtech)
port map (fl_wp_n, vcc(0));
data_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (fl_dq, memo.data(31 downto 24), memo.vbdrive(31 downto 24), memi.data(31 downto 24));
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 13)
port map (dram_addr, memo.sa(12 downto 0));
ba_pad : outpadv generic map (width => 2)
port map (dram_ba, memo.sa(14 downto 13));
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (dram_dq(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (dram_dqm, sdo.dqm(3 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, vcc(0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when sw(0) = '0' else uart_rxd; u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when sw(0) = '1' else duo.txd;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : iopad generic map (tech => padtech)
port map (gpio(35), spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (gpio(34), spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (gpio(33), spio.sck, spio.sckoen, spii.sck);
slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(32), slvsel(0), gnd(0), open);
end generate spic;
spibridge : if CFG_SPI2AHB /= 0 generate -- SPI to AHB bridge
withapb : if CFG_SPI2AHB_APB /= 0 generate
spi2ahb0 : spi2ahb_apb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
resen => CFG_SPI2AHB_RESEN, pindex => 11, paddr => 11, pmask => 16#fff#,
pirq => 11, filter => CFG_SPI2AHB_FILTER, cpol => CFG_SPI2AHB_CPOL,
cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi, apbo(11), spislvi, spislvo);
end generate;
woapb : if CFG_SPI2AHB_APB = 0 generate
spi2ahb0 : spi2ahb
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
ahbaddrh => CFG_SPI2AHB_ADDRH, ahbaddrl => CFG_SPI2AHB_ADDRL,
ahbmaskh => CFG_SPI2AHB_MASKH, ahbmaskl => CFG_SPI2AHB_MASKL,
filter => CFG_SPI2AHB_FILTER,
cpol => CFG_SPI2AHB_CPOL, cpha => CFG_SPI2AHB_CPHA)
port map (rstn, clkm, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
spislvi, spislvo);
end generate;
spislv_miso_pad : iopad generic map (tech => padtech)
port map (gpio(31), spislvo.miso, spislvo.misooen, spislvi.miso);
spislvl_mosi_pad : iopad generic map (tech => padtech)
port map (gpio(30), spislvo.mosi, spislvo.mosioen, spislvi.mosi);
spislv_sck_pad : iopad generic map (tech => padtech)
port map (gpio(29), spislvo.sck, spislvo.sckoen, spislvi.sck);
spislv_slvsel_pad : iopad generic map (tech => padtech)
port map (gpio(28), gnd(0), vcc(0), spislvi.spisel);
end generate;
nospibridge : if CFG_SPI2AHB = 0 or CFG_SPI2AHB_APB = 0 generate
apbo(11) <= apb_none;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 16,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SPI2AHB),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (enet0_gtx_clk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (enet0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (enet0_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (enet0_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (enet0_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (enet0_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (enet0_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (enet0_rx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (enet0_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (enet0_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (enet0_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (enet0_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (enet0_mdc, etho.mdc);
eth0_rst_pad : odpad generic map (tech => padtech)
port map (enet0_rst_n, rstn);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 TerAsic DE2_115 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
package p_MEMORY is
-- To simplify (and accelerate) the RAM address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address which is at a different power of two than the ROM base.
-- Otherwise, the base must be subtracted from the address on every
-- reference, which means having an adder in the critical path.
-- Not good at all.
-- The address ranges for ROM, RAM and I/O must be distinct in the
-- uppermost 16 bits of the address (bits 31..16).
constant HI_SEL_BITS : integer := 31;
constant LO_SEL_BITS : integer := 16;
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00004000";
constant x_DATA_BASE_ADDR : reg32 := x"00040000";
constant x_DATA_MEM_SZ : reg32 := x"00020000";
constant x_IO_BASE_ADDR : reg32 := x"3c000000";
constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_SDRAM_BASE_ADDR : reg32 := x"04000000";
constant x_SDRAM_MEM_SZ : reg32 := x"02000000";
constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLBrefill
constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- CacheError
constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- generalExcpHandler
constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separInterrHandler
constant x_EXCEPTION_BFC0 : reg32 := x"000004E0"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000500"; -- main()
-- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
constant SDRAM_BASE_ADDR : integer := to_integer(signed(x_SDRAM_BASE_ADDR));
constant SDRAM_MEM_SZ : integer := to_integer(signed(x_SDRAM_MEM_SZ));
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
-- maximum number of IO devices, must be a power of two.
constant IO_MAX_NUM_DEVS : integer := 16;
constant IO_ADDR_BITS : integer := log2_ceil(IO_MAX_NUM_DEVS * IO_ADDR_RANGE);
-- I/O addresses are IO_ADDR_RANGE apart
constant IO_PRINT_ADDR : integer := IO_BASE_ADDR;
constant IO_STDOUT_ADDR : integer := IO_BASE_ADDR + 1*IO_ADDR_RANGE;
constant IO_STDIN_ADDR : integer := IO_BASE_ADDR + 2*IO_ADDR_RANGE;
constant IO_READ_ADDR : integer := IO_BASE_ADDR + 3*IO_ADDR_RANGE;
constant IO_WRITE_ADDR : integer := IO_BASE_ADDR + 4*IO_ADDR_RANGE;
constant IO_COUNT_ADDR : integer := IO_BASE_ADDR + 5*IO_ADDR_RANGE;
constant IO_FPU_ADDR : integer := IO_BASE_ADDR + 6*IO_ADDR_RANGE;
constant IO_UART_ADDR : integer := IO_BASE_ADDR + 7*IO_ADDR_RANGE;
constant IO_STATS_ADDR : integer := IO_BASE_ADDR + 8*IO_ADDR_RANGE;
constant IO_DSP7SEG_ADDR : integer := IO_BASE_ADDR + 9*IO_ADDR_RANGE;
constant IO_KEYBD_ADDR : integer := IO_BASE_ADDR + 10*IO_ADDR_RANGE;
constant IO_LCD_ADDR : integer := IO_BASE_ADDR + 11*IO_ADDR_RANGE;
constant IO_SDC_ADDR : integer := IO_BASE_ADDR + 12*IO_ADDR_RANGE;
constant IO_DMA_ADDR : integer := IO_BASE_ADDR + 13*IO_ADDR_RANGE;
constant IO_HIGHEST_ADDR : integer :=
IO_BASE_ADDR + (IO_MAX_NUM_DEVS - 1)*IO_ADDR_RANGE;
-- DATA CACHE parameters ================================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that DC_INDEX_BITS >= 6 (64 sets/way)
constant DC_TOTAL_CAPACITY : natural := 2*1024;
constant DC_NUM_WAYS : natural := 1; -- direct mapped
constant DC_VIA_CAPACITY : natural := DC_TOTAL_CAPACITY / DC_NUM_WAYS;
constant DC_BTS_PER_WORD : natural := 32;
constant DC_BYTES_PER_WORD : natural := 4;
constant DC_WORDS_PER_BLOCK : natural := 4;
constant DC_NUM_WORDS : natural := DC_VIA_CAPACITY / DC_BYTES_PER_WORD;
constant DC_NUM_BLOCKS : natural := DC_NUM_WORDS / DC_WORDS_PER_BLOCK;
constant DC_INDEX_BITS : natural := log2_ceil( DC_NUM_BLOCKS );
constant DC_WORD_SEL_BITS : natural := log2_ceil( DC_WORDS_PER_BLOCK );
constant DC_BYTE_SEL_BITS : natural := log2_ceil( DC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant DC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_unsigned(DC_INDEX_BITS - 6, 3));
constant DC_LINE_SIZE: reg3 :=
std_logic_vector(to_unsigned(DC_WORD_SEL_BITS + 1, 3));
constant DC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_unsigned(DC_NUM_WAYS - 1, 3));
-- INSTRUCTION CACHE parameters =========================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that IC_INDEX_BITS >= 6 (64 sets/via)
constant IC_TOTAL_CAPACITY : natural := 1024; -- 2*1024;
constant IC_NUM_WAYS : natural := 1; -- direct mapped
constant IC_VIA_CAPACITY : natural := IC_TOTAL_CAPACITY / IC_NUM_WAYS;
constant IC_BTS_PER_WORD : natural := 32;
constant IC_BYTES_PER_WORD : natural := 4;
constant IC_WORDS_PER_BLOCK : natural := 4;
constant IC_NUM_WORDS : natural := IC_VIA_CAPACITY / IC_BYTES_PER_WORD;
constant IC_NUM_BLOCKS : natural := IC_NUM_WORDS / IC_WORDS_PER_BLOCK;
constant IC_INDEX_BITS : natural := log2_ceil( IC_NUM_BLOCKS );
constant IC_WORD_SEL_BITS : natural := log2_ceil( IC_WORDS_PER_BLOCK );
constant IC_BYTE_SEL_BITS : natural := log2_ceil( IC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant IC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_unsigned(IC_INDEX_BITS - 6, 3));
constant IC_LINE_SIZE: reg3 :=
std_logic_vector(to_unsigned(IC_WORD_SEL_BITS + 1, 3));
constant IC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_unsigned(IC_NUM_WAYS - 1, 3));
-- constants to access the cache statistics counters
constant dcache_Stats_ref : reg3 := "000";
constant dcache_Stats_rdhit : reg3 := "001";
constant dcache_Stats_wrhit : reg3 := "010";
constant dcache_Stats_flush : reg3 := "011";
constant icache_Stats_ref : reg3 := "100";
constant icache_Stats_hit : reg3 := "101";
-- MMU parameters ========================================================
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant MMU_CAPACITY : natural := 8;
constant MMU_CAPACITY_BITS : natural := log2_ceil( MMU_CAPACITY );
constant MMU_SIZE: reg6 :=
std_logic_vector(to_unsigned( (MMU_CAPACITY-1), 6) );
constant MMU_WIRED_INIT : reg32 := x"00000000";
constant VABITS : natural := 32;
constant PABITS : natural := 32;
constant PAGE_SZ : natural := 4096; -- 4k pages
constant PAGE_SZ_BITS : natural := log2_ceil( PAGE_SZ );
constant PPN_BITS : natural := PABITS - PAGE_SZ_BITS;
constant VA_HI_BIT : natural := 31; -- VAaddr in EntryHi 31..PG_size
constant VA_LO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant ASID_HI_BIT : natural := 7; -- ASID in EntryHi 7..0
constant ASID_LO_BIT : natural := 0;
constant EHI_ASIDLO_BIT : natural := 0;
constant EHI_ASIDHI_BIT : natural := 7;
constant EHI_G_BIT : natural := 8;
constant EHI_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant EHI_AHI_BIT : natural := 31;
constant EHI_ZEROS : std_logic_vector(PAGE_SZ_BITS-EHI_G_BIT-1 downto 0) := (others => '0');
constant TAG_ASIDLO_BIT : natural := 0;
constant TAG_ASIDHI_BIT : natural := 7;
constant TAG_G_BIT : natural := 8;
constant TAG_Z_BIT : natural := 9;
constant TAG_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant TAG_AHI_BIT : natural := 31;
constant ELO_G_BIT : natural := 0;
constant ELO_V_BIT : natural := 1;
constant ELO_D_BIT : natural := 2;
constant ELO_CLO_BIT : natural := 3;
constant ELO_CHI_BIT : natural := 5;
constant ELO_ALO_BIT : natural := 6;
constant ELO_AHI_BIT : natural := ELO_ALO_BIT + PPN_BITS - 1;
constant DAT_G_BIT : natural := 0;
constant DAT_V_BIT : natural := 1;
constant DAT_D_BIT : natural := 2;
constant DAT_CLO_BIT : natural := 3;
constant DAT_CHI_BIT : natural := 5;
constant DAT_ALO_BIT : natural := 6;
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
subtype MMU_idx_bits is std_logic_vector(MMU_CAPACITY_BITS-1 downto 0);
constant MMU_idx_0s : std_logic_vector(30 downto MMU_CAPACITY_BITS) :=
(others => '0');
constant MMU_IDX_BIT : natural := 31; -- probe hit=1, miss=0
-- VA tags map a pair of PHY pages, thus VAddr is 1 bit less than (VABITS-1..PAGE_SZ_BITS)
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
constant x_ROM_PPN_0 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_ROM_PPN_1 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_ROM_PPN_2 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_ROM_PPN_3 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_ROM_PPN_4 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_ROM_PPN_5 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_unsigned(INST_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_RAM_PPN_2 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_RAM_PPN_3 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_RAM_PPN_4 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_RAM_PPN_5 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_unsigned(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
x_RAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 2 pages reserved for I/O devices
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_unsigned(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_unsigned(IO_BASE_ADDR + 1*PAGE_SZ, 32));
constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_unsigned(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
-- package body p_MEMORY is
-- end p_MEMORY;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Salida : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(ALUOP, Oper1, Oper2)
begin
case ALUOP is
when "000000" =>
Salida <= Oper1 + Oper2;
when "000001" =>
Salida <= Oper1 - Oper2;
when "000010" =>
Salida <= Oper1 and Oper2;
when "000011" =>
Salida <= Oper1 and not Oper2;
when "000100" =>
Salida <= Oper1 or Oper2;
when "000101" =>
Salida <= Oper1 or not Oper2;
when "000110" =>
Salida <= Oper1 xor Oper2;
when "000111" =>
Salida <= Oper1 xnor Oper2;
when others =>
Salida <= (others=>'1');
end case;
end process;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_module is Port (
CLK : in STD_LOGIC;
VGA_RED : out STD_LOGIC_VECTOR(3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR(3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : out STD_LOGIC;
VGA_HSYNC : out STD_LOGIC;
SW : in std_logic_vector(0 downto 0));
end top_module;
architecture Behavioral of top_module is
component vga800x600 port(
clk : IN std_logic;
red : OUT std_logic_vector(3 downto 0);
green : OUT std_logic_vector(3 downto 0);
blue : OUT std_logic_vector(3 downto 0);
vsync : OUT std_logic;
hsync : OUT std_logic;
SW : IN std_logic);
end component;
component clock_manager port (
CLK_IN1 : in std_logic;
pixel_clock : out std_logic);
end component;
signal rgb : std_logic_vector (11 downto 0);
signal pixel_clock : std_logic;
begin
pll1: clock_manager port map (
CLK_IN1 => CLK,
pixel_clock => pixel_clock
);
vga1: vga800x600 PORT MAP(
clk => pixel_clock,
red => VGA_RED,
green => VGA_GREEN,
blue => VGA_BLUE,
vsync => VGA_VSYNC,
hsync => VGA_HSYNC ,
SW => SW(0)
);
end Behavioral;
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 18:18:58 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_TEST_wrapper.bd
--Design : design_TEST_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end design_TEST_wrapper;
architecture STRUCTURE of design_TEST_wrapper is
component design_TEST is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component design_TEST;
begin
design_TEST_i: component design_TEST
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
|
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_xsvi_fanin_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_xsvi_fanin_plbw;
architecture structural of sg_xsvi_fanin_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_xsvi_fanin_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Wed Mar 30 17:30:47 2016
--Host : csteach0 running 64-bit Ubuntu 14.04.4 LTS
--Command : generate_target kuuga_test_harness.bd
--Design : kuuga_test_harness
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity kuuga_test_harness is
port (
Agito_Done : out STD_LOGIC;
Agito_Input_Loc : in STD_LOGIC_VECTOR ( 31 downto 0 );
Agito_Result : out STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_CLK : in STD_LOGIC;
Kuuga_Input_Loc : in STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_RST : in STD_LOGIC;
Kuuga_Result : out STD_LOGIC_VECTOR ( 31 downto 0 );
Kuuga_done : out STD_LOGIC;
start : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of kuuga_test_harness : entity is "kuuga_test_harness,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=kuuga_test_harness,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=3,numReposBlks=3,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of kuuga_test_harness : entity is "kuuga_test_harness.hwdef";
end kuuga_test_harness;
architecture STRUCTURE of kuuga_test_harness is
component kuuga_test_harness_kuuga_0_0 is
port (
ap_clk : in STD_LOGIC;
ap_rst : in STD_LOGIC;
ap_start : in STD_LOGIC;
ap_done : out STD_LOGIC;
ap_idle : out STD_LOGIC;
ap_ready : out STD_LOGIC;
ap_return : out STD_LOGIC_VECTOR ( 31 downto 0 );
output_loc : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component kuuga_test_harness_kuuga_0_0;
component kuuga_test_harness_agito_0_0 is
port (
ap_clk : in STD_LOGIC;
ap_rst : in STD_LOGIC;
ap_start : in STD_LOGIC;
ap_done : out STD_LOGIC;
ap_idle : out STD_LOGIC;
ap_ready : out STD_LOGIC;
ap_return : out STD_LOGIC_VECTOR ( 31 downto 0 );
output_loc : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component kuuga_test_harness_agito_0_0;
component kuuga_test_harness_clk_gen_0_0 is
port (
clk : out STD_LOGIC;
sync_rst : out STD_LOGIC
);
end component kuuga_test_harness_clk_gen_0_0;
signal Agito_Input_Loc_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal CLK_1 : STD_LOGIC;
signal RST_1 : STD_LOGIC;
signal agito_0_ap_done : STD_LOGIC;
signal agito_0_ap_return : STD_LOGIC_VECTOR ( 31 downto 0 );
signal clk_gen_0_clk : STD_LOGIC;
signal clk_gen_0_sync_rst : STD_LOGIC;
signal input_location_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal kuuga_0_ap_done : STD_LOGIC;
signal kuuga_0_ap_return : STD_LOGIC_VECTOR ( 31 downto 0 );
signal start_1 : STD_LOGIC;
signal NLW_agito_0_ap_idle_UNCONNECTED : STD_LOGIC;
signal NLW_agito_0_ap_ready_UNCONNECTED : STD_LOGIC;
signal NLW_kuuga_0_ap_idle_UNCONNECTED : STD_LOGIC;
signal NLW_kuuga_0_ap_ready_UNCONNECTED : STD_LOGIC;
begin
Agito_Done <= agito_0_ap_done;
Agito_Input_Loc_1(31 downto 0) <= Agito_Input_Loc(31 downto 0);
Agito_Result(31 downto 0) <= agito_0_ap_return(31 downto 0);
CLK_1 <= Kuuga_CLK;
Kuuga_Result(31 downto 0) <= kuuga_0_ap_return(31 downto 0);
Kuuga_done <= kuuga_0_ap_done;
RST_1 <= Kuuga_RST;
input_location_1(31 downto 0) <= Kuuga_Input_Loc(31 downto 0);
start_1 <= start;
agito_0: component kuuga_test_harness_agito_0_0
port map (
ap_clk => clk_gen_0_clk,
ap_done => agito_0_ap_done,
ap_idle => NLW_agito_0_ap_idle_UNCONNECTED,
ap_ready => NLW_agito_0_ap_ready_UNCONNECTED,
ap_return(31 downto 0) => agito_0_ap_return(31 downto 0),
ap_rst => clk_gen_0_sync_rst,
ap_start => start_1,
output_loc(31 downto 0) => Agito_Input_Loc_1(31 downto 0)
);
clk_gen_0: component kuuga_test_harness_clk_gen_0_0
port map (
clk => clk_gen_0_clk,
sync_rst => clk_gen_0_sync_rst
);
kuuga_0: component kuuga_test_harness_kuuga_0_0
port map (
ap_clk => CLK_1,
ap_done => kuuga_0_ap_done,
ap_idle => NLW_kuuga_0_ap_idle_UNCONNECTED,
ap_ready => NLW_kuuga_0_ap_ready_UNCONNECTED,
ap_return(31 downto 0) => kuuga_0_ap_return(31 downto 0),
ap_rst => RST_1,
ap_start => start_1,
output_loc(31 downto 0) => input_location_1(31 downto 0)
);
end STRUCTURE;
|
-- $Id: s3board_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: s3board_dummy - syn
-- Description: s3board minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_s3board
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.1.3 rename input pin CLK -> I_CLK50
-- 2010-04-17 278 1.1.2 rename sram_dummy -> s3_sram_dummy
-- 2007-12-16 101 1.1.1 use _N for active low
-- 2007-12-09 100 1.1 add sram memory signals, dummy handle them
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.s3boardlib.all;
entity s3board_dummy is -- S3BOARD dummy (base; loopback)
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3board_dummy;
architecture syn of s3board_dummy is
begin
O_TXD <= I_RXD;
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:50:28 07/21/2014
-- Design Name:
-- Module Name: /home/qfi/Documents/aeshw/aes-core/aes-core/decryption_module_tb.vhd
-- Project Name: aes-core
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: decryption_module
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY decryption_module_tb IS
END decryption_module_tb;
ARCHITECTURE behavior OF decryption_module_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decryption_module
PORT(
clk : IN std_logic;
reset : IN std_logic;
dec_start : IN std_logic;
dec_end : OUT std_logic;
din : IN std_logic_vector(127 downto 0);
dout : OUT std_logic_vector(127 downto 0);
addr_rkey : OUT std_logic_vector(3 downto 0);
rkey_in : IN std_logic_vector(127 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal dec_start : std_logic := '0';
signal din : std_logic_vector(127 downto 0) := (others => '0');
signal rkey_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal dec_end : std_logic;
signal dout : std_logic_vector(127 downto 0);
signal addr_rkey : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decryption_module PORT MAP (
clk => clk,
reset => reset,
dec_start => dec_start,
dec_end => dec_end,
din => din,
dout => dout,
addr_rkey => addr_rkey,
rkey_in => rkey_in
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
dec_start <= '1';
din <= x"69c4e0d86a7b0430d8cdb78070b4c55a"; -- plaintext
wait for clk_period;
assert addr_rkey = x"A" report "decryption : wrong round key address" severity failure; -- counter initialized
wait for clk_period;
assert addr_rkey = x"9" report "decryption : wrong round key address" severity failure;
rkey_in <= x"13111d7fe3944a17f307a78b4d2b30c5"; -- round key 0 now available (one cycle after round key address "A" due to synchronous read)
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- pre round finished
rkey_in <= x"549932d1f08557681093ed9cbe2c974e"; -- round key 1 now available
assert dout = x"7ad5fda789ef4e272bca100b3d9ff59f" report "decryption : wrong result in round 0" severity failure; -- pre round finished
assert addr_rkey = x"8" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 1 finished
rkey_in <= x"47438735a41c65b9e016baf4aebf7ad2"; -- round key 2 now available
assert dout = x"54d990a16ba09ab596bbf40ea111702f" report "decryption : wrong result in round 1" severity failure;
assert addr_rkey = x"7" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 2 finished
rkey_in <= x"14f9701ae35fe28c440adf4d4ea9c026"; -- round key 3 now available
assert dout = x"3e1c22c0b6fcbf768da85067f6170495" report "decryption : wrong result in round 2" severity failure;
assert addr_rkey = x"6" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 3 finished
rkey_in <= x"5e390f7df7a69296a7553dc10aa31f6b"; -- round key 4 now available
assert dout = x"b458124c68b68a014b99f82e5f15554c" report "decryption : wrong result in round 3" severity failure;
assert addr_rkey = x"5" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 4 finished
rkey_in <= x"3caaa3e8a99f9deb50f3af57adf622aa"; -- round key 5 now available
assert dout = x"e8dab6901477d4653ff7f5e2e747dd4f" report "decryption : wrong result in round 4" severity failure;
assert addr_rkey = x"4" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 5 finished
rkey_in <= x"47f7f7bc95353e03f96c32bcfd058dfd"; -- round key 6 now available
assert dout = x"36339d50f9b539269f2c092dc4406d23" report "decryption : wrong result in round 5" severity failure;
assert addr_rkey = x"3" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 6 finished
rkey_in <= x"b6ff744ed2c2c9bf6c590cbf0469bf41"; -- round key 7 now available
assert dout = x"2d6d7ef03f33e334093602dd5bfb12c7" report "decryption : wrong result in round 6" severity failure;
assert addr_rkey = x"2" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 7 finished
rkey_in <= x"b692cf0b643dbdf1be9bc5006830b3fe"; -- round key 8 now available
assert dout = x"3bd92268fc74fb735767cbe0c0590e2d" report "decryption : wrong result in round 7" severity failure;
assert addr_rkey = x"1" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 8 finished
rkey_in <= x"d6aa74fdd2af72fadaa678f1d6ab76fe"; -- round key 9 now available
assert dout = x"a7be1a6997ad739bd8c9ca451f618b61" report "decryption : wrong result in round 8" severity failure;
assert addr_rkey = x"0" report "decryption : wrong round key address" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 9 finished
rkey_in <= x"000102030405060708090a0b0c0d0e0f"; -- round key 10 now available
assert dout = x"6353e08c0960e104cd70b751bacad0e7" report "decryption : wrong result in round 9" severity failure;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- not yet finished
wait for clk_period;
-- round 10 finished
assert dout = x"00112233445566778899aabbccddeeff" report "decryption : wrong result in round 10" severity failure;
assert dec_end = '1' report "decryption : wrong end signal" severity failure; -- finished
wait for clk_period;
assert dec_end = '0' report "decryption : wrong end signal" severity failure; -- ready
wait;
end process;
END;
|
entity ADDER_TREE is
generic (
IN_WIDTH : integer := 14;
OUT_WIDTH : integer := 15
);
port (
Q : out std_logic_vector((OUT_WIDTH - 1) downto 0)
);
end entity ADDER_TREE;
|
-------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
-------------------------------------------------------------------------------
-- Filename: xip_cross_clk_sync.vhd
-- Version: v3.0
-- Description: This is the CDC file for XIP mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Created second version of the core.
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity xip_cross_clk_sync is
generic (
C_S_AXI4_DATA_WIDTH : integer;
C_SPI_MEM_ADDR_BITS : integer;
Async_Clk : integer ;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESET : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
mst_modf_err_cdc_from_spi : in std_logic;
mst_modf_err_cdc_to_axi : out std_logic;
mst_modf_err_cdc_to_axi4 : out std_logic;
----------------------------
one_byte_xfer_cdc_from_axi : in std_logic;
one_byte_xfer_cdc_to_spi : out std_logic;
----------------------
two_byte_xfer_cdc_from_axi : in std_logic;
two_byte_xfer_cdc_to_spi : out std_logic;
----------------------
four_byte_xfer_cdc_from_axi : in std_logic;
four_byte_xfer_cdc_to_spi : out std_logic;
----------------------
Transmit_Addr_cdc_from_axi : in std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
Transmit_Addr_cdc_to_spi : out std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
----------------------
load_cmd_cdc_from_axi : in std_logic;
load_cmd_cdc_to_spi : out std_logic;
--------------------------
CPOL_cdc_from_axi : in std_logic;
CPOL_cdc_to_spi : out std_logic;
--------------------------
CPHA_cdc_from_axi : in std_logic;
CPHA_cdc_to_spi : out std_logic;
--------------------------
SS_cdc_from_axi : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_cdc_to_spi : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
--------------------------
type_of_burst_cdc_from_axi : in std_logic;-- _vector(1 downto 0);
type_of_burst_cdc_to_spi : out std_logic;-- _vector(1 downto 0);
--------------------------
axi_length_cdc_from_axi : in std_logic_vector(7 downto 0);
axi_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
dtr_length_cdc_from_axi : in std_logic_vector(7 downto 0);
dtr_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
load_axi_data_cdc_from_axi : in std_logic;
load_axi_data_cdc_to_spi : out std_logic;
------------------------------
Rx_FIFO_Full_cdc_from_spi : in std_logic;
Rx_FIFO_Full_cdc_to_axi : out std_logic;
Rx_FIFO_Full_cdc_to_axi4 : out std_logic;
------------------------------
wb_hpm_done_cdc_from_spi : in std_logic;
wb_hpm_done_cdc_to_axi : out std_logic
);
end entity xip_cross_clk_sync;
-------------------------------------------------------------------------------
architecture imp of xip_cross_clk_sync is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
signal size_length_cdc_to_spi_d1 : std_logic_vector(1 downto 0);
signal size_length_cdc_to_spi_d2 : std_logic_vector(1 downto 0);
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2 : std_logic;
signal spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal byte_xfer_cdc_from_axi_d1 : std_logic;
signal byte_xfer_cdc_from_axi_d2 : std_logic;
signal hw_xfer_cdc_from_axi_d1 : std_logic;
signal hw_xfer_cdc_from_axi_d2 : std_logic;
signal word_xfer_cdc_from_axi_d1 : std_logic;
signal word_xfer_cdc_from_axi_d2 : std_logic;
signal SS_cdc_from_spi_d1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_cdc_from_spi_d2 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal mst_modf_err_d1 : std_logic;
signal mst_modf_err_d2 : std_logic;
signal mst_modf_err_d3 : std_logic;
signal mst_modf_err_d4 : std_logic;
signal dtr_length_cdc_from_axi_d1 : std_logic_vector(7 downto 0);
signal dtr_length_cdc_from_axi_d2 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d1 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d2 : std_logic_vector(7 downto 0);
signal CPOL_cdc_to_spi_d1 : std_logic;
signal CPOL_cdc_to_spi_d2 : std_logic;
signal CPHA_cdc_to_spi_d1 : std_logic;
signal CPHA_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d1 : std_logic;
signal load_axi_data_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d3 : std_logic;
signal Transmit_Addr_cdc_from_axi_d1 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal Transmit_Addr_cdc_from_axi_d2 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal type_of_burst_cdc_to_spi_d1 : std_logic;-- _vector(1 downto 0);
signal type_of_burst_cdc_to_spi_d2 : std_logic;-- _vector(1 downto 0);
signal load_cmd_cdc_from_axi_d1 : std_logic;
signal load_cmd_cdc_from_axi_d2 : std_logic;
signal load_cmd_cdc_from_axi_d3 : std_logic;
signal load_cmd_cdc_from_axi_int_2 : std_logic;
signal rx_fifo_full_d1 : std_logic;
signal rx_fifo_full_d2 : std_logic;
signal rx_fifo_full_d3 : std_logic;
signal rx_fifo_full_d4 : std_logic;
signal ld_axi_data_cdc_from_axi_int_2 : std_logic;
signal wb_hpm_done_cdc_from_spi_d1 : std_logic;
signal wb_hpm_done_cdc_from_spi_d2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of XFER_DONE_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of BYTE_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of HW_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of WORD_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of TYP_OF_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_AXI_DATA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_CMD_SYNC_AXI2SPI : label is "TRUE";
-- -- attribute ASYNC_REG of TRANSMIT_DATA_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of CPOL_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of CPHA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of WB_HPM_DONE_SYNC_SPI2AXI : label is "TRUE";
attribute KEEP : string;
attribute KEEP of SS_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d3 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of type_of_burst_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of rx_fifo_full_d2 : signal is "TRUE";
attribute KEEP of CPHA_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of CPOL_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of Transmit_Addr_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d3 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of word_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of hw_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of byte_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d4 : signal is "TRUE";
attribute KEEP of spiXfer_done_d2 : signal is "TRUE";
attribute KEEP of spiXfer_done_d3 : signal is "TRUE";
attribute KEEP of axi_length_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of dtr_length_cdc_from_axi_d2 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
-----
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => S_AXI4_ACLK,
D => spiXfer_done_cdc_from_spi_int_2,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => S_AXI4_ACLK,
D => spiXfer_done_d1,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => S_AXI4_ACLK,
D => spiXfer_done_d2,
R => S_AXI4_ARESET
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d1,
C => S_AXI_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI_ARESETN
);
MST_MODF_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d2,
C => S_AXI_ACLK,
D => mst_modf_err_d1,
R => S_AXI_ARESETN
);
mst_modf_err_cdc_to_axi <= mst_modf_err_d2;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d3,
C => S_AXI4_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI4_ARESET
);
MST_MODF_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d4,
C => S_AXI4_ACLK,
D => mst_modf_err_d3,
R => S_AXI4_ARESET
);
mst_modf_err_cdc_to_axi4 <= mst_modf_err_d4;
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => one_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
BYTE_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => byte_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
one_byte_xfer_cdc_to_spi <= byte_xfer_cdc_from_axi_d2;
------------------------------------------------
HW_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => two_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
HW_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => hw_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
two_byte_xfer_cdc_to_spi <= hw_xfer_cdc_from_axi_d2;
------------------------------------------------
WORD_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => four_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
WORD_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => word_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
four_byte_xfer_cdc_to_spi <= word_xfer_cdc_from_axi_d2;
------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
-------------------------------------
-- from AXI4 to SPI
LD_CMD_SYNC_AXI2SPI: component FDR
port map (
Q => load_cmd_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_1: component FDR
port map (
Q => load_cmd_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_2: component FDR
port map (
Q => load_cmd_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
--------------------------------------------------------------------------
-- from AXI4 to SPI
TRANS_ADDR_SYNC_GEN: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TRANS_ADDR_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TRANS_ADDR_SYNC_GEN;
-- Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2; -- 4/19/2013
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d1; -- 4/19/2013
------------------------------------------------
-- from AXI4 Lite to SPI
CPOL_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPOL_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPOL_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPOL_cdc_to_spi <= CPOL_cdc_to_spi_d2;
------------------------------------------------
-- from AXI4 Lite to SPI
CPHA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPHA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPHA_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPHA_cdc_to_spi <= CPHA_cdc_to_spi_d2;
------------------------------------------------
LD_AXI_DATA_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
-------------------------------------
LD_AXI_DATA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => ld_axi_data_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_2: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d3,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
------------------------------------------------
SS_SYNC_AXI_SPI_GEN: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
SS_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d1(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SS_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d2(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SS_SYNC_AXI_SPI_GEN;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
TYP_OF_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
--end generate TYP_OF_XFER_GEN;
------------------------------
type_of_burst_cdc_to_spi <= type_of_burst_cdc_to_spi_d2;
------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
AXI_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d1(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
AXI_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d2(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_to_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
DTR_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
-- from SPI to AXI Lite
Rx_FIFO_Full_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d1,
C => S_AXI_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d2,
C => S_AXI_ACLK,
D => rx_fifo_full_d1,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_cdc_to_axi <= rx_fifo_full_d2;
-------------------------------------------------------------------------------
-- from SPI to AXI4
Rx_FIFO_Full_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d3,
C => S_AXI4_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d4,
C => S_AXI4_ACLK,
D => rx_fifo_full_d3,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_cdc_to_axi4 <= rx_fifo_full_d4;
-------------------------------------------------------------------------------
-- from SPI to AXI4
WB_HPM_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d1,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi,
R => S_AXI4_ARESET
);
WB_HPM_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d2,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi_d1,
R => S_AXI4_ARESET
);
wb_hpm_done_cdc_to_axi <= wb_hpm_done_cdc_from_spi_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
-------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
--spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor spiXfer_done_cdc_from_spi_int_2;
--spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
spiXfer_done_d3 <= '0';
else
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI_ARESETN ,
scndry_out => mst_modf_err_cdc_to_axi
);
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => mst_modf_err_cdc_to_axi4
);
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => one_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => one_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
HW_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => two_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => two_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
WORD_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => four_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => four_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
--load_cmd_cdc_from_axi_d1 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
--load_cmd_cdc_from_axi_d1 <= load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH_CDC;
LD_CMD_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => load_cmd_cdc_from_axi_int_2,--load_cmd_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_cmd_cdc_from_axi_d2
);
LD_CMD_cdc_from_AXI_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_cmd_cdc_from_axi_d3 <= '0';
else
load_cmd_cdc_from_axi_d3 <= load_cmd_cdc_from_axi_d2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
-------------------------------------------------------------------------------
TRANS_ADDR_SYNC_GEN_CDC: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => Transmit_Addr_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => Transmit_Addr_cdc_from_axi_d2(i)
);
end generate TRANS_ADDR_SYNC_GEN_CDC;
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2;
-------------------------------------------------------------------------------
CPOL_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPOL_cdc_to_spi
);
-------------------------------------------------------------------------------
CPHA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPHA_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_AXI_DATA_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
--load_axi_data_cdc_to_spi_d1 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
-- load_axi_data_cdc_to_spi_d1 <= ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH_CDC;
LD_AXI_DATA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => ld_axi_data_cdc_from_axi_int_2,--load_axi_data_cdc_to_spi_d1 ,
prmry_vect_in => (others => '0' ),
scndry_aclk => EXT_SPI_CLK ,
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_axi_data_cdc_to_spi_d2
);
LD_AXI_DATA_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_axi_data_cdc_to_spi_d3 <= '0';
else
load_axi_data_cdc_to_spi_d3 <= load_axi_data_cdc_to_spi_d2 ;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
SS_SYNC_AXI_SPI_GEN_CDC: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
SS_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => SS_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
scndry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => (others => '0' ),
scndry_out => SS_cdc_from_spi_d2(i)
);
end generate SS_SYNC_AXI_SPI_GEN_CDC;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => type_of_burst_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => type_of_burst_cdc_to_spi
);
---------------------------------------------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-------------
AXI_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => axi_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => axi_length_cdc_to_spi_d2(i)
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN_CDC;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => dtr_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => dtr_length_cdc_from_axi_d2(i)
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN_CDC;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI_ACLK ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => Rx_FIFO_Full_cdc_to_axi
);
------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => Rx_FIFO_Full_cdc_to_axi4
);
-------------------------------------------------------------------------------
WB_HPM_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => wb_hpm_done_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => wb_hpm_done_cdc_to_axi
);
-------------------------------------------------------------------------------
byte_xfer_cdc_from_axi_d2 <= '0' ;
hw_xfer_cdc_from_axi_d2 <= '0' ;
word_xfer_cdc_from_axi_d2 <= '0' ;
mst_modf_err_d2 <= '0' ;
mst_modf_err_d4 <= '0' ;
CPOL_cdc_to_spi_d2 <= '0' ;
CPHA_cdc_to_spi_d2 <= '0' ;
type_of_burst_cdc_to_spi_d2 <= '0' ;
rx_fifo_full_d2 <= '0' ;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
---------------------
|
-------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
-------------------------------------------------------------------------------
-- Filename: xip_cross_clk_sync.vhd
-- Version: v3.0
-- Description: This is the CDC file for XIP mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Created second version of the core.
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity xip_cross_clk_sync is
generic (
C_S_AXI4_DATA_WIDTH : integer;
C_SPI_MEM_ADDR_BITS : integer;
Async_Clk : integer ;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESET : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
mst_modf_err_cdc_from_spi : in std_logic;
mst_modf_err_cdc_to_axi : out std_logic;
mst_modf_err_cdc_to_axi4 : out std_logic;
----------------------------
one_byte_xfer_cdc_from_axi : in std_logic;
one_byte_xfer_cdc_to_spi : out std_logic;
----------------------
two_byte_xfer_cdc_from_axi : in std_logic;
two_byte_xfer_cdc_to_spi : out std_logic;
----------------------
four_byte_xfer_cdc_from_axi : in std_logic;
four_byte_xfer_cdc_to_spi : out std_logic;
----------------------
Transmit_Addr_cdc_from_axi : in std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
Transmit_Addr_cdc_to_spi : out std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
----------------------
load_cmd_cdc_from_axi : in std_logic;
load_cmd_cdc_to_spi : out std_logic;
--------------------------
CPOL_cdc_from_axi : in std_logic;
CPOL_cdc_to_spi : out std_logic;
--------------------------
CPHA_cdc_from_axi : in std_logic;
CPHA_cdc_to_spi : out std_logic;
--------------------------
SS_cdc_from_axi : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_cdc_to_spi : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
--------------------------
type_of_burst_cdc_from_axi : in std_logic;-- _vector(1 downto 0);
type_of_burst_cdc_to_spi : out std_logic;-- _vector(1 downto 0);
--------------------------
axi_length_cdc_from_axi : in std_logic_vector(7 downto 0);
axi_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
dtr_length_cdc_from_axi : in std_logic_vector(7 downto 0);
dtr_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
load_axi_data_cdc_from_axi : in std_logic;
load_axi_data_cdc_to_spi : out std_logic;
------------------------------
Rx_FIFO_Full_cdc_from_spi : in std_logic;
Rx_FIFO_Full_cdc_to_axi : out std_logic;
Rx_FIFO_Full_cdc_to_axi4 : out std_logic;
------------------------------
wb_hpm_done_cdc_from_spi : in std_logic;
wb_hpm_done_cdc_to_axi : out std_logic
);
end entity xip_cross_clk_sync;
-------------------------------------------------------------------------------
architecture imp of xip_cross_clk_sync is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
signal size_length_cdc_to_spi_d1 : std_logic_vector(1 downto 0);
signal size_length_cdc_to_spi_d2 : std_logic_vector(1 downto 0);
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2 : std_logic;
signal spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal byte_xfer_cdc_from_axi_d1 : std_logic;
signal byte_xfer_cdc_from_axi_d2 : std_logic;
signal hw_xfer_cdc_from_axi_d1 : std_logic;
signal hw_xfer_cdc_from_axi_d2 : std_logic;
signal word_xfer_cdc_from_axi_d1 : std_logic;
signal word_xfer_cdc_from_axi_d2 : std_logic;
signal SS_cdc_from_spi_d1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_cdc_from_spi_d2 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal mst_modf_err_d1 : std_logic;
signal mst_modf_err_d2 : std_logic;
signal mst_modf_err_d3 : std_logic;
signal mst_modf_err_d4 : std_logic;
signal dtr_length_cdc_from_axi_d1 : std_logic_vector(7 downto 0);
signal dtr_length_cdc_from_axi_d2 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d1 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d2 : std_logic_vector(7 downto 0);
signal CPOL_cdc_to_spi_d1 : std_logic;
signal CPOL_cdc_to_spi_d2 : std_logic;
signal CPHA_cdc_to_spi_d1 : std_logic;
signal CPHA_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d1 : std_logic;
signal load_axi_data_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d3 : std_logic;
signal Transmit_Addr_cdc_from_axi_d1 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal Transmit_Addr_cdc_from_axi_d2 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal type_of_burst_cdc_to_spi_d1 : std_logic;-- _vector(1 downto 0);
signal type_of_burst_cdc_to_spi_d2 : std_logic;-- _vector(1 downto 0);
signal load_cmd_cdc_from_axi_d1 : std_logic;
signal load_cmd_cdc_from_axi_d2 : std_logic;
signal load_cmd_cdc_from_axi_d3 : std_logic;
signal load_cmd_cdc_from_axi_int_2 : std_logic;
signal rx_fifo_full_d1 : std_logic;
signal rx_fifo_full_d2 : std_logic;
signal rx_fifo_full_d3 : std_logic;
signal rx_fifo_full_d4 : std_logic;
signal ld_axi_data_cdc_from_axi_int_2 : std_logic;
signal wb_hpm_done_cdc_from_spi_d1 : std_logic;
signal wb_hpm_done_cdc_from_spi_d2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of XFER_DONE_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of BYTE_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of HW_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of WORD_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of TYP_OF_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_AXI_DATA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_CMD_SYNC_AXI2SPI : label is "TRUE";
-- -- attribute ASYNC_REG of TRANSMIT_DATA_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of CPOL_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of CPHA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of WB_HPM_DONE_SYNC_SPI2AXI : label is "TRUE";
attribute KEEP : string;
attribute KEEP of SS_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d3 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of type_of_burst_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of rx_fifo_full_d2 : signal is "TRUE";
attribute KEEP of CPHA_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of CPOL_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of Transmit_Addr_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d3 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of word_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of hw_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of byte_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d4 : signal is "TRUE";
attribute KEEP of spiXfer_done_d2 : signal is "TRUE";
attribute KEEP of spiXfer_done_d3 : signal is "TRUE";
attribute KEEP of axi_length_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of dtr_length_cdc_from_axi_d2 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
-----
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => S_AXI4_ACLK,
D => spiXfer_done_cdc_from_spi_int_2,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => S_AXI4_ACLK,
D => spiXfer_done_d1,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => S_AXI4_ACLK,
D => spiXfer_done_d2,
R => S_AXI4_ARESET
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d1,
C => S_AXI_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI_ARESETN
);
MST_MODF_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d2,
C => S_AXI_ACLK,
D => mst_modf_err_d1,
R => S_AXI_ARESETN
);
mst_modf_err_cdc_to_axi <= mst_modf_err_d2;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d3,
C => S_AXI4_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI4_ARESET
);
MST_MODF_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d4,
C => S_AXI4_ACLK,
D => mst_modf_err_d3,
R => S_AXI4_ARESET
);
mst_modf_err_cdc_to_axi4 <= mst_modf_err_d4;
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => one_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
BYTE_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => byte_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
one_byte_xfer_cdc_to_spi <= byte_xfer_cdc_from_axi_d2;
------------------------------------------------
HW_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => two_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
HW_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => hw_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
two_byte_xfer_cdc_to_spi <= hw_xfer_cdc_from_axi_d2;
------------------------------------------------
WORD_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => four_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
WORD_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => word_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
four_byte_xfer_cdc_to_spi <= word_xfer_cdc_from_axi_d2;
------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
-------------------------------------
-- from AXI4 to SPI
LD_CMD_SYNC_AXI2SPI: component FDR
port map (
Q => load_cmd_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_1: component FDR
port map (
Q => load_cmd_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_2: component FDR
port map (
Q => load_cmd_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
--------------------------------------------------------------------------
-- from AXI4 to SPI
TRANS_ADDR_SYNC_GEN: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TRANS_ADDR_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TRANS_ADDR_SYNC_GEN;
-- Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2; -- 4/19/2013
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d1; -- 4/19/2013
------------------------------------------------
-- from AXI4 Lite to SPI
CPOL_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPOL_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPOL_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPOL_cdc_to_spi <= CPOL_cdc_to_spi_d2;
------------------------------------------------
-- from AXI4 Lite to SPI
CPHA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPHA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPHA_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPHA_cdc_to_spi <= CPHA_cdc_to_spi_d2;
------------------------------------------------
LD_AXI_DATA_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
-------------------------------------
LD_AXI_DATA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => ld_axi_data_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_2: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d3,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
------------------------------------------------
SS_SYNC_AXI_SPI_GEN: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
SS_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d1(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SS_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d2(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SS_SYNC_AXI_SPI_GEN;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
TYP_OF_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
--end generate TYP_OF_XFER_GEN;
------------------------------
type_of_burst_cdc_to_spi <= type_of_burst_cdc_to_spi_d2;
------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
AXI_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d1(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
AXI_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d2(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_to_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
DTR_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
-- from SPI to AXI Lite
Rx_FIFO_Full_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d1,
C => S_AXI_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d2,
C => S_AXI_ACLK,
D => rx_fifo_full_d1,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_cdc_to_axi <= rx_fifo_full_d2;
-------------------------------------------------------------------------------
-- from SPI to AXI4
Rx_FIFO_Full_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d3,
C => S_AXI4_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d4,
C => S_AXI4_ACLK,
D => rx_fifo_full_d3,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_cdc_to_axi4 <= rx_fifo_full_d4;
-------------------------------------------------------------------------------
-- from SPI to AXI4
WB_HPM_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d1,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi,
R => S_AXI4_ARESET
);
WB_HPM_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d2,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi_d1,
R => S_AXI4_ARESET
);
wb_hpm_done_cdc_to_axi <= wb_hpm_done_cdc_from_spi_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
-------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
--spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor spiXfer_done_cdc_from_spi_int_2;
--spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
spiXfer_done_d3 <= '0';
else
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI_ARESETN ,
scndry_out => mst_modf_err_cdc_to_axi
);
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => mst_modf_err_cdc_to_axi4
);
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => one_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => one_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
HW_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => two_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => two_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
WORD_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => four_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => four_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
--load_cmd_cdc_from_axi_d1 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
--load_cmd_cdc_from_axi_d1 <= load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH_CDC;
LD_CMD_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => load_cmd_cdc_from_axi_int_2,--load_cmd_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_cmd_cdc_from_axi_d2
);
LD_CMD_cdc_from_AXI_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_cmd_cdc_from_axi_d3 <= '0';
else
load_cmd_cdc_from_axi_d3 <= load_cmd_cdc_from_axi_d2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
-------------------------------------------------------------------------------
TRANS_ADDR_SYNC_GEN_CDC: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => Transmit_Addr_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => Transmit_Addr_cdc_from_axi_d2(i)
);
end generate TRANS_ADDR_SYNC_GEN_CDC;
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2;
-------------------------------------------------------------------------------
CPOL_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPOL_cdc_to_spi
);
-------------------------------------------------------------------------------
CPHA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPHA_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_AXI_DATA_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
--load_axi_data_cdc_to_spi_d1 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
-- load_axi_data_cdc_to_spi_d1 <= ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH_CDC;
LD_AXI_DATA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => ld_axi_data_cdc_from_axi_int_2,--load_axi_data_cdc_to_spi_d1 ,
prmry_vect_in => (others => '0' ),
scndry_aclk => EXT_SPI_CLK ,
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_axi_data_cdc_to_spi_d2
);
LD_AXI_DATA_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_axi_data_cdc_to_spi_d3 <= '0';
else
load_axi_data_cdc_to_spi_d3 <= load_axi_data_cdc_to_spi_d2 ;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
SS_SYNC_AXI_SPI_GEN_CDC: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
SS_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => SS_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
scndry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => (others => '0' ),
scndry_out => SS_cdc_from_spi_d2(i)
);
end generate SS_SYNC_AXI_SPI_GEN_CDC;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => type_of_burst_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => type_of_burst_cdc_to_spi
);
---------------------------------------------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-------------
AXI_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => axi_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => axi_length_cdc_to_spi_d2(i)
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN_CDC;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => dtr_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => dtr_length_cdc_from_axi_d2(i)
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN_CDC;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI_ACLK ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => Rx_FIFO_Full_cdc_to_axi
);
------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => Rx_FIFO_Full_cdc_to_axi4
);
-------------------------------------------------------------------------------
WB_HPM_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => wb_hpm_done_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => wb_hpm_done_cdc_to_axi
);
-------------------------------------------------------------------------------
byte_xfer_cdc_from_axi_d2 <= '0' ;
hw_xfer_cdc_from_axi_d2 <= '0' ;
word_xfer_cdc_from_axi_d2 <= '0' ;
mst_modf_err_d2 <= '0' ;
mst_modf_err_d4 <= '0' ;
CPOL_cdc_to_spi_d2 <= '0' ;
CPHA_cdc_to_spi_d2 <= '0' ;
type_of_burst_cdc_to_spi_d2 <= '0' ;
rx_fifo_full_d2 <= '0' ;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
---------------------
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`protect end_protected
|
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_register_bank_a_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_register_bank_a_module;
architecture europa of Video_System_CPU_register_bank_a_module is
component altsyncram is
GENERIC (
address_reg_b : STRING;
init_file : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
rdcontrol_reg_b : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
signal ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
q <= ram_q;
the_altsyncram : altsyncram
generic map(
address_reg_b => "CLOCK0",
init_file => lpm_file,
maximum_depth => 0,
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
rdcontrol_reg_b => "CLOCK0",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_b => 32,
widthad_a => 5,
widthad_b => 5
)
port map(
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
q_b => ram_q,
wren_a => wren
);
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_register_bank_b_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_register_bank_b_module;
architecture europa of Video_System_CPU_register_bank_b_module is
component altsyncram is
GENERIC (
address_reg_b : STRING;
init_file : STRING;
maximum_depth : NATURAL;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
rdcontrol_reg_b : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal clock0 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
signal ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
q <= ram_q;
the_altsyncram : altsyncram
generic map(
address_reg_b => "CLOCK0",
init_file => lpm_file,
maximum_depth => 0,
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
rdcontrol_reg_b => "CLOCK0",
read_during_write_mode_mixed_ports => "DONT_CARE",
width_a => 32,
width_b => 32,
widthad_a => 5,
widthad_b => 5
)
port map(
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
q_b => ram_q,
wren_a => wren
);
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_debug is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal debugreq : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal ocireg_ers : IN STD_LOGIC;
signal ocireg_mrs : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal st_ready_test_idle : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocireg : IN STD_LOGIC;
signal xbrk_break : IN STD_LOGIC;
-- outputs:
signal debugack : OUT STD_LOGIC;
signal monitor_error : OUT STD_LOGIC;
signal monitor_go : OUT STD_LOGIC;
signal monitor_ready : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal resetlatch : OUT STD_LOGIC;
signal resetrequest : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_debug;
architecture europa of Video_System_CPU_nios2_oci_debug is
signal internal_debugack : STD_LOGIC;
signal internal_resetlatch : STD_LOGIC;
signal jtag_break : STD_LOGIC;
signal probepresent : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of jtag_break : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of monitor_error : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of monitor_go : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of monitor_ready : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of probepresent : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of resetlatch : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of resetrequest : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
begin
process (clk, jrst_n)
begin
if jrst_n = '0' then
probepresent <= std_logic'('0');
resetrequest <= std_logic'('0');
jtag_break <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(take_action_ocimem_a) = '1' then
resetrequest <= jdo(22);
jtag_break <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jdo(21)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(jdo(20)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(jtag_break))))));
probepresent <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jdo(19)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(jdo(18)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(probepresent))))));
internal_resetlatch <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jdo(24)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_resetlatch)))));
elsif std_logic'(reset) = '1' then
jtag_break <= probepresent;
internal_resetlatch <= std_logic'('1');
elsif std_logic'(((NOT internal_debugack AND debugreq) AND probepresent)) = '1' then
jtag_break <= std_logic'('1');
end if;
end if;
end process;
process (clk, jrst_n)
begin
if jrst_n = '0' then
monitor_ready <= std_logic'('0');
monitor_error <= std_logic'('0');
monitor_go <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((take_action_ocimem_a AND jdo(25))) = '1' then
monitor_ready <= std_logic'('0');
elsif std_logic'((take_action_ocireg AND ocireg_mrs)) = '1' then
monitor_ready <= std_logic'('1');
end if;
if std_logic'((take_action_ocimem_a AND jdo(25))) = '1' then
monitor_error <= std_logic'('0');
elsif std_logic'((take_action_ocireg AND ocireg_ers)) = '1' then
monitor_error <= std_logic'('1');
end if;
if std_logic'((take_action_ocimem_a AND jdo(23))) = '1' then
monitor_go <= std_logic'('1');
elsif std_logic'(st_ready_test_idle) = '1' then
monitor_go <= std_logic'('0');
end if;
end if;
end process;
oci_hbreak_req <= ((jtag_break OR dbrk_break) OR xbrk_break) OR debugreq;
internal_debugack <= NOT hbreak_enabled;
--vhdl renameroo for output signals
debugack <= internal_debugack;
--vhdl renameroo for output signals
resetlatch <= internal_resetlatch;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_ociram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_ociram_lpm_dram_bdp_component_module;
architecture europa of Video_System_CPU_ociram_lpm_dram_bdp_component_module is
component altsyncram is
GENERIC (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clocken1 : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component altsyncram;
signal internal_q_a : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_q_b : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
the_altsyncram : altsyncram
generic map(
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
init_file => lpm_file,
intended_device_family => "CYCLONEII",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "OLD_DATA",
width_a => 32,
width_b => 32,
width_byteena_a => 4,
widthad_a => 8,
widthad_b => 8,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE"
)
port map(
address_a => address_a,
address_b => address_b,
byteena_a => byteena_a,
clock0 => clock0,
clock1 => clock1,
clocken0 => clocken0,
clocken1 => clocken1,
data_a => data_a,
data_b => data_b,
q_a => internal_q_a,
q_b => internal_q_b,
wren_a => wren_a,
wren_b => wren_b
);
--vhdl renameroo for output signals
q_a <= internal_q_a;
--vhdl renameroo for output signals
q_b <= internal_q_b;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_ocimem is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal resetrequest : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocimem_b : IN STD_LOGIC;
signal take_no_action_ocimem_a : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal MonDReg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_ram_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity Video_System_CPU_nios2_ocimem;
architecture europa of Video_System_CPU_nios2_ocimem is
component Video_System_CPU_ociram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_ociram_lpm_dram_bdp_component_module;
signal MonAReg : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal MonRd : STD_LOGIC;
signal MonRd1 : STD_LOGIC;
signal MonWr : STD_LOGIC;
signal avalon : STD_LOGIC;
signal cfgdout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_MonDReg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_oci_ram_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal module_input1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal module_input2 : STD_LOGIC;
signal module_input3 : STD_LOGIC;
signal module_input4 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input5 : STD_LOGIC;
signal sramdout : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of MonDReg, MonAReg, MonRd1, MonRd, MonWr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
--synthesis translate_off
constant Video_System_CPU_ociram_lpm_dram_bdp_component_lpm_file : string := "Video_System_CPU_ociram_default_contents.hex";
--synthesis translate_on
--synthesis read_comments_as_HDL on
--constant Video_System_CPU_ociram_lpm_dram_bdp_component_lpm_file : string := "Video_System_CPU_ociram_default_contents.mif";
--synthesis read_comments_as_HDL off
begin
avalon <= begintransfer AND NOT resetrequest;
process (clk, jrst_n)
begin
if jrst_n = '0' then
MonWr <= std_logic'('0');
MonRd <= std_logic'('0');
MonRd1 <= std_logic'('0');
MonAReg <= std_logic_vector'("00000000000");
internal_MonDReg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(take_no_action_ocimem_a) = '1' then
MonAReg(10 DOWNTO 2) <= A_EXT (((std_logic_vector'("000000000000000000000000") & (MonAReg(10 DOWNTO 2))) + std_logic_vector'("000000000000000000000000000000001")), 9);
MonRd <= std_logic'('1');
elsif std_logic'(take_action_ocimem_a) = '1' then
MonAReg(10 DOWNTO 2) <= Std_Logic_Vector'(A_ToStdLogicVector(jdo(17)) & jdo(33 DOWNTO 26));
MonRd <= std_logic'('1');
elsif std_logic'(take_action_ocimem_b) = '1' then
MonAReg(10 DOWNTO 2) <= A_EXT (((std_logic_vector'("000000000000000000000000") & (MonAReg(10 DOWNTO 2))) + std_logic_vector'("000000000000000000000000000000001")), 9);
internal_MonDReg <= jdo(34 DOWNTO 3);
MonWr <= std_logic'('1');
else
if std_logic'(NOT avalon) = '1' then
MonWr <= std_logic'('0');
MonRd <= std_logic'('0');
end if;
if std_logic'(MonRd1) = '1' then
internal_MonDReg <= A_WE_StdLogicVector((std_logic'(MonAReg(10)) = '1'), cfgdout, sramdout);
end if;
end if;
MonRd1 <= MonRd;
end if;
end process;
--Video_System_CPU_ociram_lpm_dram_bdp_component, which is an nios_tdp_ram
Video_System_CPU_ociram_lpm_dram_bdp_component : Video_System_CPU_ociram_lpm_dram_bdp_component_module
generic map(
lpm_file => Video_System_CPU_ociram_lpm_dram_bdp_component_lpm_file
)
port map(
q_a => internal_oci_ram_readdata,
q_b => sramdout,
address_a => module_input,
address_b => module_input1,
byteena_a => byteenable,
clock0 => clk,
clock1 => clk,
clocken0 => module_input2,
clocken1 => module_input3,
data_a => writedata,
data_b => module_input4,
wren_a => module_input5,
wren_b => MonWr
);
module_input <= address(7 DOWNTO 0);
module_input1 <= MonAReg(9 DOWNTO 2);
module_input2 <= std_logic'('1');
module_input3 <= std_logic'('1');
module_input4 <= internal_MonDReg(31 DOWNTO 0);
module_input5 <= ((chipselect AND write) AND debugaccess) AND NOT address(8);
cfgdout <= A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("000"))), std_logic_vector'("00000000000010000100000000100000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("001"))), std_logic_vector'("00000000000000000001010000010100"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("010"))), std_logic_vector'("00000000000001000000000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("011"))), std_logic_vector'("00000000000000000000000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("100"))), std_logic_vector'("00100000000000000000000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("101"))), std_logic_vector'("00000000000010000100000000000000"), A_WE_StdLogicVector(((MonAReg(4 DOWNTO 2) = std_logic_vector'("110"))), std_logic_vector'("00000000000000000000000000000000"), std_logic_vector'("00000000000000000000000000000000"))))))));
--vhdl renameroo for output signals
MonDReg <= internal_MonDReg;
--vhdl renameroo for output signals
oci_ram_readdata <= internal_oci_ram_readdata;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_avalon_reg is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_go : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_reg_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal ocireg_ers : OUT STD_LOGIC;
signal ocireg_mrs : OUT STD_LOGIC;
signal take_action_ocireg : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_avalon_reg;
architecture europa of Video_System_CPU_nios2_avalon_reg is
signal internal_oci_ienable1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_oci_single_step_mode1 : STD_LOGIC;
signal internal_take_action_ocireg : STD_LOGIC;
signal oci_reg_00_addressed : STD_LOGIC;
signal oci_reg_01_addressed : STD_LOGIC;
signal ocireg_sstep : STD_LOGIC;
signal take_action_oci_intr_mask_reg : STD_LOGIC;
signal write_strobe : STD_LOGIC;
begin
oci_reg_00_addressed <= to_std_logic((address = std_logic_vector'("100000000")));
oci_reg_01_addressed <= to_std_logic((address = std_logic_vector'("100000001")));
write_strobe <= (chipselect AND write) AND debugaccess;
internal_take_action_ocireg <= write_strobe AND oci_reg_00_addressed;
take_action_oci_intr_mask_reg <= write_strobe AND oci_reg_01_addressed;
ocireg_ers <= writedata(1);
ocireg_mrs <= writedata(0);
ocireg_sstep <= writedata(3);
oci_reg_readdata <= A_WE_StdLogicVector((std_logic'(oci_reg_00_addressed) = '1'), Std_Logic_Vector'(std_logic_vector'("0000000000000000000000000000") & A_ToStdLogicVector(internal_oci_single_step_mode1) & A_ToStdLogicVector(monitor_go) & A_ToStdLogicVector(monitor_ready) & A_ToStdLogicVector(monitor_error)), A_WE_StdLogicVector((std_logic'(oci_reg_01_addressed) = '1'), internal_oci_ienable1, std_logic_vector'("00000000000000000000000000000000")));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_oci_single_step_mode1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(internal_take_action_ocireg) = '1' then
internal_oci_single_step_mode1 <= ocireg_sstep;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_oci_ienable1 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(take_action_oci_intr_mask_reg) = '1' then
internal_oci_ienable1 <= writedata OR NOT (std_logic_vector'("00000000000000000000000000000000"));
end if;
end if;
end process;
--vhdl renameroo for output signals
oci_ienable <= internal_oci_ienable1;
--vhdl renameroo for output signals
oci_single_step_mode <= internal_oci_single_step_mode1;
--vhdl renameroo for output signals
take_action_ocireg <= internal_take_action_ocireg;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_break is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal dbrk_goto0 : IN STD_LOGIC;
signal dbrk_goto1 : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_break_a : IN STD_LOGIC;
signal take_action_break_b : IN STD_LOGIC;
signal take_action_break_c : IN STD_LOGIC;
signal take_no_action_break_a : IN STD_LOGIC;
signal take_no_action_break_b : IN STD_LOGIC;
signal take_no_action_break_c : IN STD_LOGIC;
signal xbrk_goto0 : IN STD_LOGIC;
signal xbrk_goto1 : IN STD_LOGIC;
-- outputs:
signal break_readreg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : OUT STD_LOGIC;
signal dbrk_hit1_latch : OUT STD_LOGIC;
signal dbrk_hit2_latch : OUT STD_LOGIC;
signal dbrk_hit3_latch : OUT STD_LOGIC;
signal trigbrktype : OUT STD_LOGIC;
signal trigger_state_0 : OUT STD_LOGIC;
signal trigger_state_1 : OUT STD_LOGIC;
signal xbrk_ctrl0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_break;
architecture europa of Video_System_CPU_nios2_oci_break is
signal break_a_wpr : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal break_a_wpr_high_bits : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal break_a_wpr_low_bits : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal break_b_rr : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal break_c_rr : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dbrk0_high_value : STD_LOGIC;
signal dbrk0_low_value : STD_LOGIC;
signal dbrk1_high_value : STD_LOGIC;
signal dbrk1_low_value : STD_LOGIC;
signal dbrk2_high_value : STD_LOGIC;
signal dbrk2_low_value : STD_LOGIC;
signal dbrk3_high_value : STD_LOGIC;
signal dbrk3_low_value : STD_LOGIC;
signal internal_trigger_state_0 : STD_LOGIC;
signal internal_trigger_state_1 : STD_LOGIC;
signal take_action_any_break : STD_LOGIC;
signal trigger_state : STD_LOGIC;
signal xbrk0_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal xbrk1_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal xbrk2_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal xbrk3_value : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of break_readreg : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of trigbrktype : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl0 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl1 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl2 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of xbrk_ctrl3 : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
begin
break_a_wpr <= jdo(35 DOWNTO 32);
break_a_wpr_high_bits <= break_a_wpr(3 DOWNTO 2);
break_a_wpr_low_bits <= break_a_wpr(1 DOWNTO 0);
break_b_rr <= jdo(33 DOWNTO 32);
break_c_rr <= jdo(33 DOWNTO 32);
take_action_any_break <= (take_action_break_a OR take_action_break_b) OR take_action_break_c;
process (clk, jrst_n)
begin
if jrst_n = '0' then
xbrk_ctrl0 <= std_logic_vector'("00000000");
xbrk_ctrl1 <= std_logic_vector'("00000000");
xbrk_ctrl2 <= std_logic_vector'("00000000");
xbrk_ctrl3 <= std_logic_vector'("00000000");
trigbrktype <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(take_action_any_break) = '1' then
trigbrktype <= std_logic'('0');
elsif std_logic'(dbrk_break) = '1' then
trigbrktype <= std_logic'('1');
end if;
if std_logic'(take_action_break_b) = '1' then
if ((break_b_rr = std_logic_vector'("00"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000001"))) then
xbrk_ctrl0(0) <= jdo(27);
xbrk_ctrl0(1) <= jdo(28);
xbrk_ctrl0(2) <= jdo(29);
xbrk_ctrl0(3) <= jdo(30);
xbrk_ctrl0(4) <= jdo(21);
xbrk_ctrl0(5) <= jdo(20);
xbrk_ctrl0(6) <= jdo(19);
xbrk_ctrl0(7) <= jdo(18);
end if;
if ((break_b_rr = std_logic_vector'("01"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000010"))) then
xbrk_ctrl1(0) <= jdo(27);
xbrk_ctrl1(1) <= jdo(28);
xbrk_ctrl1(2) <= jdo(29);
xbrk_ctrl1(3) <= jdo(30);
xbrk_ctrl1(4) <= jdo(21);
xbrk_ctrl1(5) <= jdo(20);
xbrk_ctrl1(6) <= jdo(19);
xbrk_ctrl1(7) <= jdo(18);
end if;
if ((break_b_rr = std_logic_vector'("10"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000011"))) then
xbrk_ctrl2(0) <= jdo(27);
xbrk_ctrl2(1) <= jdo(28);
xbrk_ctrl2(2) <= jdo(29);
xbrk_ctrl2(3) <= jdo(30);
xbrk_ctrl2(4) <= jdo(21);
xbrk_ctrl2(5) <= jdo(20);
xbrk_ctrl2(6) <= jdo(19);
xbrk_ctrl2(7) <= jdo(18);
end if;
if ((break_b_rr = std_logic_vector'("11"))) AND ((std_logic_vector'("00000000000000000000000000000000")>=std_logic_vector'("00000000000000000000000000000100"))) then
xbrk_ctrl3(0) <= jdo(27);
xbrk_ctrl3(1) <= jdo(28);
xbrk_ctrl3(2) <= jdo(29);
xbrk_ctrl3(3) <= jdo(30);
xbrk_ctrl3(4) <= jdo(21);
xbrk_ctrl3(5) <= jdo(20);
xbrk_ctrl3(6) <= jdo(19);
xbrk_ctrl3(7) <= jdo(18);
end if;
end if;
end if;
end process;
dbrk_hit0_latch <= std_logic'('0');
dbrk0_low_value <= std_logic'('0');
dbrk0_high_value <= std_logic'('0');
dbrk_hit1_latch <= std_logic'('0');
dbrk1_low_value <= std_logic'('0');
dbrk1_high_value <= std_logic'('0');
dbrk_hit2_latch <= std_logic'('0');
dbrk2_low_value <= std_logic'('0');
dbrk2_high_value <= std_logic'('0');
dbrk_hit3_latch <= std_logic'('0');
dbrk3_low_value <= std_logic'('0');
dbrk3_high_value <= std_logic'('0');
xbrk0_value <= std_logic_vector'("00000000000000000000000000000000");
xbrk1_value <= std_logic_vector'("00000000000000000000000000000000");
xbrk2_value <= std_logic_vector'("00000000000000000000000000000000");
xbrk3_value <= std_logic_vector'("00000000000000000000000000000000");
process (clk, jrst_n)
begin
if jrst_n = '0' then
break_readreg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(take_action_any_break) = '1' then
break_readreg <= jdo(31 DOWNTO 0);
elsif std_logic'(take_no_action_break_a) = '1' then
case break_a_wpr_high_bits is
when std_logic_vector'("00") =>
case break_a_wpr_low_bits is -- synthesis full_case
when std_logic_vector'("00") =>
break_readreg <= xbrk0_value;
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= xbrk1_value;
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
break_readreg <= xbrk2_value;
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
break_readreg <= xbrk3_value;
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_low_bits
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= std_logic_vector'("00000000000000000000000000000000");
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
case break_a_wpr_low_bits is -- synthesis full_case
when std_logic_vector'("00") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk0_low_value));
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk1_low_value));
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk2_low_value));
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk3_low_value));
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_low_bits
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
case break_a_wpr_low_bits is -- synthesis full_case
when std_logic_vector'("00") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk0_high_value));
-- when std_logic_vector'("00")
when std_logic_vector'("01") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk1_high_value));
-- when std_logic_vector'("01")
when std_logic_vector'("10") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk2_high_value));
-- when std_logic_vector'("10")
when std_logic_vector'("11") =>
break_readreg <= std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dbrk3_high_value));
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_low_bits
-- when std_logic_vector'("11")
when others =>
-- when others
end case; -- break_a_wpr_high_bits
elsif std_logic'(take_no_action_break_b) = '1' then
break_readreg <= jdo(31 DOWNTO 0);
elsif std_logic'(take_no_action_break_c) = '1' then
break_readreg <= jdo(31 DOWNTO 0);
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
trigger_state <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((internal_trigger_state_1 AND ((xbrk_goto0 OR dbrk_goto0)))) = '1' then
trigger_state <= std_logic'('0');
elsif std_logic'((internal_trigger_state_0 AND ((xbrk_goto1 OR dbrk_goto1)))) = '1' then
trigger_state <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
internal_trigger_state_0 <= NOT trigger_state;
internal_trigger_state_1 <= trigger_state;
--vhdl renameroo for output signals
trigger_state_0 <= internal_trigger_state_0;
--vhdl renameroo for output signals
trigger_state_1 <= internal_trigger_state_1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_xbrk is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal trigger_state_0 : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal xbrk_ctrl0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- outputs:
signal xbrk_break : OUT STD_LOGIC;
signal xbrk_goto0 : OUT STD_LOGIC;
signal xbrk_goto1 : OUT STD_LOGIC;
signal xbrk_traceoff : OUT STD_LOGIC;
signal xbrk_traceon : OUT STD_LOGIC;
signal xbrk_trigout : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_xbrk;
architecture europa of Video_System_CPU_nios2_oci_xbrk is
signal D_cpu_addr_en : STD_LOGIC;
signal E_cpu_addr_en : STD_LOGIC;
signal E_xbrk_goto0 : STD_LOGIC;
signal E_xbrk_goto1 : STD_LOGIC;
signal E_xbrk_traceoff : STD_LOGIC;
signal E_xbrk_traceon : STD_LOGIC;
signal E_xbrk_trigout : STD_LOGIC;
signal cpu_i_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal xbrk0_armed : STD_LOGIC;
signal xbrk0_break_hit : STD_LOGIC;
signal xbrk0_goto0_hit : STD_LOGIC;
signal xbrk0_goto1_hit : STD_LOGIC;
signal xbrk0_toff_hit : STD_LOGIC;
signal xbrk0_ton_hit : STD_LOGIC;
signal xbrk0_tout_hit : STD_LOGIC;
signal xbrk1_armed : STD_LOGIC;
signal xbrk1_break_hit : STD_LOGIC;
signal xbrk1_goto0_hit : STD_LOGIC;
signal xbrk1_goto1_hit : STD_LOGIC;
signal xbrk1_toff_hit : STD_LOGIC;
signal xbrk1_ton_hit : STD_LOGIC;
signal xbrk1_tout_hit : STD_LOGIC;
signal xbrk2_armed : STD_LOGIC;
signal xbrk2_break_hit : STD_LOGIC;
signal xbrk2_goto0_hit : STD_LOGIC;
signal xbrk2_goto1_hit : STD_LOGIC;
signal xbrk2_toff_hit : STD_LOGIC;
signal xbrk2_ton_hit : STD_LOGIC;
signal xbrk2_tout_hit : STD_LOGIC;
signal xbrk3_armed : STD_LOGIC;
signal xbrk3_break_hit : STD_LOGIC;
signal xbrk3_goto0_hit : STD_LOGIC;
signal xbrk3_goto1_hit : STD_LOGIC;
signal xbrk3_toff_hit : STD_LOGIC;
signal xbrk3_ton_hit : STD_LOGIC;
signal xbrk3_tout_hit : STD_LOGIC;
signal xbrk_break_hit : STD_LOGIC;
signal xbrk_goto0_hit : STD_LOGIC;
signal xbrk_goto1_hit : STD_LOGIC;
signal xbrk_toff_hit : STD_LOGIC;
signal xbrk_ton_hit : STD_LOGIC;
signal xbrk_tout_hit : STD_LOGIC;
begin
cpu_i_address <= F_pc & std_logic_vector'("00");
D_cpu_addr_en <= D_valid;
E_cpu_addr_en <= E_valid;
xbrk0_break_hit <= std_logic'('0');
xbrk0_ton_hit <= std_logic'('0');
xbrk0_toff_hit <= std_logic'('0');
xbrk0_tout_hit <= std_logic'('0');
xbrk0_goto0_hit <= std_logic'('0');
xbrk0_goto1_hit <= std_logic'('0');
xbrk1_break_hit <= std_logic'('0');
xbrk1_ton_hit <= std_logic'('0');
xbrk1_toff_hit <= std_logic'('0');
xbrk1_tout_hit <= std_logic'('0');
xbrk1_goto0_hit <= std_logic'('0');
xbrk1_goto1_hit <= std_logic'('0');
xbrk2_break_hit <= std_logic'('0');
xbrk2_ton_hit <= std_logic'('0');
xbrk2_toff_hit <= std_logic'('0');
xbrk2_tout_hit <= std_logic'('0');
xbrk2_goto0_hit <= std_logic'('0');
xbrk2_goto1_hit <= std_logic'('0');
xbrk3_break_hit <= std_logic'('0');
xbrk3_ton_hit <= std_logic'('0');
xbrk3_toff_hit <= std_logic'('0');
xbrk3_tout_hit <= std_logic'('0');
xbrk3_goto0_hit <= std_logic'('0');
xbrk3_goto1_hit <= std_logic'('0');
xbrk_break_hit <= (((xbrk0_break_hit) OR (xbrk1_break_hit)) OR (xbrk2_break_hit)) OR (xbrk3_break_hit);
xbrk_ton_hit <= (((xbrk0_ton_hit) OR (xbrk1_ton_hit)) OR (xbrk2_ton_hit)) OR (xbrk3_ton_hit);
xbrk_toff_hit <= (((xbrk0_toff_hit) OR (xbrk1_toff_hit)) OR (xbrk2_toff_hit)) OR (xbrk3_toff_hit);
xbrk_tout_hit <= (((xbrk0_tout_hit) OR (xbrk1_tout_hit)) OR (xbrk2_tout_hit)) OR (xbrk3_tout_hit);
xbrk_goto0_hit <= (((xbrk0_goto0_hit) OR (xbrk1_goto0_hit)) OR (xbrk2_goto0_hit)) OR (xbrk3_goto0_hit);
xbrk_goto1_hit <= (((xbrk0_goto1_hit) OR (xbrk1_goto1_hit)) OR (xbrk2_goto1_hit)) OR (xbrk3_goto1_hit);
process (clk, reset_n)
begin
if reset_n = '0' then
xbrk_break <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
xbrk_break <= xbrk_break_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_traceon <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_traceon <= xbrk_ton_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_traceoff <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_traceoff <= xbrk_toff_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_trigout <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_trigout <= xbrk_tout_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_goto0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_goto0 <= xbrk_goto0_hit;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_xbrk_goto1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(E_cpu_addr_en) = '1' then
E_xbrk_goto1 <= xbrk_goto1_hit;
end if;
end if;
end process;
xbrk_traceon <= std_logic'('0');
xbrk_traceoff <= std_logic'('0');
xbrk_trigout <= std_logic'('0');
xbrk_goto0 <= std_logic'('0');
xbrk_goto1 <= std_logic'('0');
xbrk0_armed <= ((xbrk_ctrl0(4) AND trigger_state_0)) OR ((xbrk_ctrl0(5) AND trigger_state_1));
xbrk1_armed <= ((xbrk_ctrl1(4) AND trigger_state_0)) OR ((xbrk_ctrl1(5) AND trigger_state_1));
xbrk2_armed <= ((xbrk_ctrl2(4) AND trigger_state_0)) OR ((xbrk_ctrl2(5) AND trigger_state_1));
xbrk3_armed <= ((xbrk_ctrl3(4) AND trigger_state_0)) OR ((xbrk_ctrl3(5) AND trigger_state_1));
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_dbrk is
port (
-- inputs:
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal cpu_d_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : OUT STD_LOGIC;
signal cpu_d_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : OUT STD_LOGIC;
signal cpu_d_write : OUT STD_LOGIC;
signal cpu_d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_break : OUT STD_LOGIC;
signal dbrk_goto0 : OUT STD_LOGIC;
signal dbrk_goto1 : OUT STD_LOGIC;
signal dbrk_traceme : OUT STD_LOGIC;
signal dbrk_traceoff : OUT STD_LOGIC;
signal dbrk_traceon : OUT STD_LOGIC;
signal dbrk_trigout : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_dbrk;
architecture europa of Video_System_CPU_nios2_oci_dbrk is
signal dbrk0_armed : STD_LOGIC;
signal dbrk0_break_pulse : STD_LOGIC;
signal dbrk0_goto0 : STD_LOGIC;
signal dbrk0_goto1 : STD_LOGIC;
signal dbrk0_traceme : STD_LOGIC;
signal dbrk0_traceoff : STD_LOGIC;
signal dbrk0_traceon : STD_LOGIC;
signal dbrk0_trigout : STD_LOGIC;
signal dbrk1_armed : STD_LOGIC;
signal dbrk1_break_pulse : STD_LOGIC;
signal dbrk1_goto0 : STD_LOGIC;
signal dbrk1_goto1 : STD_LOGIC;
signal dbrk1_traceme : STD_LOGIC;
signal dbrk1_traceoff : STD_LOGIC;
signal dbrk1_traceon : STD_LOGIC;
signal dbrk1_trigout : STD_LOGIC;
signal dbrk2_armed : STD_LOGIC;
signal dbrk2_break_pulse : STD_LOGIC;
signal dbrk2_goto0 : STD_LOGIC;
signal dbrk2_goto1 : STD_LOGIC;
signal dbrk2_traceme : STD_LOGIC;
signal dbrk2_traceoff : STD_LOGIC;
signal dbrk2_traceon : STD_LOGIC;
signal dbrk2_trigout : STD_LOGIC;
signal dbrk3_armed : STD_LOGIC;
signal dbrk3_break_pulse : STD_LOGIC;
signal dbrk3_goto0 : STD_LOGIC;
signal dbrk3_goto1 : STD_LOGIC;
signal dbrk3_traceme : STD_LOGIC;
signal dbrk3_traceoff : STD_LOGIC;
signal dbrk3_traceon : STD_LOGIC;
signal dbrk3_trigout : STD_LOGIC;
signal dbrk_break_pulse : STD_LOGIC;
signal dbrk_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_cpu_d_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_cpu_d_write : STD_LOGIC;
signal internal_cpu_d_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_dbrk_break : STD_LOGIC;
begin
cpu_d_address <= d_address;
internal_cpu_d_readdata <= av_ld_data_aligned_filtered;
cpu_d_read <= d_read;
internal_cpu_d_writedata <= E_st_data;
internal_cpu_d_write <= d_write;
cpu_d_wait <= d_waitrequest;
dbrk_data <= A_WE_StdLogicVector((std_logic'(internal_cpu_d_write) = '1'), internal_cpu_d_writedata, internal_cpu_d_readdata);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_dbrk_break <= std_logic'('0');
elsif clk'event and clk = '1' then
internal_dbrk_break <= A_WE_StdLogic((std_logic'(internal_dbrk_break) = '1'), NOT debugack, dbrk_break_pulse);
end if;
end process;
dbrk0_armed <= std_logic'('0');
dbrk0_trigout <= std_logic'('0');
dbrk0_break_pulse <= std_logic'('0');
dbrk0_traceoff <= std_logic'('0');
dbrk0_traceon <= std_logic'('0');
dbrk0_traceme <= std_logic'('0');
dbrk0_goto0 <= std_logic'('0');
dbrk0_goto1 <= std_logic'('0');
dbrk1_armed <= std_logic'('0');
dbrk1_trigout <= std_logic'('0');
dbrk1_break_pulse <= std_logic'('0');
dbrk1_traceoff <= std_logic'('0');
dbrk1_traceon <= std_logic'('0');
dbrk1_traceme <= std_logic'('0');
dbrk1_goto0 <= std_logic'('0');
dbrk1_goto1 <= std_logic'('0');
dbrk2_armed <= std_logic'('0');
dbrk2_trigout <= std_logic'('0');
dbrk2_break_pulse <= std_logic'('0');
dbrk2_traceoff <= std_logic'('0');
dbrk2_traceon <= std_logic'('0');
dbrk2_traceme <= std_logic'('0');
dbrk2_goto0 <= std_logic'('0');
dbrk2_goto1 <= std_logic'('0');
dbrk3_armed <= std_logic'('0');
dbrk3_trigout <= std_logic'('0');
dbrk3_break_pulse <= std_logic'('0');
dbrk3_traceoff <= std_logic'('0');
dbrk3_traceon <= std_logic'('0');
dbrk3_traceme <= std_logic'('0');
dbrk3_goto0 <= std_logic'('0');
dbrk3_goto1 <= std_logic'('0');
process (clk, reset_n)
begin
if reset_n = '0' then
dbrk_trigout <= std_logic'('0');
dbrk_break_pulse <= std_logic'('0');
dbrk_traceoff <= std_logic'('0');
dbrk_traceon <= std_logic'('0');
dbrk_traceme <= std_logic'('0');
dbrk_goto0 <= std_logic'('0');
dbrk_goto1 <= std_logic'('0');
elsif clk'event and clk = '1' then
dbrk_trigout <= ((dbrk0_trigout OR dbrk1_trigout) OR dbrk2_trigout) OR dbrk3_trigout;
dbrk_break_pulse <= ((dbrk0_break_pulse OR dbrk1_break_pulse) OR dbrk2_break_pulse) OR dbrk3_break_pulse;
dbrk_traceoff <= ((dbrk0_traceoff OR dbrk1_traceoff) OR dbrk2_traceoff) OR dbrk3_traceoff;
dbrk_traceon <= ((dbrk0_traceon OR dbrk1_traceon) OR dbrk2_traceon) OR dbrk3_traceon;
dbrk_traceme <= ((dbrk0_traceme OR dbrk1_traceme) OR dbrk2_traceme) OR dbrk3_traceme;
dbrk_goto0 <= ((dbrk0_goto0 OR dbrk1_goto0) OR dbrk2_goto0) OR dbrk3_goto0;
dbrk_goto1 <= ((dbrk0_goto1 OR dbrk1_goto1) OR dbrk2_goto1) OR dbrk3_goto1;
end if;
end process;
--vhdl renameroo for output signals
cpu_d_readdata <= internal_cpu_d_readdata;
--vhdl renameroo for output signals
cpu_d_write <= internal_cpu_d_write;
--vhdl renameroo for output signals
cpu_d_writedata <= internal_cpu_d_writedata;
--vhdl renameroo for output signals
dbrk_break <= internal_dbrk_break;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_itrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal trc_enb : IN STD_LOGIC;
signal xbrk_traceoff : IN STD_LOGIC;
signal xbrk_traceon : IN STD_LOGIC;
signal xbrk_wrap_traceoff : IN STD_LOGIC;
-- outputs:
signal dct_buffer : OUT STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal itm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_ctrl : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal trc_on : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_itrace;
architecture europa of Video_System_CPU_nios2_oci_itrace is
signal curr_pid : STD_LOGIC;
signal dct_code : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dct_is_taken : STD_LOGIC;
signal excaddr : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal instr_retired : STD_LOGIC;
signal internal_dct_buffer : STD_LOGIC_VECTOR (29 DOWNTO 0);
signal internal_dct_count : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_trc_ctrl : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal internal_trc_on : STD_LOGIC;
signal is_advanced_exception : STD_LOGIC;
signal is_cond_dct : STD_LOGIC;
signal is_dct : STD_LOGIC;
signal is_exception_no_break : STD_LOGIC;
signal is_fast_tlb_miss_exception : STD_LOGIC;
signal is_idct : STD_LOGIC;
signal not_in_debug_mode : STD_LOGIC;
signal pending_curr_pid : STD_LOGIC;
signal pending_excaddr : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pending_exctype : STD_LOGIC;
signal pending_frametype : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pending_prev_pid : STD_LOGIC;
signal prev_pid : STD_LOGIC;
signal prev_pid_valid : STD_LOGIC;
signal record_dct_outcome_in_sync : STD_LOGIC;
signal record_itrace : STD_LOGIC;
signal retired_pcb : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal snapped_curr_pid : STD_LOGIC;
signal snapped_pid : STD_LOGIC;
signal snapped_prev_pid : STD_LOGIC;
signal sync_code : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sync_interval : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal sync_pending : STD_LOGIC;
signal sync_timer : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal sync_timer_next : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_clear : STD_LOGIC;
signal trc_ctrl_reg : STD_LOGIC_VECTOR (10 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of curr_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of dct_buffer : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of dct_count : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of itm : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_curr_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_exctype : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_frametype : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of pending_prev_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of prev_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of prev_pid_valid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of snapped_curr_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of snapped_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of snapped_prev_pid : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of sync_timer : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of trc_clear : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of trc_ctrl_reg : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
begin
is_cond_dct <= std_logic'('0');
is_dct <= std_logic'('0');
dct_is_taken <= std_logic'('0');
is_idct <= std_logic'('0');
retired_pcb <= std_logic_vector'("00000000000000000000000000000000");
not_in_debug_mode <= std_logic'('0');
instr_retired <= std_logic'('0');
is_advanced_exception <= std_logic'('0');
is_exception_no_break <= std_logic'('0');
is_fast_tlb_miss_exception <= std_logic'('0');
curr_pid <= std_logic'('0');
excaddr <= std_logic_vector'("00000000000000000000000000000000");
sync_code <= internal_trc_ctrl(3 DOWNTO 2);
sync_interval <= Std_Logic_Vector'(A_ToStdLogicVector((sync_code(1) AND sync_code(0))) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector((sync_code(1) AND NOT sync_code(0))) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector((NOT sync_code(1) AND sync_code(0))) & std_logic_vector'("00"));
sync_pending <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (sync_timer)) = std_logic_vector'("00000000000000000000000000000000")));
record_dct_outcome_in_sync <= dct_is_taken AND sync_pending;
sync_timer_next <= A_EXT (A_WE_StdLogicVector((std_logic'(sync_pending) = '1'), (std_logic_vector'("00000000000000000000000000") & (sync_timer)), (((std_logic_vector'("00000000000000000000000000") & (sync_timer)) - std_logic_vector'("000000000000000000000000000000001")))), 7);
record_itrace <= internal_trc_on AND internal_trc_ctrl(4);
dct_code <= Std_Logic_Vector'(A_ToStdLogicVector(is_cond_dct) & A_ToStdLogicVector(dct_is_taken));
process (clk, jrst_n)
begin
if jrst_n = '0' then
trc_clear <= std_logic'('0');
elsif clk'event and clk = '1' then
trc_clear <= (NOT trc_enb AND take_action_tracectrl) AND jdo(4);
end if;
end process;
process (clk, jrst_n)
begin
if jrst_n = '0' then
itm <= std_logic_vector'("000000000000000000000000000000000000");
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= std_logic_vector'("0000000");
pending_frametype <= std_logic_vector'("0000");
pending_exctype <= std_logic'('0');
pending_excaddr <= std_logic_vector'("00000000000000000000000000000000");
prev_pid <= std_logic'('0');
prev_pid_valid <= std_logic'('0');
snapped_pid <= std_logic'('0');
snapped_curr_pid <= std_logic'('0');
snapped_prev_pid <= std_logic'('0');
pending_curr_pid <= std_logic'('0');
pending_prev_pid <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((trc_clear OR ((NOT(or_reduce(std_logic_vector'("00000000000000000000000000000000"))) AND NOT(or_reduce(std_logic_vector'("00000000000000000000000000000000"))))))) = '1' then
itm <= std_logic_vector'("000000000000000000000000000000000000");
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= std_logic_vector'("0000000");
pending_frametype <= std_logic_vector'("0000");
pending_exctype <= std_logic'('0');
pending_excaddr <= std_logic_vector'("00000000000000000000000000000000");
prev_pid <= std_logic'('0');
prev_pid_valid <= std_logic'('0');
snapped_pid <= std_logic'('0');
snapped_curr_pid <= std_logic'('0');
snapped_prev_pid <= std_logic'('0');
pending_curr_pid <= std_logic'('0');
pending_prev_pid <= std_logic'('0');
else
if std_logic'(NOT(prev_pid_valid)) = '1' then
prev_pid <= curr_pid;
prev_pid_valid <= std_logic'('1');
end if;
if std_logic'(((to_std_logic(((std_logic'(curr_pid) /= std_logic'(prev_pid)))) AND prev_pid_valid) AND NOT(snapped_pid))) = '1' then
snapped_pid <= std_logic'('1');
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= std_logic'('1');
end if;
if std_logic'((instr_retired OR is_advanced_exception)) = '1' then
if std_logic'(NOT record_itrace) = '1' then
pending_frametype <= std_logic_vector'("1010");
elsif std_logic'(is_exception_no_break) = '1' then
pending_frametype <= std_logic_vector'("0010");
pending_excaddr <= excaddr;
if std_logic'(is_fast_tlb_miss_exception) = '1' then
pending_exctype <= std_logic'('1');
else
pending_exctype <= std_logic'('0');
end if;
elsif std_logic'(is_idct) = '1' then
pending_frametype <= std_logic_vector'("1001");
elsif std_logic'(record_dct_outcome_in_sync) = '1' then
pending_frametype <= std_logic_vector'("1000");
elsif std_logic'((NOT(is_dct) AND snapped_pid)) = '1' then
pending_frametype <= std_logic_vector'("0011");
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= std_logic'('0');
else
pending_frametype <= std_logic_vector'("0000");
end if;
if std_logic'((to_std_logic((((std_logic_vector'("0000000000000000000000000000") & (internal_dct_count)) /= std_logic_vector'("00000000000000000000000000000000")))) AND (((((NOT record_itrace OR is_exception_no_break) OR is_idct) OR record_dct_outcome_in_sync) OR ((NOT(is_dct) AND snapped_pid)))))) = '1' then
itm <= Std_Logic_Vector'(std_logic_vector'("0001") & internal_dct_buffer & std_logic_vector'("00"));
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= sync_timer_next;
else
if std_logic'((((record_itrace AND ((is_dct AND to_std_logic(((internal_dct_count /= std_logic_vector'("1111"))))))) AND NOT record_dct_outcome_in_sync) AND NOT is_advanced_exception)) = '1' then
internal_dct_buffer <= dct_code & internal_dct_buffer(29 DOWNTO 2);
internal_dct_count <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (internal_dct_count)) + std_logic_vector'("000000000000000000000000000000001")), 4);
end if;
if std_logic'((record_itrace AND to_std_logic(((pending_frametype = std_logic_vector'("0010")))))) = '1' then
itm <= Std_Logic_Vector'(std_logic_vector'("0010") & pending_excaddr(31 DOWNTO 1) & A_ToStdLogicVector(pending_exctype));
elsif std_logic'((record_itrace AND to_std_logic((((((pending_frametype = std_logic_vector'("1000"))) OR ((pending_frametype = std_logic_vector'("1010")))) OR ((pending_frametype = std_logic_vector'("1001")))))))) = '1' then
itm <= pending_frametype & retired_pcb;
sync_timer <= sync_interval;
if ((((std_logic_vector'("00000000000000000000000000000000") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(to_std_logic(((((pending_frametype = std_logic_vector'("1000"))) OR ((pending_frametype = std_logic_vector'("1010")))))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(snapped_pid))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(prev_pid_valid))))) /= std_logic_vector'("00000000000000000000000000000000") then
snapped_pid <= std_logic'('1');
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end if;
elsif ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(record_itrace))) AND std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(to_std_logic(((pending_frametype = std_logic_vector'("0011"))))))))) /= std_logic_vector'("00000000000000000000000000000000") then
itm <= std_logic_vector'("00000000000000000000000000") & (Std_Logic_Vector'(std_logic_vector'("0011") & std_logic_vector'("00") & A_ToStdLogicVector(pending_prev_pid) & std_logic_vector'("00") & A_ToStdLogicVector(pending_curr_pid)));
elsif std_logic'((record_itrace AND is_dct)) = '1' then
if internal_dct_count = std_logic_vector'("1111") then
itm <= Std_Logic_Vector'(std_logic_vector'("0001") & dct_code & internal_dct_buffer);
internal_dct_buffer <= std_logic_vector'("000000000000000000000000000000");
internal_dct_count <= std_logic_vector'("0000");
sync_timer <= sync_timer_next;
else
itm <= std_logic_vector'("000000000000000000000000000000000000");
end if;
else
itm <= Std_Logic_Vector'(std_logic_vector'("0000") & std_logic_vector'("00000000000000000000000000000000"));
end if;
end if;
else
itm <= Std_Logic_Vector'(std_logic_vector'("0000") & std_logic_vector'("00000000000000000000000000000000"));
end if;
end if;
end if;
end process;
process (clk, jrst_n)
begin
if jrst_n = '0' then
trc_ctrl_reg(0) <= std_logic'('0');
trc_ctrl_reg(1) <= std_logic'('0');
trc_ctrl_reg(3 DOWNTO 2) <= std_logic_vector'("00");
trc_ctrl_reg(4) <= std_logic'('0');
trc_ctrl_reg(7 DOWNTO 5) <= std_logic_vector'("000");
trc_ctrl_reg(8) <= std_logic'('0');
trc_ctrl_reg(9) <= std_logic'('0');
trc_ctrl_reg(10) <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(take_action_tracectrl) = '1' then
trc_ctrl_reg(0) <= jdo(5);
trc_ctrl_reg(1) <= jdo(6);
trc_ctrl_reg(3 DOWNTO 2) <= jdo(8 DOWNTO 7);
trc_ctrl_reg(4) <= jdo(9);
trc_ctrl_reg(9) <= jdo(14);
trc_ctrl_reg(10) <= jdo(2);
if true then
trc_ctrl_reg(7 DOWNTO 5) <= jdo(12 DOWNTO 10);
end if;
if ((std_logic_vector'("00000000000000000000000000000000") AND std_logic_vector'("00000000000000000000000000000000"))) /= std_logic_vector'("00000000000000000000000000000000") then
trc_ctrl_reg(8) <= jdo(13);
end if;
elsif std_logic'(xbrk_wrap_traceoff) = '1' then
trc_ctrl_reg(1) <= std_logic'('0');
trc_ctrl_reg(0) <= std_logic'('0');
elsif std_logic'((dbrk_traceoff OR xbrk_traceoff)) = '1' then
trc_ctrl_reg(1) <= std_logic'('0');
elsif std_logic'((trc_ctrl_reg(0) AND ((dbrk_traceon OR xbrk_traceon)))) = '1' then
trc_ctrl_reg(1) <= std_logic'('1');
end if;
end if;
end process;
internal_trc_ctrl <= A_EXT (A_WE_StdLogicVector((std_logic'(((or_reduce(std_logic_vector'("00000000000000000000000000000000")) OR or_reduce(std_logic_vector'("00000000000000000000000000000000"))))) = '1'), (std_logic_vector'("000000000000000") & (Std_Logic_Vector'(std_logic_vector'("000000") & trc_ctrl_reg))), std_logic_vector'("00000000000000000000000000000000")), 16);
internal_trc_on <= internal_trc_ctrl(1) AND ((internal_trc_ctrl(9) OR not_in_debug_mode));
--vhdl renameroo for output signals
dct_buffer <= internal_dct_buffer;
--vhdl renameroo for output signals
dct_count <= internal_dct_count;
--vhdl renameroo for output signals
trc_ctrl <= internal_trc_ctrl;
--vhdl renameroo for output signals
trc_on <= internal_trc_on;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_td_mode is
port (
-- inputs:
signal ctrl : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-- outputs:
signal td_mode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_td_mode;
architecture europa of Video_System_CPU_nios2_oci_td_mode is
signal ctrl_bits_for_mux : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
ctrl_bits_for_mux <= ctrl(7 DOWNTO 5);
process (ctrl_bits_for_mux)
begin
case ctrl_bits_for_mux is
when std_logic_vector'("000") =>
td_mode <= std_logic_vector'("0000");
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
td_mode <= std_logic_vector'("1000");
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
td_mode <= std_logic_vector'("0100");
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
td_mode <= std_logic_vector'("1100");
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
td_mode <= std_logic_vector'("0010");
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
td_mode <= std_logic_vector'("1010");
-- when std_logic_vector'("101")
when std_logic_vector'("110") =>
td_mode <= std_logic_vector'("0101");
-- when std_logic_vector'("110")
when std_logic_vector'("111") =>
td_mode <= std_logic_vector'("1111");
-- when std_logic_vector'("111")
when others =>
-- when others
end case; -- ctrl_bits_for_mux
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_dtrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal cpu_d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : IN STD_LOGIC;
signal cpu_d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : IN STD_LOGIC;
signal cpu_d_write : IN STD_LOGIC;
signal cpu_d_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal atm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal dtm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_dtrace;
architecture europa of Video_System_CPU_nios2_oci_dtrace is
component Video_System_CPU_nios2_oci_td_mode is
port (
-- inputs:
signal ctrl : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-- outputs:
signal td_mode : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_td_mode;
signal cpu_d_address_0_padded : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_readdata_0_padded : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_writedata_0_padded : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input6 : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal record_load_addr : STD_LOGIC;
signal record_load_data : STD_LOGIC;
signal record_store_addr : STD_LOGIC;
signal record_store_data : STD_LOGIC;
signal td_mode_trc_ctrl : STD_LOGIC_VECTOR (3 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of atm : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of dtm : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
begin
cpu_d_writedata_0_padded <= cpu_d_writedata OR std_logic_vector'("00000000000000000000000000000000");
cpu_d_readdata_0_padded <= cpu_d_readdata OR std_logic_vector'("00000000000000000000000000000000");
cpu_d_address_0_padded <= (std_logic_vector'("000000000000") & (cpu_d_address)) OR std_logic_vector'("00000000000000000000000000000000");
--Video_System_CPU_nios2_oci_trc_ctrl_td_mode, which is an e_instance
Video_System_CPU_nios2_oci_trc_ctrl_td_mode : Video_System_CPU_nios2_oci_td_mode
port map(
td_mode => td_mode_trc_ctrl,
ctrl => module_input6
);
module_input6 <= trc_ctrl(8 DOWNTO 0);
(record_load_addr, record_store_addr, record_load_data, record_store_data) <= td_mode_trc_ctrl;
process (clk, jrst_n)
begin
if jrst_n = '0' then
atm <= std_logic_vector'("000000000000000000000000000000000000");
dtm <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if (std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000") then
if std_logic'(((cpu_d_write AND NOT cpu_d_wait) AND record_store_addr)) = '1' then
atm <= Std_Logic_Vector'(std_logic_vector'("0101") & cpu_d_address_0_padded);
elsif std_logic'(((cpu_d_read AND NOT cpu_d_wait) AND record_load_addr)) = '1' then
atm <= Std_Logic_Vector'(std_logic_vector'("0100") & cpu_d_address_0_padded);
else
atm <= Std_Logic_Vector'(std_logic_vector'("0000") & cpu_d_address_0_padded);
end if;
if std_logic'(((cpu_d_write AND NOT cpu_d_wait) AND record_store_data)) = '1' then
dtm <= Std_Logic_Vector'(std_logic_vector'("0111") & cpu_d_writedata_0_padded);
elsif std_logic'(((cpu_d_read AND NOT cpu_d_wait) AND record_load_data)) = '1' then
dtm <= Std_Logic_Vector'(std_logic_vector'("0110") & cpu_d_readdata_0_padded);
else
dtm <= Std_Logic_Vector'(std_logic_vector'("0000") & cpu_d_readdata_0_padded);
end if;
else
atm <= std_logic_vector'("000000000000000000000000000000000000");
dtm <= std_logic_vector'("000000000000000000000000000000000000");
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_compute_tm_count is
port (
-- inputs:
signal atm_valid : IN STD_LOGIC;
signal dtm_valid : IN STD_LOGIC;
signal itm_valid : IN STD_LOGIC;
-- outputs:
signal compute_tm_count : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_compute_tm_count;
architecture europa of Video_System_CPU_nios2_oci_compute_tm_count is
signal switch_for_mux : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
switch_for_mux <= Std_Logic_Vector'(A_ToStdLogicVector(itm_valid) & A_ToStdLogicVector(atm_valid) & A_ToStdLogicVector(dtm_valid));
process (switch_for_mux)
begin
case switch_for_mux is
when std_logic_vector'("000") =>
compute_tm_count <= std_logic_vector'("00");
-- when std_logic_vector'("000")
when std_logic_vector'("001") =>
compute_tm_count <= std_logic_vector'("01");
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
compute_tm_count <= std_logic_vector'("01");
-- when std_logic_vector'("010")
when std_logic_vector'("011") =>
compute_tm_count <= std_logic_vector'("10");
-- when std_logic_vector'("011")
when std_logic_vector'("100") =>
compute_tm_count <= std_logic_vector'("01");
-- when std_logic_vector'("100")
when std_logic_vector'("101") =>
compute_tm_count <= std_logic_vector'("10");
-- when std_logic_vector'("101")
when std_logic_vector'("110") =>
compute_tm_count <= std_logic_vector'("10");
-- when std_logic_vector'("110")
when std_logic_vector'("111") =>
compute_tm_count <= std_logic_vector'("11");
-- when std_logic_vector'("111")
when others =>
-- when others
end case; -- switch_for_mux
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_fifowp_inc is
port (
-- inputs:
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifowp_inc : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_fifowp_inc;
architecture europa of Video_System_CPU_nios2_oci_fifowp_inc is
begin
process (free2, free3, tm_count)
begin
if std_logic'((free3 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count)) = std_logic_vector'("00000000000000000000000000000011")))))) = '1' then
fifowp_inc <= std_logic_vector'("0011");
elsif std_logic'((free2 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000010")))))) = '1' then
fifowp_inc <= std_logic_vector'("0010");
elsif (std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000001") then
fifowp_inc <= std_logic_vector'("0001");
else
fifowp_inc <= std_logic_vector'("0000");
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_fifocount_inc is
port (
-- inputs:
signal empty : IN STD_LOGIC;
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifocount_inc : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_fifocount_inc;
architecture europa of Video_System_CPU_nios2_oci_fifocount_inc is
begin
process (empty, free2, free3, tm_count)
begin
if std_logic'(empty) = '1' then
fifocount_inc <= std_logic_vector'("000") & (tm_count(1 DOWNTO 0));
elsif std_logic'((free3 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count)) = std_logic_vector'("00000000000000000000000000000011")))))) = '1' then
fifocount_inc <= std_logic_vector'("00010");
elsif std_logic'((free2 AND to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000010")))))) = '1' then
fifocount_inc <= std_logic_vector'("00001");
elsif (std_logic_vector'("000000000000000000000000000000") & (tm_count))>=std_logic_vector'("00000000000000000000000000000001") then
fifocount_inc <= std_logic_vector'("00000");
else
fifocount_inc <= A_REP(std_logic'('1'), 5);
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_fifo is
port (
-- inputs:
signal atm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_traceme : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal dct_buffer : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dtm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal itm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal trc_on : IN STD_LOGIC;
-- outputs:
signal tw : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_fifo;
architecture europa of Video_System_CPU_nios2_oci_fifo is
component Video_System_CPU_nios2_oci_compute_tm_count is
port (
-- inputs:
signal atm_valid : IN STD_LOGIC;
signal dtm_valid : IN STD_LOGIC;
signal itm_valid : IN STD_LOGIC;
-- outputs:
signal compute_tm_count : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_compute_tm_count;
component Video_System_CPU_nios2_oci_fifowp_inc is
port (
-- inputs:
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifowp_inc : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_fifowp_inc;
component Video_System_CPU_nios2_oci_fifocount_inc is
port (
-- inputs:
signal empty : IN STD_LOGIC;
signal free2 : IN STD_LOGIC;
signal free3 : IN STD_LOGIC;
signal tm_count : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- outputs:
signal fifocount_inc : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_fifocount_inc;
component Video_System_CPU_oci_test_bench is
port (
-- inputs:
signal dct_buffer : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC
);
end component Video_System_CPU_oci_test_bench;
signal atm_valid : STD_LOGIC;
signal compute_tm_count_tm_count : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dtm_valid : STD_LOGIC;
signal empty : STD_LOGIC;
signal fifo_0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_0_enable : STD_LOGIC;
signal fifo_0_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_10 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_10_enable : STD_LOGIC;
signal fifo_10_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_11 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_11_enable : STD_LOGIC;
signal fifo_11_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_12 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_12_enable : STD_LOGIC;
signal fifo_12_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_13 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_13_enable : STD_LOGIC;
signal fifo_13_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_14 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_14_enable : STD_LOGIC;
signal fifo_14_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_15 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_15_enable : STD_LOGIC;
signal fifo_15_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_1_enable : STD_LOGIC;
signal fifo_1_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_2_enable : STD_LOGIC;
signal fifo_2_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_3 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_3_enable : STD_LOGIC;
signal fifo_3_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_4_enable : STD_LOGIC;
signal fifo_4_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_5 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_5_enable : STD_LOGIC;
signal fifo_5_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_6_enable : STD_LOGIC;
signal fifo_6_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_7 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_7_enable : STD_LOGIC;
signal fifo_7_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_8 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_8_enable : STD_LOGIC;
signal fifo_8_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_9 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_9_enable : STD_LOGIC;
signal fifo_9_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifo_read_mux : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fifocount : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal fifocount_inc_fifocount : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal fifohead : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal fiforp : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp2 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifowp_inc_fifowp : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal free2 : STD_LOGIC;
signal free3 : STD_LOGIC;
signal itm_valid : STD_LOGIC;
signal ovf_pending : STD_LOGIC;
signal ovr_pending_atm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal ovr_pending_dtm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tm_count : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal tm_count_ge1 : STD_LOGIC;
signal tm_count_ge2 : STD_LOGIC;
signal tm_count_ge3 : STD_LOGIC;
signal trc_this : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of fifocount : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of fiforp : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of fifowp : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of ovf_pending : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
begin
trc_this <= (trc_on OR ((dbrk_traceon AND NOT dbrk_traceoff))) OR dbrk_traceme;
itm_valid <= or_reduce(itm(35 DOWNTO 32));
atm_valid <= or_reduce(atm(35 DOWNTO 32)) AND trc_this;
dtm_valid <= or_reduce(dtm(35 DOWNTO 32)) AND trc_this;
free2 <= NOT fifocount(4);
free3 <= NOT fifocount(4) AND nand_reduce(fifocount(3 DOWNTO 0));
empty <= NOT or_reduce(fifocount);
fifowp1 <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (fifowp)) + std_logic_vector'("000000000000000000000000000000001")), 4);
fifowp2 <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (fifowp)) + std_logic_vector'("000000000000000000000000000000010")), 4);
--Video_System_CPU_nios2_oci_compute_tm_count_tm_count, which is an e_instance
Video_System_CPU_nios2_oci_compute_tm_count_tm_count : Video_System_CPU_nios2_oci_compute_tm_count
port map(
compute_tm_count => compute_tm_count_tm_count,
atm_valid => atm_valid,
dtm_valid => dtm_valid,
itm_valid => itm_valid
);
tm_count <= compute_tm_count_tm_count;
--Video_System_CPU_nios2_oci_fifowp_inc_fifowp, which is an e_instance
Video_System_CPU_nios2_oci_fifowp_inc_fifowp : Video_System_CPU_nios2_oci_fifowp_inc
port map(
fifowp_inc => fifowp_inc_fifowp,
free2 => free2,
free3 => free3,
tm_count => tm_count
);
--Video_System_CPU_nios2_oci_fifocount_inc_fifocount, which is an e_instance
Video_System_CPU_nios2_oci_fifocount_inc_fifocount : Video_System_CPU_nios2_oci_fifocount_inc
port map(
fifocount_inc => fifocount_inc_fifocount,
empty => empty,
free2 => free2,
free3 => free3,
tm_count => tm_count
);
--the_Video_System_CPU_oci_test_bench, which is an e_instance
the_Video_System_CPU_oci_test_bench : Video_System_CPU_oci_test_bench
port map(
dct_buffer => dct_buffer,
dct_count => dct_count,
test_ending => test_ending,
test_has_ended => test_has_ended
);
process (clk, jrst_n)
begin
if jrst_n = '0' then
fiforp <= std_logic_vector'("0000");
fifowp <= std_logic_vector'("0000");
fifocount <= std_logic_vector'("00000");
ovf_pending <= std_logic'('1');
elsif clk'event and clk = '1' then
fifowp <= A_EXT (((std_logic_vector'("0") & (fifowp)) + (std_logic_vector'("0") & (fifowp_inc_fifowp))), 4);
fifocount <= A_EXT (((std_logic_vector'("0") & (fifocount)) + (std_logic_vector'("0") & (fifocount_inc_fifocount))), 5);
if std_logic'(NOT empty) = '1' then
fiforp <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (fiforp)) + std_logic_vector'("000000000000000000000000000000001")), 4);
end if;
if std_logic'(((NOT trc_this OR ((NOT free2 AND tm_count(1)))) OR ((NOT free3 AND (and_reduce(tm_count)))))) = '1' then
ovf_pending <= std_logic'('1');
elsif std_logic'((atm_valid OR dtm_valid)) = '1' then
ovf_pending <= std_logic'('0');
end if;
end if;
end process;
fifohead <= fifo_read_mux;
tw <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000")), ((A_WE_StdLogicVector((std_logic'(empty) = '1'), std_logic_vector'("0000"), fifohead(35 DOWNTO 32))) & fifohead(31 DOWNTO 0)), itm);
fifo_0_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0000"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0000"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_0 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_0_enable) = '1' then
fifo_0 <= fifo_0_mux;
end if;
end if;
end process;
fifo_0_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0000")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0000")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0000")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0000")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_1_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0001"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0001"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_1 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_1_enable) = '1' then
fifo_1 <= fifo_1_mux;
end if;
end if;
end process;
fifo_1_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0001")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0001")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0001")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0001")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_2_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0010"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0010"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_2 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_2_enable) = '1' then
fifo_2 <= fifo_2_mux;
end if;
end if;
end process;
fifo_2_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0010")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0010")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0010")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0010")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_3_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0011"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0011"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_3 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_3_enable) = '1' then
fifo_3 <= fifo_3_mux;
end if;
end if;
end process;
fifo_3_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0011")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0011")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0011")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0011")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_4_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0100"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0100"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_4 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_4_enable) = '1' then
fifo_4 <= fifo_4_mux;
end if;
end if;
end process;
fifo_4_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0100")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0100")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0100")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0100")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_5_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0101"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0101"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_5 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_5_enable) = '1' then
fifo_5 <= fifo_5_mux;
end if;
end if;
end process;
fifo_5_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0101")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0101")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0101")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0101")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_6_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0110"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0110"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_6 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_6_enable) = '1' then
fifo_6 <= fifo_6_mux;
end if;
end if;
end process;
fifo_6_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0110")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0110")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0110")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0110")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_7_enable <= (((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("0111"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("0111"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_7 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_7_enable) = '1' then
fifo_7 <= fifo_7_mux;
end if;
end if;
end process;
fifo_7_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("0111")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0111")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0111")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("0111")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_8_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1000"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1000"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_8 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_8_enable) = '1' then
fifo_8 <= fifo_8_mux;
end if;
end if;
end process;
fifo_8_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1000")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1000")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1000")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1000")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_9_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1001"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1001"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_9 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_9_enable) = '1' then
fifo_9 <= fifo_9_mux;
end if;
end if;
end process;
fifo_9_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1001")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1001")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1001")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1001")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_10_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1010"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1010"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_10 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_10_enable) = '1' then
fifo_10 <= fifo_10_mux;
end if;
end if;
end process;
fifo_10_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1010")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1010")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1010")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1010")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_11_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1011"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1011"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_11 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_11_enable) = '1' then
fifo_11 <= fifo_11_mux;
end if;
end if;
end process;
fifo_11_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1011")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1011")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1011")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1011")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_12_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1100"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1100"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_12 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_12_enable) = '1' then
fifo_12 <= fifo_12_mux;
end if;
end if;
end process;
fifo_12_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1100")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1100")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1100")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1100")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_13_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1101"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1101"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_13 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_13_enable) = '1' then
fifo_13 <= fifo_13_mux;
end if;
end if;
end process;
fifo_13_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1101")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1101")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1101")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1101")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_14_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1110"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1110"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_14 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_14_enable) = '1' then
fifo_14 <= fifo_14_mux;
end if;
end if;
end process;
fifo_14_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1110")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1110")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1110")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1110")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
fifo_15_enable <= (((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND tm_count_ge1)) OR (((free2 AND to_std_logic(((fifowp1 = std_logic_vector'("1111"))))) AND tm_count_ge2))) OR (((free3 AND to_std_logic(((fifowp2 = std_logic_vector'("1111"))))) AND tm_count_ge3));
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_15 <= std_logic_vector'("000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(fifo_15_enable) = '1' then
fifo_15 <= fifo_15_mux;
end if;
end if;
end process;
fifo_15_mux <= A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND itm_valid))) = '1'), itm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND atm_valid))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp = std_logic_vector'("1111")))) AND dtm_valid))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1111")))) AND (((free2 AND itm_valid) AND atm_valid))))) = '1'), ovr_pending_atm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1111")))) AND (((free2 AND itm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, A_WE_StdLogicVector((std_logic'(((to_std_logic(((fifowp1 = std_logic_vector'("1111")))) AND (((free2 AND atm_valid) AND dtm_valid))))) = '1'), ovr_pending_dtm, ovr_pending_dtm))))));
tm_count_ge1 <= or_reduce(tm_count);
tm_count_ge2 <= tm_count(1);
tm_count_ge3 <= and_reduce(tm_count);
ovr_pending_atm <= Std_Logic_Vector'(A_ToStdLogicVector(ovf_pending) & atm(34 DOWNTO 0));
ovr_pending_dtm <= Std_Logic_Vector'(A_ToStdLogicVector(ovf_pending) & dtm(34 DOWNTO 0));
fifo_read_mux <= A_WE_StdLogicVector(((fiforp = std_logic_vector'("0000"))), fifo_0, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0001"))), fifo_1, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0010"))), fifo_2, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0011"))), fifo_3, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0100"))), fifo_4, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0101"))), fifo_5, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0110"))), fifo_6, A_WE_StdLogicVector(((fiforp = std_logic_vector'("0111"))), fifo_7, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1000"))), fifo_8, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1001"))), fifo_9, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1010"))), fifo_10, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1011"))), fifo_11, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1100"))), fifo_12, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1101"))), fifo_13, A_WE_StdLogicVector(((fiforp = std_logic_vector'("1110"))), fifo_14, fifo_15)))))))))))))));
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_pib is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clkx2 : IN STD_LOGIC;
signal jrst_n : IN STD_LOGIC;
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tr_clk : OUT STD_LOGIC;
signal tr_data : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end entity Video_System_CPU_nios2_oci_pib;
architecture europa of Video_System_CPU_nios2_oci_pib is
signal phase : STD_LOGIC;
signal tr_clk_reg : STD_LOGIC;
signal tr_data_reg : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal x1 : STD_LOGIC;
signal x2 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of tr_clk_reg : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of tr_data_reg : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of x1 : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of x2 : signal is "SUPPRESS_DA_RULE_INTERNAL=R101";
begin
phase <= x1 XOR x2;
process (clk, jrst_n)
begin
if jrst_n = '0' then
x1 <= std_logic'('0');
elsif clk'event and clk = '1' then
x1 <= NOT x1;
end if;
end process;
process (clkx2, jrst_n)
begin
if jrst_n = '0' then
x2 <= std_logic'('0');
tr_clk_reg <= std_logic'('0');
tr_data_reg <= std_logic_vector'("000000000000000000");
elsif clkx2'event and clkx2 = '1' then
x2 <= x1;
tr_clk_reg <= NOT phase;
tr_data_reg <= A_WE_StdLogicVector((std_logic'(phase) = '1'), tw(17 DOWNTO 0), tw(35 DOWNTO 18));
end if;
end process;
tr_clk <= Vector_To_Std_Logic(A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000")), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(tr_clk_reg))), std_logic_vector'("00000000000000000000000000000000")));
tr_data <= A_EXT (A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000")) /= std_logic_vector'("00000000000000000000000000000000")), (std_logic_vector'("00000000000000") & (tr_data_reg)), std_logic_vector'("00000000000000000000000000000000")), 18);
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.all;
entity Video_System_CPU_traceram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end entity Video_System_CPU_traceram_lpm_dram_bdp_component_module;
architecture europa of Video_System_CPU_traceram_lpm_dram_bdp_component_module is
component altsyncram is
GENERIC (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
width_a : NATURAL;
width_b : NATURAL;
widthad_a : NATURAL;
widthad_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING
);
PORT (
signal q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal q_a : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal data_b : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
signal address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component altsyncram;
signal internal_q_a1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal internal_q_b1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
begin
the_altsyncram : altsyncram
generic map(
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
init_file => lpm_file,
intended_device_family => "CYCLONEII",
lpm_type => "altsyncram",
numwords_a => 128,
numwords_b => 128,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
ram_block_type => "AUTO",
read_during_write_mode_mixed_ports => "OLD_DATA",
width_a => 36,
width_b => 36,
widthad_a => 7,
widthad_b => 7,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE"
)
port map(
address_a => address_a,
address_b => address_b,
clock0 => clock0,
clock1 => clock1,
clocken0 => clocken0,
clocken1 => clocken1,
data_a => data_a,
data_b => data_b,
q_a => internal_q_a1,
q_b => internal_q_b1,
wren_a => wren_a,
wren_b => wren_b
);
--vhdl renameroo for output signals
q_a <= internal_q_a1;
--vhdl renameroo for output signals
q_b <= internal_q_b1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci_im is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal take_action_tracemem_a : IN STD_LOGIC;
signal take_action_tracemem_b : IN STD_LOGIC;
signal take_no_action_tracemem_a : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tracemem_on : OUT STD_LOGIC;
signal tracemem_trcdata : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : OUT STD_LOGIC;
signal trc_enb : OUT STD_LOGIC;
signal trc_im_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_wrap : OUT STD_LOGIC;
signal xbrk_wrap_traceoff : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci_im;
architecture europa of Video_System_CPU_nios2_oci_im is
component Video_System_CPU_traceram_lpm_dram_bdp_component_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal clock0 : IN STD_LOGIC;
signal clock1 : IN STD_LOGIC;
signal clocken0 : IN STD_LOGIC;
signal clocken1 : IN STD_LOGIC;
signal data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal data_b : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal wren_a : IN STD_LOGIC;
signal wren_b : IN STD_LOGIC;
-- outputs:
signal q_a : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component Video_System_CPU_traceram_lpm_dram_bdp_component_module;
signal internal_trc_enb : STD_LOGIC;
signal internal_trc_im_addr : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal internal_trc_wrap : STD_LOGIC;
signal module_input10 : STD_LOGIC;
signal module_input7 : STD_LOGIC;
signal module_input8 : STD_LOGIC;
signal module_input9 : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_im_data : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_jtag_addr : STD_LOGIC_VECTOR (16 DOWNTO 0);
signal trc_jtag_data : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_on_chip : STD_LOGIC;
signal tw_valid : STD_LOGIC;
signal unused_bdpram_port_q_a : STD_LOGIC_VECTOR (35 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of trc_im_addr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
attribute ALTERA_ATTRIBUTE of trc_jtag_addr : signal is "SUPPRESS_DA_RULE_INTERNAL=D101";
attribute ALTERA_ATTRIBUTE of trc_wrap : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103,R101""";
constant Video_System_CPU_traceram_lpm_dram_bdp_component_lpm_file : string := "";
begin
trc_im_data <= tw;
process (clk, jrst_n)
begin
if jrst_n = '0' then
internal_trc_im_addr <= std_logic_vector'("0000000");
internal_trc_wrap <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(NOT(or_reduce(std_logic_vector'("00000000000000000000000000000000")))) = '1' then
internal_trc_im_addr <= std_logic_vector'("0000000");
internal_trc_wrap <= std_logic'('0');
elsif std_logic'((take_action_tracectrl AND ((jdo(4) OR jdo(3))))) = '1' then
if std_logic'(jdo(4)) = '1' then
internal_trc_im_addr <= std_logic_vector'("0000000");
end if;
if std_logic'(jdo(3)) = '1' then
internal_trc_wrap <= std_logic'('0');
end if;
elsif std_logic'(((internal_trc_enb AND trc_on_chip) AND tw_valid)) = '1' then
internal_trc_im_addr <= A_EXT (((std_logic_vector'("00000000000000000000000000") & (internal_trc_im_addr)) + std_logic_vector'("000000000000000000000000000000001")), 7);
if std_logic'(and_reduce(internal_trc_im_addr)) = '1' then
internal_trc_wrap <= std_logic'('1');
end if;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
trc_jtag_addr <= std_logic_vector'("00000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(((take_action_tracemem_a OR take_no_action_tracemem_a) OR take_action_tracemem_b)) = '1' then
trc_jtag_addr <= A_EXT (A_WE_StdLogicVector((std_logic'(take_action_tracemem_a) = '1'), (std_logic_vector'("0000000000000000") & (jdo(35 DOWNTO 19))), ((std_logic_vector'("0000000000000000") & (trc_jtag_addr)) + std_logic_vector'("000000000000000000000000000000001"))), 17);
end if;
end if;
end process;
internal_trc_enb <= trc_ctrl(0);
trc_on_chip <= NOT trc_ctrl(8);
tw_valid <= or_reduce(trc_im_data(35 DOWNTO 32));
xbrk_wrap_traceoff <= trc_ctrl(10) AND internal_trc_wrap;
tracemem_trcdata <= A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000000"))) /= std_logic_vector'("00000000000000000000000000000000")), trc_jtag_data, std_logic_vector'("000000000000000000000000000000000000"));
tracemem_tw <= internal_trc_wrap;
tracemem_on <= internal_trc_enb;
--Video_System_CPU_traceram_lpm_dram_bdp_component, which is an nios_tdp_ram
Video_System_CPU_traceram_lpm_dram_bdp_component : Video_System_CPU_traceram_lpm_dram_bdp_component_module
generic map(
lpm_file => Video_System_CPU_traceram_lpm_dram_bdp_component_lpm_file
)
port map(
q_a => unused_bdpram_port_q_a,
q_b => trc_jtag_data,
address_a => internal_trc_im_addr,
address_b => trc_jtag_addr (6 DOWNTO 0),
clock0 => clk,
clock1 => clk,
clocken0 => module_input7,
clocken1 => module_input8,
data_a => trc_im_data,
data_b => module_input9,
wren_a => module_input10,
wren_b => take_action_tracemem_b
);
module_input7 <= std_logic'('1');
module_input8 <= std_logic'('1');
module_input9 <= jdo(36 DOWNTO 1);
module_input10 <= tw_valid AND internal_trc_enb;
--vhdl renameroo for output signals
trc_enb <= internal_trc_enb;
--vhdl renameroo for output signals
trc_im_addr <= internal_trc_im_addr;
--vhdl renameroo for output signals
trc_wrap <= internal_trc_wrap;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_performance_monitors is
end entity Video_System_CPU_nios2_performance_monitors;
architecture europa of Video_System_CPU_nios2_performance_monitors is
begin
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_nios2_oci is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal resetrequest : OUT STD_LOGIC
);
end entity Video_System_CPU_nios2_oci;
architecture europa of Video_System_CPU_nios2_oci is
component Video_System_CPU_nios2_oci_debug is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal debugreq : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal ocireg_ers : IN STD_LOGIC;
signal ocireg_mrs : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal st_ready_test_idle : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocireg : IN STD_LOGIC;
signal xbrk_break : IN STD_LOGIC;
-- outputs:
signal debugack : OUT STD_LOGIC;
signal monitor_error : OUT STD_LOGIC;
signal monitor_go : OUT STD_LOGIC;
signal monitor_ready : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal resetlatch : OUT STD_LOGIC;
signal resetrequest : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_debug;
component Video_System_CPU_nios2_ocimem is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal resetrequest : IN STD_LOGIC;
signal take_action_ocimem_a : IN STD_LOGIC;
signal take_action_ocimem_b : IN STD_LOGIC;
signal take_no_action_ocimem_a : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal MonDReg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_ram_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_nios2_ocimem;
component Video_System_CPU_nios2_avalon_reg is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_go : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_reg_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal ocireg_ers : OUT STD_LOGIC;
signal ocireg_mrs : OUT STD_LOGIC;
signal take_action_ocireg : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_avalon_reg;
component Video_System_CPU_nios2_oci_break is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_break : IN STD_LOGIC;
signal dbrk_goto0 : IN STD_LOGIC;
signal dbrk_goto1 : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_break_a : IN STD_LOGIC;
signal take_action_break_b : IN STD_LOGIC;
signal take_action_break_c : IN STD_LOGIC;
signal take_no_action_break_a : IN STD_LOGIC;
signal take_no_action_break_b : IN STD_LOGIC;
signal take_no_action_break_c : IN STD_LOGIC;
signal xbrk_goto0 : IN STD_LOGIC;
signal xbrk_goto1 : IN STD_LOGIC;
-- outputs:
signal break_readreg : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_hit0_latch : OUT STD_LOGIC;
signal dbrk_hit1_latch : OUT STD_LOGIC;
signal dbrk_hit2_latch : OUT STD_LOGIC;
signal dbrk_hit3_latch : OUT STD_LOGIC;
signal trigbrktype : OUT STD_LOGIC;
signal trigger_state_0 : OUT STD_LOGIC;
signal trigger_state_1 : OUT STD_LOGIC;
signal xbrk_ctrl0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_break;
component Video_System_CPU_nios2_oci_xbrk is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal trigger_state_0 : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
signal xbrk_ctrl0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- outputs:
signal xbrk_break : OUT STD_LOGIC;
signal xbrk_goto0 : OUT STD_LOGIC;
signal xbrk_goto1 : OUT STD_LOGIC;
signal xbrk_traceoff : OUT STD_LOGIC;
signal xbrk_traceon : OUT STD_LOGIC;
signal xbrk_trigout : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_xbrk;
component Video_System_CPU_nios2_oci_dbrk is
port (
-- inputs:
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal cpu_d_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : OUT STD_LOGIC;
signal cpu_d_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : OUT STD_LOGIC;
signal cpu_d_write : OUT STD_LOGIC;
signal cpu_d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_break : OUT STD_LOGIC;
signal dbrk_goto0 : OUT STD_LOGIC;
signal dbrk_goto1 : OUT STD_LOGIC;
signal dbrk_traceme : OUT STD_LOGIC;
signal dbrk_traceoff : OUT STD_LOGIC;
signal dbrk_traceon : OUT STD_LOGIC;
signal dbrk_trigout : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_dbrk;
component Video_System_CPU_nios2_oci_itrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal trc_enb : IN STD_LOGIC;
signal xbrk_traceoff : IN STD_LOGIC;
signal xbrk_traceon : IN STD_LOGIC;
signal xbrk_wrap_traceoff : IN STD_LOGIC;
-- outputs:
signal dct_buffer : OUT STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal itm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal trc_ctrl : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal trc_on : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_itrace;
component Video_System_CPU_nios2_oci_dtrace is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal cpu_d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : IN STD_LOGIC;
signal cpu_d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : IN STD_LOGIC;
signal cpu_d_write : IN STD_LOGIC;
signal cpu_d_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal atm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal dtm : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_dtrace;
component Video_System_CPU_nios2_oci_fifo is
port (
-- inputs:
signal atm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_traceme : IN STD_LOGIC;
signal dbrk_traceoff : IN STD_LOGIC;
signal dbrk_traceon : IN STD_LOGIC;
signal dct_buffer : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dtm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal itm : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal trc_on : IN STD_LOGIC;
-- outputs:
signal tw : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_fifo;
component Video_System_CPU_nios2_oci_pib is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clkx2 : IN STD_LOGIC;
signal jrst_n : IN STD_LOGIC;
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tr_clk : OUT STD_LOGIC;
signal tr_data : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component Video_System_CPU_nios2_oci_pib;
component Video_System_CPU_nios2_oci_im is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal jdo : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal take_action_tracectrl : IN STD_LOGIC;
signal take_action_tracemem_a : IN STD_LOGIC;
signal take_action_tracemem_b : IN STD_LOGIC;
signal take_no_action_tracemem_a : IN STD_LOGIC;
signal trc_ctrl : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal tw : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
-- outputs:
signal tracemem_on : OUT STD_LOGIC;
signal tracemem_trcdata : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : OUT STD_LOGIC;
signal trc_enb : OUT STD_LOGIC;
signal trc_im_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_wrap : OUT STD_LOGIC;
signal xbrk_wrap_traceoff : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci_im;
component Video_System_CPU_nios2_performance_monitors is
end component Video_System_CPU_nios2_performance_monitors;
component Video_System_CPU_jtag_debug_module_wrapper is
port (
-- inputs:
signal MonDReg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal break_readreg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dbrk_hit0_latch : IN STD_LOGIC;
signal dbrk_hit1_latch : IN STD_LOGIC;
signal dbrk_hit2_latch : IN STD_LOGIC;
signal dbrk_hit3_latch : IN STD_LOGIC;
signal debugack : IN STD_LOGIC;
signal monitor_error : IN STD_LOGIC;
signal monitor_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal resetlatch : IN STD_LOGIC;
signal tracemem_on : IN STD_LOGIC;
signal tracemem_trcdata : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : IN STD_LOGIC;
signal trc_im_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : IN STD_LOGIC;
signal trc_wrap : IN STD_LOGIC;
signal trigbrktype : IN STD_LOGIC;
signal trigger_state_1 : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : OUT STD_LOGIC;
signal st_ready_test_idle : OUT STD_LOGIC;
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end component Video_System_CPU_jtag_debug_module_wrapper;
signal MonDReg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal atm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal break_readreg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clkx2 : STD_LOGIC;
signal cpu_d_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal cpu_d_read : STD_LOGIC;
signal cpu_d_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal cpu_d_wait : STD_LOGIC;
signal cpu_d_write : STD_LOGIC;
signal cpu_d_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbrk_break : STD_LOGIC;
signal dbrk_goto0 : STD_LOGIC;
signal dbrk_goto1 : STD_LOGIC;
signal dbrk_hit0_latch : STD_LOGIC;
signal dbrk_hit1_latch : STD_LOGIC;
signal dbrk_hit2_latch : STD_LOGIC;
signal dbrk_hit3_latch : STD_LOGIC;
signal dbrk_traceme : STD_LOGIC;
signal dbrk_traceoff : STD_LOGIC;
signal dbrk_traceon : STD_LOGIC;
signal dbrk_trigout : STD_LOGIC;
signal dct_buffer : STD_LOGIC_VECTOR (29 DOWNTO 0);
signal dct_count : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal debugack : STD_LOGIC;
signal debugreq : STD_LOGIC;
signal dtm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal dummy_sink : STD_LOGIC;
signal internal_oci_hbreak_req : STD_LOGIC;
signal internal_oci_ienable : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_oci_single_step_mode : STD_LOGIC;
signal internal_resetrequest : STD_LOGIC;
signal itm : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal jdo : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal jrst_n : STD_LOGIC;
signal monitor_error : STD_LOGIC;
signal monitor_go : STD_LOGIC;
signal monitor_ready : STD_LOGIC;
signal oci_ram_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_reg_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ocireg_ers : STD_LOGIC;
signal ocireg_mrs : STD_LOGIC;
signal resetlatch : STD_LOGIC;
signal st_ready_test_idle : STD_LOGIC;
signal take_action_break_a : STD_LOGIC;
signal take_action_break_b : STD_LOGIC;
signal take_action_break_c : STD_LOGIC;
signal take_action_ocimem_a : STD_LOGIC;
signal take_action_ocimem_b : STD_LOGIC;
signal take_action_ocireg : STD_LOGIC;
signal take_action_tracectrl : STD_LOGIC;
signal take_action_tracemem_a : STD_LOGIC;
signal take_action_tracemem_b : STD_LOGIC;
signal take_no_action_break_a : STD_LOGIC;
signal take_no_action_break_b : STD_LOGIC;
signal take_no_action_break_c : STD_LOGIC;
signal take_no_action_ocimem_a : STD_LOGIC;
signal take_no_action_tracemem_a : STD_LOGIC;
signal tr_clk : STD_LOGIC;
signal tr_data : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal tracemem_on : STD_LOGIC;
signal tracemem_trcdata : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tracemem_tw : STD_LOGIC;
signal trc_ctrl : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal trc_enb : STD_LOGIC;
signal trc_im_addr : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal trc_on : STD_LOGIC;
signal trc_wrap : STD_LOGIC;
signal trigbrktype : STD_LOGIC;
signal trigger_state_0 : STD_LOGIC;
signal trigger_state_1 : STD_LOGIC;
signal trigout : STD_LOGIC;
signal tw : STD_LOGIC_VECTOR (35 DOWNTO 0);
signal xbrk_break : STD_LOGIC;
signal xbrk_ctrl0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_ctrl3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal xbrk_goto0 : STD_LOGIC;
signal xbrk_goto1 : STD_LOGIC;
signal xbrk_traceoff : STD_LOGIC;
signal xbrk_traceon : STD_LOGIC;
signal xbrk_trigout : STD_LOGIC;
signal xbrk_wrap_traceoff : STD_LOGIC;
begin
--the_Video_System_CPU_nios2_oci_debug, which is an e_instance
the_Video_System_CPU_nios2_oci_debug : Video_System_CPU_nios2_oci_debug
port map(
debugack => debugack,
monitor_error => monitor_error,
monitor_go => monitor_go,
monitor_ready => monitor_ready,
oci_hbreak_req => internal_oci_hbreak_req,
resetlatch => resetlatch,
resetrequest => internal_resetrequest,
clk => clk,
dbrk_break => dbrk_break,
debugreq => debugreq,
hbreak_enabled => hbreak_enabled,
jdo => jdo,
jrst_n => jrst_n,
ocireg_ers => ocireg_ers,
ocireg_mrs => ocireg_mrs,
reset => reset,
st_ready_test_idle => st_ready_test_idle,
take_action_ocimem_a => take_action_ocimem_a,
take_action_ocireg => take_action_ocireg,
xbrk_break => xbrk_break
);
--the_Video_System_CPU_nios2_ocimem, which is an e_instance
the_Video_System_CPU_nios2_ocimem : Video_System_CPU_nios2_ocimem
port map(
MonDReg => MonDReg,
oci_ram_readdata => oci_ram_readdata,
address => address,
begintransfer => begintransfer,
byteenable => byteenable,
chipselect => chipselect,
clk => clk,
debugaccess => debugaccess,
jdo => jdo,
jrst_n => jrst_n,
resetrequest => internal_resetrequest,
take_action_ocimem_a => take_action_ocimem_a,
take_action_ocimem_b => take_action_ocimem_b,
take_no_action_ocimem_a => take_no_action_ocimem_a,
write => write,
writedata => writedata
);
--the_Video_System_CPU_nios2_avalon_reg, which is an e_instance
the_Video_System_CPU_nios2_avalon_reg : Video_System_CPU_nios2_avalon_reg
port map(
oci_ienable => internal_oci_ienable,
oci_reg_readdata => oci_reg_readdata,
oci_single_step_mode => internal_oci_single_step_mode,
ocireg_ers => ocireg_ers,
ocireg_mrs => ocireg_mrs,
take_action_ocireg => take_action_ocireg,
address => address,
chipselect => chipselect,
clk => clk,
debugaccess => debugaccess,
monitor_error => monitor_error,
monitor_go => monitor_go,
monitor_ready => monitor_ready,
reset_n => reset_n,
write => write,
writedata => writedata
);
--the_Video_System_CPU_nios2_oci_break, which is an e_instance
the_Video_System_CPU_nios2_oci_break : Video_System_CPU_nios2_oci_break
port map(
break_readreg => break_readreg,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
trigbrktype => trigbrktype,
trigger_state_0 => trigger_state_0,
trigger_state_1 => trigger_state_1,
xbrk_ctrl0 => xbrk_ctrl0,
xbrk_ctrl1 => xbrk_ctrl1,
xbrk_ctrl2 => xbrk_ctrl2,
xbrk_ctrl3 => xbrk_ctrl3,
clk => clk,
dbrk_break => dbrk_break,
dbrk_goto0 => dbrk_goto0,
dbrk_goto1 => dbrk_goto1,
jdo => jdo,
jrst_n => jrst_n,
reset_n => reset_n,
take_action_break_a => take_action_break_a,
take_action_break_b => take_action_break_b,
take_action_break_c => take_action_break_c,
take_no_action_break_a => take_no_action_break_a,
take_no_action_break_b => take_no_action_break_b,
take_no_action_break_c => take_no_action_break_c,
xbrk_goto0 => xbrk_goto0,
xbrk_goto1 => xbrk_goto1
);
--the_Video_System_CPU_nios2_oci_xbrk, which is an e_instance
the_Video_System_CPU_nios2_oci_xbrk : Video_System_CPU_nios2_oci_xbrk
port map(
xbrk_break => xbrk_break,
xbrk_goto0 => xbrk_goto0,
xbrk_goto1 => xbrk_goto1,
xbrk_traceoff => xbrk_traceoff,
xbrk_traceon => xbrk_traceon,
xbrk_trigout => xbrk_trigout,
D_valid => D_valid,
E_valid => E_valid,
F_pc => F_pc,
clk => clk,
reset_n => reset_n,
trigger_state_0 => trigger_state_0,
trigger_state_1 => trigger_state_1,
xbrk_ctrl0 => xbrk_ctrl0,
xbrk_ctrl1 => xbrk_ctrl1,
xbrk_ctrl2 => xbrk_ctrl2,
xbrk_ctrl3 => xbrk_ctrl3
);
--the_Video_System_CPU_nios2_oci_dbrk, which is an e_instance
the_Video_System_CPU_nios2_oci_dbrk : Video_System_CPU_nios2_oci_dbrk
port map(
cpu_d_address => cpu_d_address,
cpu_d_read => cpu_d_read,
cpu_d_readdata => cpu_d_readdata,
cpu_d_wait => cpu_d_wait,
cpu_d_write => cpu_d_write,
cpu_d_writedata => cpu_d_writedata,
dbrk_break => dbrk_break,
dbrk_goto0 => dbrk_goto0,
dbrk_goto1 => dbrk_goto1,
dbrk_traceme => dbrk_traceme,
dbrk_traceoff => dbrk_traceoff,
dbrk_traceon => dbrk_traceon,
dbrk_trigout => dbrk_trigout,
E_st_data => E_st_data,
av_ld_data_aligned_filtered => av_ld_data_aligned_filtered,
clk => clk,
d_address => d_address,
d_read => d_read,
d_waitrequest => d_waitrequest,
d_write => d_write,
debugack => debugack,
reset_n => reset_n
);
--the_Video_System_CPU_nios2_oci_itrace, which is an e_instance
the_Video_System_CPU_nios2_oci_itrace : Video_System_CPU_nios2_oci_itrace
port map(
dct_buffer => dct_buffer,
dct_count => dct_count,
itm => itm,
trc_ctrl => trc_ctrl,
trc_on => trc_on,
clk => clk,
dbrk_traceoff => dbrk_traceoff,
dbrk_traceon => dbrk_traceon,
jdo => jdo (15 DOWNTO 0),
jrst_n => jrst_n,
take_action_tracectrl => take_action_tracectrl,
trc_enb => trc_enb,
xbrk_traceoff => xbrk_traceoff,
xbrk_traceon => xbrk_traceon,
xbrk_wrap_traceoff => xbrk_wrap_traceoff
);
--the_Video_System_CPU_nios2_oci_dtrace, which is an e_instance
the_Video_System_CPU_nios2_oci_dtrace : Video_System_CPU_nios2_oci_dtrace
port map(
atm => atm,
dtm => dtm,
clk => clk,
cpu_d_address => cpu_d_address,
cpu_d_read => cpu_d_read,
cpu_d_readdata => cpu_d_readdata,
cpu_d_wait => cpu_d_wait,
cpu_d_write => cpu_d_write,
cpu_d_writedata => cpu_d_writedata,
jrst_n => jrst_n,
trc_ctrl => trc_ctrl
);
--the_Video_System_CPU_nios2_oci_fifo, which is an e_instance
the_Video_System_CPU_nios2_oci_fifo : Video_System_CPU_nios2_oci_fifo
port map(
tw => tw,
atm => atm,
clk => clk,
dbrk_traceme => dbrk_traceme,
dbrk_traceoff => dbrk_traceoff,
dbrk_traceon => dbrk_traceon,
dct_buffer => dct_buffer,
dct_count => dct_count,
dtm => dtm,
itm => itm,
jrst_n => jrst_n,
reset_n => reset_n,
test_ending => test_ending,
test_has_ended => test_has_ended,
trc_on => trc_on
);
--the_Video_System_CPU_nios2_oci_pib, which is an e_instance
the_Video_System_CPU_nios2_oci_pib : Video_System_CPU_nios2_oci_pib
port map(
tr_clk => tr_clk,
tr_data => tr_data,
clk => clk,
clkx2 => clkx2,
jrst_n => jrst_n,
tw => tw
);
--the_Video_System_CPU_nios2_oci_im, which is an e_instance
the_Video_System_CPU_nios2_oci_im : Video_System_CPU_nios2_oci_im
port map(
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_enb => trc_enb,
trc_im_addr => trc_im_addr,
trc_wrap => trc_wrap,
xbrk_wrap_traceoff => xbrk_wrap_traceoff,
clk => clk,
jdo => jdo,
jrst_n => jrst_n,
reset_n => reset_n,
take_action_tracectrl => take_action_tracectrl,
take_action_tracemem_a => take_action_tracemem_a,
take_action_tracemem_b => take_action_tracemem_b,
take_no_action_tracemem_a => take_no_action_tracemem_a,
trc_ctrl => trc_ctrl,
tw => tw
);
trigout <= dbrk_trigout OR xbrk_trigout;
readdata <= A_WE_StdLogicVector((std_logic'(address(8)) = '1'), oci_reg_readdata, oci_ram_readdata);
jtag_debug_module_debugaccess_to_roms <= debugack;
--the_Video_System_CPU_jtag_debug_module_wrapper, which is an e_instance
the_Video_System_CPU_jtag_debug_module_wrapper : Video_System_CPU_jtag_debug_module_wrapper
port map(
jdo => jdo,
jrst_n => jrst_n,
st_ready_test_idle => st_ready_test_idle,
take_action_break_a => take_action_break_a,
take_action_break_b => take_action_break_b,
take_action_break_c => take_action_break_c,
take_action_ocimem_a => take_action_ocimem_a,
take_action_ocimem_b => take_action_ocimem_b,
take_action_tracectrl => take_action_tracectrl,
take_action_tracemem_a => take_action_tracemem_a,
take_action_tracemem_b => take_action_tracemem_b,
take_no_action_break_a => take_no_action_break_a,
take_no_action_break_b => take_no_action_break_b,
take_no_action_break_c => take_no_action_break_c,
take_no_action_ocimem_a => take_no_action_ocimem_a,
take_no_action_tracemem_a => take_no_action_tracemem_a,
MonDReg => MonDReg,
break_readreg => break_readreg,
clk => clk,
dbrk_hit0_latch => dbrk_hit0_latch,
dbrk_hit1_latch => dbrk_hit1_latch,
dbrk_hit2_latch => dbrk_hit2_latch,
dbrk_hit3_latch => dbrk_hit3_latch,
debugack => debugack,
monitor_error => monitor_error,
monitor_ready => monitor_ready,
reset_n => reset_n,
resetlatch => resetlatch,
tracemem_on => tracemem_on,
tracemem_trcdata => tracemem_trcdata,
tracemem_tw => tracemem_tw,
trc_im_addr => trc_im_addr,
trc_on => trc_on,
trc_wrap => trc_wrap,
trigbrktype => trigbrktype,
trigger_state_1 => trigger_state_1
);
--dummy sink, which is an e_mux
dummy_sink <= Vector_To_Std_Logic(((((std_logic_vector'("00000000000000000") & (A_TOSTDLOGICVECTOR(tr_clk))) OR tr_data) OR (std_logic_vector'("00000000000000000") & (A_TOSTDLOGICVECTOR(trigout)))) OR (std_logic_vector'("00000000000000000") & (A_TOSTDLOGICVECTOR(debugack)))));
debugreq <= std_logic'('0');
clkx2 <= std_logic'('0');
--vhdl renameroo for output signals
oci_hbreak_req <= internal_oci_hbreak_req;
--vhdl renameroo for output signals
oci_ienable <= internal_oci_ienable;
--vhdl renameroo for output signals
oci_single_step_mode <= internal_oci_single_step_mode;
--vhdl renameroo for output signals
resetrequest <= internal_resetrequest;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d_irq : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_waitrequest : IN STD_LOGIC;
signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_waitrequest : IN STD_LOGIC;
signal jtag_debug_module_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal jtag_debug_module_begintransfer : IN STD_LOGIC;
signal jtag_debug_module_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal jtag_debug_module_debugaccess : IN STD_LOGIC;
signal jtag_debug_module_select : IN STD_LOGIC;
signal jtag_debug_module_write : IN STD_LOGIC;
signal jtag_debug_module_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : OUT STD_LOGIC;
signal d_write : OUT STD_LOGIC;
signal d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal i_read : OUT STD_LOGIC;
signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
signal jtag_debug_module_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal jtag_debug_module_resetrequest : OUT STD_LOGIC;
signal no_ci_readra : OUT STD_LOGIC
);
end entity Video_System_CPU;
architecture europa of Video_System_CPU is
component Video_System_CPU_test_bench is
port (
-- inputs:
signal D_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal D_iw_op : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_opx : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_valid : IN STD_LOGIC;
signal E_alu_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_mem_byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pcb : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_valid : IN STD_LOGIC;
signal R_ctrl_exception : IN STD_LOGIC;
signal R_ctrl_ld : IN STD_LOGIC;
signal R_ctrl_ld_non_io : IN STD_LOGIC;
signal R_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal R_wr_dst_reg : IN STD_LOGIC;
signal W_bstatus_reg : IN STD_LOGIC;
signal W_cmp_result : IN STD_LOGIC;
signal W_estatus_reg : IN STD_LOGIC;
signal W_ienable_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_mem_baddr : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal W_rf_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_status_reg : IN STD_LOGIC;
signal W_valid : IN STD_LOGIC;
signal W_vinst : IN STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_unfiltered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_write_nxt : IN STD_LOGIC;
signal i_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal i_read : IN STD_LOGIC;
signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal av_ld_data_aligned_filtered : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal d_write : OUT STD_LOGIC;
signal test_has_ended : OUT STD_LOGIC
);
end component Video_System_CPU_test_bench;
component Video_System_CPU_register_bank_a_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_register_bank_a_module;
component Video_System_CPU_register_bank_b_module is
generic (
lpm_file : STRING := "UNUSED"
);
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component Video_System_CPU_register_bank_b_module;
component Video_System_CPU_nios2_oci is
port (
-- inputs:
signal D_valid : IN STD_LOGIC;
signal E_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal F_pc : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal av_ld_data_aligned_filtered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_waitrequest : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal debugaccess : IN STD_LOGIC;
signal hbreak_enabled : IN STD_LOGIC;
signal reset : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal test_ending : IN STD_LOGIC;
signal test_has_ended : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
signal oci_hbreak_req : OUT STD_LOGIC;
signal oci_ienable : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal resetrequest : OUT STD_LOGIC
);
end component Video_System_CPU_nios2_oci;
signal D_compare_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_ctrl_alu_force_xor : STD_LOGIC;
signal D_ctrl_alu_signed_comparison : STD_LOGIC;
signal D_ctrl_alu_subtract : STD_LOGIC;
signal D_ctrl_b_is_dst : STD_LOGIC;
signal D_ctrl_br : STD_LOGIC;
signal D_ctrl_br_cmp : STD_LOGIC;
signal D_ctrl_br_uncond : STD_LOGIC;
signal D_ctrl_break : STD_LOGIC;
signal D_ctrl_crst : STD_LOGIC;
signal D_ctrl_custom : STD_LOGIC;
signal D_ctrl_custom_multi : STD_LOGIC;
signal D_ctrl_exception : STD_LOGIC;
signal D_ctrl_force_src2_zero : STD_LOGIC;
signal D_ctrl_hi_imm16 : STD_LOGIC;
signal D_ctrl_ignore_dst : STD_LOGIC;
signal D_ctrl_implicit_dst_eretaddr : STD_LOGIC;
signal D_ctrl_implicit_dst_retaddr : STD_LOGIC;
signal D_ctrl_jmp_direct : STD_LOGIC;
signal D_ctrl_jmp_indirect : STD_LOGIC;
signal D_ctrl_ld : STD_LOGIC;
signal D_ctrl_ld_io : STD_LOGIC;
signal D_ctrl_ld_non_io : STD_LOGIC;
signal D_ctrl_ld_signed : STD_LOGIC;
signal D_ctrl_logic : STD_LOGIC;
signal D_ctrl_rdctl_inst : STD_LOGIC;
signal D_ctrl_retaddr : STD_LOGIC;
signal D_ctrl_rot_right : STD_LOGIC;
signal D_ctrl_shift_logical : STD_LOGIC;
signal D_ctrl_shift_right_arith : STD_LOGIC;
signal D_ctrl_shift_rot : STD_LOGIC;
signal D_ctrl_shift_rot_right : STD_LOGIC;
signal D_ctrl_src2_choose_imm : STD_LOGIC;
signal D_ctrl_st : STD_LOGIC;
signal D_ctrl_uncond_cti_non_br : STD_LOGIC;
signal D_ctrl_unsigned_lo_imm16 : STD_LOGIC;
signal D_ctrl_wrctl_inst : STD_LOGIC;
signal D_dst_regnum : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_inst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal D_iw : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal D_iw_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_c : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_control_regnum : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal D_iw_custom_n : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal D_iw_custom_readra : STD_LOGIC;
signal D_iw_custom_readrb : STD_LOGIC;
signal D_iw_custom_writerc : STD_LOGIC;
signal D_iw_imm16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal D_iw_imm26 : STD_LOGIC_VECTOR (25 DOWNTO 0);
signal D_iw_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_memsz : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_iw_op : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_opx : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal D_iw_shift_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_iw_trap_break_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal D_jmp_direct_target_waddr : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal D_logic_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_logic_op_raw : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal D_mem16 : STD_LOGIC;
signal D_mem32 : STD_LOGIC;
signal D_mem8 : STD_LOGIC;
signal D_op_add : STD_LOGIC;
signal D_op_addi : STD_LOGIC;
signal D_op_and : STD_LOGIC;
signal D_op_andhi : STD_LOGIC;
signal D_op_andi : STD_LOGIC;
signal D_op_beq : STD_LOGIC;
signal D_op_bge : STD_LOGIC;
signal D_op_bgeu : STD_LOGIC;
signal D_op_blt : STD_LOGIC;
signal D_op_bltu : STD_LOGIC;
signal D_op_bne : STD_LOGIC;
signal D_op_br : STD_LOGIC;
signal D_op_break : STD_LOGIC;
signal D_op_bret : STD_LOGIC;
signal D_op_call : STD_LOGIC;
signal D_op_callr : STD_LOGIC;
signal D_op_cmpeq : STD_LOGIC;
signal D_op_cmpeqi : STD_LOGIC;
signal D_op_cmpge : STD_LOGIC;
signal D_op_cmpgei : STD_LOGIC;
signal D_op_cmpgeu : STD_LOGIC;
signal D_op_cmpgeui : STD_LOGIC;
signal D_op_cmplt : STD_LOGIC;
signal D_op_cmplti : STD_LOGIC;
signal D_op_cmpltu : STD_LOGIC;
signal D_op_cmpltui : STD_LOGIC;
signal D_op_cmpne : STD_LOGIC;
signal D_op_cmpnei : STD_LOGIC;
signal D_op_crst : STD_LOGIC;
signal D_op_custom : STD_LOGIC;
signal D_op_div : STD_LOGIC;
signal D_op_divu : STD_LOGIC;
signal D_op_eret : STD_LOGIC;
signal D_op_flushd : STD_LOGIC;
signal D_op_flushda : STD_LOGIC;
signal D_op_flushi : STD_LOGIC;
signal D_op_flushp : STD_LOGIC;
signal D_op_hbreak : STD_LOGIC;
signal D_op_initd : STD_LOGIC;
signal D_op_initda : STD_LOGIC;
signal D_op_initi : STD_LOGIC;
signal D_op_intr : STD_LOGIC;
signal D_op_jmp : STD_LOGIC;
signal D_op_jmpi : STD_LOGIC;
signal D_op_ldb : STD_LOGIC;
signal D_op_ldbio : STD_LOGIC;
signal D_op_ldbu : STD_LOGIC;
signal D_op_ldbuio : STD_LOGIC;
signal D_op_ldh : STD_LOGIC;
signal D_op_ldhio : STD_LOGIC;
signal D_op_ldhu : STD_LOGIC;
signal D_op_ldhuio : STD_LOGIC;
signal D_op_ldl : STD_LOGIC;
signal D_op_ldw : STD_LOGIC;
signal D_op_ldwio : STD_LOGIC;
signal D_op_mul : STD_LOGIC;
signal D_op_muli : STD_LOGIC;
signal D_op_mulxss : STD_LOGIC;
signal D_op_mulxsu : STD_LOGIC;
signal D_op_mulxuu : STD_LOGIC;
signal D_op_nextpc : STD_LOGIC;
signal D_op_nor : STD_LOGIC;
signal D_op_opx : STD_LOGIC;
signal D_op_or : STD_LOGIC;
signal D_op_orhi : STD_LOGIC;
signal D_op_ori : STD_LOGIC;
signal D_op_rdctl : STD_LOGIC;
signal D_op_rdprs : STD_LOGIC;
signal D_op_ret : STD_LOGIC;
signal D_op_rol : STD_LOGIC;
signal D_op_roli : STD_LOGIC;
signal D_op_ror : STD_LOGIC;
signal D_op_rsv02 : STD_LOGIC;
signal D_op_rsv09 : STD_LOGIC;
signal D_op_rsv10 : STD_LOGIC;
signal D_op_rsv17 : STD_LOGIC;
signal D_op_rsv18 : STD_LOGIC;
signal D_op_rsv25 : STD_LOGIC;
signal D_op_rsv26 : STD_LOGIC;
signal D_op_rsv33 : STD_LOGIC;
signal D_op_rsv34 : STD_LOGIC;
signal D_op_rsv41 : STD_LOGIC;
signal D_op_rsv42 : STD_LOGIC;
signal D_op_rsv49 : STD_LOGIC;
signal D_op_rsv57 : STD_LOGIC;
signal D_op_rsv61 : STD_LOGIC;
signal D_op_rsv62 : STD_LOGIC;
signal D_op_rsv63 : STD_LOGIC;
signal D_op_rsvx00 : STD_LOGIC;
signal D_op_rsvx10 : STD_LOGIC;
signal D_op_rsvx15 : STD_LOGIC;
signal D_op_rsvx17 : STD_LOGIC;
signal D_op_rsvx21 : STD_LOGIC;
signal D_op_rsvx25 : STD_LOGIC;
signal D_op_rsvx33 : STD_LOGIC;
signal D_op_rsvx34 : STD_LOGIC;
signal D_op_rsvx35 : STD_LOGIC;
signal D_op_rsvx42 : STD_LOGIC;
signal D_op_rsvx43 : STD_LOGIC;
signal D_op_rsvx44 : STD_LOGIC;
signal D_op_rsvx47 : STD_LOGIC;
signal D_op_rsvx50 : STD_LOGIC;
signal D_op_rsvx51 : STD_LOGIC;
signal D_op_rsvx55 : STD_LOGIC;
signal D_op_rsvx56 : STD_LOGIC;
signal D_op_rsvx60 : STD_LOGIC;
signal D_op_rsvx63 : STD_LOGIC;
signal D_op_sll : STD_LOGIC;
signal D_op_slli : STD_LOGIC;
signal D_op_sra : STD_LOGIC;
signal D_op_srai : STD_LOGIC;
signal D_op_srl : STD_LOGIC;
signal D_op_srli : STD_LOGIC;
signal D_op_stb : STD_LOGIC;
signal D_op_stbio : STD_LOGIC;
signal D_op_stc : STD_LOGIC;
signal D_op_sth : STD_LOGIC;
signal D_op_sthio : STD_LOGIC;
signal D_op_stw : STD_LOGIC;
signal D_op_stwio : STD_LOGIC;
signal D_op_sub : STD_LOGIC;
signal D_op_sync : STD_LOGIC;
signal D_op_trap : STD_LOGIC;
signal D_op_wrctl : STD_LOGIC;
signal D_op_wrprs : STD_LOGIC;
signal D_op_xor : STD_LOGIC;
signal D_op_xorhi : STD_LOGIC;
signal D_op_xori : STD_LOGIC;
signal D_valid : STD_LOGIC;
signal D_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal D_wr_dst_reg : STD_LOGIC;
signal E_alu_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_alu_sub : STD_LOGIC;
signal E_arith_result : STD_LOGIC_VECTOR (32 DOWNTO 0);
signal E_arith_src1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_arith_src2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_ci_multi_stall : STD_LOGIC;
signal E_ci_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_cmp_result : STD_LOGIC;
signal E_control_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_eq : STD_LOGIC;
signal E_invert_arith_src_msb : STD_LOGIC;
signal E_ld_stall : STD_LOGIC;
signal E_logic_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_logic_result_is_0 : STD_LOGIC;
signal E_lt : STD_LOGIC;
signal E_mem_baddr : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal E_mem_byte_en : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal E_new_inst : STD_LOGIC;
signal E_shift_rot_cnt : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal E_shift_rot_cnt_nxt : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal E_shift_rot_done : STD_LOGIC;
signal E_shift_rot_fill_bit : STD_LOGIC;
signal E_shift_rot_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_shift_rot_result_nxt : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_shift_rot_stall : STD_LOGIC;
signal E_src1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_src2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_st_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_st_stall : STD_LOGIC;
signal E_stall : STD_LOGIC;
signal E_valid : STD_LOGIC;
signal E_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal E_wrctl_bstatus : STD_LOGIC;
signal E_wrctl_estatus : STD_LOGIC;
signal E_wrctl_ienable : STD_LOGIC;
signal E_wrctl_status : STD_LOGIC;
signal F_av_iw : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal F_av_iw_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_c : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_control_regnum : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal F_av_iw_custom_n : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal F_av_iw_custom_readra : STD_LOGIC;
signal F_av_iw_custom_readrb : STD_LOGIC;
signal F_av_iw_custom_writerc : STD_LOGIC;
signal F_av_iw_imm16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal F_av_iw_imm26 : STD_LOGIC_VECTOR (25 DOWNTO 0);
signal F_av_iw_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_memsz : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal F_av_iw_op : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_av_iw_opx : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_av_iw_shift_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_iw_trap_break_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_av_mem16 : STD_LOGIC;
signal F_av_mem32 : STD_LOGIC;
signal F_av_mem8 : STD_LOGIC;
signal F_inst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal F_iw : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal F_iw_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_c : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_control_regnum : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal F_iw_custom_n : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal F_iw_custom_readra : STD_LOGIC;
signal F_iw_custom_readrb : STD_LOGIC;
signal F_iw_custom_writerc : STD_LOGIC;
signal F_iw_imm16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal F_iw_imm26 : STD_LOGIC_VECTOR (25 DOWNTO 0);
signal F_iw_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_memsz : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal F_iw_op : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_iw_opx : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal F_iw_shift_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_iw_trap_break_imm5 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal F_mem16 : STD_LOGIC;
signal F_mem32 : STD_LOGIC;
signal F_mem8 : STD_LOGIC;
signal F_op_add : STD_LOGIC;
signal F_op_addi : STD_LOGIC;
signal F_op_and : STD_LOGIC;
signal F_op_andhi : STD_LOGIC;
signal F_op_andi : STD_LOGIC;
signal F_op_beq : STD_LOGIC;
signal F_op_bge : STD_LOGIC;
signal F_op_bgeu : STD_LOGIC;
signal F_op_blt : STD_LOGIC;
signal F_op_bltu : STD_LOGIC;
signal F_op_bne : STD_LOGIC;
signal F_op_br : STD_LOGIC;
signal F_op_break : STD_LOGIC;
signal F_op_bret : STD_LOGIC;
signal F_op_call : STD_LOGIC;
signal F_op_callr : STD_LOGIC;
signal F_op_cmpeq : STD_LOGIC;
signal F_op_cmpeqi : STD_LOGIC;
signal F_op_cmpge : STD_LOGIC;
signal F_op_cmpgei : STD_LOGIC;
signal F_op_cmpgeu : STD_LOGIC;
signal F_op_cmpgeui : STD_LOGIC;
signal F_op_cmplt : STD_LOGIC;
signal F_op_cmplti : STD_LOGIC;
signal F_op_cmpltu : STD_LOGIC;
signal F_op_cmpltui : STD_LOGIC;
signal F_op_cmpne : STD_LOGIC;
signal F_op_cmpnei : STD_LOGIC;
signal F_op_crst : STD_LOGIC;
signal F_op_custom : STD_LOGIC;
signal F_op_div : STD_LOGIC;
signal F_op_divu : STD_LOGIC;
signal F_op_eret : STD_LOGIC;
signal F_op_flushd : STD_LOGIC;
signal F_op_flushda : STD_LOGIC;
signal F_op_flushi : STD_LOGIC;
signal F_op_flushp : STD_LOGIC;
signal F_op_hbreak : STD_LOGIC;
signal F_op_initd : STD_LOGIC;
signal F_op_initda : STD_LOGIC;
signal F_op_initi : STD_LOGIC;
signal F_op_intr : STD_LOGIC;
signal F_op_jmp : STD_LOGIC;
signal F_op_jmpi : STD_LOGIC;
signal F_op_ldb : STD_LOGIC;
signal F_op_ldbio : STD_LOGIC;
signal F_op_ldbu : STD_LOGIC;
signal F_op_ldbuio : STD_LOGIC;
signal F_op_ldh : STD_LOGIC;
signal F_op_ldhio : STD_LOGIC;
signal F_op_ldhu : STD_LOGIC;
signal F_op_ldhuio : STD_LOGIC;
signal F_op_ldl : STD_LOGIC;
signal F_op_ldw : STD_LOGIC;
signal F_op_ldwio : STD_LOGIC;
signal F_op_mul : STD_LOGIC;
signal F_op_muli : STD_LOGIC;
signal F_op_mulxss : STD_LOGIC;
signal F_op_mulxsu : STD_LOGIC;
signal F_op_mulxuu : STD_LOGIC;
signal F_op_nextpc : STD_LOGIC;
signal F_op_nor : STD_LOGIC;
signal F_op_opx : STD_LOGIC;
signal F_op_or : STD_LOGIC;
signal F_op_orhi : STD_LOGIC;
signal F_op_ori : STD_LOGIC;
signal F_op_rdctl : STD_LOGIC;
signal F_op_rdprs : STD_LOGIC;
signal F_op_ret : STD_LOGIC;
signal F_op_rol : STD_LOGIC;
signal F_op_roli : STD_LOGIC;
signal F_op_ror : STD_LOGIC;
signal F_op_rsv02 : STD_LOGIC;
signal F_op_rsv09 : STD_LOGIC;
signal F_op_rsv10 : STD_LOGIC;
signal F_op_rsv17 : STD_LOGIC;
signal F_op_rsv18 : STD_LOGIC;
signal F_op_rsv25 : STD_LOGIC;
signal F_op_rsv26 : STD_LOGIC;
signal F_op_rsv33 : STD_LOGIC;
signal F_op_rsv34 : STD_LOGIC;
signal F_op_rsv41 : STD_LOGIC;
signal F_op_rsv42 : STD_LOGIC;
signal F_op_rsv49 : STD_LOGIC;
signal F_op_rsv57 : STD_LOGIC;
signal F_op_rsv61 : STD_LOGIC;
signal F_op_rsv62 : STD_LOGIC;
signal F_op_rsv63 : STD_LOGIC;
signal F_op_rsvx00 : STD_LOGIC;
signal F_op_rsvx10 : STD_LOGIC;
signal F_op_rsvx15 : STD_LOGIC;
signal F_op_rsvx17 : STD_LOGIC;
signal F_op_rsvx21 : STD_LOGIC;
signal F_op_rsvx25 : STD_LOGIC;
signal F_op_rsvx33 : STD_LOGIC;
signal F_op_rsvx34 : STD_LOGIC;
signal F_op_rsvx35 : STD_LOGIC;
signal F_op_rsvx42 : STD_LOGIC;
signal F_op_rsvx43 : STD_LOGIC;
signal F_op_rsvx44 : STD_LOGIC;
signal F_op_rsvx47 : STD_LOGIC;
signal F_op_rsvx50 : STD_LOGIC;
signal F_op_rsvx51 : STD_LOGIC;
signal F_op_rsvx55 : STD_LOGIC;
signal F_op_rsvx56 : STD_LOGIC;
signal F_op_rsvx60 : STD_LOGIC;
signal F_op_rsvx63 : STD_LOGIC;
signal F_op_sll : STD_LOGIC;
signal F_op_slli : STD_LOGIC;
signal F_op_sra : STD_LOGIC;
signal F_op_srai : STD_LOGIC;
signal F_op_srl : STD_LOGIC;
signal F_op_srli : STD_LOGIC;
signal F_op_stb : STD_LOGIC;
signal F_op_stbio : STD_LOGIC;
signal F_op_stc : STD_LOGIC;
signal F_op_sth : STD_LOGIC;
signal F_op_sthio : STD_LOGIC;
signal F_op_stw : STD_LOGIC;
signal F_op_stwio : STD_LOGIC;
signal F_op_sub : STD_LOGIC;
signal F_op_sync : STD_LOGIC;
signal F_op_trap : STD_LOGIC;
signal F_op_wrctl : STD_LOGIC;
signal F_op_wrprs : STD_LOGIC;
signal F_op_xor : STD_LOGIC;
signal F_op_xorhi : STD_LOGIC;
signal F_op_xori : STD_LOGIC;
signal F_pc : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_en : STD_LOGIC;
signal F_pc_no_crst_nxt : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_nxt : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_plus_one : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal F_pc_sel_nxt : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal F_pcb : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_pcb_nxt : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_pcb_plus_four : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal F_valid : STD_LOGIC;
signal F_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal R_compare_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal R_ctrl_alu_force_xor : STD_LOGIC;
signal R_ctrl_alu_force_xor_nxt : STD_LOGIC;
signal R_ctrl_alu_signed_comparison : STD_LOGIC;
signal R_ctrl_alu_signed_comparison_nxt : STD_LOGIC;
signal R_ctrl_alu_subtract : STD_LOGIC;
signal R_ctrl_alu_subtract_nxt : STD_LOGIC;
signal R_ctrl_b_is_dst : STD_LOGIC;
signal R_ctrl_b_is_dst_nxt : STD_LOGIC;
signal R_ctrl_br : STD_LOGIC;
signal R_ctrl_br_cmp : STD_LOGIC;
signal R_ctrl_br_cmp_nxt : STD_LOGIC;
signal R_ctrl_br_nxt : STD_LOGIC;
signal R_ctrl_br_uncond : STD_LOGIC;
signal R_ctrl_br_uncond_nxt : STD_LOGIC;
signal R_ctrl_break : STD_LOGIC;
signal R_ctrl_break_nxt : STD_LOGIC;
signal R_ctrl_crst : STD_LOGIC;
signal R_ctrl_crst_nxt : STD_LOGIC;
signal R_ctrl_custom : STD_LOGIC;
signal R_ctrl_custom_multi : STD_LOGIC;
signal R_ctrl_custom_multi_nxt : STD_LOGIC;
signal R_ctrl_custom_nxt : STD_LOGIC;
signal R_ctrl_exception : STD_LOGIC;
signal R_ctrl_exception_nxt : STD_LOGIC;
signal R_ctrl_force_src2_zero : STD_LOGIC;
signal R_ctrl_force_src2_zero_nxt : STD_LOGIC;
signal R_ctrl_hi_imm16 : STD_LOGIC;
signal R_ctrl_hi_imm16_nxt : STD_LOGIC;
signal R_ctrl_ignore_dst : STD_LOGIC;
signal R_ctrl_ignore_dst_nxt : STD_LOGIC;
signal R_ctrl_implicit_dst_eretaddr : STD_LOGIC;
signal R_ctrl_implicit_dst_eretaddr_nxt : STD_LOGIC;
signal R_ctrl_implicit_dst_retaddr : STD_LOGIC;
signal R_ctrl_implicit_dst_retaddr_nxt : STD_LOGIC;
signal R_ctrl_jmp_direct : STD_LOGIC;
signal R_ctrl_jmp_direct_nxt : STD_LOGIC;
signal R_ctrl_jmp_indirect : STD_LOGIC;
signal R_ctrl_jmp_indirect_nxt : STD_LOGIC;
signal R_ctrl_ld : STD_LOGIC;
signal R_ctrl_ld_io : STD_LOGIC;
signal R_ctrl_ld_io_nxt : STD_LOGIC;
signal R_ctrl_ld_non_io : STD_LOGIC;
signal R_ctrl_ld_non_io_nxt : STD_LOGIC;
signal R_ctrl_ld_nxt : STD_LOGIC;
signal R_ctrl_ld_signed : STD_LOGIC;
signal R_ctrl_ld_signed_nxt : STD_LOGIC;
signal R_ctrl_logic : STD_LOGIC;
signal R_ctrl_logic_nxt : STD_LOGIC;
signal R_ctrl_rdctl_inst : STD_LOGIC;
signal R_ctrl_rdctl_inst_nxt : STD_LOGIC;
signal R_ctrl_retaddr : STD_LOGIC;
signal R_ctrl_retaddr_nxt : STD_LOGIC;
signal R_ctrl_rot_right : STD_LOGIC;
signal R_ctrl_rot_right_nxt : STD_LOGIC;
signal R_ctrl_shift_logical : STD_LOGIC;
signal R_ctrl_shift_logical_nxt : STD_LOGIC;
signal R_ctrl_shift_right_arith : STD_LOGIC;
signal R_ctrl_shift_right_arith_nxt : STD_LOGIC;
signal R_ctrl_shift_rot : STD_LOGIC;
signal R_ctrl_shift_rot_nxt : STD_LOGIC;
signal R_ctrl_shift_rot_right : STD_LOGIC;
signal R_ctrl_shift_rot_right_nxt : STD_LOGIC;
signal R_ctrl_src2_choose_imm : STD_LOGIC;
signal R_ctrl_src2_choose_imm_nxt : STD_LOGIC;
signal R_ctrl_st : STD_LOGIC;
signal R_ctrl_st_nxt : STD_LOGIC;
signal R_ctrl_uncond_cti_non_br : STD_LOGIC;
signal R_ctrl_uncond_cti_non_br_nxt : STD_LOGIC;
signal R_ctrl_unsigned_lo_imm16 : STD_LOGIC;
signal R_ctrl_unsigned_lo_imm16_nxt : STD_LOGIC;
signal R_ctrl_wrctl_inst : STD_LOGIC;
signal R_ctrl_wrctl_inst_nxt : STD_LOGIC;
signal R_dst_regnum : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal R_en : STD_LOGIC;
signal R_logic_op : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal R_rf_a : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_rf_b : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_src1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_src2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal R_src2_hi : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_src2_lo : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_src2_use_imm : STD_LOGIC;
signal R_stb_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal R_sth_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal R_valid : STD_LOGIC;
signal R_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal R_wr_dst_reg : STD_LOGIC;
signal W_alu_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_br_taken : STD_LOGIC;
signal W_bstatus_reg : STD_LOGIC;
signal W_bstatus_reg_inst_nxt : STD_LOGIC;
signal W_bstatus_reg_nxt : STD_LOGIC;
signal W_cmp_result : STD_LOGIC;
signal W_control_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_estatus_reg : STD_LOGIC;
signal W_estatus_reg_inst_nxt : STD_LOGIC;
signal W_estatus_reg_nxt : STD_LOGIC;
signal W_ienable_reg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ienable_reg_nxt : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_ipending_reg_nxt : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_mem_baddr : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal W_rf_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_rf_wren : STD_LOGIC;
signal W_status_reg : STD_LOGIC;
signal W_status_reg_pie : STD_LOGIC;
signal W_status_reg_pie_inst_nxt : STD_LOGIC;
signal W_status_reg_pie_nxt : STD_LOGIC;
signal W_valid : STD_LOGIC;
signal W_vinst : STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_wr_data_non_zero : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_fill_bit : STD_LOGIC;
signal av_ld_align_cycle : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal av_ld_align_cycle_nxt : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal av_ld_align_one_more_cycle : STD_LOGIC;
signal av_ld_aligning_data : STD_LOGIC;
signal av_ld_aligning_data_nxt : STD_LOGIC;
signal av_ld_byte0_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte0_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte1_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte1_data_en : STD_LOGIC;
signal av_ld_byte1_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte2_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte2_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte3_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_byte3_data_nxt : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal av_ld_data_aligned_filtered : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_data_aligned_unfiltered : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal av_ld_done : STD_LOGIC;
signal av_ld_extend : STD_LOGIC;
signal av_ld_getting_data : STD_LOGIC;
signal av_ld_rshift8 : STD_LOGIC;
signal av_ld_waiting_for_data : STD_LOGIC;
signal av_ld_waiting_for_data_nxt : STD_LOGIC;
signal av_sign_bit : STD_LOGIC;
signal d_read_nxt : STD_LOGIC;
signal d_write_nxt : STD_LOGIC;
signal hbreak_enabled : STD_LOGIC;
signal hbreak_pending : STD_LOGIC;
signal hbreak_pending_nxt : STD_LOGIC;
signal hbreak_req : STD_LOGIC;
signal i_read_nxt : STD_LOGIC;
signal iactive : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_d_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal internal_d_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_d_read : STD_LOGIC;
signal internal_d_write : STD_LOGIC;
signal internal_i_address : STD_LOGIC_VECTOR (19 DOWNTO 0);
signal internal_i_read : STD_LOGIC;
signal internal_jtag_debug_module_debugaccess_to_roms : STD_LOGIC;
signal internal_jtag_debug_module_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_jtag_debug_module_resetrequest : STD_LOGIC;
signal intr_req : STD_LOGIC;
signal jtag_debug_module_clk : STD_LOGIC;
signal jtag_debug_module_reset : STD_LOGIC;
signal oci_hbreak_req : STD_LOGIC;
signal oci_ienable : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oci_single_step_mode : STD_LOGIC;
signal oci_tb_hbreak_req : STD_LOGIC;
signal test_ending : STD_LOGIC;
signal test_has_ended : STD_LOGIC;
signal wait_for_one_post_bret_inst : STD_LOGIC;
attribute ALTERA_IP_DEBUG_VISIBLE : boolean;
attribute ALTERA_IP_DEBUG_VISIBLE of D_iw : signal is true;
attribute ALTERA_IP_DEBUG_VISIBLE of F_pc : signal is true;
attribute ALTERA_IP_DEBUG_VISIBLE of R_dst_regnum : signal is true;
attribute ALTERA_IP_DEBUG_VISIBLE of W_valid : signal is true;
--synthesis translate_off
constant Video_System_CPU_register_bank_a_lpm_file : string := "Video_System_CPU_rf_ram_a.hex";
--synthesis translate_on
--synthesis read_comments_as_HDL on
--constant Video_System_CPU_register_bank_a_lpm_file : string := "Video_System_CPU_rf_ram_a.mif";
--synthesis read_comments_as_HDL off
--synthesis translate_off
constant Video_System_CPU_register_bank_b_lpm_file : string := "Video_System_CPU_rf_ram_b.hex";
--synthesis translate_on
--synthesis read_comments_as_HDL on
--constant Video_System_CPU_register_bank_b_lpm_file : string := "Video_System_CPU_rf_ram_b.mif";
--synthesis read_comments_as_HDL off
begin
--the_Video_System_CPU_test_bench, which is an e_instance
the_Video_System_CPU_test_bench : Video_System_CPU_test_bench
port map(
av_ld_data_aligned_filtered => av_ld_data_aligned_filtered,
d_write => internal_d_write,
test_has_ended => test_has_ended,
D_iw => D_iw,
D_iw_op => D_iw_op,
D_iw_opx => D_iw_opx,
D_valid => D_valid,
E_alu_result => E_alu_result,
E_mem_byte_en => E_mem_byte_en,
E_st_data => E_st_data,
E_valid => E_valid,
F_pcb => F_pcb,
F_valid => F_valid,
R_ctrl_exception => R_ctrl_exception,
R_ctrl_ld => R_ctrl_ld,
R_ctrl_ld_non_io => R_ctrl_ld_non_io,
R_dst_regnum => R_dst_regnum,
R_wr_dst_reg => R_wr_dst_reg,
W_bstatus_reg => W_bstatus_reg,
W_cmp_result => W_cmp_result,
W_estatus_reg => W_estatus_reg,
W_ienable_reg => W_ienable_reg,
W_ipending_reg => W_ipending_reg,
W_mem_baddr => W_mem_baddr,
W_rf_wr_data => W_rf_wr_data,
W_status_reg => W_status_reg,
W_valid => W_valid,
W_vinst => W_vinst,
W_wr_data => W_wr_data,
av_ld_data_aligned_unfiltered => av_ld_data_aligned_unfiltered,
clk => clk,
d_address => internal_d_address,
d_byteenable => internal_d_byteenable,
d_read => internal_d_read,
d_write_nxt => d_write_nxt,
i_address => internal_i_address,
i_read => internal_i_read,
i_readdata => i_readdata,
i_waitrequest => i_waitrequest,
reset_n => reset_n
);
F_av_iw_a <= F_av_iw(31 DOWNTO 27);
F_av_iw_b <= F_av_iw(26 DOWNTO 22);
F_av_iw_c <= F_av_iw(21 DOWNTO 17);
F_av_iw_custom_n <= F_av_iw(13 DOWNTO 6);
F_av_iw_custom_readra <= F_av_iw(16);
F_av_iw_custom_readrb <= F_av_iw(15);
F_av_iw_custom_writerc <= F_av_iw(14);
F_av_iw_opx <= F_av_iw(16 DOWNTO 11);
F_av_iw_op <= F_av_iw(5 DOWNTO 0);
F_av_iw_shift_imm5 <= F_av_iw(10 DOWNTO 6);
F_av_iw_trap_break_imm5 <= F_av_iw(10 DOWNTO 6);
F_av_iw_imm5 <= F_av_iw(10 DOWNTO 6);
F_av_iw_imm16 <= F_av_iw(21 DOWNTO 6);
F_av_iw_imm26 <= F_av_iw(31 DOWNTO 6);
F_av_iw_memsz <= F_av_iw(4 DOWNTO 3);
F_av_iw_control_regnum <= F_av_iw(8 DOWNTO 6);
F_av_mem8 <= to_std_logic((F_av_iw_memsz = std_logic_vector'("00")));
F_av_mem16 <= to_std_logic((F_av_iw_memsz = std_logic_vector'("01")));
F_av_mem32 <= to_std_logic((std_logic'(F_av_iw_memsz(1)) = std_logic'(std_logic'('1'))));
F_iw_a <= F_iw(31 DOWNTO 27);
F_iw_b <= F_iw(26 DOWNTO 22);
F_iw_c <= F_iw(21 DOWNTO 17);
F_iw_custom_n <= F_iw(13 DOWNTO 6);
F_iw_custom_readra <= F_iw(16);
F_iw_custom_readrb <= F_iw(15);
F_iw_custom_writerc <= F_iw(14);
F_iw_opx <= F_iw(16 DOWNTO 11);
F_iw_op <= F_iw(5 DOWNTO 0);
F_iw_shift_imm5 <= F_iw(10 DOWNTO 6);
F_iw_trap_break_imm5 <= F_iw(10 DOWNTO 6);
F_iw_imm5 <= F_iw(10 DOWNTO 6);
F_iw_imm16 <= F_iw(21 DOWNTO 6);
F_iw_imm26 <= F_iw(31 DOWNTO 6);
F_iw_memsz <= F_iw(4 DOWNTO 3);
F_iw_control_regnum <= F_iw(8 DOWNTO 6);
F_mem8 <= to_std_logic((F_iw_memsz = std_logic_vector'("00")));
F_mem16 <= to_std_logic((F_iw_memsz = std_logic_vector'("01")));
F_mem32 <= to_std_logic((std_logic'(F_iw_memsz(1)) = std_logic'(std_logic'('1'))));
D_iw_a <= D_iw(31 DOWNTO 27);
D_iw_b <= D_iw(26 DOWNTO 22);
D_iw_c <= D_iw(21 DOWNTO 17);
D_iw_custom_n <= D_iw(13 DOWNTO 6);
D_iw_custom_readra <= D_iw(16);
D_iw_custom_readrb <= D_iw(15);
D_iw_custom_writerc <= D_iw(14);
D_iw_opx <= D_iw(16 DOWNTO 11);
D_iw_op <= D_iw(5 DOWNTO 0);
D_iw_shift_imm5 <= D_iw(10 DOWNTO 6);
D_iw_trap_break_imm5 <= D_iw(10 DOWNTO 6);
D_iw_imm5 <= D_iw(10 DOWNTO 6);
D_iw_imm16 <= D_iw(21 DOWNTO 6);
D_iw_imm26 <= D_iw(31 DOWNTO 6);
D_iw_memsz <= D_iw(4 DOWNTO 3);
D_iw_control_regnum <= D_iw(8 DOWNTO 6);
D_mem8 <= to_std_logic((D_iw_memsz = std_logic_vector'("00")));
D_mem16 <= to_std_logic((D_iw_memsz = std_logic_vector'("01")));
D_mem32 <= to_std_logic((std_logic'(D_iw_memsz(1)) = std_logic'(std_logic'('1'))));
F_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
F_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
F_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
F_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
F_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
F_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
F_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
F_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
F_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
F_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
F_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
F_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
F_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
F_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
F_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
F_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
F_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
F_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
F_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
F_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
F_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
F_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
F_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
F_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
F_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
F_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
F_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
F_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
F_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
F_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
F_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
F_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
F_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
F_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
F_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
F_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
F_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
F_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
F_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
F_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
F_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
F_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
F_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
F_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
F_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
F_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
F_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
F_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
F_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
F_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
F_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
F_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
F_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
F_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
F_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
F_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
F_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
F_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
F_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
F_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
F_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
F_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
F_op_eret <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
F_op_roli <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
F_op_rol <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
F_op_flushp <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
F_op_ret <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
F_op_nor <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
F_op_mulxuu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
F_op_cmpge <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
F_op_bret <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
F_op_ror <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
F_op_flushi <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
F_op_jmp <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
F_op_and <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
F_op_cmplt <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
F_op_slli <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
F_op_sll <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
F_op_wrprs <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
F_op_or <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
F_op_mulxsu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
F_op_cmpne <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
F_op_srli <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
F_op_srl <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
F_op_nextpc <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
F_op_callr <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
F_op_xor <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
F_op_mulxss <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
F_op_cmpeq <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
F_op_divu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
F_op_div <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
F_op_rdctl <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
F_op_mul <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
F_op_cmpgeu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
F_op_initi <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
F_op_trap <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
F_op_wrctl <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
F_op_cmpltu <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
F_op_add <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
F_op_break <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
F_op_hbreak <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
F_op_sync <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
F_op_sub <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
F_op_srai <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
F_op_sra <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
F_op_intr <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
F_op_crst <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
F_op_rsvx00 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
F_op_rsvx10 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
F_op_rsvx15 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
F_op_rsvx17 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
F_op_rsvx21 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
F_op_rsvx25 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
F_op_rsvx33 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
F_op_rsvx34 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
F_op_rsvx35 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
F_op_rsvx42 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
F_op_rsvx43 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
F_op_rsvx44 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
F_op_rsvx47 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
F_op_rsvx50 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
F_op_rsvx51 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
F_op_rsvx55 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
F_op_rsvx56 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
F_op_rsvx60 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
F_op_rsvx63 <= F_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (F_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
F_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
F_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (F_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
D_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
D_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
D_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
D_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
D_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
D_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
D_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
D_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
D_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
D_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
D_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
D_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
D_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
D_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
D_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
D_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
D_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
D_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
D_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
D_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
D_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
D_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
D_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
D_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
D_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
D_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
D_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
D_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
D_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
D_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
D_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
D_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
D_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
D_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
D_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
D_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
D_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
D_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
D_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
D_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
D_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
D_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
D_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
D_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
D_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
D_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
D_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
D_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
D_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
D_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
D_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
D_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
D_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
D_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
D_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
D_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
D_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
D_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
D_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
D_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
D_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
D_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
D_op_eret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
D_op_roli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
D_op_rol <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
D_op_flushp <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
D_op_ret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
D_op_nor <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
D_op_mulxuu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
D_op_cmpge <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
D_op_bret <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
D_op_ror <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
D_op_flushi <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
D_op_jmp <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
D_op_and <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
D_op_cmplt <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
D_op_slli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
D_op_sll <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
D_op_wrprs <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
D_op_or <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
D_op_mulxsu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
D_op_cmpne <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
D_op_srli <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
D_op_srl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
D_op_nextpc <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
D_op_callr <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
D_op_xor <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
D_op_mulxss <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
D_op_cmpeq <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
D_op_divu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
D_op_div <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
D_op_rdctl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
D_op_mul <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
D_op_cmpgeu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
D_op_initi <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
D_op_trap <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
D_op_wrctl <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
D_op_cmpltu <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
D_op_add <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
D_op_break <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
D_op_hbreak <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
D_op_sync <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
D_op_sub <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
D_op_srai <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
D_op_sra <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
D_op_intr <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
D_op_crst <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
D_op_rsvx00 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
D_op_rsvx10 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
D_op_rsvx15 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
D_op_rsvx17 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
D_op_rsvx21 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
D_op_rsvx25 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
D_op_rsvx33 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
D_op_rsvx34 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
D_op_rsvx35 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
D_op_rsvx42 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
D_op_rsvx43 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
D_op_rsvx44 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
D_op_rsvx47 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
D_op_rsvx50 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
D_op_rsvx51 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
D_op_rsvx55 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
D_op_rsvx56 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
D_op_rsvx60 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
D_op_rsvx63 <= D_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (D_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
D_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
D_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (D_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
R_en <= std_logic'('1');
E_ci_result <= std_logic_vector'("00000000000000000000000000000000");
--custom_instruction_master, which is an e_custom_instruction_master
no_ci_readra <= std_logic'('0');
E_ci_multi_stall <= std_logic'('0');
iactive <= d_irq(31 DOWNTO 0) AND std_logic_vector'("00000000000000000000000000000000");
F_pc_sel_nxt <= A_WE_StdLogicVector((std_logic'(R_ctrl_exception) = '1'), std_logic_vector'("00"), A_WE_StdLogicVector((std_logic'(R_ctrl_break) = '1'), std_logic_vector'("01"), A_WE_StdLogicVector((std_logic'(((W_br_taken OR R_ctrl_uncond_cti_non_br))) = '1'), std_logic_vector'("10"), std_logic_vector'("11"))));
F_pc_no_crst_nxt <= A_EXT (A_WE_StdLogicVector(((F_pc_sel_nxt = std_logic_vector'("00"))), std_logic_vector'("00000000000000100001000000001000"), A_WE_StdLogicVector(((F_pc_sel_nxt = std_logic_vector'("01"))), std_logic_vector'("00000000000000100010001000001000"), (std_logic_vector'("00000000000000") & (A_WE_StdLogicVector(((F_pc_sel_nxt = std_logic_vector'("10"))), E_arith_result(19 DOWNTO 2), F_pc_plus_one))))), 18);
F_pc_nxt <= F_pc_no_crst_nxt;
F_pcb_nxt <= F_pc_nxt & std_logic_vector'("00");
F_pc_en <= W_valid;
F_pc_plus_one <= A_EXT (((std_logic_vector'("000000000000000") & (F_pc)) + std_logic_vector'("000000000000000000000000000000001")), 18);
process (clk, reset_n)
begin
if reset_n = '0' then
F_pc <= std_logic_vector'("100001000000000000");
elsif clk'event and clk = '1' then
if std_logic'(F_pc_en) = '1' then
F_pc <= F_pc_nxt;
end if;
end if;
end process;
F_pcb <= F_pc & std_logic_vector'("00");
F_pcb_plus_four <= F_pc_plus_one & std_logic_vector'("00");
F_valid <= internal_i_read AND NOT i_waitrequest;
i_read_nxt <= W_valid OR ((internal_i_read AND i_waitrequest));
internal_i_address <= F_pc & std_logic_vector'("00");
process (clk, reset_n)
begin
if reset_n = '0' then
internal_i_read <= std_logic'('1');
elsif clk'event and clk = '1' then
internal_i_read <= i_read_nxt;
end if;
end process;
oci_tb_hbreak_req <= oci_hbreak_req;
hbreak_req <= (((oci_tb_hbreak_req OR hbreak_pending)) AND hbreak_enabled) AND NOT ((wait_for_one_post_bret_inst AND NOT W_valid));
hbreak_pending_nxt <= A_WE_StdLogic((std_logic'(hbreak_pending) = '1'), hbreak_enabled, hbreak_req);
process (clk, reset_n)
begin
if reset_n = '0' then
wait_for_one_post_bret_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
wait_for_one_post_bret_inst <= A_WE_StdLogic((std_logic'(((NOT hbreak_enabled AND oci_single_step_mode))) = '1'), std_logic'('1'), A_WE_StdLogic((std_logic'(((F_valid OR NOT oci_single_step_mode))) = '1'), std_logic'('0'), wait_for_one_post_bret_inst));
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
hbreak_pending <= std_logic'('0');
elsif clk'event and clk = '1' then
hbreak_pending <= hbreak_pending_nxt;
end if;
end process;
intr_req <= W_status_reg_pie AND to_std_logic(((W_ipending_reg /= std_logic_vector'("00000000000000000000000000000000"))));
F_av_iw <= i_readdata;
F_iw <= A_WE_StdLogicVector((std_logic'(hbreak_req) = '1'), std_logic_vector'("00000000001111011010100000111010"), A_WE_StdLogicVector((std_logic'(std_logic'('0')) = '1'), std_logic_vector'("00000000000000011111000000111010"), A_WE_StdLogicVector((std_logic'(intr_req) = '1'), std_logic_vector'("00000000001110111110100000111010"), F_av_iw)));
process (clk, reset_n)
begin
if reset_n = '0' then
D_iw <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(F_valid) = '1' then
D_iw <= F_iw;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
D_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
D_valid <= F_valid;
end if;
end process;
D_dst_regnum <= A_WE_StdLogicVector((std_logic'(D_ctrl_implicit_dst_retaddr) = '1'), std_logic_vector'("11111"), A_WE_StdLogicVector((std_logic'(D_ctrl_implicit_dst_eretaddr) = '1'), std_logic_vector'("11101"), A_WE_StdLogicVector((std_logic'(D_ctrl_b_is_dst) = '1'), D_iw_b, D_iw_c)));
D_wr_dst_reg <= to_std_logic((((std_logic_vector'("000000000000000000000000000") & (D_dst_regnum)) /= std_logic_vector'("00000000000000000000000000000000")))) AND NOT D_ctrl_ignore_dst;
D_logic_op_raw <= A_WE_StdLogicVector((std_logic'(D_op_opx) = '1'), D_iw_opx(4 DOWNTO 3), D_iw_op(4 DOWNTO 3));
D_logic_op <= A_WE_StdLogicVector((std_logic'(D_ctrl_alu_force_xor) = '1'), std_logic_vector'("11"), D_logic_op_raw);
D_compare_op <= A_WE_StdLogicVector((std_logic'(D_op_opx) = '1'), D_iw_opx(4 DOWNTO 3), D_iw_op(4 DOWNTO 3));
D_jmp_direct_target_waddr <= A_EXT (D_iw(31 DOWNTO 6), 18);
process (clk, reset_n)
begin
if reset_n = '0' then
R_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
R_valid <= D_valid;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_wr_dst_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
R_wr_dst_reg <= D_wr_dst_reg;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_dst_regnum <= std_logic_vector'("00000");
elsif clk'event and clk = '1' then
R_dst_regnum <= D_dst_regnum;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_logic_op <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
R_logic_op <= D_logic_op;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_compare_op <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
R_compare_op <= D_compare_op;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
R_src2_use_imm <= std_logic'('0');
elsif clk'event and clk = '1' then
R_src2_use_imm <= D_ctrl_src2_choose_imm OR ((D_ctrl_br AND R_valid));
end if;
end process;
W_rf_wren <= ((R_wr_dst_reg AND W_valid)) OR NOT reset_n;
W_rf_wr_data <= A_WE_StdLogicVector((std_logic'(R_ctrl_ld) = '1'), av_ld_data_aligned_filtered, W_wr_data);
--Video_System_CPU_register_bank_a, which is an nios_sdp_ram
Video_System_CPU_register_bank_a : Video_System_CPU_register_bank_a_module
generic map(
lpm_file => Video_System_CPU_register_bank_a_lpm_file
)
port map(
q => R_rf_a,
clock => clk,
data => W_rf_wr_data,
rdaddress => D_iw_a,
wraddress => R_dst_regnum,
wren => W_rf_wren
);
--Video_System_CPU_register_bank_b, which is an nios_sdp_ram
Video_System_CPU_register_bank_b : Video_System_CPU_register_bank_b_module
generic map(
lpm_file => Video_System_CPU_register_bank_b_lpm_file
)
port map(
q => R_rf_b,
clock => clk,
data => W_rf_wr_data,
rdaddress => D_iw_b,
wraddress => R_dst_regnum,
wren => W_rf_wren
);
R_src1 <= A_WE_StdLogicVector((std_logic'(((((R_ctrl_br AND E_valid)) OR ((R_ctrl_retaddr AND R_valid))))) = '1'), (std_logic_vector'("000000000000") & ((F_pc_plus_one & std_logic_vector'("00")))), A_WE_StdLogicVector((std_logic'(((R_ctrl_jmp_direct AND E_valid))) = '1'), (std_logic_vector'("000000000000") & ((D_jmp_direct_target_waddr & std_logic_vector'("00")))), R_rf_a));
R_src2_lo <= A_WE_StdLogicVector((std_logic'(((R_ctrl_force_src2_zero OR R_ctrl_hi_imm16))) = '1'), std_logic_vector'("0000000000000000"), A_WE_StdLogicVector((std_logic'((R_src2_use_imm)) = '1'), D_iw_imm16, R_rf_b(15 DOWNTO 0)));
R_src2_hi <= A_WE_StdLogicVector((std_logic'(((R_ctrl_force_src2_zero OR R_ctrl_unsigned_lo_imm16))) = '1'), std_logic_vector'("0000000000000000"), A_WE_StdLogicVector((std_logic'((R_ctrl_hi_imm16)) = '1'), D_iw_imm16, A_WE_StdLogicVector((std_logic'((R_src2_use_imm)) = '1'), A_REP(D_iw_imm16(15) , 16), R_rf_b(31 DOWNTO 16))));
R_src2 <= R_src2_hi & R_src2_lo;
process (clk, reset_n)
begin
if reset_n = '0' then
E_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
E_valid <= R_valid OR E_stall;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_new_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
E_new_inst <= R_valid;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_src1 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
E_src1 <= R_src1;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_src2 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
E_src2 <= R_src2;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_invert_arith_src_msb <= std_logic'('0');
elsif clk'event and clk = '1' then
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison AND R_valid;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_alu_sub <= std_logic'('0');
elsif clk'event and clk = '1' then
E_alu_sub <= D_ctrl_alu_subtract AND R_valid;
end if;
end process;
E_stall <= ((E_shift_rot_stall OR E_ld_stall) OR E_st_stall) OR E_ci_multi_stall;
E_arith_src1 <= Std_Logic_Vector'(A_ToStdLogicVector((E_src1(31) XOR E_invert_arith_src_msb)) & E_src1(30 DOWNTO 0));
E_arith_src2 <= Std_Logic_Vector'(A_ToStdLogicVector((E_src2(31) XOR E_invert_arith_src_msb)) & E_src2(30 DOWNTO 0));
E_arith_result <= A_WE_StdLogicVector((std_logic'(E_alu_sub) = '1'), ((std_logic_vector'("0") & (E_arith_src1)) - (std_logic_vector'("0") & (E_arith_src2))), ((std_logic_vector'("0") & (E_arith_src1)) + (std_logic_vector'("0") & (E_arith_src2))));
E_mem_baddr <= E_arith_result(19 DOWNTO 0);
E_logic_result <= A_WE_StdLogicVector(((R_logic_op = std_logic_vector'("00"))), (NOT ((E_src1 OR E_src2))), A_WE_StdLogicVector(((R_logic_op = std_logic_vector'("01"))), ((E_src1 AND E_src2)), A_WE_StdLogicVector(((R_logic_op = std_logic_vector'("10"))), ((E_src1 OR E_src2)), ((E_src1 XOR E_src2)))));
E_logic_result_is_0 <= to_std_logic((E_logic_result = std_logic_vector'("00000000000000000000000000000000")));
E_eq <= E_logic_result_is_0;
E_lt <= E_arith_result(32);
E_cmp_result <= A_WE_StdLogic(((R_compare_op = std_logic_vector'("00"))), E_eq, A_WE_StdLogic(((R_compare_op = std_logic_vector'("01"))), NOT E_lt, A_WE_StdLogic(((R_compare_op = std_logic_vector'("10"))), E_lt, NOT E_eq)));
E_shift_rot_cnt_nxt <= A_EXT (A_WE_StdLogicVector((std_logic'(E_new_inst) = '1'), (std_logic_vector'("0000000000000000000000000000") & (E_src2(4 DOWNTO 0))), ((std_logic_vector'("0000000000000000000000000000") & (E_shift_rot_cnt)) - std_logic_vector'("000000000000000000000000000000001"))), 5);
E_shift_rot_done <= to_std_logic((((std_logic_vector'("000000000000000000000000000") & (E_shift_rot_cnt)) = std_logic_vector'("00000000000000000000000000000000")))) AND NOT E_new_inst;
E_shift_rot_stall <= (R_ctrl_shift_rot AND E_valid) AND NOT E_shift_rot_done;
E_shift_rot_fill_bit <= A_WE_StdLogic((std_logic'(R_ctrl_shift_logical) = '1'), std_logic'('0'), (A_WE_StdLogic((std_logic'(R_ctrl_rot_right) = '1'), E_shift_rot_result(0), E_shift_rot_result(31))));
E_shift_rot_result_nxt <= A_WE_StdLogicVector((std_logic'((E_new_inst)) = '1'), E_src1, A_WE_StdLogicVector((std_logic'((R_ctrl_shift_rot_right)) = '1'), Std_Logic_Vector'(A_ToStdLogicVector(E_shift_rot_fill_bit) & E_shift_rot_result(31 DOWNTO 1)), Std_Logic_Vector'(E_shift_rot_result(30 DOWNTO 0) & A_ToStdLogicVector(E_shift_rot_fill_bit))));
process (clk, reset_n)
begin
if reset_n = '0' then
E_shift_rot_result <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
E_shift_rot_result <= E_shift_rot_result_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
E_shift_rot_cnt <= std_logic_vector'("00000");
elsif clk'event and clk = '1' then
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end if;
end process;
E_control_rd_data <= A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_status_reg))), A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("001"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_estatus_reg))), A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("010"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_bstatus_reg))), A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("011"))), W_ienable_reg, A_WE_StdLogicVector(((D_iw_control_regnum = std_logic_vector'("100"))), W_ipending_reg, std_logic_vector'("00000000000000000000000000000000"))))));
E_alu_result <= A_EXT (A_WE_StdLogicVector((std_logic'(((R_ctrl_br_cmp OR R_ctrl_rdctl_inst))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'((R_ctrl_shift_rot)) = '1'), (std_logic_vector'("0") & (E_shift_rot_result)), A_WE_StdLogicVector((std_logic'((R_ctrl_logic)) = '1'), (std_logic_vector'("0") & (E_logic_result)), A_WE_StdLogicVector((std_logic'((R_ctrl_custom)) = '1'), (std_logic_vector'("0") & (E_ci_result)), E_arith_result)))), 32);
R_stb_data <= R_rf_b(7 DOWNTO 0);
R_sth_data <= R_rf_b(15 DOWNTO 0);
E_st_data <= A_WE_StdLogicVector((std_logic'((D_mem8)) = '1'), (R_stb_data & R_stb_data & R_stb_data & R_stb_data), A_WE_StdLogicVector((std_logic'((D_mem16)) = '1'), (R_sth_data & R_sth_data), R_rf_b));
E_mem_byte_en <= A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("00")))), std_logic_vector'("0001"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("01")))), std_logic_vector'("0010"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("10")))), std_logic_vector'("0100"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("00") & std_logic_vector'("11")))), std_logic_vector'("1000"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("00")))), std_logic_vector'("0011"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("01")))), std_logic_vector'("0011"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("10")))), std_logic_vector'("1100"), A_WE_StdLogicVector((((D_iw_memsz & E_mem_baddr(1 DOWNTO 0)) = Std_Logic_Vector'(std_logic_vector'("01") & std_logic_vector'("11")))), std_logic_vector'("1100"), std_logic_vector'("1111")))))))));
d_read_nxt <= ((R_ctrl_ld AND E_new_inst)) OR ((internal_d_read AND d_waitrequest));
E_ld_stall <= R_ctrl_ld AND ((((E_valid AND NOT av_ld_done)) OR E_new_inst));
d_write_nxt <= ((R_ctrl_st AND E_new_inst)) OR ((internal_d_write AND d_waitrequest));
E_st_stall <= d_write_nxt;
internal_d_address <= W_mem_baddr;
av_ld_getting_data <= internal_d_read AND NOT d_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_d_read <= std_logic'('0');
elsif clk'event and clk = '1' then
internal_d_read <= d_read_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
d_writedata <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
d_writedata <= E_st_data;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_d_byteenable <= std_logic_vector'("0000");
elsif clk'event and clk = '1' then
internal_d_byteenable <= E_mem_byte_en;
end if;
end process;
av_ld_align_cycle_nxt <= A_EXT (A_WE_StdLogicVector((std_logic'(av_ld_getting_data) = '1'), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("0000000000000000000000000000000") & (av_ld_align_cycle)) + std_logic_vector'("000000000000000000000000000000001")))), 2);
av_ld_align_one_more_cycle <= to_std_logic(((std_logic_vector'("000000000000000000000000000000") & (av_ld_align_cycle)) = (A_WE_StdLogicVector((std_logic'(D_mem16) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000011")))));
av_ld_aligning_data_nxt <= A_WE_StdLogic((std_logic'(av_ld_aligning_data) = '1'), NOT av_ld_align_one_more_cycle, ((NOT D_mem32 AND av_ld_getting_data)));
av_ld_waiting_for_data_nxt <= A_WE_StdLogic((std_logic'(av_ld_waiting_for_data) = '1'), NOT av_ld_getting_data, ((R_ctrl_ld AND E_new_inst)));
av_ld_done <= NOT av_ld_waiting_for_data_nxt AND ((D_mem32 OR NOT av_ld_aligning_data_nxt));
av_ld_rshift8 <= av_ld_aligning_data AND to_std_logic(((av_ld_align_cycle<(W_mem_baddr(1 DOWNTO 0)))));
av_ld_extend <= av_ld_aligning_data;
av_ld_byte0_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte1_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), av_ld_byte0_data, d_readdata(7 DOWNTO 0)));
av_ld_byte1_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte2_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), A_REP(av_fill_bit, 8), d_readdata(15 DOWNTO 8)));
av_ld_byte2_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte3_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), A_REP(av_fill_bit, 8), d_readdata(23 DOWNTO 16)));
av_ld_byte3_data_nxt <= A_WE_StdLogicVector((std_logic'(av_ld_rshift8) = '1'), av_ld_byte3_data, A_WE_StdLogicVector((std_logic'(av_ld_extend) = '1'), A_REP(av_fill_bit, 8), d_readdata(31 DOWNTO 24)));
av_ld_byte1_data_en <= NOT (((av_ld_extend AND D_mem16) AND NOT av_ld_rshift8));
av_ld_data_aligned_unfiltered <= av_ld_byte3_data & av_ld_byte2_data & av_ld_byte1_data & av_ld_byte0_data;
av_sign_bit <= A_WE_StdLogic((std_logic'(D_mem16) = '1'), av_ld_byte1_data(7), av_ld_byte0_data(7));
av_fill_bit <= av_sign_bit AND R_ctrl_ld_signed;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_align_cycle <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_waiting_for_data <= std_logic'('0');
elsif clk'event and clk = '1' then
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_aligning_data <= std_logic'('0');
elsif clk'event and clk = '1' then
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte0_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte1_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
if std_logic'(av_ld_byte1_data_en) = '1' then
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte2_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
av_ld_byte3_data <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_valid <= std_logic'('0');
elsif clk'event and clk = '1' then
W_valid <= E_valid AND NOT E_stall;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_control_rd_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_control_rd_data <= E_control_rd_data;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_cmp_result <= std_logic'('0');
elsif clk'event and clk = '1' then
W_cmp_result <= E_cmp_result;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_alu_result <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_alu_result <= E_alu_result;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_status_reg_pie <= std_logic'('0');
elsif clk'event and clk = '1' then
W_status_reg_pie <= W_status_reg_pie_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_estatus_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
W_estatus_reg <= W_estatus_reg_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_bstatus_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
W_bstatus_reg <= W_bstatus_reg_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_ienable_reg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_ienable_reg <= W_ienable_reg_nxt;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
W_ipending_reg <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
W_ipending_reg <= W_ipending_reg_nxt;
end if;
end process;
W_wr_data_non_zero <= A_WE_StdLogicVector((std_logic'(R_ctrl_br_cmp) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(W_cmp_result))), A_WE_StdLogicVector((std_logic'(R_ctrl_rdctl_inst) = '1'), W_control_rd_data, W_alu_result(31 DOWNTO 0)));
W_wr_data <= W_wr_data_non_zero;
W_br_taken <= R_ctrl_br AND W_cmp_result;
W_mem_baddr <= W_alu_result(19 DOWNTO 0);
W_status_reg <= W_status_reg_pie;
E_wrctl_status <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("000"))));
E_wrctl_estatus <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("001"))));
E_wrctl_bstatus <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("010"))));
E_wrctl_ienable <= R_ctrl_wrctl_inst AND to_std_logic(((D_iw_control_regnum = std_logic_vector'("011"))));
W_status_reg_pie_inst_nxt <= A_WE_StdLogic((std_logic'((((R_ctrl_exception OR R_ctrl_break) OR R_ctrl_crst))) = '1'), std_logic'('0'), A_WE_StdLogic((std_logic'((D_op_eret)) = '1'), W_estatus_reg, A_WE_StdLogic((std_logic'((D_op_bret)) = '1'), W_bstatus_reg, A_WE_StdLogic((std_logic'((E_wrctl_status)) = '1'), E_src1(0), W_status_reg_pie))));
W_status_reg_pie_nxt <= A_WE_StdLogic((std_logic'(E_valid) = '1'), W_status_reg_pie_inst_nxt, W_status_reg_pie);
W_estatus_reg_inst_nxt <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((R_ctrl_crst)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(A_WE_StdLogic((std_logic'((R_ctrl_exception)) = '1'), W_status_reg, A_WE_StdLogic((std_logic'((E_wrctl_estatus)) = '1'), E_src1(0), W_estatus_reg)))))));
W_estatus_reg_nxt <= A_WE_StdLogic((std_logic'(E_valid) = '1'), W_estatus_reg_inst_nxt, W_estatus_reg);
W_bstatus_reg_inst_nxt <= A_WE_StdLogic((std_logic'((R_ctrl_break)) = '1'), W_status_reg, A_WE_StdLogic((std_logic'((E_wrctl_bstatus)) = '1'), E_src1(0), W_bstatus_reg));
W_bstatus_reg_nxt <= A_WE_StdLogic((std_logic'(E_valid) = '1'), W_bstatus_reg_inst_nxt, W_bstatus_reg);
W_ienable_reg_nxt <= (A_WE_StdLogicVector((std_logic'(((E_wrctl_ienable AND E_valid))) = '1'), E_src1(31 DOWNTO 0), W_ienable_reg)) AND std_logic_vector'("00000000000000000000000000000000");
W_ipending_reg_nxt <= ((iactive AND W_ienable_reg) AND oci_ienable) AND std_logic_vector'("00000000000000000000000000000000");
process (clk, reset_n)
begin
if reset_n = '0' then
hbreak_enabled <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(E_valid) = '1' then
hbreak_enabled <= A_WE_StdLogic((std_logic'(R_ctrl_break) = '1'), std_logic'('0'), A_WE_StdLogic((std_logic'(D_op_bret) = '1'), std_logic'('1'), hbreak_enabled));
end if;
end if;
end process;
--the_Video_System_CPU_nios2_oci, which is an e_instance
the_Video_System_CPU_nios2_oci : Video_System_CPU_nios2_oci
port map(
jtag_debug_module_debugaccess_to_roms => internal_jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req => oci_hbreak_req,
oci_ienable => oci_ienable,
oci_single_step_mode => oci_single_step_mode,
readdata => internal_jtag_debug_module_readdata,
resetrequest => internal_jtag_debug_module_resetrequest,
D_valid => D_valid,
E_st_data => E_st_data,
E_valid => E_valid,
F_pc => F_pc,
address => jtag_debug_module_address,
av_ld_data_aligned_filtered => av_ld_data_aligned_filtered,
begintransfer => jtag_debug_module_begintransfer,
byteenable => jtag_debug_module_byteenable,
chipselect => jtag_debug_module_select,
clk => jtag_debug_module_clk,
d_address => internal_d_address,
d_read => internal_d_read,
d_waitrequest => d_waitrequest,
d_write => internal_d_write,
debugaccess => jtag_debug_module_debugaccess,
hbreak_enabled => hbreak_enabled,
reset => jtag_debug_module_reset,
reset_n => reset_n,
test_ending => test_ending,
test_has_ended => test_has_ended,
write => jtag_debug_module_write,
writedata => jtag_debug_module_writedata
);
--jtag_debug_module, which is an e_avalon_slave
jtag_debug_module_clk <= clk;
jtag_debug_module_reset <= NOT reset_n;
D_ctrl_custom <= std_logic'('0');
R_ctrl_custom_nxt <= D_ctrl_custom;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_custom <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_custom <= R_ctrl_custom_nxt;
end if;
end if;
end process;
D_ctrl_custom_multi <= std_logic'('0');
R_ctrl_custom_multi_nxt <= D_ctrl_custom_multi;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_custom_multi <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end if;
end if;
end process;
D_ctrl_jmp_indirect <= ((((((D_op_eret OR D_op_bret) OR D_op_rsvx17) OR D_op_rsvx25) OR D_op_ret) OR D_op_jmp) OR D_op_rsvx21) OR D_op_callr;
R_ctrl_jmp_indirect_nxt <= D_ctrl_jmp_indirect;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_jmp_indirect <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end if;
end if;
end process;
D_ctrl_jmp_direct <= D_op_call OR D_op_jmpi;
R_ctrl_jmp_direct_nxt <= D_ctrl_jmp_direct;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_jmp_direct <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end if;
end if;
end process;
D_ctrl_implicit_dst_retaddr <= D_op_call OR D_op_rsv02;
R_ctrl_implicit_dst_retaddr_nxt <= D_ctrl_implicit_dst_retaddr;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_implicit_dst_retaddr <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end if;
end if;
end process;
D_ctrl_implicit_dst_eretaddr <= (((((D_op_div OR D_op_divu) OR D_op_mul) OR D_op_muli) OR D_op_mulxss) OR D_op_mulxsu) OR D_op_mulxuu;
R_ctrl_implicit_dst_eretaddr_nxt <= D_ctrl_implicit_dst_eretaddr;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_implicit_dst_eretaddr <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end if;
end if;
end process;
D_ctrl_exception <= (((((((((D_op_trap OR D_op_rsvx44) OR D_op_div) OR D_op_divu) OR D_op_mul) OR D_op_muli) OR D_op_mulxss) OR D_op_mulxsu) OR D_op_mulxuu) OR D_op_intr) OR D_op_rsvx60;
R_ctrl_exception_nxt <= D_ctrl_exception;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_exception <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_exception <= R_ctrl_exception_nxt;
end if;
end if;
end process;
D_ctrl_break <= D_op_break OR D_op_hbreak;
R_ctrl_break_nxt <= D_ctrl_break;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_break <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_break <= R_ctrl_break_nxt;
end if;
end if;
end process;
D_ctrl_crst <= D_op_crst OR D_op_rsvx63;
R_ctrl_crst_nxt <= D_ctrl_crst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_crst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_crst <= R_ctrl_crst_nxt;
end if;
end if;
end process;
D_ctrl_uncond_cti_non_br <= ((((((((D_op_call OR D_op_jmpi) OR D_op_eret) OR D_op_bret) OR D_op_rsvx17) OR D_op_rsvx25) OR D_op_ret) OR D_op_jmp) OR D_op_rsvx21) OR D_op_callr;
R_ctrl_uncond_cti_non_br_nxt <= D_ctrl_uncond_cti_non_br;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_uncond_cti_non_br <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end if;
end if;
end process;
D_ctrl_retaddr <= (((((((((((((((D_op_call OR D_op_rsv02) OR D_op_nextpc) OR D_op_callr) OR D_op_trap) OR D_op_rsvx44) OR D_op_div) OR D_op_divu) OR D_op_mul) OR D_op_muli) OR D_op_mulxss) OR D_op_mulxsu) OR D_op_mulxuu) OR D_op_intr) OR D_op_rsvx60) OR D_op_break) OR D_op_hbreak;
R_ctrl_retaddr_nxt <= D_ctrl_retaddr;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_retaddr <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end if;
end if;
end process;
D_ctrl_shift_logical <= ((D_op_slli OR D_op_sll) OR D_op_srli) OR D_op_srl;
R_ctrl_shift_logical_nxt <= D_ctrl_shift_logical;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_logical <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end if;
end if;
end process;
D_ctrl_shift_right_arith <= D_op_srai OR D_op_sra;
R_ctrl_shift_right_arith_nxt <= D_ctrl_shift_right_arith;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_right_arith <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end if;
end if;
end process;
D_ctrl_rot_right <= ((D_op_rsvx10 OR D_op_ror) OR D_op_rsvx42) OR D_op_rsvx43;
R_ctrl_rot_right_nxt <= D_ctrl_rot_right;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_rot_right <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end if;
end if;
end process;
D_ctrl_shift_rot_right <= ((((((D_op_srli OR D_op_srl) OR D_op_srai) OR D_op_sra) OR D_op_rsvx10) OR D_op_ror) OR D_op_rsvx42) OR D_op_rsvx43;
R_ctrl_shift_rot_right_nxt <= D_ctrl_shift_rot_right;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_rot_right <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end if;
end if;
end process;
D_ctrl_shift_rot <= ((((((((((((((D_op_slli OR D_op_rsvx50) OR D_op_sll) OR D_op_rsvx51) OR D_op_roli) OR D_op_rsvx34) OR D_op_rol) OR D_op_rsvx35) OR D_op_srli) OR D_op_srl) OR D_op_srai) OR D_op_sra) OR D_op_rsvx10) OR D_op_ror) OR D_op_rsvx42) OR D_op_rsvx43;
R_ctrl_shift_rot_nxt <= D_ctrl_shift_rot;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_shift_rot <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end if;
end if;
end process;
D_ctrl_logic <= ((((((((D_op_and OR D_op_or) OR D_op_xor) OR D_op_nor) OR D_op_andhi) OR D_op_orhi) OR D_op_xorhi) OR D_op_andi) OR D_op_ori) OR D_op_xori;
R_ctrl_logic_nxt <= D_ctrl_logic;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_logic <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_logic <= R_ctrl_logic_nxt;
end if;
end if;
end process;
D_ctrl_hi_imm16 <= (D_op_andhi OR D_op_orhi) OR D_op_xorhi;
R_ctrl_hi_imm16_nxt <= D_ctrl_hi_imm16;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_hi_imm16 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end if;
end if;
end process;
D_ctrl_unsigned_lo_imm16 <= (((((((((((D_op_cmpgeui OR D_op_cmpltui) OR D_op_andi) OR D_op_ori) OR D_op_xori) OR D_op_roli) OR D_op_rsvx10) OR D_op_slli) OR D_op_srli) OR D_op_rsvx34) OR D_op_rsvx42) OR D_op_rsvx50) OR D_op_srai;
R_ctrl_unsigned_lo_imm16_nxt <= D_ctrl_unsigned_lo_imm16;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_unsigned_lo_imm16 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end if;
end if;
end process;
D_ctrl_br_uncond <= D_op_br OR D_op_rsv02;
R_ctrl_br_uncond_nxt <= D_ctrl_br_uncond;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_br_uncond <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end if;
end if;
end process;
D_ctrl_br <= ((((((D_op_br OR D_op_bge) OR D_op_blt) OR D_op_bne) OR D_op_beq) OR D_op_bgeu) OR D_op_bltu) OR D_op_rsv62;
R_ctrl_br_nxt <= D_ctrl_br;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_br <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_br <= R_ctrl_br_nxt;
end if;
end if;
end process;
D_ctrl_alu_subtract <= ((((((((((((((D_op_sub OR D_op_rsvx25) OR D_op_cmplti) OR D_op_cmpltui) OR D_op_cmplt) OR D_op_cmpltu) OR D_op_blt) OR D_op_bltu) OR D_op_cmpgei) OR D_op_cmpgeui) OR D_op_cmpge) OR D_op_cmpgeu) OR D_op_bge) OR D_op_rsv10) OR D_op_bgeu) OR D_op_rsv42;
R_ctrl_alu_subtract_nxt <= D_ctrl_alu_subtract;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_alu_subtract <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end if;
end if;
end process;
D_ctrl_alu_signed_comparison <= ((((D_op_cmpge OR D_op_cmpgei) OR D_op_cmplt) OR D_op_cmplti) OR D_op_bge) OR D_op_blt;
R_ctrl_alu_signed_comparison_nxt <= D_ctrl_alu_signed_comparison;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_alu_signed_comparison <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end if;
end if;
end process;
D_ctrl_br_cmp <= ((((((((((((((((((((D_op_br OR D_op_bge) OR D_op_blt) OR D_op_bne) OR D_op_beq) OR D_op_bgeu) OR D_op_bltu) OR D_op_rsv62) OR D_op_cmpgei) OR D_op_cmplti) OR D_op_cmpnei) OR D_op_cmpgeui) OR D_op_cmpltui) OR D_op_cmpeqi) OR D_op_rsvx00) OR D_op_cmpge) OR D_op_cmplt) OR D_op_cmpne) OR D_op_cmpgeu) OR D_op_cmpltu) OR D_op_cmpeq) OR D_op_rsvx56;
R_ctrl_br_cmp_nxt <= D_ctrl_br_cmp;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_br_cmp <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end if;
end if;
end process;
D_ctrl_ld_signed <= ((((((D_op_ldb OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63;
R_ctrl_ld_signed_nxt <= D_ctrl_ld_signed;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld_signed <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end if;
end if;
end process;
D_ctrl_ld <= ((((((((((D_op_ldb OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63) OR D_op_ldbu) OR D_op_ldhu) OR D_op_ldbuio) OR D_op_ldhuio;
R_ctrl_ld_nxt <= D_ctrl_ld;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld <= R_ctrl_ld_nxt;
end if;
end if;
end process;
D_ctrl_ld_non_io <= ((((D_op_ldbu OR D_op_ldhu) OR D_op_ldb) OR D_op_ldh) OR D_op_ldw) OR D_op_ldl;
R_ctrl_ld_non_io_nxt <= D_ctrl_ld_non_io;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld_non_io <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end if;
end if;
end process;
D_ctrl_st <= ((((((D_op_stb OR D_op_sth) OR D_op_stw) OR D_op_stc) OR D_op_stbio) OR D_op_sthio) OR D_op_stwio) OR D_op_rsv61;
R_ctrl_st_nxt <= D_ctrl_st;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_st <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_st <= R_ctrl_st_nxt;
end if;
end if;
end process;
D_ctrl_ld_io <= ((((D_op_ldbuio OR D_op_ldhuio) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63;
R_ctrl_ld_io_nxt <= D_ctrl_ld_io;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ld_io <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end if;
end if;
end process;
D_ctrl_b_is_dst <= (((((((((((((((((((((((((((((((((((((D_op_addi OR D_op_andhi) OR D_op_orhi) OR D_op_xorhi) OR D_op_andi) OR D_op_ori) OR D_op_xori) OR D_op_call) OR D_op_rdprs) OR D_op_cmpgei) OR D_op_cmplti) OR D_op_cmpnei) OR D_op_cmpgeui) OR D_op_cmpltui) OR D_op_cmpeqi) OR D_op_jmpi) OR D_op_rsv09) OR D_op_rsv17) OR D_op_rsv25) OR D_op_rsv33) OR D_op_rsv41) OR D_op_rsv49) OR D_op_rsv57) OR D_op_ldb) OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63) OR D_op_ldbu) OR D_op_ldhu) OR D_op_ldbuio) OR D_op_ldhuio) OR D_op_initd) OR D_op_initda) OR D_op_flushd) OR D_op_flushda;
R_ctrl_b_is_dst_nxt <= D_ctrl_b_is_dst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_b_is_dst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end if;
end if;
end process;
D_ctrl_ignore_dst <= ((((((((((((((((((((((D_op_br OR D_op_bge) OR D_op_blt) OR D_op_bne) OR D_op_beq) OR D_op_bgeu) OR D_op_bltu) OR D_op_rsv62) OR D_op_stb) OR D_op_sth) OR D_op_stw) OR D_op_stc) OR D_op_stbio) OR D_op_sthio) OR D_op_stwio) OR D_op_rsv61) OR D_op_jmpi) OR D_op_rsv09) OR D_op_rsv17) OR D_op_rsv25) OR D_op_rsv33) OR D_op_rsv41) OR D_op_rsv49) OR D_op_rsv57;
R_ctrl_ignore_dst_nxt <= D_ctrl_ignore_dst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_ignore_dst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end if;
end if;
end process;
D_ctrl_src2_choose_imm <= (((((((((((((((((((((((((((((((((((((((((((((((((((((D_op_addi OR D_op_andhi) OR D_op_orhi) OR D_op_xorhi) OR D_op_andi) OR D_op_ori) OR D_op_xori) OR D_op_call) OR D_op_rdprs) OR D_op_cmpgei) OR D_op_cmplti) OR D_op_cmpnei) OR D_op_cmpgeui) OR D_op_cmpltui) OR D_op_cmpeqi) OR D_op_jmpi) OR D_op_rsv09) OR D_op_rsv17) OR D_op_rsv25) OR D_op_rsv33) OR D_op_rsv41) OR D_op_rsv49) OR D_op_rsv57) OR D_op_ldb) OR D_op_ldh) OR D_op_ldl) OR D_op_ldw) OR D_op_ldbio) OR D_op_ldhio) OR D_op_ldwio) OR D_op_rsv63) OR D_op_ldbu) OR D_op_ldhu) OR D_op_ldbuio) OR D_op_ldhuio) OR D_op_initd) OR D_op_initda) OR D_op_flushd) OR D_op_flushda) OR D_op_stb) OR D_op_sth) OR D_op_stw) OR D_op_stc) OR D_op_stbio) OR D_op_sthio) OR D_op_stwio) OR D_op_rsv61) OR D_op_roli) OR D_op_rsvx10) OR D_op_slli) OR D_op_srli) OR D_op_rsvx34) OR D_op_rsvx42) OR D_op_rsvx50) OR D_op_srai;
R_ctrl_src2_choose_imm_nxt <= D_ctrl_src2_choose_imm;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_src2_choose_imm <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end if;
end if;
end process;
D_ctrl_wrctl_inst <= D_op_wrctl;
R_ctrl_wrctl_inst_nxt <= D_ctrl_wrctl_inst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_wrctl_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end if;
end if;
end process;
D_ctrl_rdctl_inst <= D_op_rdctl;
R_ctrl_rdctl_inst_nxt <= D_ctrl_rdctl_inst;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_rdctl_inst <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end if;
end if;
end process;
D_ctrl_force_src2_zero <= ((((((((((((((((D_op_call OR D_op_rsv02) OR D_op_nextpc) OR D_op_callr) OR D_op_trap) OR D_op_rsvx44) OR D_op_intr) OR D_op_rsvx60) OR D_op_break) OR D_op_hbreak) OR D_op_eret) OR D_op_bret) OR D_op_rsvx17) OR D_op_rsvx25) OR D_op_ret) OR D_op_jmp) OR D_op_rsvx21) OR D_op_jmpi;
R_ctrl_force_src2_zero_nxt <= D_ctrl_force_src2_zero;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_force_src2_zero <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end if;
end if;
end process;
D_ctrl_alu_force_xor <= ((((((((((((((((D_op_cmpgei OR D_op_cmpgeui) OR D_op_cmpeqi) OR D_op_cmpge) OR D_op_cmpgeu) OR D_op_cmpeq) OR D_op_cmpnei) OR D_op_cmpne) OR D_op_bge) OR D_op_rsv10) OR D_op_bgeu) OR D_op_rsv42) OR D_op_beq) OR D_op_rsv34) OR D_op_bne) OR D_op_rsv62) OR D_op_br) OR D_op_rsv02;
R_ctrl_alu_force_xor_nxt <= D_ctrl_alu_force_xor;
process (clk, reset_n)
begin
if reset_n = '0' then
R_ctrl_alu_force_xor <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(R_en) = '1' then
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end if;
end if;
end process;
--data_master, which is an e_avalon_master
--instruction_master, which is an e_avalon_master
--vhdl renameroo for output signals
d_address <= internal_d_address;
--vhdl renameroo for output signals
d_byteenable <= internal_d_byteenable;
--vhdl renameroo for output signals
d_read <= internal_d_read;
--vhdl renameroo for output signals
d_write <= internal_d_write;
--vhdl renameroo for output signals
i_address <= internal_i_address;
--vhdl renameroo for output signals
i_read <= internal_i_read;
--vhdl renameroo for output signals
jtag_debug_module_debugaccess_to_roms <= internal_jtag_debug_module_debugaccess_to_roms;
--vhdl renameroo for output signals
jtag_debug_module_readdata <= internal_jtag_debug_module_readdata;
--vhdl renameroo for output signals
jtag_debug_module_resetrequest <= internal_jtag_debug_module_resetrequest;
--synthesis translate_off
F_inst <= A_WE_StdLogicVector((std_logic'((F_op_call)) = '1'), std_logic_vector'("00100000001000000010000001100011011000010110110001101100"), A_WE_StdLogicVector((std_logic'((F_op_jmpi)) = '1'), std_logic_vector'("00100000001000000010000001101010011011010111000001101001"), A_WE_StdLogicVector((std_logic'((F_op_ldbu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110001001110101"), A_WE_StdLogicVector((std_logic'((F_op_addi)) = '1'), std_logic_vector'("00100000001000000010000001100001011001000110010001101001"), A_WE_StdLogicVector((std_logic'((F_op_stb)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001100010"), A_WE_StdLogicVector((std_logic'((F_op_br)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110001001110010"), A_WE_StdLogicVector((std_logic'((F_op_ldb)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001100010"), A_WE_StdLogicVector((std_logic'((F_op_cmpgei)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101101001"), A_WE_StdLogicVector((std_logic'((F_op_ldhu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110100001110101"), A_WE_StdLogicVector((std_logic'((F_op_andi)) = '1'), std_logic_vector'("00100000001000000010000001100001011011100110010001101001"), A_WE_StdLogicVector((std_logic'((F_op_sth)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001101000"), A_WE_StdLogicVector((std_logic'((F_op_bge)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110011101100101"), A_WE_StdLogicVector((std_logic'((F_op_ldh)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001101000"), A_WE_StdLogicVector((std_logic'((F_op_cmplti)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001101001"), A_WE_StdLogicVector((std_logic'((F_op_initda)) = '1'), std_logic_vector'("00100000011010010110111001101001011101000110010001100001"), A_WE_StdLogicVector((std_logic'((F_op_ori)) = '1'), std_logic_vector'("00100000001000000010000000100000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((F_op_stw)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001110111"), A_WE_StdLogicVector((std_logic'((F_op_blt)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110110001110100"), A_WE_StdLogicVector((std_logic'((F_op_ldw)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001110111"), A_WE_StdLogicVector((std_logic'((F_op_cmpnei)) = '1'), std_logic_vector'("00100000011000110110110101110000011011100110010101101001"), A_WE_StdLogicVector((std_logic'((F_op_flushda)) = '1'), std_logic_vector'("01100110011011000111010101110011011010000110010001100001"), A_WE_StdLogicVector((std_logic'((F_op_xori)) = '1'), std_logic_vector'("00100000001000000010000001111000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((F_op_bne)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110111001100101"), A_WE_StdLogicVector((std_logic'((F_op_cmpeqi)) = '1'), std_logic_vector'("00100000011000110110110101110000011001010111000101101001"), A_WE_StdLogicVector((std_logic'((F_op_ldbuio)) = '1'), std_logic_vector'("00100000011011000110010001100010011101010110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_muli)) = '1'), std_logic_vector'("00100000001000000010000001101101011101010110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_stbio)) = '1'), std_logic_vector'("00100000001000000111001101110100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_beq)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110010101110001"), A_WE_StdLogicVector((std_logic'((F_op_ldbio)) = '1'), std_logic_vector'("00100000001000000110110001100100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_cmpgeui)) = '1'), std_logic_vector'("01100011011011010111000001100111011001010111010101101001"), A_WE_StdLogicVector((std_logic'((F_op_ldhuio)) = '1'), std_logic_vector'("00100000011011000110010001101000011101010110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_andhi)) = '1'), std_logic_vector'("00100000001000000110000101101110011001000110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_sthio)) = '1'), std_logic_vector'("00100000001000000111001101110100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_bgeu)) = '1'), std_logic_vector'("00100000001000000010000001100010011001110110010101110101"), A_WE_StdLogicVector((std_logic'((F_op_ldhio)) = '1'), std_logic_vector'("00100000001000000110110001100100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_cmpltui)) = '1'), std_logic_vector'("01100011011011010111000001101100011101000111010101101001"), A_WE_StdLogicVector((std_logic'((F_op_initd)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001100100"), A_WE_StdLogicVector((std_logic'((F_op_orhi)) = '1'), std_logic_vector'("00100000001000000010000001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_stwio)) = '1'), std_logic_vector'("00100000001000000111001101110100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_bltu)) = '1'), std_logic_vector'("00100000001000000010000001100010011011000111010001110101"), A_WE_StdLogicVector((std_logic'((F_op_ldwio)) = '1'), std_logic_vector'("00100000001000000110110001100100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((F_op_flushd)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001100100"), A_WE_StdLogicVector((std_logic'((F_op_xorhi)) = '1'), std_logic_vector'("00100000001000000111100001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_eret)) = '1'), std_logic_vector'("00100000001000000010000001100101011100100110010101110100"), A_WE_StdLogicVector((std_logic'((F_op_roli)) = '1'), std_logic_vector'("00100000001000000010000001110010011011110110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_rol)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101101100"), A_WE_StdLogicVector((std_logic'((F_op_flushp)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001110000"), A_WE_StdLogicVector((std_logic'((F_op_ret)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110010101110100"), A_WE_StdLogicVector((std_logic'((F_op_nor)) = '1'), std_logic_vector'("00100000001000000010000000100000011011100110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_mulxuu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111010101110101"), A_WE_StdLogicVector((std_logic'((F_op_cmpge)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110011101100101"), A_WE_StdLogicVector((std_logic'((F_op_bret)) = '1'), std_logic_vector'("00100000001000000010000001100010011100100110010101110100"), A_WE_StdLogicVector((std_logic'((F_op_ror)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_flushi)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001101001"), A_WE_StdLogicVector((std_logic'((F_op_jmp)) = '1'), std_logic_vector'("00100000001000000010000000100000011010100110110101110000"), A_WE_StdLogicVector((std_logic'((F_op_and)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110111001100100"), A_WE_StdLogicVector((std_logic'((F_op_cmplt)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110110001110100"), A_WE_StdLogicVector((std_logic'((F_op_slli)) = '1'), std_logic_vector'("00100000001000000010000001110011011011000110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_sll)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110110110001101100"), A_WE_StdLogicVector((std_logic'((F_op_or)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_mulxsu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110101"), A_WE_StdLogicVector((std_logic'((F_op_cmpne)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110111001100101"), A_WE_StdLogicVector((std_logic'((F_op_srli)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110110001101001"), A_WE_StdLogicVector((std_logic'((F_op_srl)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001101100"), A_WE_StdLogicVector((std_logic'((F_op_nextpc)) = '1'), std_logic_vector'("00100000011011100110010101111000011101000111000001100011"), A_WE_StdLogicVector((std_logic'((F_op_callr)) = '1'), std_logic_vector'("00100000001000000110001101100001011011000110110001110010"), A_WE_StdLogicVector((std_logic'((F_op_xor)) = '1'), std_logic_vector'("00100000001000000010000000100000011110000110111101110010"), A_WE_StdLogicVector((std_logic'((F_op_mulxss)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110011"), A_WE_StdLogicVector((std_logic'((F_op_cmpeq)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110010101110001"), A_WE_StdLogicVector((std_logic'((F_op_divu)) = '1'), std_logic_vector'("00100000001000000010000001100100011010010111011001110101"), A_WE_StdLogicVector((std_logic'((F_op_div)) = '1'), std_logic_vector'("00100000001000000010000000100000011001000110100101110110"), A_WE_StdLogicVector((std_logic'((F_op_rdctl)) = '1'), std_logic_vector'("00100000001000000111001001100100011000110111010001101100"), A_WE_StdLogicVector((std_logic'((F_op_mul)) = '1'), std_logic_vector'("00100000001000000010000000100000011011010111010101101100"), A_WE_StdLogicVector((std_logic'((F_op_cmpgeu)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101110101"), A_WE_StdLogicVector((std_logic'((F_op_initi)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001101001"), A_WE_StdLogicVector((std_logic'((F_op_trap)) = '1'), std_logic_vector'("00100000001000000010000001110100011100100110000101110000"), A_WE_StdLogicVector((std_logic'((F_op_wrctl)) = '1'), std_logic_vector'("00100000001000000111011101110010011000110111010001101100"), A_WE_StdLogicVector((std_logic'((F_op_cmpltu)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001110101"), A_WE_StdLogicVector((std_logic'((F_op_add)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110010001100100"), A_WE_StdLogicVector((std_logic'((F_op_break)) = '1'), std_logic_vector'("00100000001000000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((F_op_hbreak)) = '1'), std_logic_vector'("00100000011010000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((F_op_sync)) = '1'), std_logic_vector'("00100000001000000010000001110011011110010110111001100011"), A_WE_StdLogicVector((std_logic'((F_op_sub)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010101100010"), A_WE_StdLogicVector((std_logic'((F_op_srai)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110000101101001"), A_WE_StdLogicVector((std_logic'((F_op_sra)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001100001"), A_WE_StdLogicVector((std_logic'((F_op_intr)) = '1'), std_logic_vector'("00100000001000000010000001101001011011100111010001110010"), std_logic_vector'("00100000001000000010000000100000010000100100000101000100")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));
D_inst <= A_WE_StdLogicVector((std_logic'((D_op_call)) = '1'), std_logic_vector'("00100000001000000010000001100011011000010110110001101100"), A_WE_StdLogicVector((std_logic'((D_op_jmpi)) = '1'), std_logic_vector'("00100000001000000010000001101010011011010111000001101001"), A_WE_StdLogicVector((std_logic'((D_op_ldbu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110001001110101"), A_WE_StdLogicVector((std_logic'((D_op_addi)) = '1'), std_logic_vector'("00100000001000000010000001100001011001000110010001101001"), A_WE_StdLogicVector((std_logic'((D_op_stb)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001100010"), A_WE_StdLogicVector((std_logic'((D_op_br)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110001001110010"), A_WE_StdLogicVector((std_logic'((D_op_ldb)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001100010"), A_WE_StdLogicVector((std_logic'((D_op_cmpgei)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101101001"), A_WE_StdLogicVector((std_logic'((D_op_ldhu)) = '1'), std_logic_vector'("00100000001000000010000001101100011001000110100001110101"), A_WE_StdLogicVector((std_logic'((D_op_andi)) = '1'), std_logic_vector'("00100000001000000010000001100001011011100110010001101001"), A_WE_StdLogicVector((std_logic'((D_op_sth)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001101000"), A_WE_StdLogicVector((std_logic'((D_op_bge)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110011101100101"), A_WE_StdLogicVector((std_logic'((D_op_ldh)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001101000"), A_WE_StdLogicVector((std_logic'((D_op_cmplti)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001101001"), A_WE_StdLogicVector((std_logic'((D_op_initda)) = '1'), std_logic_vector'("00100000011010010110111001101001011101000110010001100001"), A_WE_StdLogicVector((std_logic'((D_op_ori)) = '1'), std_logic_vector'("00100000001000000010000000100000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((D_op_stw)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010001110111"), A_WE_StdLogicVector((std_logic'((D_op_blt)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110110001110100"), A_WE_StdLogicVector((std_logic'((D_op_ldw)) = '1'), std_logic_vector'("00100000001000000010000000100000011011000110010001110111"), A_WE_StdLogicVector((std_logic'((D_op_cmpnei)) = '1'), std_logic_vector'("00100000011000110110110101110000011011100110010101101001"), A_WE_StdLogicVector((std_logic'((D_op_flushda)) = '1'), std_logic_vector'("01100110011011000111010101110011011010000110010001100001"), A_WE_StdLogicVector((std_logic'((D_op_xori)) = '1'), std_logic_vector'("00100000001000000010000001111000011011110111001001101001"), A_WE_StdLogicVector((std_logic'((D_op_bne)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110111001100101"), A_WE_StdLogicVector((std_logic'((D_op_cmpeqi)) = '1'), std_logic_vector'("00100000011000110110110101110000011001010111000101101001"), A_WE_StdLogicVector((std_logic'((D_op_ldbuio)) = '1'), std_logic_vector'("00100000011011000110010001100010011101010110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_muli)) = '1'), std_logic_vector'("00100000001000000010000001101101011101010110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_stbio)) = '1'), std_logic_vector'("00100000001000000111001101110100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_beq)) = '1'), std_logic_vector'("00100000001000000010000000100000011000100110010101110001"), A_WE_StdLogicVector((std_logic'((D_op_ldbio)) = '1'), std_logic_vector'("00100000001000000110110001100100011000100110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_cmpgeui)) = '1'), std_logic_vector'("01100011011011010111000001100111011001010111010101101001"), A_WE_StdLogicVector((std_logic'((D_op_ldhuio)) = '1'), std_logic_vector'("00100000011011000110010001101000011101010110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_andhi)) = '1'), std_logic_vector'("00100000001000000110000101101110011001000110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_sthio)) = '1'), std_logic_vector'("00100000001000000111001101110100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_bgeu)) = '1'), std_logic_vector'("00100000001000000010000001100010011001110110010101110101"), A_WE_StdLogicVector((std_logic'((D_op_ldhio)) = '1'), std_logic_vector'("00100000001000000110110001100100011010000110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_cmpltui)) = '1'), std_logic_vector'("01100011011011010111000001101100011101000111010101101001"), A_WE_StdLogicVector((std_logic'((D_op_initd)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001100100"), A_WE_StdLogicVector((std_logic'((D_op_orhi)) = '1'), std_logic_vector'("00100000001000000010000001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_stwio)) = '1'), std_logic_vector'("00100000001000000111001101110100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_bltu)) = '1'), std_logic_vector'("00100000001000000010000001100010011011000111010001110101"), A_WE_StdLogicVector((std_logic'((D_op_ldwio)) = '1'), std_logic_vector'("00100000001000000110110001100100011101110110100101101111"), A_WE_StdLogicVector((std_logic'((D_op_flushd)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001100100"), A_WE_StdLogicVector((std_logic'((D_op_xorhi)) = '1'), std_logic_vector'("00100000001000000111100001101111011100100110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_eret)) = '1'), std_logic_vector'("00100000001000000010000001100101011100100110010101110100"), A_WE_StdLogicVector((std_logic'((D_op_roli)) = '1'), std_logic_vector'("00100000001000000010000001110010011011110110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_rol)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101101100"), A_WE_StdLogicVector((std_logic'((D_op_flushp)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001110000"), A_WE_StdLogicVector((std_logic'((D_op_ret)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110010101110100"), A_WE_StdLogicVector((std_logic'((D_op_nor)) = '1'), std_logic_vector'("00100000001000000010000000100000011011100110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_mulxuu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111010101110101"), A_WE_StdLogicVector((std_logic'((D_op_cmpge)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110011101100101"), A_WE_StdLogicVector((std_logic'((D_op_bret)) = '1'), std_logic_vector'("00100000001000000010000001100010011100100110010101110100"), A_WE_StdLogicVector((std_logic'((D_op_ror)) = '1'), std_logic_vector'("00100000001000000010000000100000011100100110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_flushi)) = '1'), std_logic_vector'("00100000011001100110110001110101011100110110100001101001"), A_WE_StdLogicVector((std_logic'((D_op_jmp)) = '1'), std_logic_vector'("00100000001000000010000000100000011010100110110101110000"), A_WE_StdLogicVector((std_logic'((D_op_and)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110111001100100"), A_WE_StdLogicVector((std_logic'((D_op_cmplt)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110110001110100"), A_WE_StdLogicVector((std_logic'((D_op_slli)) = '1'), std_logic_vector'("00100000001000000010000001110011011011000110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_sll)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110110110001101100"), A_WE_StdLogicVector((std_logic'((D_op_or)) = '1'), std_logic_vector'("00100000001000000010000000100000001000000110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_mulxsu)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110101"), A_WE_StdLogicVector((std_logic'((D_op_cmpne)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110111001100101"), A_WE_StdLogicVector((std_logic'((D_op_srli)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110110001101001"), A_WE_StdLogicVector((std_logic'((D_op_srl)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001101100"), A_WE_StdLogicVector((std_logic'((D_op_nextpc)) = '1'), std_logic_vector'("00100000011011100110010101111000011101000111000001100011"), A_WE_StdLogicVector((std_logic'((D_op_callr)) = '1'), std_logic_vector'("00100000001000000110001101100001011011000110110001110010"), A_WE_StdLogicVector((std_logic'((D_op_xor)) = '1'), std_logic_vector'("00100000001000000010000000100000011110000110111101110010"), A_WE_StdLogicVector((std_logic'((D_op_mulxss)) = '1'), std_logic_vector'("00100000011011010111010101101100011110000111001101110011"), A_WE_StdLogicVector((std_logic'((D_op_cmpeq)) = '1'), std_logic_vector'("00100000001000000110001101101101011100000110010101110001"), A_WE_StdLogicVector((std_logic'((D_op_divu)) = '1'), std_logic_vector'("00100000001000000010000001100100011010010111011001110101"), A_WE_StdLogicVector((std_logic'((D_op_div)) = '1'), std_logic_vector'("00100000001000000010000000100000011001000110100101110110"), A_WE_StdLogicVector((std_logic'((D_op_rdctl)) = '1'), std_logic_vector'("00100000001000000111001001100100011000110111010001101100"), A_WE_StdLogicVector((std_logic'((D_op_mul)) = '1'), std_logic_vector'("00100000001000000010000000100000011011010111010101101100"), A_WE_StdLogicVector((std_logic'((D_op_cmpgeu)) = '1'), std_logic_vector'("00100000011000110110110101110000011001110110010101110101"), A_WE_StdLogicVector((std_logic'((D_op_initi)) = '1'), std_logic_vector'("00100000001000000110100101101110011010010111010001101001"), A_WE_StdLogicVector((std_logic'((D_op_trap)) = '1'), std_logic_vector'("00100000001000000010000001110100011100100110000101110000"), A_WE_StdLogicVector((std_logic'((D_op_wrctl)) = '1'), std_logic_vector'("00100000001000000111011101110010011000110111010001101100"), A_WE_StdLogicVector((std_logic'((D_op_cmpltu)) = '1'), std_logic_vector'("00100000011000110110110101110000011011000111010001110101"), A_WE_StdLogicVector((std_logic'((D_op_add)) = '1'), std_logic_vector'("00100000001000000010000000100000011000010110010001100100"), A_WE_StdLogicVector((std_logic'((D_op_break)) = '1'), std_logic_vector'("00100000001000000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((D_op_hbreak)) = '1'), std_logic_vector'("00100000011010000110001001110010011001010110000101101011"), A_WE_StdLogicVector((std_logic'((D_op_sync)) = '1'), std_logic_vector'("00100000001000000010000001110011011110010110111001100011"), A_WE_StdLogicVector((std_logic'((D_op_sub)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111010101100010"), A_WE_StdLogicVector((std_logic'((D_op_srai)) = '1'), std_logic_vector'("00100000001000000010000001110011011100100110000101101001"), A_WE_StdLogicVector((std_logic'((D_op_sra)) = '1'), std_logic_vector'("00100000001000000010000000100000011100110111001001100001"), A_WE_StdLogicVector((std_logic'((D_op_intr)) = '1'), std_logic_vector'("00100000001000000010000001101001011011100111010001110010"), std_logic_vector'("00100000001000000010000000100000010000100100000101000100")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));
F_vinst <= A_WE_StdLogicVector((std_logic'(F_valid) = '1'), F_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
D_vinst <= A_WE_StdLogicVector((std_logic'(D_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
R_vinst <= A_WE_StdLogicVector((std_logic'(R_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
E_vinst <= A_WE_StdLogicVector((std_logic'(E_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
W_vinst <= A_WE_StdLogicVector((std_logic'(W_valid) = '1'), D_inst, A_REP_VECTOR(std_logic_vector'("00101101"), 7));
--synthesis translate_on
end europa;
|
-- NEED RESULT: ARCH00292: Floating point types and predefined floating point types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00292
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1.4 (1)
-- 3.1.4 (2)
-- 3.1.4 (3)
-- 3.1.4.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00292)
-- ENT00292_Test_Bench(ARCH00292_Test_Bench)
--
-- REVISION HISTORY:
--
-- 22-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00292 of E00000 is
begin
P :
process
type negative_interval is range -1.0 to 0.0 ;
type positive_interval is range 0.0 to +1.0 ;
-- this tests 3.1.4 (1)
type symmetric_interval is range
negative_interval'left to positive_interval'right ;
-- this tests 3.1.4 (3)
type backward_interval is range
positive_interval'right downto negative_interval'left ;
-- this tests 3.1.4 (2)
type big_interval is range -1.0E31 to +1.0E31 ;
begin
test_report ( "ARCH00292" ,
"Floating point types and predefined floating point types" ,
(symmetric_interval'left = -1.0) and
(symmetric_interval'right = +1.0) and
(backward_interval'left = +1.0) and
(backward_interval'right = -1.0) and
(big_interval'left = -1.0E31) and
(big_interval'right = +1.0E31) and
-- these test 3.1.4.1 (1) :
(real'left < real'right) and
(real'left <= -1.0E31) and
(real'right >= +1.0E31)
) ;
wait ;
end process P ;
end ARCH00292 ;
entity ENT00292_Test_Bench is
end ENT00292_Test_Bench ;
architecture ARCH00292_Test_Bench of ENT00292_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00292 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00292_Test_Bench ;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_10_2 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_10_2;
ARCHITECTURE sys_axi_nic_10_2_arch OF sys_axi_nic_10_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_10_2_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_10_2_arch;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: i2s_data_interface - Behavioral
-- Description: Send & Receive I2S data
-- New_sample is asserted for one cycle when a new sample has been
-- received (and one transmitted)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2s_data_interface is
Port ( clk : in STD_LOGIC;
audio_l_in : in STD_LOGIC_VECTOR (23 downto 0);
audio_r_in : in STD_LOGIC_VECTOR (23 downto 0);
audio_l_out : out STD_LOGIC_VECTOR (23 downto 0);
audio_r_out : out STD_LOGIC_VECTOR (23 downto 0);
new_sample : out STD_LOGIC;
i2s_bclk : in STD_LOGIC;
i2s_d_out : out STD_LOGIC;
i2s_d_in : in STD_LOGIC;
i2s_lr : in STD_LOGIC);
end i2s_data_interface;
architecture Behavioral of i2s_data_interface is
signal bit_counter : unsigned(5 downto 0) := (others => '0');
signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0');
signal lr_delay : std_logic_vector(9 downto 0) := (others => '0');
signal sr_in : std_logic_vector(126 downto 0) := (others => '0');
signal sr_out : std_logic_vector(63 downto 0) := (others => '0');
signal i2s_lr_last : std_logic := '0';
signal i2s_d_in_last : std_logic := '0';
begin
process(clk)
begin
-- Process to predict when the falling edge of i2s_bclk should be
if rising_edge(clk) then
new_sample <= '0';
------------------------------
-- is there a rising edge two cycles ago? If so the data bit is
-- validand we can capture a bit
------------------------------
if bclk_delay(bclk_delay'high-1 downto bclk_delay'high-2) = "10" then
sr_in <= sr_in(sr_in'high-1 downto 0) & i2s_d_in_last;
end if;
------------------------------
-- Was there a rising edge on BCLK 9 cycles ago?
-- If so, this should be about the falling edge so
-- the output can change.
------------------------------
if bclk_delay(1 downto 0) = "10" then
i2s_d_out <= sr_out(sr_out'high);
-- if we are starting a new frame, then load the samples into the shift register
if i2s_lr = '1' and i2s_lr_last = '0' then
audio_l_out <= sr_in(sr_in'high downto sr_in'high-23);
audio_r_out <= sr_in(sr_in'high-32 downto sr_in'high-23-32);
sr_out <= audio_l_in & x"00" & audio_r_in & x"00";
new_sample <= '1';
else
sr_out <= sr_out(sr_out'high-1 downto 0) & '0';
end if;
-- remember what lr was, for edge detection
i2s_lr_last <= i2s_lr;
end if;
bclk_delay <= i2s_bclk & bclk_delay(bclk_delay'high downto 1);
i2s_d_in_last <= i2s_d_in;
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: i2s_data_interface - Behavioral
-- Description: Send & Receive I2S data
-- New_sample is asserted for one cycle when a new sample has been
-- received (and one transmitted)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2s_data_interface is
Port ( clk : in STD_LOGIC;
audio_l_in : in STD_LOGIC_VECTOR (23 downto 0);
audio_r_in : in STD_LOGIC_VECTOR (23 downto 0);
audio_l_out : out STD_LOGIC_VECTOR (23 downto 0);
audio_r_out : out STD_LOGIC_VECTOR (23 downto 0);
new_sample : out STD_LOGIC;
i2s_bclk : in STD_LOGIC;
i2s_d_out : out STD_LOGIC;
i2s_d_in : in STD_LOGIC;
i2s_lr : in STD_LOGIC);
end i2s_data_interface;
architecture Behavioral of i2s_data_interface is
signal bit_counter : unsigned(5 downto 0) := (others => '0');
signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0');
signal lr_delay : std_logic_vector(9 downto 0) := (others => '0');
signal sr_in : std_logic_vector(126 downto 0) := (others => '0');
signal sr_out : std_logic_vector(63 downto 0) := (others => '0');
signal i2s_lr_last : std_logic := '0';
signal i2s_d_in_last : std_logic := '0';
begin
process(clk)
begin
-- Process to predict when the falling edge of i2s_bclk should be
if rising_edge(clk) then
new_sample <= '0';
------------------------------
-- is there a rising edge two cycles ago? If so the data bit is
-- validand we can capture a bit
------------------------------
if bclk_delay(bclk_delay'high-1 downto bclk_delay'high-2) = "10" then
sr_in <= sr_in(sr_in'high-1 downto 0) & i2s_d_in_last;
end if;
------------------------------
-- Was there a rising edge on BCLK 9 cycles ago?
-- If so, this should be about the falling edge so
-- the output can change.
------------------------------
if bclk_delay(1 downto 0) = "10" then
i2s_d_out <= sr_out(sr_out'high);
-- if we are starting a new frame, then load the samples into the shift register
if i2s_lr = '1' and i2s_lr_last = '0' then
audio_l_out <= sr_in(sr_in'high downto sr_in'high-23);
audio_r_out <= sr_in(sr_in'high-32 downto sr_in'high-23-32);
sr_out <= audio_l_in & x"00" & audio_r_in & x"00";
new_sample <= '1';
else
sr_out <= sr_out(sr_out'high-1 downto 0) & '0';
end if;
-- remember what lr was, for edge detection
i2s_lr_last <= i2s_lr;
end if;
bclk_delay <= i2s_bclk & bclk_delay(bclk_delay'high downto 1);
i2s_d_in_last <= i2s_d_in;
end if;
end process;
end Behavioral; |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_io is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
intready: in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type := (others => (others => DontCareValue) );
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type := (others => '1');
slot_interrupt: in slot_std_logic_type := (others => '0' )
);
end entity zpuino_io;
architecture behave of zpuino_io is
constant io_registered_read: boolean := true;
signal ivecs: std_logic_vector(17 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_cyc: std_logic;
signal io_stb: std_logic;
signal io_we: std_logic;
signal io_device_ack: std_logic;
signal io_read_selected: cpuword_type;
signal wb_in_transaction: std_logic;
-- I/O Signals
signal slot_cyc_i: slot_std_logic_type;
signal slot_we_i: slot_std_logic_type;
signal slot_stb_i: slot_std_logic_type;
signal slot_read_i: slot_cpuword_type;
signal slot_write_i: slot_cpuword_type;
signal slot_address_i: slot_address_type;
signal slot_ack_i: slot_std_logic_type;
signal slot_interrupt_i: slot_std_logic_type;
signal timer_read: std_logic_vector(wordSize-1 downto 0);
signal timer_ack: std_logic;
begin
slot_cyc <= slot_cyc_i;
slot_we <= slot_we_i;
slot_stb <= slot_stb_i;
slot_read_i <= slot_read;
slot_write <= slot_write_i;
slot_address <= slot_address_i;
slot_ack_i <= slot_ack;
slot_interrupt_i <= slot_interrupt;
-- Ack generator (We have an hack for slot4 here)
process(slot_ack_i, timer_ack)
begin
io_device_ack <= '0';
for i in 0 to num_devices-1 loop
if i/=4 then
if slot_ack_i(i) = '1' then
io_device_ack<='1';
end if;
end if;
end loop;
if timer_ack='1' then
io_device_ack<='1';
end if;
end process;
iobusy: if zpuino_iobusyinput=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_in_transaction <= '0';
else
if wb_in_transaction='0' then
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
elsif io_device_ack='1' then
io_stb<='0';
--io_we<='0'; -- safe side
-- How to keep cyc ????
end if;
if wb_cyc_i='1' then
wb_in_transaction<='1';
else
io_cyc <= '0';
wb_in_transaction<='0';
end if;
if wb_stb_i='1' and wb_cyc_i='1' then
addr_save_q <= wb_adr_i;
end if;
if wb_we_i='1' then
write_save_q <= wb_dat_i;
end if;
end if;
end if;
end process;
io_address <= addr_save_q;
io_write <= write_save_q;
rread: if io_registered_read=true generate
-- Read/ack
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o<='0';
wb_dat_o<=(others => DontCareValue);
else
wb_ack_o <= io_device_ack;
wb_dat_o <= io_read_selected;
end if;
end if;
end process;
end generate;
nrread: if io_registered_read=false generate
process(io_device_ack)
begin
wb_ack_o <= io_device_ack;
end process;
process(io_read_selected)
begin
wb_dat_o <= io_read_selected;
end process;
end generate;
end generate;
noiobusy: if zpuino_iobusyinput=false generate
-- TODO: remove this
io_address <= wb_adr_i;
io_write <= wb_dat_i;
io_cyc <= wb_cyc_i;
io_stb <= wb_stb_i;
io_we <= wb_we_i;
wb_ack_o <= io_device_ack;
end generate;
-- Interrupt vectors
process(slot_interrupt_i)
begin
for i in 0 to num_devices-1 loop
ivecs(i) <= slot_interrupt_i(i);
end loop;
end process;
-- Write and address signals, shared by all slots
process(wb_dat_i,wb_adr_i,io_write,io_address)
begin
for i in 0 to num_devices-1 loop
slot_write_i(i) <= io_write;
slot_address_i(i) <= io_address(maxAddrBitIncIO-1 downto 2);
end loop;
end process;
process(io_address,slot_read_i,timer_read)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
if slotNumber/=4 then
io_read_selected <= slot_read_i(slotNumber);
else
io_read_selected <= timer_read;
end if;
end process;
-- Enable signals
process(io_address,wb_stb_i,wb_cyc_i,wb_we_i,io_stb,io_cyc,io_we)
variable slotNumber: integer range 0 to num_devices-1;
begin
slotNumber := to_integer(unsigned(io_address(maxAddrBitIncIO-1 downto maxAddrBitIncIO-zpuino_number_io_select_bits)));
for i in 0 to num_devices-1 loop
slot_stb_i(i) <= io_stb;
slot_we_i(i) <= io_we;
if i = slotNumber then
slot_cyc_i(i) <= io_cyc;
else
slot_cyc_i(i) <= '0';
end if;
end loop;
end process;
--
-- IO SLOT 4
--
intr_inst: zpuino_intr
generic map (
INTERRUPT_LINES => 18
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer_read,
wb_dat_i => slot_write_i(4),
wb_adr_i => slot_address_i(4),
wb_we_i => slot_we_i(4),
wb_cyc_i => slot_cyc_i(4),
wb_stb_i => slot_stb_i(4),
wb_ack_o => timer_ack,--slot_ack_i(4),
wb_inta_o => wb_inta_o, -- Interrupt signal to core
poppc_inst=> intready,
cache_flush => cache_flush,
memory_enable => memory_enable,
intr_in => ivecs,
intr_cfglvl => "110000000000000000"
);
end behave;
|
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