content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Feb 15 09:42:21 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE -nodelta ../../macro.xls
--
-- !!! Do not edit this fi... |
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.... |
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.... |
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:25 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
f... |
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
f... |
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
f... |
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
f... |
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
f... |
library ieee;
use ieee.std_logic_1164.all;
entity and6 is
port (i0, i1, i2, i3, i4, i5 : std_logic;
o : out std_logic);
end and6;
architecture behav of and6 is
component and3 is
port (a, b, c : std_logic;
o : out std_logic);
end component;
signal t1, t2 : std_logic;
begin
a1: and3
... |
------------------------------------------------------------------------------
--! Copyright (C) 2017 , Emmanuel Amadio
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code m... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
--!
--! Copyright 2019 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
-- Title : On Board Programer (OBP, WB-debuger simplification)
-- Project : OBP
-------------------------------------------------------------------------------
-- File : obp.vhd
-- Author : Jose Jimenez Montañez, Miguel Jimenez Lopez
-- Company : University of Granada (UGR)
-- Created : 2014-06-... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity MeioSomador4Bits is
port(
HEX0 : out vl_logic_vector(6 downto 0);
HEX1 : out vl_logic_vector(6 downto 0);
LEDR : out vl_logic_vector(4 downto 0);
SW : in vl_logic_vector(8 dow... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:20 2017
-- Host : WK117 running 64-bit major release ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debounce is
generic(non_sampling_clk_cycles_num : integer := 15000000); -- number of clock cycles that the button value is not sampled
-- for ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
package bpm_cores_pkg is
-------------------------------------------------------------------------------
-- Types
----------------------------------------------------------... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
-- NEED RESULT: ARCH00065.P1_1: Next with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00065.P1_1: Next with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00065.P1_1: Next statement does not effect outer loop passed
-- NEED RESULT: ARCH00065.P1_2: Next... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: Counter3bMOD5.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: Counter3bMOD5.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================... |
-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Triplicate data on write.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Decoder
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Decoder is
gen... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:50:37 04/01/2017
-- Design Name:
-- Module Name: shifregister_5bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Depend... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gray_compare is
generic (
width : positive
);
port (
-- These gray counters are interpreted as the MSB being a looped indicator
-- and the rest being the actual value. Invert the MSB of the value
-- (that is, gray(width... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gray_compare is
generic (
width : positive
);
port (
-- These gray counters are interpreted as the MSB being a looped indicator
-- and the rest being the actual value. Invert the MSB of the value
-- (that is, gray(width... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Test_Pattern_Generator_example is
end entity;
architecture rtl of tb_Test_Pattern_Generator_example is
component tb_Test_Pattern_Generator
end component;
begin
tb_Test_Pattern_Generator_instance :
component tb_Test_Pattern_Genera... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Test_Pattern_Generator_example is
end entity;
architecture rtl of tb_Test_Pattern_Generator_example is
component tb_Test_Pattern_Generator
end component;
begin
tb_Test_Pattern_Generator_instance :
component tb_Test_Pattern_Genera... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
----------------------------... |
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_data_steer.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Data_Steer - entity/architecture pair
----------------------------... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Com... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Salida : out STD_LOGIC_VECTOR (... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_module is Port (
CLK : in STD_LOGIC;
VGA_RED : out STD_LOGIC_VECTOR(3 downto 0);
VGA_GREEN : out STD_LOGIC_VECTOR(3 downto 0);
VGA_BLUE : out STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : out STD_LOGIC;
VGA_HSYNC : out STD_LOGIC;
SW : in std_logic_vector(0 dow... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 18:18:58 2016
--Host : DESKTOP-I329812 running 64-bit major re... |
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., an... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Wed Mar 30 17:30:47 2016
--Host : csteach0 running 64-bit Ubuntu 14.04.4 LT... |
-- $Id: s3board_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: s3board_dummy - syn
-- Description: s3b... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:50:28 07/21/2014
-- Design Name:
-- Module Name: /home/qfi/Documents/aeshw/aes-core/aes-core/decryption_module_tb.vhd
-- Project Name: aes-core
-- Target Device:
-- Tool versions: ... |
entity ADDER_TREE is
generic (
IN_WIDTH : integer := 14;
OUT_WIDTH : integer := 15
);
port (
Q : out std_logic_vector((OUT_WIDTH - 1) downto 0)
);
end entity ADDER_TREE;
|
-------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012... |
-------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-- NEED RESULT: ARCH00292: Floating point types and predefined floating point types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-----------------------------------------------... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: i2s_data_interface - Behavioral
-- Description: Send & Receive I2S data
-- New_sample is asserted for one cycle when a new sample has been
-- ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: i2s_data_interface - Behavioral
-- Description: Send & Receive I2S data
-- New_sample is asserted for one cycle when a new sample has been
-- ... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
--
-- IO dispatcher for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribu... |
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